| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_dsn_ccc_pkt.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
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| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
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| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_dsn_ccc_pkt |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | |
| 40 | wr_req_vld, |
| 41 | cdp2pkt_addr, |
| 42 | cdp2pkt_data, |
| 43 | // cdp2pkt_src_bus, |
| 44 | buf_id_in, |
| 45 | |
| 46 | fsm2pkt_valid, |
| 47 | |
| 48 | j2d_csr_ring_out, |
| 49 | pkt2ctl_dbg_grp_b_1 |
| 50 | ); |
| 51 | |
| 52 | // ---------------------------------------------------------------------------- |
| 53 | // Parameters |
| 54 | // ---------------------------------------------------------------------------- |
| 55 | parameter IDLE = 2'b00, // state machine states |
| 56 | RDMS = 2'b01, |
| 57 | RDLS = 2'b10, |
| 58 | BUSY = 2'b11; |
| 59 | |
| 60 | // ---------------------------------------------------------------------------- |
| 61 | // Ports |
| 62 | // ---------------------------------------------------------------------------- |
| 63 | input clk; |
| 64 | input rst_l; |
| 65 | |
| 66 | input [`FIRE_CSR_DATA_BITS] cdp2pkt_data; |
| 67 | // input [`FIRE_CSR_SRCB_BITS] cdp2pkt_src_bus; |
| 68 | input [1:0] buf_id_in; |
| 69 | input [`FIRE_CSR_ADDR_BITS] cdp2pkt_addr; |
| 70 | |
| 71 | input wr_req_vld; |
| 72 | input fsm2pkt_valid; |
| 73 | |
| 74 | output [`FIRE_CSR_RING_BITS] j2d_csr_ring_out; |
| 75 | output [2:0] pkt2ctl_dbg_grp_b_1; |
| 76 | |
| 77 | // ---------------------------------------------------------------------------- |
| 78 | // Variables |
| 79 | // ---------------------------------------------------------------------------- |
| 80 | wire [`FIRE_CSR_RING_BITS] j2d_csr_ring_out, addr_phase; |
| 81 | wire [`FIRE_CSR_CMND_BITS] cmnd; |
| 82 | |
| 83 | reg [`FIRE_CSR_RING_BITS] ring, nxt_ring; |
| 84 | reg [1:0] state, nxt_state; |
| 85 | reg [1:0] select; |
| 86 | |
| 87 | // ---------------------------------------------------------------------------- |
| 88 | // Zero In Checkers |
| 89 | // ---------------------------------------------------------------------------- |
| 90 | |
| 91 | // ---------------------------------------------------------------------------- |
| 92 | // Combinational |
| 93 | // ---------------------------------------------------------------------------- |
| 94 | assign j2d_csr_ring_out = ring; |
| 95 | |
| 96 | // next state |
| 97 | always @ (state or fsm2pkt_valid) begin |
| 98 | nxt_state = IDLE; |
| 99 | case (state) |
| 100 | IDLE : begin |
| 101 | if (fsm2pkt_valid) nxt_state = RDMS; |
| 102 | else nxt_state = IDLE; |
| 103 | end |
| 104 | RDMS : nxt_state = RDLS; |
| 105 | RDLS : nxt_state = BUSY; |
| 106 | BUSY : begin |
| 107 | if (fsm2pkt_valid) nxt_state = BUSY; |
| 108 | else nxt_state = IDLE; |
| 109 | end |
| 110 | // default: nxt_state = 2'bxx; |
| 111 | endcase |
| 112 | end |
| 113 | |
| 114 | always @ (state or fsm2pkt_valid or wr_req_vld) begin |
| 115 | select = 2'b00; |
| 116 | case (state) |
| 117 | IDLE : begin |
| 118 | if (fsm2pkt_valid) begin |
| 119 | select = 2'b01; |
| 120 | end |
| 121 | else begin |
| 122 | select = 2'b00; |
| 123 | end |
| 124 | end |
| 125 | RDMS : begin |
| 126 | select = {wr_req_vld, 1'b0}; |
| 127 | end |
| 128 | RDLS : begin |
| 129 | select = {wr_req_vld, wr_req_vld}; |
| 130 | end |
| 131 | BUSY : begin |
| 132 | select = 2'b00; |
| 133 | end |
| 134 | // default: select = 2'bxx; |
| 135 | endcase |
| 136 | end |
| 137 | |
| 138 | assign cmnd = wr_req_vld ? `FIRE_CSR_CMND_WREQ : `FIRE_CSR_CMND_RREQ; |
| 139 | //BP 3-08-04 src bus decodes for fast, medium and slow, see FIRE/JBC MAS sec. 6.15.11.3.4 |
| 140 | wire [1:0] cdp2pkt_src_bus; |
| 141 | wire fast_bus, medium_bus, slow_bus; |
| 142 | //BP 4.29.04 note these decodes are using addresses such that the bit positions are byte aligned |
| 143 | // see the code /jbc/csr/ars/ops/rtl/fire_jlc_csr_ars.v line 333 |
| 144 | assign fast_bus = ( (cdp2pkt_addr[19:16] == 4'h0) || // fast bus |
| 145 | (cdp2pkt_addr[19:16] == 4'h1) || |
| 146 | (cdp2pkt_addr[19:16] == 4'h2) || |
| 147 | (cdp2pkt_addr[19:16] == 4'h3) ); |
| 148 | assign medium_bus = ( (cdp2pkt_addr[19:16] == 4'h4) || // medium bus |
| 149 | (cdp2pkt_addr[19:16] == 4'h5) || |
| 150 | (cdp2pkt_addr[19:16] == 4'h6) || |
| 151 | (cdp2pkt_addr[19:16] == 4'h7) ); |
| 152 | assign slow_bus = ( (cdp2pkt_addr[19:16] == 4'h8) || // slow bus |
| 153 | (cdp2pkt_addr[19:16] == 4'h9) || |
| 154 | (cdp2pkt_addr[19:16] == 4'ha) || |
| 155 | (cdp2pkt_addr[19:16] == 4'hb) || |
| 156 | (cdp2pkt_addr[19:16] == 4'hc) || |
| 157 | (cdp2pkt_addr[19:16] == 4'hd) || |
| 158 | (cdp2pkt_addr[19:16] == 4'he) || |
| 159 | (cdp2pkt_addr[19:16] == 4'hf) ); |
| 160 | assign cdp2pkt_src_bus[0] = (fast_bus || slow_bus) && ~buf_id_in[0]; |
| 161 | assign cdp2pkt_src_bus[1] = (fast_bus || medium_bus) && ~buf_id_in[0]; |
| 162 | assign addr_phase[`FIRE_CSR_RING_CMND_BITS] = cmnd; |
| 163 | assign addr_phase[`FIRE_CSR_RING_SRCB_BITS] = cdp2pkt_src_bus; |
| 164 | // BP note: cdp2pkt_addr in N2 is a byte address, so I need to drop the bottom 3 bits here |
| 165 | // because the address out onto the ring is [22:3] |
| 166 | assign addr_phase[`FIRE_CSR_RING_ADDR_BITS] = {3'b0,cdp2pkt_addr[26:3]}; |
| 167 | |
| 168 | always @ (select or addr_phase or cdp2pkt_data) begin |
| 169 | nxt_ring = 0; |
| 170 | case (select) // synopsys infer_mux |
| 171 | 2'b00 : nxt_ring = 0; |
| 172 | 2'b01 : nxt_ring = addr_phase; |
| 173 | 2'b10 : nxt_ring = cdp2pkt_data[`FIRE_CSR_RDMS_BITS]; |
| 174 | 2'b11 : nxt_ring = cdp2pkt_data[`FIRE_CSR_RDLS_BITS]; |
| 175 | // default nxt_ring = 32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx; |
| 176 | endcase |
| 177 | end |
| 178 | |
| 179 | // ---------------------------------------------------------------------------- |
| 180 | // Sequential |
| 181 | // ---------------------------------------------------------------------------- |
| 182 | always @ (posedge clk) begin |
| 183 | if (!rst_l) begin |
| 184 | ring <= 0; |
| 185 | state <= IDLE; |
| 186 | end |
| 187 | else begin |
| 188 | ring <= nxt_ring; |
| 189 | state <= nxt_state; |
| 190 | end |
| 191 | end |
| 192 | |
| 193 | // ---------------------------------------------------------------------------- |
| 194 | // debug --- for dbg group b sub sel 1 |
| 195 | // ---------------------------------------------------------------------------- |
| 196 | assign pkt2ctl_dbg_grp_b_1[2:0] = cmnd[2:0]; |
| 197 | |
| 198 | endmodule // dmu_dsn_ddd_pkt |