| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_ilu_cib.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_ilu_cib ( |
| 36 | clk, |
| 37 | rst_wmr_, |
| 38 | rst_dmu_async_por_, |
| 39 | por_l, |
| 40 | rst_l, |
| 41 | |
| 42 | j2d_instance_id, |
| 43 | |
| 44 | // ilu <-> tlu misc |
| 45 | p2d_mps, |
| 46 | p2d_ue_int, |
| 47 | p2d_ce_int, |
| 48 | p2d_oe_int, |
| 49 | |
| 50 | // D-P drain interface |
| 51 | // d2p_drain, |
| 52 | p2d_drain, |
| 53 | |
| 54 | // ilu <-> dmu misc |
| 55 | y2k_mps, |
| 56 | y2k_int_l, |
| 57 | |
| 58 | // CSR ring |
| 59 | k2y_csr_ring_out, |
| 60 | y2k_csr_ring_in, |
| 61 | d2p_csr_req, |
| 62 | p2d_csr_ack, |
| 63 | d2p_csr_rcd, |
| 64 | p2d_csr_req, |
| 65 | d2p_csr_ack, |
| 66 | p2d_csr_rcd, |
| 67 | |
| 68 | // internal interface |
| 69 | iil2cib_ihb_pe, |
| 70 | cib2iil_ihb_pe_drain, // caused by iil2cib_ihb_pe |
| 71 | cib2iil_pec_drain, // caused by p2d_drain |
| 72 | cib2eil_ihb_pe_drain, |
| 73 | cib2eil_pec_drain, |
| 74 | |
| 75 | // CSR <-> EDB i/f |
| 76 | ilu_diagnos_edi_par_hw_read, |
| 77 | ilu_diagnos_ehi_par_hw_read, |
| 78 | ilu_diagnos_edi_trig_hw_clr, |
| 79 | ilu_diagnos_edi_trig_hw_read, |
| 80 | ilu_diagnos_ehi_trig_hw_clr, |
| 81 | ilu_diagnos_ehi_trig_hw_read, |
| 82 | |
| 83 | // CSR <-> PEU/PSR i/f |
| 84 | ilu_diagnos_rate_scale_hw_read, |
| 85 | |
| 86 | // debug |
| 87 | low_dbg_sel_a, |
| 88 | low_dbg_sel_b, |
| 89 | cib_dbg_a, |
| 90 | cib_dbg_b, |
| 91 | // enables to rx tx pll BP n2 5-24-05 |
| 92 | //BP n2 5-24-05 |
| 93 | dmu_psr_pll_en_sds0, |
| 94 | dmu_psr_pll_en_sds1, |
| 95 | dmu_psr_rx_en_b0_sds0, |
| 96 | dmu_psr_rx_en_b1_sds0, |
| 97 | dmu_psr_rx_en_b2_sds0, |
| 98 | dmu_psr_rx_en_b3_sds0, |
| 99 | dmu_psr_rx_en_b0_sds1, |
| 100 | dmu_psr_rx_en_b1_sds1, |
| 101 | dmu_psr_rx_en_b2_sds1, |
| 102 | dmu_psr_rx_en_b3_sds1, |
| 103 | dmu_psr_tx_en_b0_sds0, |
| 104 | dmu_psr_tx_en_b1_sds0, |
| 105 | dmu_psr_tx_en_b2_sds0, |
| 106 | dmu_psr_tx_en_b3_sds0, |
| 107 | dmu_psr_tx_en_b0_sds1, |
| 108 | dmu_psr_tx_en_b1_sds1, |
| 109 | dmu_psr_tx_en_b2_sds1, |
| 110 | dmu_psr_tx_en_b3_sds1, |
| 111 | tcu_test_protect |
| 112 | ); |
| 113 | |
| 114 | //synopsys sync_set_reset "rst_l" |
| 115 | |
| 116 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 117 | |
| 118 | //------------------------------------------------------------------------ |
| 119 | // Clock and Reset Signals |
| 120 | //------------------------------------------------------------------------ |
| 121 | input clk; // input clock |
| 122 | input rst_wmr_; // raw warm reset |
| 123 | input por_l; // hard reset |
| 124 | input rst_l; // soft reset |
| 125 | input rst_dmu_async_por_; // asyc assertion for serdes enables |
| 126 | |
| 127 | |
| 128 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; |
| 129 | |
| 130 | //------------------------------------------------------------------------ |
| 131 | // ilu <-> tlu misc. interface |
| 132 | //------------------------------------------------------------------------ |
| 133 | input [`FIRE_P2D_MPS_WDTH-1:0] p2d_mps; // max. payld size |
| 134 | input p2d_ue_int; // uncorrectable error |
| 135 | input p2d_ce_int; // correctable error |
| 136 | input p2d_oe_int; // other error |
| 137 | |
| 138 | //------------------------------------------------------------------------ |
| 139 | // |
| 140 | // DMC - PEC drain interface |
| 141 | //------------------------------------------------------------------------ |
| 142 | input p2d_drain; |
| 143 | // output d2p_drain; |
| 144 | |
| 145 | //------------------------------------------------------------------------ |
| 146 | // ilu <-> dmu misc. interface |
| 147 | //------------------------------------------------------------------------ |
| 148 | output [`FIRE_DLC_MPS-1:0] y2k_mps; // max. payld size to CMU |
| 149 | output y2k_int_l; // interrupt req to IMU |
| 150 | |
| 151 | //------------------------------------------------------------------------ |
| 152 | // CSR ring to DMU |
| 153 | //------------------------------------------------------------------------ |
| 154 | input [`FIRE_CSR_RING_WIDTH-1:0] k2y_csr_ring_out; |
| 155 | output [`FIRE_CSR_RING_WIDTH-1:0] y2k_csr_ring_in; |
| 156 | |
| 157 | //------------------------------------------------------------------------ |
| 158 | // CSR ring to TLU |
| 159 | //------------------------------------------------------------------------ |
| 160 | output d2p_csr_req; |
| 161 | input p2d_csr_ack; |
| 162 | output [`FIRE_D2P_CSR_RING_WDTH-1:0] d2p_csr_rcd; |
| 163 | input p2d_csr_req; |
| 164 | output d2p_csr_ack; |
| 165 | input [`FIRE_P2D_CSR_RING_WDTH-1:0] p2d_csr_rcd; |
| 166 | |
| 167 | //------------------------------------------------------------------------ |
| 168 | // Internal module interface |
| 169 | //------------------------------------------------------------------------ |
| 170 | input iil2cib_ihb_pe; // ingress header parity error |
| 171 | output cib2iil_ihb_pe_drain; // caused by iil2cib_ihb_pe |
| 172 | output cib2iil_pec_drain; // caused by p2d_drain |
| 173 | output cib2eil_ihb_pe_drain; |
| 174 | output cib2eil_pec_drain; |
| 175 | |
| 176 | //------------------------------------------------------------------------ |
| 177 | // debug |
| 178 | //------------------------------------------------------------------------ |
| 179 | input [2:0] low_dbg_sel_a; |
| 180 | input [2:0] low_dbg_sel_b; |
| 181 | output [`FIRE_DBG_DATA_BITS] cib_dbg_a; |
| 182 | output [`FIRE_DBG_DATA_BITS] cib_dbg_b; |
| 183 | |
| 184 | // CSR to EDB signals for diagnostic register |
| 185 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read; |
| 186 | // This signal provides the current value of ilu_diagnos_edi_par. |
| 187 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read; |
| 188 | // This signal provides the current value of ilu_diagnos_ehi_par. |
| 189 | input ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for |
| 190 | // ilu_diagnos_edi_trig. When set |
| 191 | // ilu_diagnos will be set to zero. |
| 192 | output ilu_diagnos_edi_trig_hw_read; // This signal provides the current value |
| 193 | // of ilu_diagnos_edi_trig. |
| 194 | input ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for |
| 195 | // ilu_diagnos_ehi_trig. When set |
| 196 | // ilu_diagnos will be set to zero. |
| 197 | output ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value |
| 198 | // of ilu_diagnos_ehi_trig. |
| 199 | |
| 200 | |
| 201 | //------------------------------------------------------------------------ |
| 202 | // BP n2 5-24-05 |
| 203 | // to PEU for pll-enable, tx-lane-enable and rx-lane-enables |
| 204 | //------------------------------------------------------------------------ |
| 205 | output dmu_psr_pll_en_sds0; |
| 206 | output dmu_psr_pll_en_sds1; |
| 207 | output dmu_psr_rx_en_b0_sds0; |
| 208 | output dmu_psr_rx_en_b1_sds0; |
| 209 | output dmu_psr_rx_en_b2_sds0; |
| 210 | output dmu_psr_rx_en_b3_sds0; |
| 211 | output dmu_psr_rx_en_b0_sds1; |
| 212 | output dmu_psr_rx_en_b1_sds1; |
| 213 | output dmu_psr_rx_en_b2_sds1; |
| 214 | output dmu_psr_rx_en_b3_sds1; |
| 215 | output dmu_psr_tx_en_b0_sds0; |
| 216 | output dmu_psr_tx_en_b1_sds0; |
| 217 | output dmu_psr_tx_en_b2_sds0; |
| 218 | output dmu_psr_tx_en_b3_sds0; |
| 219 | output dmu_psr_tx_en_b0_sds1; |
| 220 | output dmu_psr_tx_en_b1_sds1; |
| 221 | output dmu_psr_tx_en_b2_sds1; |
| 222 | output dmu_psr_tx_en_b3_sds1; |
| 223 | input tcu_test_protect; |
| 224 | |
| 225 | //SV - 05/31/05 |
| 226 | output [1:0] ilu_diagnos_rate_scale_hw_read; |
| 227 | |
| 228 | |
| 229 | |
| 230 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 231 | |
| 232 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 233 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; |
| 234 | |
| 235 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~ |
| 236 | |
| 237 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1]; |
| 238 | reg [2:0] dbg_sel [0:1]; |
| 239 | |
| 240 | integer i; |
| 241 | |
| 242 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 243 | |
| 244 | //------------------------------------------------------------------------ |
| 245 | |
| 246 | wire [`FIRE_CSR_RING_BITS] byp2dcs_csr_ring; |
| 247 | wire [`FIRE_CSR_RING_BITS] dcd2byp_csr_ring; |
| 248 | wire [`FIRE_CSR_RING_BITS] byp2dcc_csr_ring; |
| 249 | |
| 250 | |
| 251 | //------------------------------------------------------------------------ |
| 252 | // DCC - DCM interface |
| 253 | //------------------------------------------------------------------------ |
| 254 | wire [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_wr_data; // to csr block |
| 255 | wire [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] csrbus_addr; // to csr block |
| 256 | wire csrbus_wr; // to csr block |
| 257 | wire csrbus_valid; // to csr block |
| 258 | wire [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] csrbus_src_bus; // to csr block |
| 259 | |
| 260 | wire [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_read_data; // from csr block |
| 261 | wire csrbus_done; // from csr block |
| 262 | wire csrbus_mapped; // from csr block |
| 263 | wire csrbus_acc_vio; // from csr block |
| 264 | |
| 265 | //------------------------------------------------------------------------ |
| 266 | // DCM(CSR) - CIM interface |
| 267 | //------------------------------------------------------------------------ |
| 268 | |
| 269 | wire pec_int_en_pec_hw_read; // This signal provides the current value of |
| 270 | // pec_int_en_pec. |
| 271 | wire pec_int_en_pec_ilu_hw_read; // This signal provides the current value of |
| 272 | // pec_int_en_pec_ilu. |
| 273 | wire pec_int_en_pec_ue_hw_read; // This signal provides the current value of |
| 274 | // pec_int_en_pec_ue. |
| 275 | wire pec_int_en_pec_ce_hw_read; // This signal provides the current value of |
| 276 | // pec_int_en_pec_ce. |
| 277 | wire pec_int_en_pec_oe_hw_read; // This signal provides the current value of |
| 278 | // pec_int_en_pec_oe. |
| 279 | wire pec_en_err_ilu_ext_read_data; // Ext read data (decode) |
| 280 | wire pec_en_err_ue_ext_read_data; // Ext read data (decode) |
| 281 | wire pec_en_err_ce_ext_read_data; // Ext read data (decode) |
| 282 | wire pec_en_err_oe_ext_read_data; // Ext read data (decode) |
| 283 | |
| 284 | |
| 285 | wire ilu_int_en_spare3_s_hw_read; // This signal provides the current value |
| 286 | // of ilu_int_en_spare3_s. |
| 287 | wire ilu_int_en_spare2_s_hw_read; // This signal provides the current value |
| 288 | // of ilu_int_en_spare2_s. |
| 289 | wire ilu_int_en_spare1_s_hw_read; // This signal provides the current value |
| 290 | // of ilu_int_en_spare1_s. |
| 291 | wire ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value |
| 292 | // of ilu_int_en_ihb_pe_s. |
| 293 | wire ilu_int_en_spare3_p_hw_read; // This signal provides the current value |
| 294 | // of ilu_int_en_spare3_p. |
| 295 | wire ilu_int_en_spare2_p_hw_read; // This signal provides the current value |
| 296 | // of ilu_int_en_spare2_p. |
| 297 | wire ilu_int_en_spare1_p_hw_read; // This signal provides the current value |
| 298 | // of ilu_int_en_spare1_p. |
| 299 | wire ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value |
| 300 | // of ilu_int_en_ihb_pe_p. |
| 301 | wire ilu_log_en_spare3_hw_read; // This signal provides the current value of |
| 302 | // ilu_log_en_spare3. |
| 303 | wire ilu_log_en_spare2_hw_read; // This signal provides the current value of |
| 304 | // ilu_log_en_spare2. |
| 305 | wire ilu_log_en_spare1_hw_read; // This signal provides the current value of |
| 306 | // ilu_log_en_spare1. |
| 307 | wire ilu_log_en_ihb_pe_hw_read; // This signal provides the current value of |
| 308 | // ilu_log_en_ihb_pe. |
| 309 | wire ilu_en_err_spare3_s_ext_read_data; // Ext read data (decode) |
| 310 | wire ilu_en_err_spare2_s_ext_read_data; // Ext read data (decode) |
| 311 | wire ilu_en_err_spare1_s_ext_read_data; // Ext read data (decode) |
| 312 | wire ilu_en_err_ihb_pe_s_ext_read_data; // Ext read data (decode) |
| 313 | wire ilu_en_err_spare3_p_ext_read_data; // Ext read data (decode) |
| 314 | wire ilu_en_err_spare2_p_ext_read_data; // Ext read data (decode) |
| 315 | wire ilu_en_err_spare1_p_ext_read_data; // Ext read data (decode) |
| 316 | wire ilu_en_err_ihb_pe_p_ext_read_data; // Ext read data (decode) |
| 317 | wire ilu_log_err_spare3_s_hw_set; // Hardware set signal for |
| 318 | // ilu_log_err_spare3_s. When set |
| 319 | // ilu_log_err will be set to one. |
| 320 | wire ilu_log_err_spare3_s_hw_read; // This signal provides the current value |
| 321 | // of ilu_log_err_spare3_s. |
| 322 | wire ilu_log_err_spare2_s_hw_set; // Hardware set signal for |
| 323 | // ilu_log_err_spare2_s. When set |
| 324 | // ilu_log_err will be set to one. |
| 325 | wire ilu_log_err_spare2_s_hw_read; // This signal provides the current value |
| 326 | // of ilu_log_err_spare2_s. |
| 327 | wire ilu_log_err_spare1_s_hw_set; // Hardware set signal for |
| 328 | // ilu_log_err_spare1_s. When set |
| 329 | // ilu_log_err will be set to one. |
| 330 | wire ilu_log_err_spare1_s_hw_read; // This signal provides the current value |
| 331 | // of ilu_log_err_spare1_s. |
| 332 | wire ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for |
| 333 | // ilu_log_err_ihb_pe_s. When set |
| 334 | // ilu_log_err will be set to one. |
| 335 | wire ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value |
| 336 | // of ilu_log_err_ihb_pe_s. |
| 337 | wire ilu_log_err_spare3_p_hw_set; // Hardware set signal for |
| 338 | // ilu_log_err_spare3_p. When set |
| 339 | // ilu_log_err will be set to one. |
| 340 | wire ilu_log_err_spare3_p_hw_read; // This signal provides the current value |
| 341 | // of ilu_log_err_spare3_p. |
| 342 | wire ilu_log_err_spare2_p_hw_set; // Hardware set signal for |
| 343 | // ilu_log_err_spare2_p. When set |
| 344 | // ilu_log_err will be set to one. |
| 345 | wire ilu_log_err_spare2_p_hw_read; // This signal provides the current value |
| 346 | // of ilu_log_err_spare2_p. |
| 347 | wire ilu_log_err_spare1_p_hw_set; // Hardware set signal for |
| 348 | // ilu_log_err_spare1_p. When set |
| 349 | // ilu_log_err will be set to one. |
| 350 | wire ilu_log_err_spare1_p_hw_read; // This signal provides the current value |
| 351 | // of ilu_log_err_spare1_p. |
| 352 | wire ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for |
| 353 | // ilu_log_err_ihb_pe_p. When set |
| 354 | // ilu_log_err will be set to one. |
| 355 | wire ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value |
| 356 | // of ilu_log_err_ihb_pe_p. |
| 357 | wire dbg_ue_int,dbg_ce_int,dbg_oe_int; |
| 358 | wire ilu_diagnos_enpll1_hw_read; // enable SERDES PLL1 |
| 359 | wire ilu_diagnos_enpll0_hw_read; // enable SERDES PLL0 |
| 360 | wire ilu_diagnos_entx7_hw_read; // enable SERDES tx7 |
| 361 | wire ilu_diagnos_entx6_hw_read; // enable SERDES tx6 |
| 362 | wire ilu_diagnos_entx5_hw_read; // enable SERDES tx5 |
| 363 | wire ilu_diagnos_entx4_hw_read; // enable SERDES tx4 |
| 364 | wire ilu_diagnos_entx3_hw_read; // enable SERDES tx3 |
| 365 | wire ilu_diagnos_entx2_hw_read; // enable SERDES tx2 |
| 366 | wire ilu_diagnos_entx1_hw_read; // enable SERDES tx1 |
| 367 | wire ilu_diagnos_entx0_hw_read; // enable SERDES tx0 |
| 368 | wire ilu_diagnos_enrx7_hw_read; // enable SERDES rx7 |
| 369 | wire ilu_diagnos_enrx6_hw_read; // enable SERDES rx6 |
| 370 | wire ilu_diagnos_enrx5_hw_read; // enable SERDES rx5 |
| 371 | wire ilu_diagnos_enrx4_hw_read; // enable SERDES rx4 |
| 372 | wire ilu_diagnos_enrx3_hw_read; // enable SERDES rx3 |
| 373 | wire ilu_diagnos_enrx2_hw_read; // enable SERDES rx2 |
| 374 | wire ilu_diagnos_enrx1_hw_read; // enable SERDES rx1 |
| 375 | wire ilu_diagnos_enrx0_hw_read; // enable SERDES rx0 |
| 376 | |
| 377 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 378 | |
| 379 | |
| 380 | //--------------------------------------------------------------------- |
| 381 | // debug |
| 382 | //--------------------------------------------------------------------- |
| 383 | |
| 384 | always @ (low_dbg_sel_a or low_dbg_sel_b) begin |
| 385 | dbg_sel[0] = low_dbg_sel_a; |
| 386 | dbg_sel[1] = low_dbg_sel_b; |
| 387 | end |
| 388 | |
| 389 | always @ (dbg_sel[0] or dbg_sel[1] or |
| 390 | y2k_mps or |
| 391 | dbg_ue_int or |
| 392 | dbg_ce_int or |
| 393 | dbg_oe_int or |
| 394 | cib2eil_pec_drain or |
| 395 | y2k_int_l ) begin |
| 396 | for (i = 0; i < 2; i = i + 1) begin |
| 397 | case (dbg_sel[i]) // synopsys infer_mux |
| 398 | // 3'b000: nxt_dbg_bus[i] = {p2d_mps, p2d_ue_int, p2d_ce_int, |
| 399 | // p2d_oe_int, p2d_drain, y2k_int_l}; |
| 400 | 3'b000: nxt_dbg_bus[i] = {y2k_mps, dbg_ue_int, dbg_ce_int, |
| 401 | dbg_oe_int, cib2eil_pec_drain, y2k_int_l}; |
| 402 | 3'b001: nxt_dbg_bus[i] = 8'b0; |
| 403 | 3'b010: nxt_dbg_bus[i] = 8'b0; |
| 404 | 3'b011: nxt_dbg_bus[i] = 8'b0; |
| 405 | 3'b100: nxt_dbg_bus[i] = 8'b0; |
| 406 | 3'b101: nxt_dbg_bus[i] = 8'b0; |
| 407 | 3'b110: nxt_dbg_bus[i] = 8'b0; |
| 408 | 3'b111: nxt_dbg_bus[i] = 8'b0; |
| 409 | endcase |
| 410 | end |
| 411 | end |
| 412 | |
| 413 | assign cib_dbg_a = dbg_bus[0]; |
| 414 | assign cib_dbg_b = dbg_bus[1]; |
| 415 | |
| 416 | always @ (posedge clk) |
| 417 | if(~rst_l) begin : dbg_rst |
| 418 | integer j; |
| 419 | for (j = 0; j < 2; j = j + 1) begin |
| 420 | dbg_bus[j] <= {8{1'b0}}; |
| 421 | end |
| 422 | end |
| 423 | else begin : dbg_out |
| 424 | integer j; |
| 425 | for (j = 0; j < 2; j = j + 1) begin |
| 426 | dbg_bus[j] <= nxt_dbg_bus[j]; |
| 427 | end |
| 428 | end |
| 429 | |
| 430 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 431 | |
| 432 | // The current hook up of the 6 DCC's is as follows |
| 433 | // |
| 434 | // to from |
| 435 | // DMC DMC |
| 436 | // | | |
| 437 | // DCC | |
| 438 | // | | |
| 439 | // -------BYP------- |
| 440 | // | | |
| 441 | // DCD DCS |
| 442 | // | | |
| 443 | // | | |
| 444 | // | | |
| 445 | // PEC PEC |
| 446 | // from to |
| 447 | |
| 448 | |
| 449 | |
| 450 | //------------------------------------------------------------------------ |
| 451 | // SERDES enables forced to 0 during pwron |
| 452 | //------------------------------------------------------------------------ |
| 453 | wire serdes_por_; |
| 454 | wire [17:0] x; |
| 455 | assign dmu_psr_pll_en_sds1 = serdes_por_ ? ilu_diagnos_enpll1_hw_read : 1'b1 ; |
| 456 | assign dmu_psr_pll_en_sds0 =serdes_por_ ? ilu_diagnos_enpll0_hw_read : 1'b1 ; |
| 457 | |
| 458 | assign dmu_psr_tx_en_b3_sds1 =serdes_por_ ? ilu_diagnos_entx7_hw_read : 1'b1 ; |
| 459 | assign dmu_psr_tx_en_b2_sds1 =serdes_por_ ? ilu_diagnos_entx6_hw_read : 1'b1 ; |
| 460 | assign dmu_psr_tx_en_b1_sds1 =serdes_por_ ? ilu_diagnos_entx5_hw_read : 1'b1 ; |
| 461 | assign dmu_psr_tx_en_b0_sds1 =serdes_por_ ? ilu_diagnos_entx4_hw_read : 1'b1 ; |
| 462 | assign dmu_psr_tx_en_b3_sds0 =serdes_por_ ? ilu_diagnos_entx3_hw_read : 1'b1 ; |
| 463 | assign dmu_psr_tx_en_b2_sds0 =serdes_por_ ? ilu_diagnos_entx2_hw_read : 1'b1 ; |
| 464 | assign dmu_psr_tx_en_b1_sds0 =serdes_por_ ? ilu_diagnos_entx1_hw_read : 1'b1 ; |
| 465 | assign dmu_psr_tx_en_b0_sds0 =serdes_por_ ? ilu_diagnos_entx0_hw_read : 1'b1 ; |
| 466 | |
| 467 | assign dmu_psr_rx_en_b3_sds1 =serdes_por_ ? ilu_diagnos_enrx7_hw_read : 1'b1 ; |
| 468 | assign dmu_psr_rx_en_b2_sds1 =serdes_por_ ? ilu_diagnos_enrx6_hw_read : 1'b1 ; |
| 469 | assign dmu_psr_rx_en_b1_sds1 =serdes_por_ ? ilu_diagnos_enrx5_hw_read : 1'b1 ; |
| 470 | assign dmu_psr_rx_en_b0_sds1 =serdes_por_ ? ilu_diagnos_enrx4_hw_read : 1'b1 ; |
| 471 | assign dmu_psr_rx_en_b3_sds0 =serdes_por_ ? ilu_diagnos_enrx3_hw_read : 1'b1 ; |
| 472 | assign dmu_psr_rx_en_b2_sds0 =serdes_por_ ? ilu_diagnos_enrx2_hw_read : 1'b1 ; |
| 473 | assign dmu_psr_rx_en_b1_sds0 =serdes_por_ ? ilu_diagnos_enrx1_hw_read : 1'b1 ; |
| 474 | assign dmu_psr_rx_en_b0_sds0 =serdes_por_ ? ilu_diagnos_enrx0_hw_read : 1'b1 ; |
| 475 | |
| 476 | wire rst_dmu_async_por_q_; |
| 477 | wire [1:0] csr_peu_rate_scale,csr_peu_rate_scale_mux_out; |
| 478 | reg tcu_test_protect_d; |
| 479 | reg [1:0] csr_peu_rate_scale_d; |
| 480 | |
| 481 | cl_a1_clksyncff_4x por_sync_flop ( .d(rst_dmu_async_por_), .si(1'b0), .q( rst_dmu_async_por_q_), .so(), |
| 482 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); |
| 483 | |
| 484 | assign serdes_por_ = rst_dmu_async_por_ & rst_dmu_async_por_q_ & ~tcu_test_protect_d; |
| 485 | |
| 486 | always @ (posedge clk) begin |
| 487 | if(~por_l) begin |
| 488 | tcu_test_protect_d <= {1'b0}; |
| 489 | end |
| 490 | else begin |
| 491 | tcu_test_protect_d <= tcu_test_protect; |
| 492 | end |
| 493 | end |
| 494 | |
| 495 | always @ (posedge clk) begin |
| 496 | if(~rst_l | ~por_l) begin |
| 497 | csr_peu_rate_scale_d <= csr_peu_rate_scale; |
| 498 | end |
| 499 | else begin |
| 500 | csr_peu_rate_scale_d <= csr_peu_rate_scale_d; |
| 501 | end |
| 502 | end |
| 503 | |
| 504 | // BP N2 11-10-05, only change rate_scale to peu during wmr_l |
| 505 | |
| 506 | assign csr_peu_rate_scale_mux_out = ~rst_wmr_ ? csr_peu_rate_scale : csr_peu_rate_scale_d ; |
| 507 | assign ilu_diagnos_rate_scale_hw_read = ~serdes_por_ ? 2'b00 : csr_peu_rate_scale_mux_out ; |
| 508 | |
| 509 | // -0in constant -var ilu_diagnos_rate_scale_hw_read -active rst_wmr_ |
| 510 | |
| 511 | //------------------------------------------------------------------------ |
| 512 | // DCB (bypass) |
| 513 | //------------------------------------------------------------------------ |
| 514 | |
| 515 | pcie_common_dcb byp ( |
| 516 | |
| 517 | .csr_byp_ring_out (byp2dcc_csr_ring), |
| 518 | .csr_ext_ring_out (byp2dcs_csr_ring), |
| 519 | .clk (clk), |
| 520 | .rst_l (rst_l), |
| 521 | .byp_src (`FIRE_CSR_SRCB_MEDM), |
| 522 | .csr_byp_ring_in (k2y_csr_ring_out), |
| 523 | .csr_ext_ring_in (dcd2byp_csr_ring) |
| 524 | ); |
| 525 | |
| 526 | |
| 527 | //------------------------------------------------------------------------ |
| 528 | // DCB (bypass) |
| 529 | //------------------------------------------------------------------------ |
| 530 | |
| 531 | pcie_common_dcc dcc ( |
| 532 | |
| 533 | .csr_ring_out (y2k_csr_ring_in), |
| 534 | .csrbus_wr_data (csrbus_wr_data), |
| 535 | .csrbus_addr (csrbus_addr), |
| 536 | .csrbus_wr (csrbus_wr), |
| 537 | .csrbus_valid (csrbus_valid), |
| 538 | .csrbus_src_bus (csrbus_src_bus), |
| 539 | .clk (clk), |
| 540 | .rst_l (rst_l), |
| 541 | .csr_ring_in (byp2dcc_csr_ring), |
| 542 | .csrbus_read_data (csrbus_read_data), |
| 543 | .csrbus_done (csrbus_done), |
| 544 | .csrbus_mapped (csrbus_mapped), |
| 545 | .csrbus_acc_vio (csrbus_acc_vio)); |
| 546 | |
| 547 | |
| 548 | //------------------------------------------------------------------------ |
| 549 | // DCS (To PEC) |
| 550 | //------------------------------------------------------------------------ |
| 551 | |
| 552 | |
| 553 | pcie_common_dcs dcs ( |
| 554 | |
| 555 | .clk (clk), |
| 556 | .rst_l (rst_l), |
| 557 | .csr_rng_data (byp2dcs_csr_ring), |
| 558 | .csr_pkt_ack (p2d_csr_ack), |
| 559 | .csr_pkt_data (d2p_csr_rcd), |
| 560 | .csr_pkt_req (d2p_csr_req)); |
| 561 | |
| 562 | //------------------------------------------------------------------------ |
| 563 | // DCD (From PEC) |
| 564 | //------------------------------------------------------------------------ |
| 565 | |
| 566 | |
| 567 | |
| 568 | pcie_common_dcd dcd( |
| 569 | .clk (clk), |
| 570 | .rst_l (rst_l), |
| 571 | .csr_pkt_data (p2d_csr_rcd), |
| 572 | .csr_pkt_req (p2d_csr_req), |
| 573 | .csr_pkt_ack (d2p_csr_ack), |
| 574 | .csr_rng_data (dcd2byp_csr_ring)); |
| 575 | |
| 576 | |
| 577 | |
| 578 | //------------------------------------------------------------------------ |
| 579 | // DCM |
| 580 | //------------------------------------------------------------------------ |
| 581 | |
| 582 | dmu_ilu_cib_csr csr ( |
| 583 | .clk (clk), |
| 584 | .csrbus_valid (csrbus_valid), |
| 585 | .csrbus_done (csrbus_done), |
| 586 | .csrbus_mapped (csrbus_mapped), |
| 587 | .csrbus_wr_data (csrbus_wr_data), |
| 588 | .csrbus_wr (csrbus_wr), |
| 589 | .csrbus_read_data (csrbus_read_data), |
| 590 | .csrbus_addr (csrbus_addr), |
| 591 | .rst_l (rst_l), |
| 592 | .por_l (por_l), |
| 593 | .csrbus_src_bus (csrbus_src_bus), |
| 594 | .csrbus_acc_vio (csrbus_acc_vio), |
| 595 | .instance_id (j2d_instance_id), |
| 596 | .pec_int_en_pec_hw_read (pec_int_en_pec_hw_read), |
| 597 | .pec_int_en_pec_ilu_hw_read (pec_int_en_pec_ilu_hw_read), |
| 598 | .pec_int_en_pec_ue_hw_read (pec_int_en_pec_ue_hw_read), |
| 599 | .pec_int_en_pec_ce_hw_read (pec_int_en_pec_ce_hw_read), |
| 600 | .pec_int_en_pec_oe_hw_read (pec_int_en_pec_oe_hw_read), |
| 601 | .pec_en_err_ilu_ext_read_data (pec_en_err_ilu_ext_read_data), |
| 602 | .pec_en_err_ue_ext_read_data (pec_en_err_ue_ext_read_data), |
| 603 | .pec_en_err_ce_ext_read_data (pec_en_err_ce_ext_read_data), |
| 604 | .pec_en_err_oe_ext_read_data (pec_en_err_oe_ext_read_data), |
| 605 | .ilu_int_en_spare3_s_hw_read (ilu_int_en_spare3_s_hw_read), |
| 606 | .ilu_int_en_spare2_s_hw_read (ilu_int_en_spare2_s_hw_read), |
| 607 | .ilu_int_en_spare1_s_hw_read (ilu_int_en_spare1_s_hw_read), |
| 608 | .ilu_int_en_ihb_pe_s_hw_read (ilu_int_en_ihb_pe_s_hw_read), |
| 609 | .ilu_int_en_spare3_p_hw_read (ilu_int_en_spare3_p_hw_read), |
| 610 | .ilu_int_en_spare2_p_hw_read (ilu_int_en_spare2_p_hw_read), |
| 611 | .ilu_int_en_spare1_p_hw_read (ilu_int_en_spare1_p_hw_read), |
| 612 | .ilu_int_en_ihb_pe_p_hw_read (ilu_int_en_ihb_pe_p_hw_read), |
| 613 | .ilu_log_en_spare3_hw_read (ilu_log_en_spare3_hw_read), |
| 614 | .ilu_log_en_spare2_hw_read (ilu_log_en_spare2_hw_read), |
| 615 | .ilu_log_en_spare1_hw_read (ilu_log_en_spare1_hw_read), |
| 616 | .ilu_log_en_ihb_pe_hw_read (ilu_log_en_ihb_pe_hw_read), |
| 617 | .ilu_en_err_spare3_s_ext_read_data (ilu_en_err_spare3_s_ext_read_data), |
| 618 | .ilu_en_err_spare2_s_ext_read_data (ilu_en_err_spare2_s_ext_read_data), |
| 619 | .ilu_en_err_spare1_s_ext_read_data (ilu_en_err_spare1_s_ext_read_data), |
| 620 | .ilu_en_err_ihb_pe_s_ext_read_data (ilu_en_err_ihb_pe_s_ext_read_data), |
| 621 | .ilu_en_err_spare3_p_ext_read_data (ilu_en_err_spare3_p_ext_read_data), |
| 622 | .ilu_en_err_spare2_p_ext_read_data (ilu_en_err_spare2_p_ext_read_data), |
| 623 | .ilu_en_err_spare1_p_ext_read_data (ilu_en_err_spare1_p_ext_read_data), |
| 624 | .ilu_en_err_ihb_pe_p_ext_read_data (ilu_en_err_ihb_pe_p_ext_read_data), |
| 625 | .ilu_log_err_spare3_s_hw_set (ilu_log_err_spare3_s_hw_set), |
| 626 | .ilu_log_err_spare3_s_hw_read (ilu_log_err_spare3_s_hw_read), |
| 627 | .ilu_log_err_spare2_s_hw_set (ilu_log_err_spare2_s_hw_set), |
| 628 | .ilu_log_err_spare2_s_hw_read (ilu_log_err_spare2_s_hw_read), |
| 629 | .ilu_log_err_spare1_s_hw_set (ilu_log_err_spare1_s_hw_set), |
| 630 | .ilu_log_err_spare1_s_hw_read (ilu_log_err_spare1_s_hw_read), |
| 631 | .ilu_log_err_ihb_pe_s_hw_set (ilu_log_err_ihb_pe_s_hw_set), |
| 632 | .ilu_log_err_ihb_pe_s_hw_read (ilu_log_err_ihb_pe_s_hw_read), |
| 633 | .ilu_log_err_spare3_p_hw_set (ilu_log_err_spare3_p_hw_set), |
| 634 | .ilu_log_err_spare3_p_hw_read (ilu_log_err_spare3_p_hw_read), |
| 635 | .ilu_log_err_spare2_p_hw_set (ilu_log_err_spare2_p_hw_set), |
| 636 | .ilu_log_err_spare2_p_hw_read (ilu_log_err_spare2_p_hw_read), |
| 637 | .ilu_log_err_spare1_p_hw_set (ilu_log_err_spare1_p_hw_set), |
| 638 | .ilu_log_err_spare1_p_hw_read (ilu_log_err_spare1_p_hw_read), |
| 639 | .ilu_log_err_ihb_pe_p_hw_set (ilu_log_err_ihb_pe_p_hw_set), |
| 640 | .ilu_log_err_ihb_pe_p_hw_read (ilu_log_err_ihb_pe_p_hw_read), |
| 641 | .ilu_diagnos_edi_par_hw_read (ilu_diagnos_edi_par_hw_read), |
| 642 | .ilu_diagnos_ehi_par_hw_read (ilu_diagnos_ehi_par_hw_read), |
| 643 | .ilu_diagnos_edi_trig_hw_clr (ilu_diagnos_edi_trig_hw_clr), |
| 644 | .ilu_diagnos_edi_trig_hw_read (ilu_diagnos_edi_trig_hw_read), |
| 645 | .ilu_diagnos_ehi_trig_hw_clr (ilu_diagnos_ehi_trig_hw_clr), |
| 646 | .ilu_diagnos_ehi_trig_hw_read (ilu_diagnos_ehi_trig_hw_read), |
| 647 | .ilu_diagnos_enpll1_hw_read (ilu_diagnos_enpll1_hw_read ), |
| 648 | .ilu_diagnos_enpll0_hw_read (ilu_diagnos_enpll0_hw_read ), |
| 649 | .ilu_diagnos_entx7_hw_read (ilu_diagnos_entx7_hw_read ), |
| 650 | .ilu_diagnos_entx6_hw_read (ilu_diagnos_entx6_hw_read ), |
| 651 | .ilu_diagnos_entx5_hw_read (ilu_diagnos_entx5_hw_read ), |
| 652 | .ilu_diagnos_entx4_hw_read (ilu_diagnos_entx4_hw_read ), |
| 653 | .ilu_diagnos_entx3_hw_read (ilu_diagnos_entx3_hw_read ), |
| 654 | .ilu_diagnos_entx2_hw_read (ilu_diagnos_entx2_hw_read ), |
| 655 | .ilu_diagnos_entx1_hw_read (ilu_diagnos_entx1_hw_read ), |
| 656 | .ilu_diagnos_entx0_hw_read (ilu_diagnos_entx0_hw_read ), |
| 657 | .ilu_diagnos_enrx7_hw_read (ilu_diagnos_enrx7_hw_read ), |
| 658 | .ilu_diagnos_enrx6_hw_read (ilu_diagnos_enrx6_hw_read ), |
| 659 | .ilu_diagnos_enrx5_hw_read (ilu_diagnos_enrx5_hw_read ), |
| 660 | .ilu_diagnos_enrx4_hw_read (ilu_diagnos_enrx4_hw_read ), |
| 661 | .ilu_diagnos_enrx3_hw_read (ilu_diagnos_enrx3_hw_read ), |
| 662 | .ilu_diagnos_enrx2_hw_read (ilu_diagnos_enrx2_hw_read ), |
| 663 | .ilu_diagnos_enrx1_hw_read (ilu_diagnos_enrx1_hw_read ), |
| 664 | .ilu_diagnos_enrx0_hw_read (ilu_diagnos_enrx0_hw_read ), |
| 665 | .ilu_diagnos_rate_scale_hw_read (csr_peu_rate_scale) |
| 666 | |
| 667 | ); |
| 668 | |
| 669 | dmu_ilu_cib_cim cim ( |
| 670 | |
| 671 | .clk (clk), |
| 672 | .rst_l (rst_l), |
| 673 | .p2d_mps (p2d_mps), |
| 674 | .p2d_ue_int (p2d_ue_int), |
| 675 | .p2d_ce_int (p2d_ce_int), |
| 676 | .p2d_oe_int (p2d_oe_int), |
| 677 | .dbg_ue_int (dbg_ue_int), |
| 678 | .dbg_ce_int (dbg_ce_int), |
| 679 | .dbg_oe_int (dbg_oe_int), |
| 680 | .p2d_drain (p2d_drain), |
| 681 | .y2k_mps (y2k_mps), |
| 682 | .y2k_int_l (y2k_int_l), |
| 683 | .iil2cib_ihb_pe (iil2cib_ihb_pe), |
| 684 | .cib2iil_ihb_pe_drain (cib2iil_ihb_pe_drain), |
| 685 | .cib2iil_pec_drain (cib2iil_pec_drain), |
| 686 | .cib2eil_ihb_pe_drain (cib2eil_ihb_pe_drain), |
| 687 | .cib2eil_pec_drain (cib2eil_pec_drain), |
| 688 | .pec_int_en_pec_hw_read (pec_int_en_pec_hw_read), |
| 689 | .pec_int_en_pec_ilu_hw_read (pec_int_en_pec_ilu_hw_read), |
| 690 | .pec_int_en_pec_ue_hw_read (pec_int_en_pec_ue_hw_read), |
| 691 | .pec_int_en_pec_ce_hw_read (pec_int_en_pec_ce_hw_read), |
| 692 | .pec_int_en_pec_oe_hw_read (pec_int_en_pec_oe_hw_read), |
| 693 | .pec_en_err_ilu_ext_read_data (pec_en_err_ilu_ext_read_data), |
| 694 | .pec_en_err_ue_ext_read_data (pec_en_err_ue_ext_read_data), |
| 695 | .pec_en_err_ce_ext_read_data (pec_en_err_ce_ext_read_data), |
| 696 | .pec_en_err_oe_ext_read_data (pec_en_err_oe_ext_read_data), |
| 697 | .ilu_int_en_spare3_s_hw_read (ilu_int_en_spare3_s_hw_read), |
| 698 | .ilu_int_en_spare2_s_hw_read (ilu_int_en_spare2_s_hw_read), |
| 699 | .ilu_int_en_spare1_s_hw_read (ilu_int_en_spare1_s_hw_read), |
| 700 | .ilu_int_en_ihb_pe_s_hw_read (ilu_int_en_ihb_pe_s_hw_read), |
| 701 | .ilu_int_en_spare3_p_hw_read (ilu_int_en_spare3_p_hw_read), |
| 702 | .ilu_int_en_spare2_p_hw_read (ilu_int_en_spare2_p_hw_read), |
| 703 | .ilu_int_en_spare1_p_hw_read (ilu_int_en_spare1_p_hw_read), |
| 704 | .ilu_int_en_ihb_pe_p_hw_read (ilu_int_en_ihb_pe_p_hw_read), |
| 705 | .ilu_log_en_spare3_hw_read (ilu_log_en_spare3_hw_read), |
| 706 | .ilu_log_en_spare2_hw_read (ilu_log_en_spare2_hw_read), |
| 707 | .ilu_log_en_spare1_hw_read (ilu_log_en_spare1_hw_read), |
| 708 | .ilu_log_en_ihb_pe_hw_read (ilu_log_en_ihb_pe_hw_read), |
| 709 | .ilu_en_err_spare3_s_ext_read_data (ilu_en_err_spare3_s_ext_read_data), |
| 710 | .ilu_en_err_spare2_s_ext_read_data (ilu_en_err_spare2_s_ext_read_data), |
| 711 | .ilu_en_err_spare1_s_ext_read_data (ilu_en_err_spare1_s_ext_read_data), |
| 712 | .ilu_en_err_ihb_pe_s_ext_read_data (ilu_en_err_ihb_pe_s_ext_read_data), |
| 713 | .ilu_en_err_spare3_p_ext_read_data (ilu_en_err_spare3_p_ext_read_data), |
| 714 | .ilu_en_err_spare2_p_ext_read_data (ilu_en_err_spare2_p_ext_read_data), |
| 715 | .ilu_en_err_spare1_p_ext_read_data (ilu_en_err_spare1_p_ext_read_data), |
| 716 | .ilu_en_err_ihb_pe_p_ext_read_data (ilu_en_err_ihb_pe_p_ext_read_data), |
| 717 | .ilu_log_err_spare3_s_hw_set (ilu_log_err_spare3_s_hw_set), |
| 718 | .ilu_log_err_spare3_s_hw_read (ilu_log_err_spare3_s_hw_read), |
| 719 | .ilu_log_err_spare2_s_hw_set (ilu_log_err_spare2_s_hw_set), |
| 720 | .ilu_log_err_spare2_s_hw_read (ilu_log_err_spare2_s_hw_read), |
| 721 | .ilu_log_err_spare1_s_hw_set (ilu_log_err_spare1_s_hw_set), |
| 722 | .ilu_log_err_spare1_s_hw_read (ilu_log_err_spare1_s_hw_read), |
| 723 | .ilu_log_err_ihb_pe_s_hw_set (ilu_log_err_ihb_pe_s_hw_set), |
| 724 | .ilu_log_err_ihb_pe_s_hw_read (ilu_log_err_ihb_pe_s_hw_read), |
| 725 | .ilu_log_err_spare3_p_hw_set (ilu_log_err_spare3_p_hw_set), |
| 726 | .ilu_log_err_spare3_p_hw_read (ilu_log_err_spare3_p_hw_read), |
| 727 | .ilu_log_err_spare2_p_hw_set (ilu_log_err_spare2_p_hw_set), |
| 728 | .ilu_log_err_spare2_p_hw_read (ilu_log_err_spare2_p_hw_read), |
| 729 | .ilu_log_err_spare1_p_hw_set (ilu_log_err_spare1_p_hw_set), |
| 730 | .ilu_log_err_spare1_p_hw_read (ilu_log_err_spare1_p_hw_read), |
| 731 | .ilu_log_err_ihb_pe_p_hw_set (ilu_log_err_ihb_pe_p_hw_set), |
| 732 | .ilu_log_err_ihb_pe_p_hw_read (ilu_log_err_ihb_pe_p_hw_read)); |
| 733 | |
| 734 | |
| 735 | endmodule // dmu_ilu_cib |
| 736 | |
| 737 | |
| 738 | |