| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_csr_ilu_diagnos.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_ilu_cib_csr_ilu_diagnos |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | por_l, |
| 40 | ilu_diagnos_w_ld, |
| 41 | csrbus_wr_data, |
| 42 | ilu_diagnos_csrbus_read_data, |
| 43 | ilu_diagnos_enpll1_hw_read, |
| 44 | ilu_diagnos_enpll0_hw_read, |
| 45 | ilu_diagnos_entx7_hw_read, |
| 46 | ilu_diagnos_entx6_hw_read, |
| 47 | ilu_diagnos_entx5_hw_read, |
| 48 | ilu_diagnos_entx4_hw_read, |
| 49 | ilu_diagnos_entx3_hw_read, |
| 50 | ilu_diagnos_entx2_hw_read, |
| 51 | ilu_diagnos_entx1_hw_read, |
| 52 | ilu_diagnos_entx0_hw_read, |
| 53 | ilu_diagnos_enrx7_hw_read, |
| 54 | ilu_diagnos_enrx6_hw_read, |
| 55 | ilu_diagnos_enrx5_hw_read, |
| 56 | ilu_diagnos_enrx4_hw_read, |
| 57 | ilu_diagnos_enrx3_hw_read, |
| 58 | ilu_diagnos_enrx2_hw_read, |
| 59 | ilu_diagnos_enrx1_hw_read, |
| 60 | ilu_diagnos_enrx0_hw_read, |
| 61 | ilu_diagnos_edi_par_hw_read, |
| 62 | ilu_diagnos_ehi_par_hw_read, |
| 63 | ilu_diagnos_edi_trig_hw_clr, |
| 64 | ilu_diagnos_edi_trig_hw_read, |
| 65 | ilu_diagnos_ehi_trig_hw_clr, |
| 66 | ilu_diagnos_ehi_trig_hw_read, |
| 67 | ilu_diagnos_rate_scale_hw_read |
| 68 | ); |
| 69 | |
| 70 | //==================================================================== |
| 71 | // Polarity declarations |
| 72 | //==================================================================== |
| 73 | input clk; // Clock |
| 74 | input rst_l; // Reset signal |
| 75 | input por_l; // Reset signal |
| 76 | input ilu_diagnos_w_ld; // SW load bus |
| 77 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 78 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH-1:0] ilu_diagnos_csrbus_read_data; |
| 79 | // SW read data |
| 80 | output ilu_diagnos_enpll1_hw_read; // This signal provides the current value of |
| 81 | // ilu_diagnos_enpll1. |
| 82 | output ilu_diagnos_enpll0_hw_read; // This signal provides the current value of |
| 83 | // ilu_diagnos_enpll0. |
| 84 | output ilu_diagnos_entx7_hw_read; // This signal provides the current value of |
| 85 | // ilu_diagnos_entx7. |
| 86 | output ilu_diagnos_entx6_hw_read; // This signal provides the current value of |
| 87 | // ilu_diagnos_entx6. |
| 88 | output ilu_diagnos_entx5_hw_read; // This signal provides the current value of |
| 89 | // ilu_diagnos_entx5. |
| 90 | output ilu_diagnos_entx4_hw_read; // This signal provides the current value of |
| 91 | // ilu_diagnos_entx4. |
| 92 | output ilu_diagnos_entx3_hw_read; // This signal provides the current value of |
| 93 | // ilu_diagnos_entx3. |
| 94 | output ilu_diagnos_entx2_hw_read; // This signal provides the current value of |
| 95 | // ilu_diagnos_entx2. |
| 96 | output ilu_diagnos_entx1_hw_read; // This signal provides the current value of |
| 97 | // ilu_diagnos_entx1. |
| 98 | output ilu_diagnos_entx0_hw_read; // This signal provides the current value of |
| 99 | // ilu_diagnos_entx0. |
| 100 | output ilu_diagnos_enrx7_hw_read; // This signal provides the current value of |
| 101 | // ilu_diagnos_enrx7. |
| 102 | output ilu_diagnos_enrx6_hw_read; // This signal provides the current value of |
| 103 | // ilu_diagnos_enrx6. |
| 104 | output ilu_diagnos_enrx5_hw_read; // This signal provides the current value of |
| 105 | // ilu_diagnos_enrx5. |
| 106 | output ilu_diagnos_enrx4_hw_read; // This signal provides the current value of |
| 107 | // ilu_diagnos_enrx4. |
| 108 | output ilu_diagnos_enrx3_hw_read; // This signal provides the current value of |
| 109 | // ilu_diagnos_enrx3. |
| 110 | output ilu_diagnos_enrx2_hw_read; // This signal provides the current value of |
| 111 | // ilu_diagnos_enrx2. |
| 112 | output ilu_diagnos_enrx1_hw_read; // This signal provides the current value of |
| 113 | // ilu_diagnos_enrx1. |
| 114 | output ilu_diagnos_enrx0_hw_read; // This signal provides the current value of |
| 115 | // ilu_diagnos_enrx0. |
| 116 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read; |
| 117 | // This signal provides the current value of ilu_diagnos_edi_par. |
| 118 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read; |
| 119 | // This signal provides the current value of ilu_diagnos_ehi_par. |
| 120 | input ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for |
| 121 | // ilu_diagnos_edi_trig. When set |
| 122 | // ilu_diagnos will be set to zero. |
| 123 | output ilu_diagnos_edi_trig_hw_read; // This signal provides the current value |
| 124 | // of ilu_diagnos_edi_trig. |
| 125 | input ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for |
| 126 | // ilu_diagnos_ehi_trig. When set |
| 127 | // ilu_diagnos will be set to zero. |
| 128 | output ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value |
| 129 | // of ilu_diagnos_ehi_trig. |
| 130 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC] ilu_diagnos_rate_scale_hw_read; |
| 131 | // This signal provides the current value of ilu_diagnos_rate_scale. |
| 132 | |
| 133 | //==================================================================== |
| 134 | // Type declarations |
| 135 | //==================================================================== |
| 136 | wire clk; // Clock |
| 137 | wire rst_l; // Reset signal |
| 138 | wire por_l; // Reset signal |
| 139 | wire ilu_diagnos_w_ld; // SW load bus |
| 140 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 141 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH-1:0] ilu_diagnos_csrbus_read_data; |
| 142 | // SW read data |
| 143 | wire ilu_diagnos_enpll1_hw_read; // This signal provides the current value of |
| 144 | // ilu_diagnos_enpll1. |
| 145 | wire ilu_diagnos_enpll0_hw_read; // This signal provides the current value of |
| 146 | // ilu_diagnos_enpll0. |
| 147 | wire ilu_diagnos_entx7_hw_read; // This signal provides the current value of |
| 148 | // ilu_diagnos_entx7. |
| 149 | wire ilu_diagnos_entx6_hw_read; // This signal provides the current value of |
| 150 | // ilu_diagnos_entx6. |
| 151 | wire ilu_diagnos_entx5_hw_read; // This signal provides the current value of |
| 152 | // ilu_diagnos_entx5. |
| 153 | wire ilu_diagnos_entx4_hw_read; // This signal provides the current value of |
| 154 | // ilu_diagnos_entx4. |
| 155 | wire ilu_diagnos_entx3_hw_read; // This signal provides the current value of |
| 156 | // ilu_diagnos_entx3. |
| 157 | wire ilu_diagnos_entx2_hw_read; // This signal provides the current value of |
| 158 | // ilu_diagnos_entx2. |
| 159 | wire ilu_diagnos_entx1_hw_read; // This signal provides the current value of |
| 160 | // ilu_diagnos_entx1. |
| 161 | wire ilu_diagnos_entx0_hw_read; // This signal provides the current value of |
| 162 | // ilu_diagnos_entx0. |
| 163 | wire ilu_diagnos_enrx7_hw_read; // This signal provides the current value of |
| 164 | // ilu_diagnos_enrx7. |
| 165 | wire ilu_diagnos_enrx6_hw_read; // This signal provides the current value of |
| 166 | // ilu_diagnos_enrx6. |
| 167 | wire ilu_diagnos_enrx5_hw_read; // This signal provides the current value of |
| 168 | // ilu_diagnos_enrx5. |
| 169 | wire ilu_diagnos_enrx4_hw_read; // This signal provides the current value of |
| 170 | // ilu_diagnos_enrx4. |
| 171 | wire ilu_diagnos_enrx3_hw_read; // This signal provides the current value of |
| 172 | // ilu_diagnos_enrx3. |
| 173 | wire ilu_diagnos_enrx2_hw_read; // This signal provides the current value of |
| 174 | // ilu_diagnos_enrx2. |
| 175 | wire ilu_diagnos_enrx1_hw_read; // This signal provides the current value of |
| 176 | // ilu_diagnos_enrx1. |
| 177 | wire ilu_diagnos_enrx0_hw_read; // This signal provides the current value of |
| 178 | // ilu_diagnos_enrx0. |
| 179 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read; |
| 180 | // This signal provides the current value of ilu_diagnos_edi_par. |
| 181 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read; |
| 182 | // This signal provides the current value of ilu_diagnos_ehi_par. |
| 183 | wire ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for |
| 184 | // ilu_diagnos_edi_trig. When set ilu_diagnos |
| 185 | // will be set to zero. |
| 186 | wire ilu_diagnos_edi_trig_hw_read; // This signal provides the current value of |
| 187 | // ilu_diagnos_edi_trig. |
| 188 | wire ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for |
| 189 | // ilu_diagnos_ehi_trig. When set ilu_diagnos |
| 190 | // will be set to zero. |
| 191 | wire ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value of |
| 192 | // ilu_diagnos_ehi_trig. |
| 193 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC] ilu_diagnos_rate_scale_hw_read; |
| 194 | // This signal provides the current value of ilu_diagnos_rate_scale. |
| 195 | |
| 196 | //==================================================================== |
| 197 | // Logic |
| 198 | //==================================================================== |
| 199 | |
| 200 | // synopsys translate_off |
| 201 | // verilint 123 off |
| 202 | // verilint 498 off |
| 203 | reg omni_ld; |
| 204 | reg [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH-1:0] omni_data; |
| 205 | |
| 206 | // vlint flag_unsynthesizable_initial off |
| 207 | initial |
| 208 | begin |
| 209 | omni_ld = 1'b0; |
| 210 | omni_data = `FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH'b0; |
| 211 | end// vlint flag_unsynthesizable_initial on |
| 212 | |
| 213 | // verilint 123 on |
| 214 | // verilint 498 on |
| 215 | // synopsys translate_on |
| 216 | |
| 217 | //----- Hardware Data Out Mux Assignments |
| 218 | assign ilu_diagnos_enpll1_hw_read= |
| 219 | ilu_diagnos_csrbus_read_data [33]; |
| 220 | assign ilu_diagnos_enpll0_hw_read= |
| 221 | ilu_diagnos_csrbus_read_data [32]; |
| 222 | assign ilu_diagnos_entx7_hw_read= |
| 223 | ilu_diagnos_csrbus_read_data [31]; |
| 224 | assign ilu_diagnos_entx6_hw_read= |
| 225 | ilu_diagnos_csrbus_read_data [30]; |
| 226 | assign ilu_diagnos_entx5_hw_read= |
| 227 | ilu_diagnos_csrbus_read_data [29]; |
| 228 | assign ilu_diagnos_entx4_hw_read= |
| 229 | ilu_diagnos_csrbus_read_data [28]; |
| 230 | assign ilu_diagnos_entx3_hw_read= |
| 231 | ilu_diagnos_csrbus_read_data [27]; |
| 232 | assign ilu_diagnos_entx2_hw_read= |
| 233 | ilu_diagnos_csrbus_read_data [26]; |
| 234 | assign ilu_diagnos_entx1_hw_read= |
| 235 | ilu_diagnos_csrbus_read_data [25]; |
| 236 | assign ilu_diagnos_entx0_hw_read= |
| 237 | ilu_diagnos_csrbus_read_data [24]; |
| 238 | assign ilu_diagnos_enrx7_hw_read= |
| 239 | ilu_diagnos_csrbus_read_data [23]; |
| 240 | assign ilu_diagnos_enrx6_hw_read= |
| 241 | ilu_diagnos_csrbus_read_data [22]; |
| 242 | assign ilu_diagnos_enrx5_hw_read= |
| 243 | ilu_diagnos_csrbus_read_data [21]; |
| 244 | assign ilu_diagnos_enrx4_hw_read= |
| 245 | ilu_diagnos_csrbus_read_data [20]; |
| 246 | assign ilu_diagnos_enrx3_hw_read= |
| 247 | ilu_diagnos_csrbus_read_data [19]; |
| 248 | assign ilu_diagnos_enrx2_hw_read= |
| 249 | ilu_diagnos_csrbus_read_data [18]; |
| 250 | assign ilu_diagnos_enrx1_hw_read= |
| 251 | ilu_diagnos_csrbus_read_data [17]; |
| 252 | assign ilu_diagnos_enrx0_hw_read= |
| 253 | ilu_diagnos_csrbus_read_data [16]; |
| 254 | assign ilu_diagnos_edi_par_hw_read= |
| 255 | ilu_diagnos_csrbus_read_data |
| 256 | [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_SLC]; |
| 257 | assign ilu_diagnos_ehi_par_hw_read= |
| 258 | ilu_diagnos_csrbus_read_data |
| 259 | [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_SLC]; |
| 260 | assign ilu_diagnos_edi_trig_hw_read= |
| 261 | ilu_diagnos_csrbus_read_data [5]; |
| 262 | assign ilu_diagnos_ehi_trig_hw_read= |
| 263 | ilu_diagnos_csrbus_read_data [4]; |
| 264 | assign ilu_diagnos_rate_scale_hw_read= |
| 265 | ilu_diagnos_csrbus_read_data |
| 266 | [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_SLC]; |
| 267 | |
| 268 | //==================================================================== |
| 269 | // Instantiation of entries |
| 270 | //==================================================================== |
| 271 | |
| 272 | //----- Entry 0 |
| 273 | dmu_ilu_cib_csr_ilu_diagnos_entry ilu_diagnos_0 |
| 274 | ( |
| 275 | // synopsys translate_off |
| 276 | .omni_ld (omni_ld), |
| 277 | .omni_data (omni_data), |
| 278 | // synopsys translate_on |
| 279 | .clk (clk), |
| 280 | .rst_l (rst_l), |
| 281 | .por_l (por_l), |
| 282 | .w_ld (ilu_diagnos_w_ld), |
| 283 | .csrbus_wr_data (csrbus_wr_data), |
| 284 | .ilu_diagnos_csrbus_read_data (ilu_diagnos_csrbus_read_data), |
| 285 | .ilu_diagnos_edi_trig_hw_clr (ilu_diagnos_edi_trig_hw_clr), |
| 286 | .ilu_diagnos_ehi_trig_hw_clr (ilu_diagnos_ehi_trig_hw_clr) |
| 287 | ); |
| 288 | |
| 289 | endmodule // dmu_ilu_cib_csr_ilu_diagnos |