| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_csr_ilu_log_err.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_ilu_cib_csr_ilu_log_err |
| 36 | ( |
| 37 | clk, |
| 38 | por_l, |
| 39 | ilu_log_err_w_ld, |
| 40 | csrbus_wr_data, |
| 41 | rw1c_alias, |
| 42 | rw1s_alias, |
| 43 | ilu_log_err_csrbus_read_data, |
| 44 | ilu_log_err_spare3_s_hw_set, |
| 45 | ilu_log_err_spare3_s_hw_read, |
| 46 | ilu_log_err_spare2_s_hw_set, |
| 47 | ilu_log_err_spare2_s_hw_read, |
| 48 | ilu_log_err_spare1_s_hw_set, |
| 49 | ilu_log_err_spare1_s_hw_read, |
| 50 | ilu_log_err_ihb_pe_s_hw_set, |
| 51 | ilu_log_err_ihb_pe_s_hw_read, |
| 52 | ilu_log_err_spare3_p_hw_set, |
| 53 | ilu_log_err_spare3_p_hw_read, |
| 54 | ilu_log_err_spare2_p_hw_set, |
| 55 | ilu_log_err_spare2_p_hw_read, |
| 56 | ilu_log_err_spare1_p_hw_set, |
| 57 | ilu_log_err_spare1_p_hw_read, |
| 58 | ilu_log_err_ihb_pe_p_hw_set, |
| 59 | ilu_log_err_ihb_pe_p_hw_read |
| 60 | ); |
| 61 | |
| 62 | //==================================================================== |
| 63 | // Polarity declarations |
| 64 | //==================================================================== |
| 65 | input clk; // Clock |
| 66 | input por_l; // Reset signal |
| 67 | input ilu_log_err_w_ld; // SW load bus |
| 68 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 69 | input rw1c_alias; // SW load type: write-one-to-clear |
| 70 | input rw1s_alias; // SW load type: write-one-to-set |
| 71 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH-1:0] ilu_log_err_csrbus_read_data; |
| 72 | // SW read data |
| 73 | input ilu_log_err_spare3_s_hw_set; // Hardware set signal for |
| 74 | // ilu_log_err_spare3_s. When set |
| 75 | // ilu_log_err will be set to one. |
| 76 | output ilu_log_err_spare3_s_hw_read; // This signal provides the current value |
| 77 | // of ilu_log_err_spare3_s. |
| 78 | input ilu_log_err_spare2_s_hw_set; // Hardware set signal for |
| 79 | // ilu_log_err_spare2_s. When set |
| 80 | // ilu_log_err will be set to one. |
| 81 | output ilu_log_err_spare2_s_hw_read; // This signal provides the current value |
| 82 | // of ilu_log_err_spare2_s. |
| 83 | input ilu_log_err_spare1_s_hw_set; // Hardware set signal for |
| 84 | // ilu_log_err_spare1_s. When set |
| 85 | // ilu_log_err will be set to one. |
| 86 | output ilu_log_err_spare1_s_hw_read; // This signal provides the current value |
| 87 | // of ilu_log_err_spare1_s. |
| 88 | input ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for |
| 89 | // ilu_log_err_ihb_pe_s. When set |
| 90 | // ilu_log_err will be set to one. |
| 91 | output ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value |
| 92 | // of ilu_log_err_ihb_pe_s. |
| 93 | input ilu_log_err_spare3_p_hw_set; // Hardware set signal for |
| 94 | // ilu_log_err_spare3_p. When set |
| 95 | // ilu_log_err will be set to one. |
| 96 | output ilu_log_err_spare3_p_hw_read; // This signal provides the current value |
| 97 | // of ilu_log_err_spare3_p. |
| 98 | input ilu_log_err_spare2_p_hw_set; // Hardware set signal for |
| 99 | // ilu_log_err_spare2_p. When set |
| 100 | // ilu_log_err will be set to one. |
| 101 | output ilu_log_err_spare2_p_hw_read; // This signal provides the current value |
| 102 | // of ilu_log_err_spare2_p. |
| 103 | input ilu_log_err_spare1_p_hw_set; // Hardware set signal for |
| 104 | // ilu_log_err_spare1_p. When set |
| 105 | // ilu_log_err will be set to one. |
| 106 | output ilu_log_err_spare1_p_hw_read; // This signal provides the current value |
| 107 | // of ilu_log_err_spare1_p. |
| 108 | input ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for |
| 109 | // ilu_log_err_ihb_pe_p. When set |
| 110 | // ilu_log_err will be set to one. |
| 111 | output ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value |
| 112 | // of ilu_log_err_ihb_pe_p. |
| 113 | |
| 114 | //==================================================================== |
| 115 | // Type declarations |
| 116 | //==================================================================== |
| 117 | wire clk; // Clock |
| 118 | wire por_l; // Reset signal |
| 119 | wire ilu_log_err_w_ld; // SW load bus |
| 120 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 121 | wire rw1c_alias; // SW load type: write-one-to-clear |
| 122 | wire rw1s_alias; // SW load type: write-one-to-set |
| 123 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH-1:0] ilu_log_err_csrbus_read_data; |
| 124 | // SW read data |
| 125 | wire ilu_log_err_spare3_s_hw_set; // Hardware set signal for |
| 126 | // ilu_log_err_spare3_s. When set ilu_log_err |
| 127 | // will be set to one. |
| 128 | wire ilu_log_err_spare3_s_hw_read; // This signal provides the current value of |
| 129 | // ilu_log_err_spare3_s. |
| 130 | wire ilu_log_err_spare2_s_hw_set; // Hardware set signal for |
| 131 | // ilu_log_err_spare2_s. When set ilu_log_err |
| 132 | // will be set to one. |
| 133 | wire ilu_log_err_spare2_s_hw_read; // This signal provides the current value of |
| 134 | // ilu_log_err_spare2_s. |
| 135 | wire ilu_log_err_spare1_s_hw_set; // Hardware set signal for |
| 136 | // ilu_log_err_spare1_s. When set ilu_log_err |
| 137 | // will be set to one. |
| 138 | wire ilu_log_err_spare1_s_hw_read; // This signal provides the current value of |
| 139 | // ilu_log_err_spare1_s. |
| 140 | wire ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for |
| 141 | // ilu_log_err_ihb_pe_s. When set ilu_log_err |
| 142 | // will be set to one. |
| 143 | wire ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value of |
| 144 | // ilu_log_err_ihb_pe_s. |
| 145 | wire ilu_log_err_spare3_p_hw_set; // Hardware set signal for |
| 146 | // ilu_log_err_spare3_p. When set ilu_log_err |
| 147 | // will be set to one. |
| 148 | wire ilu_log_err_spare3_p_hw_read; // This signal provides the current value of |
| 149 | // ilu_log_err_spare3_p. |
| 150 | wire ilu_log_err_spare2_p_hw_set; // Hardware set signal for |
| 151 | // ilu_log_err_spare2_p. When set ilu_log_err |
| 152 | // will be set to one. |
| 153 | wire ilu_log_err_spare2_p_hw_read; // This signal provides the current value of |
| 154 | // ilu_log_err_spare2_p. |
| 155 | wire ilu_log_err_spare1_p_hw_set; // Hardware set signal for |
| 156 | // ilu_log_err_spare1_p. When set ilu_log_err |
| 157 | // will be set to one. |
| 158 | wire ilu_log_err_spare1_p_hw_read; // This signal provides the current value of |
| 159 | // ilu_log_err_spare1_p. |
| 160 | wire ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for |
| 161 | // ilu_log_err_ihb_pe_p. When set ilu_log_err |
| 162 | // will be set to one. |
| 163 | wire ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value of |
| 164 | // ilu_log_err_ihb_pe_p. |
| 165 | |
| 166 | //==================================================================== |
| 167 | // Logic |
| 168 | //==================================================================== |
| 169 | |
| 170 | // synopsys translate_off |
| 171 | // verilint 123 off |
| 172 | // verilint 498 off |
| 173 | reg omni_ld; |
| 174 | reg [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH-1:0] omni_data; |
| 175 | reg omni_rw1c_alias; |
| 176 | reg omni_rw1s_alias; |
| 177 | |
| 178 | // vlint flag_unsynthesizable_initial off |
| 179 | initial |
| 180 | begin |
| 181 | omni_ld = 1'b0; |
| 182 | omni_data = `FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH'b0; |
| 183 | omni_rw1c_alias = 1'b0; |
| 184 | omni_rw1s_alias = 1'b0; |
| 185 | end// vlint flag_unsynthesizable_initial on |
| 186 | |
| 187 | // verilint 123 on |
| 188 | // verilint 498 on |
| 189 | // synopsys translate_on |
| 190 | |
| 191 | //----- Hardware Data Out Mux Assignments |
| 192 | assign ilu_log_err_spare3_s_hw_read= |
| 193 | ilu_log_err_csrbus_read_data [39]; |
| 194 | assign ilu_log_err_spare2_s_hw_read= |
| 195 | ilu_log_err_csrbus_read_data [38]; |
| 196 | assign ilu_log_err_spare1_s_hw_read= |
| 197 | ilu_log_err_csrbus_read_data [37]; |
| 198 | assign ilu_log_err_ihb_pe_s_hw_read= |
| 199 | ilu_log_err_csrbus_read_data [36]; |
| 200 | assign ilu_log_err_spare3_p_hw_read= |
| 201 | ilu_log_err_csrbus_read_data [7]; |
| 202 | assign ilu_log_err_spare2_p_hw_read= |
| 203 | ilu_log_err_csrbus_read_data [6]; |
| 204 | assign ilu_log_err_spare1_p_hw_read= |
| 205 | ilu_log_err_csrbus_read_data [5]; |
| 206 | assign ilu_log_err_ihb_pe_p_hw_read= |
| 207 | ilu_log_err_csrbus_read_data [4]; |
| 208 | |
| 209 | //==================================================================== |
| 210 | // Instantiation of entries |
| 211 | //==================================================================== |
| 212 | |
| 213 | //----- Entry 0 |
| 214 | dmu_ilu_cib_csr_ilu_log_err_entry ilu_log_err_0 |
| 215 | ( |
| 216 | // synopsys translate_off |
| 217 | .omni_ld (omni_ld), |
| 218 | .omni_data (omni_data), |
| 219 | .omni_rw1c_alias (omni_rw1c_alias), |
| 220 | .omni_rw1s_alias (omni_rw1s_alias), |
| 221 | // synopsys translate_on |
| 222 | .clk (clk), |
| 223 | .por_l (por_l), |
| 224 | .w_ld (ilu_log_err_w_ld), |
| 225 | .csrbus_wr_data (csrbus_wr_data), |
| 226 | .rw1c_alias (rw1c_alias), |
| 227 | .rw1s_alias (rw1s_alias), |
| 228 | .ilu_log_err_csrbus_read_data (ilu_log_err_csrbus_read_data), |
| 229 | .ilu_log_err_spare3_s_hw_set (ilu_log_err_spare3_s_hw_set), |
| 230 | .ilu_log_err_spare2_s_hw_set (ilu_log_err_spare2_s_hw_set), |
| 231 | .ilu_log_err_spare1_s_hw_set (ilu_log_err_spare1_s_hw_set), |
| 232 | .ilu_log_err_ihb_pe_s_hw_set (ilu_log_err_ihb_pe_s_hw_set), |
| 233 | .ilu_log_err_spare3_p_hw_set (ilu_log_err_spare3_p_hw_set), |
| 234 | .ilu_log_err_spare2_p_hw_set (ilu_log_err_spare2_p_hw_set), |
| 235 | .ilu_log_err_spare1_p_hw_set (ilu_log_err_spare1_p_hw_set), |
| 236 | .ilu_log_err_ihb_pe_p_hw_set (ilu_log_err_ihb_pe_p_hw_set) |
| 237 | ); |
| 238 | |
| 239 | endmodule // dmu_ilu_cib_csr_ilu_log_err |