| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_csr_pec_int_en.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_ilu_cib_csr_pec_int_en |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | pec_int_en_w_ld, |
| 40 | csrbus_wr_data, |
| 41 | pec_int_en_csrbus_read_data, |
| 42 | pec_int_en_pec_hw_read, |
| 43 | pec_int_en_pec_ilu_hw_read, |
| 44 | pec_int_en_pec_ue_hw_read, |
| 45 | pec_int_en_pec_ce_hw_read, |
| 46 | pec_int_en_pec_oe_hw_read |
| 47 | ); |
| 48 | |
| 49 | //==================================================================== |
| 50 | // Polarity declarations |
| 51 | //==================================================================== |
| 52 | input clk; // Clock |
| 53 | input rst_l; // Reset signal |
| 54 | input pec_int_en_w_ld; // SW load bus |
| 55 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 56 | output [`FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH-1:0] pec_int_en_csrbus_read_data; |
| 57 | // SW read data |
| 58 | output pec_int_en_pec_hw_read; // This signal provides the current value of |
| 59 | // pec_int_en_pec. |
| 60 | output pec_int_en_pec_ilu_hw_read; // This signal provides the current value of |
| 61 | // pec_int_en_pec_ilu. |
| 62 | output pec_int_en_pec_ue_hw_read; // This signal provides the current value of |
| 63 | // pec_int_en_pec_ue. |
| 64 | output pec_int_en_pec_ce_hw_read; // This signal provides the current value of |
| 65 | // pec_int_en_pec_ce. |
| 66 | output pec_int_en_pec_oe_hw_read; // This signal provides the current value of |
| 67 | // pec_int_en_pec_oe. |
| 68 | |
| 69 | //==================================================================== |
| 70 | // Type declarations |
| 71 | //==================================================================== |
| 72 | wire clk; // Clock |
| 73 | wire rst_l; // Reset signal |
| 74 | wire pec_int_en_w_ld; // SW load bus |
| 75 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 76 | wire [`FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH-1:0] pec_int_en_csrbus_read_data; |
| 77 | // SW read data |
| 78 | wire pec_int_en_pec_hw_read; // This signal provides the current value of |
| 79 | // pec_int_en_pec. |
| 80 | wire pec_int_en_pec_ilu_hw_read; // This signal provides the current value of |
| 81 | // pec_int_en_pec_ilu. |
| 82 | wire pec_int_en_pec_ue_hw_read; // This signal provides the current value of |
| 83 | // pec_int_en_pec_ue. |
| 84 | wire pec_int_en_pec_ce_hw_read; // This signal provides the current value of |
| 85 | // pec_int_en_pec_ce. |
| 86 | wire pec_int_en_pec_oe_hw_read; // This signal provides the current value of |
| 87 | // pec_int_en_pec_oe. |
| 88 | |
| 89 | //==================================================================== |
| 90 | // Logic |
| 91 | //==================================================================== |
| 92 | |
| 93 | // synopsys translate_off |
| 94 | // verilint 123 off |
| 95 | // verilint 498 off |
| 96 | reg omni_ld; |
| 97 | reg [`FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH-1:0] omni_data; |
| 98 | |
| 99 | // vlint flag_unsynthesizable_initial off |
| 100 | initial |
| 101 | begin |
| 102 | omni_ld = 1'b0; |
| 103 | omni_data = `FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH'b0; |
| 104 | end// vlint flag_unsynthesizable_initial on |
| 105 | |
| 106 | // verilint 123 on |
| 107 | // verilint 498 on |
| 108 | // synopsys translate_on |
| 109 | |
| 110 | //----- Hardware Data Out Mux Assignments |
| 111 | assign pec_int_en_pec_hw_read= |
| 112 | pec_int_en_csrbus_read_data [63]; |
| 113 | assign pec_int_en_pec_ilu_hw_read= |
| 114 | pec_int_en_csrbus_read_data [3]; |
| 115 | assign pec_int_en_pec_ue_hw_read= |
| 116 | pec_int_en_csrbus_read_data [2]; |
| 117 | assign pec_int_en_pec_ce_hw_read= |
| 118 | pec_int_en_csrbus_read_data [1]; |
| 119 | assign pec_int_en_pec_oe_hw_read= |
| 120 | pec_int_en_csrbus_read_data [0]; |
| 121 | |
| 122 | //==================================================================== |
| 123 | // Instantiation of entries |
| 124 | //==================================================================== |
| 125 | |
| 126 | //----- Entry 0 |
| 127 | dmu_ilu_cib_csr_pec_int_en_entry pec_int_en_0 |
| 128 | ( |
| 129 | // synopsys translate_off |
| 130 | .omni_ld (omni_ld), |
| 131 | .omni_data (omni_data), |
| 132 | // synopsys translate_on |
| 133 | .clk (clk), |
| 134 | .rst_l (rst_l), |
| 135 | .w_ld (pec_int_en_w_ld), |
| 136 | .csrbus_wr_data (csrbus_wr_data), |
| 137 | .pec_int_en_csrbus_read_data (pec_int_en_csrbus_read_data) |
| 138 | ); |
| 139 | |
| 140 | endmodule // dmu_ilu_cib_csr_pec_int_en |