| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_dbg.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_dbg ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // Block Level Selects and Output Ports |
| 43 | |
| 44 | cr2im_dbg_sel_a, |
| 45 | cr2im_dbg_sel_b, |
| 46 | |
| 47 | im2cr_dbg_a, |
| 48 | im2cr_dbg_b, |
| 49 | |
| 50 | // Block Level Selects and Output Ports |
| 51 | |
| 52 | |
| 53 | dbg2eqs_dbg_sel_a, |
| 54 | dbg2eqs_dbg_sel_b, |
| 55 | eqs2dbg_dbg_a, |
| 56 | eqs2dbg_dbg_b, |
| 57 | |
| 58 | dbg2gcs_dbg_sel_a, |
| 59 | dbg2gcs_dbg_sel_b, |
| 60 | gcs2dbg_dbg_a, |
| 61 | gcs2dbg_dbg_b, |
| 62 | |
| 63 | dbg2irs_dbg_sel_a, |
| 64 | dbg2irs_dbg_sel_b, |
| 65 | irs2dbg_dbg_a, |
| 66 | irs2dbg_dbg_b, |
| 67 | |
| 68 | dbg2iss_dbg_sel_a, |
| 69 | dbg2iss_dbg_sel_b, |
| 70 | iss2dbg_dbg_a, |
| 71 | iss2dbg_dbg_b, |
| 72 | |
| 73 | dbg2ors_dbg_sel_a, |
| 74 | dbg2ors_dbg_sel_b, |
| 75 | ors2dbg_dbg_a, |
| 76 | ors2dbg_dbg_b, |
| 77 | |
| 78 | dbg2rds_dbg_sel_a, |
| 79 | dbg2rds_dbg_sel_b, |
| 80 | rds2dbg_dbg_a, |
| 81 | rds2dbg_dbg_b, |
| 82 | |
| 83 | rss2dbg_dbg_a, |
| 84 | rss2dbg_dbg_b, |
| 85 | |
| 86 | dbg2scs_dbg_sel_a, |
| 87 | dbg2scs_dbg_sel_b, |
| 88 | scs2dbg_dbg_a, |
| 89 | scs2dbg_dbg_b, |
| 90 | |
| 91 | //Idle Checkers |
| 92 | |
| 93 | rds2dbg_idle, |
| 94 | ors2dbg_idle, |
| 95 | gcs2dbg_idle |
| 96 | |
| 97 | |
| 98 | ); |
| 99 | |
| 100 | |
| 101 | //############################################################################ |
| 102 | // PORT DECLARATIONS |
| 103 | //############################################################################ |
| 104 | |
| 105 | |
| 106 | //------------------------------------------------------------------------ |
| 107 | // Clock and Reset Signals |
| 108 | //------------------------------------------------------------------------ |
| 109 | input clk; |
| 110 | input rst_l; |
| 111 | |
| 112 | //------------------------------------------------------------------------ |
| 113 | // Block Level Selects and Output Ports |
| 114 | //------------------------------------------------------------------------ |
| 115 | |
| 116 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2im_dbg_sel_a; |
| 117 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2im_dbg_sel_b; |
| 118 | |
| 119 | output [`FIRE_DEBUG_WDTH-1:0] im2cr_dbg_a; |
| 120 | output [`FIRE_DEBUG_WDTH-1:0] im2cr_dbg_b; |
| 121 | |
| 122 | |
| 123 | //------------------------------------------------------------------------ |
| 124 | // Block Level Selects and Output Ports |
| 125 | //------------------------------------------------------------------------ |
| 126 | |
| 127 | output [2:0] dbg2eqs_dbg_sel_a; |
| 128 | output [2:0] dbg2eqs_dbg_sel_b; |
| 129 | |
| 130 | input [`FIRE_DEBUG_WDTH-1:0] eqs2dbg_dbg_a; |
| 131 | input [`FIRE_DEBUG_WDTH-1:0] eqs2dbg_dbg_b; |
| 132 | |
| 133 | output [2:0] dbg2gcs_dbg_sel_a; |
| 134 | output [2:0] dbg2gcs_dbg_sel_b; |
| 135 | input [`FIRE_DEBUG_WDTH-1:0] gcs2dbg_dbg_a; |
| 136 | input [`FIRE_DEBUG_WDTH-1:0] gcs2dbg_dbg_b; |
| 137 | |
| 138 | output [2:0] dbg2irs_dbg_sel_a; |
| 139 | output [2:0] dbg2irs_dbg_sel_b; |
| 140 | input [`FIRE_DEBUG_WDTH-1:0] irs2dbg_dbg_a; |
| 141 | input [`FIRE_DEBUG_WDTH-1:0] irs2dbg_dbg_b; |
| 142 | |
| 143 | output [2:0] dbg2iss_dbg_sel_a; |
| 144 | output [2:0] dbg2iss_dbg_sel_b; |
| 145 | input [`FIRE_DEBUG_WDTH-1:0] iss2dbg_dbg_a; |
| 146 | input [`FIRE_DEBUG_WDTH-1:0] iss2dbg_dbg_b; |
| 147 | |
| 148 | output [2:0] dbg2ors_dbg_sel_a; |
| 149 | output [2:0] dbg2ors_dbg_sel_b; |
| 150 | input [`FIRE_DEBUG_WDTH-1:0] ors2dbg_dbg_a; |
| 151 | input [`FIRE_DEBUG_WDTH-1:0] ors2dbg_dbg_b; |
| 152 | |
| 153 | output [2:0] dbg2rds_dbg_sel_a; |
| 154 | output [2:0] dbg2rds_dbg_sel_b; |
| 155 | input [`FIRE_DEBUG_WDTH-1:0] rds2dbg_dbg_a; |
| 156 | input [`FIRE_DEBUG_WDTH-1:0] rds2dbg_dbg_b; |
| 157 | |
| 158 | input [`FIRE_DEBUG_WDTH-1:0] rss2dbg_dbg_a; |
| 159 | input [`FIRE_DEBUG_WDTH-1:0] rss2dbg_dbg_b; |
| 160 | |
| 161 | output [2:0] dbg2scs_dbg_sel_a; |
| 162 | output [2:0] dbg2scs_dbg_sel_b; |
| 163 | input [`FIRE_DEBUG_WDTH-1:0] scs2dbg_dbg_a; |
| 164 | input [`FIRE_DEBUG_WDTH-1:0] scs2dbg_dbg_b; |
| 165 | |
| 166 | //------------------------------------------------------------------------ |
| 167 | // Idle Checkers |
| 168 | //------------------------------------------------------------------------ |
| 169 | |
| 170 | input rds2dbg_idle; |
| 171 | input ors2dbg_idle; |
| 172 | input gcs2dbg_idle; |
| 173 | |
| 174 | //############################################################################ |
| 175 | // SIGNAL DECLARATIONS |
| 176 | //############################################################################ |
| 177 | |
| 178 | //************************************************** |
| 179 | // Wires |
| 180 | //************************************************** |
| 181 | wire imu_idle; |
| 182 | |
| 183 | //************************************************** |
| 184 | // Registers that Are Not Flops |
| 185 | //************************************************** |
| 186 | reg [`FIRE_DEBUG_WDTH-1:0] n_im2cr_dbg_a; |
| 187 | reg [`FIRE_DEBUG_WDTH-1:0] n_im2cr_dbg_b; |
| 188 | |
| 189 | |
| 190 | //************************************************** |
| 191 | // Registers that Are Flops |
| 192 | //************************************************** |
| 193 | reg [`FIRE_DEBUG_WDTH-1:0] im2cr_dbg_a; |
| 194 | reg [`FIRE_DEBUG_WDTH-1:0] im2cr_dbg_b; |
| 195 | |
| 196 | //############################################################################ |
| 197 | // ZERO IN CHECKERS |
| 198 | //############################################################################ |
| 199 | |
| 200 | |
| 201 | |
| 202 | //############################################################################ |
| 203 | // COMBINATIONAL LOGIC |
| 204 | //############################################################################ |
| 205 | |
| 206 | assign dbg2eqs_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 207 | assign dbg2eqs_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 208 | |
| 209 | assign dbg2gcs_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 210 | assign dbg2gcs_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 211 | |
| 212 | assign dbg2irs_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 213 | assign dbg2irs_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 214 | |
| 215 | assign dbg2iss_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 216 | assign dbg2iss_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 217 | |
| 218 | assign dbg2ors_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 219 | assign dbg2ors_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 220 | |
| 221 | assign dbg2rds_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 222 | assign dbg2rds_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 223 | |
| 224 | assign dbg2scs_dbg_sel_a = cr2im_dbg_sel_a[2:0]; |
| 225 | assign dbg2scs_dbg_sel_b = cr2im_dbg_sel_b[2:0]; |
| 226 | |
| 227 | |
| 228 | always @ (cr2im_dbg_sel_a or eqs2dbg_dbg_a or gcs2dbg_dbg_a or irs2dbg_dbg_a or iss2dbg_dbg_a or |
| 229 | ors2dbg_dbg_a or rds2dbg_dbg_a or rss2dbg_dbg_a or scs2dbg_dbg_a or imu_idle) |
| 230 | begin |
| 231 | case (cr2im_dbg_sel_a[5:3]) // synopsys infer_mux |
| 232 | 3'b000: n_im2cr_dbg_a = eqs2dbg_dbg_a; |
| 233 | 3'b001: n_im2cr_dbg_a = gcs2dbg_dbg_a; |
| 234 | 3'b010: n_im2cr_dbg_a = irs2dbg_dbg_a; |
| 235 | 3'b011: n_im2cr_dbg_a = iss2dbg_dbg_a; |
| 236 | 3'b100: n_im2cr_dbg_a = ors2dbg_dbg_a; |
| 237 | 3'b101: n_im2cr_dbg_a = rds2dbg_dbg_a; |
| 238 | 3'b110: n_im2cr_dbg_a = {(rss2dbg_dbg_a[7] | imu_idle), rss2dbg_dbg_a[6:0]}; |
| 239 | 3'b111: n_im2cr_dbg_a = scs2dbg_dbg_a; |
| 240 | endcase |
| 241 | end |
| 242 | |
| 243 | |
| 244 | always @ (cr2im_dbg_sel_b or eqs2dbg_dbg_b or gcs2dbg_dbg_b or irs2dbg_dbg_b or iss2dbg_dbg_b or |
| 245 | ors2dbg_dbg_b or rds2dbg_dbg_b or rss2dbg_dbg_b or scs2dbg_dbg_b or imu_idle) |
| 246 | begin |
| 247 | case (cr2im_dbg_sel_b[5:3]) // synopsys infer_mux |
| 248 | 3'b000: n_im2cr_dbg_b = eqs2dbg_dbg_b; |
| 249 | 3'b001: n_im2cr_dbg_b = gcs2dbg_dbg_b; |
| 250 | 3'b010: n_im2cr_dbg_b = irs2dbg_dbg_b; |
| 251 | 3'b011: n_im2cr_dbg_b = iss2dbg_dbg_b; |
| 252 | 3'b100: n_im2cr_dbg_b = ors2dbg_dbg_b; |
| 253 | 3'b101: n_im2cr_dbg_b = rds2dbg_dbg_b; |
| 254 | 3'b110: n_im2cr_dbg_b = {(rss2dbg_dbg_b[7] | imu_idle), rss2dbg_dbg_b[6:0]}; |
| 255 | 3'b111: n_im2cr_dbg_b = scs2dbg_dbg_b; |
| 256 | endcase |
| 257 | end |
| 258 | |
| 259 | |
| 260 | always @ (posedge clk) |
| 261 | begin |
| 262 | if (!rst_l) begin |
| 263 | im2cr_dbg_a <= 8'b0; |
| 264 | im2cr_dbg_b <= 8'b0; |
| 265 | end |
| 266 | else begin |
| 267 | im2cr_dbg_a <= n_im2cr_dbg_a; |
| 268 | im2cr_dbg_b <= n_im2cr_dbg_b; |
| 269 | end |
| 270 | end |
| 271 | //------------------------------------------------------------------------ |
| 272 | // Idle Checkers |
| 273 | //------------------------------------------------------------------------ |
| 274 | assign imu_idle = rds2dbg_idle & ors2dbg_idle & gcs2dbg_idle; |
| 275 | |
| 276 | //############################################################################ |
| 277 | // SEQUENTIAL LOGIC |
| 278 | //############################################################################ |
| 279 | |
| 280 | |
| 281 | //############################################################################ |
| 282 | // MODULE INSTANTIATIONS |
| 283 | //############################################################################ |
| 284 | |
| 285 | |
| 286 | endmodule |
| 287 | |
| 288 | |
| 289 | |
| 290 | |
| 291 | |