| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_eqs_csr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_eqs_csr |
| 36 | ( |
| 37 | clk, |
| 38 | csrbus_addr, |
| 39 | csrbus_wr_data, |
| 40 | csrbus_wr, |
| 41 | csrbus_valid, |
| 42 | csrbus_mapped, |
| 43 | csrbus_done, |
| 44 | csrbus_read_data, |
| 45 | rst_l, |
| 46 | csrbus_src_bus, |
| 47 | csrbus_acc_vio, |
| 48 | instance_id, |
| 49 | ext_wr, |
| 50 | eq_base_address_address_hw_read, |
| 51 | eq_ctrl_set_enoverr_ext_wr_data, |
| 52 | eq_ctrl_set_en_ext_wr_data, |
| 53 | eq_ctrl_set_ext_select_0, |
| 54 | eq_ctrl_set_ext_select_1, |
| 55 | eq_ctrl_set_ext_select_2, |
| 56 | eq_ctrl_set_ext_select_3, |
| 57 | eq_ctrl_set_ext_select_4, |
| 58 | eq_ctrl_set_ext_select_5, |
| 59 | eq_ctrl_set_ext_select_6, |
| 60 | eq_ctrl_set_ext_select_7, |
| 61 | eq_ctrl_set_ext_select_8, |
| 62 | eq_ctrl_set_ext_select_9, |
| 63 | eq_ctrl_set_ext_select_10, |
| 64 | eq_ctrl_set_ext_select_11, |
| 65 | eq_ctrl_set_ext_select_12, |
| 66 | eq_ctrl_set_ext_select_13, |
| 67 | eq_ctrl_set_ext_select_14, |
| 68 | eq_ctrl_set_ext_select_15, |
| 69 | eq_ctrl_set_ext_select_16, |
| 70 | eq_ctrl_set_ext_select_17, |
| 71 | eq_ctrl_set_ext_select_18, |
| 72 | eq_ctrl_set_ext_select_19, |
| 73 | eq_ctrl_set_ext_select_20, |
| 74 | eq_ctrl_set_ext_select_21, |
| 75 | eq_ctrl_set_ext_select_22, |
| 76 | eq_ctrl_set_ext_select_23, |
| 77 | eq_ctrl_set_ext_select_24, |
| 78 | eq_ctrl_set_ext_select_25, |
| 79 | eq_ctrl_set_ext_select_26, |
| 80 | eq_ctrl_set_ext_select_27, |
| 81 | eq_ctrl_set_ext_select_28, |
| 82 | eq_ctrl_set_ext_select_29, |
| 83 | eq_ctrl_set_ext_select_30, |
| 84 | eq_ctrl_set_ext_select_31, |
| 85 | eq_ctrl_set_ext_select_32, |
| 86 | eq_ctrl_set_ext_select_33, |
| 87 | eq_ctrl_set_ext_select_34, |
| 88 | eq_ctrl_set_ext_select_35, |
| 89 | eq_ctrl_clr_coverr_ext_wr_data, |
| 90 | eq_ctrl_clr_e2i_ext_wr_data, |
| 91 | eq_ctrl_clr_dis_ext_wr_data, |
| 92 | eq_ctrl_clr_ext_select_0, |
| 93 | eq_ctrl_clr_ext_select_1, |
| 94 | eq_ctrl_clr_ext_select_2, |
| 95 | eq_ctrl_clr_ext_select_3, |
| 96 | eq_ctrl_clr_ext_select_4, |
| 97 | eq_ctrl_clr_ext_select_5, |
| 98 | eq_ctrl_clr_ext_select_6, |
| 99 | eq_ctrl_clr_ext_select_7, |
| 100 | eq_ctrl_clr_ext_select_8, |
| 101 | eq_ctrl_clr_ext_select_9, |
| 102 | eq_ctrl_clr_ext_select_10, |
| 103 | eq_ctrl_clr_ext_select_11, |
| 104 | eq_ctrl_clr_ext_select_12, |
| 105 | eq_ctrl_clr_ext_select_13, |
| 106 | eq_ctrl_clr_ext_select_14, |
| 107 | eq_ctrl_clr_ext_select_15, |
| 108 | eq_ctrl_clr_ext_select_16, |
| 109 | eq_ctrl_clr_ext_select_17, |
| 110 | eq_ctrl_clr_ext_select_18, |
| 111 | eq_ctrl_clr_ext_select_19, |
| 112 | eq_ctrl_clr_ext_select_20, |
| 113 | eq_ctrl_clr_ext_select_21, |
| 114 | eq_ctrl_clr_ext_select_22, |
| 115 | eq_ctrl_clr_ext_select_23, |
| 116 | eq_ctrl_clr_ext_select_24, |
| 117 | eq_ctrl_clr_ext_select_25, |
| 118 | eq_ctrl_clr_ext_select_26, |
| 119 | eq_ctrl_clr_ext_select_27, |
| 120 | eq_ctrl_clr_ext_select_28, |
| 121 | eq_ctrl_clr_ext_select_29, |
| 122 | eq_ctrl_clr_ext_select_30, |
| 123 | eq_ctrl_clr_ext_select_31, |
| 124 | eq_ctrl_clr_ext_select_32, |
| 125 | eq_ctrl_clr_ext_select_33, |
| 126 | eq_ctrl_clr_ext_select_34, |
| 127 | eq_ctrl_clr_ext_select_35, |
| 128 | eq_state_state_ext_read_data_0, |
| 129 | eq_state_state_ext_read_data_1, |
| 130 | eq_state_state_ext_read_data_2, |
| 131 | eq_state_state_ext_read_data_3, |
| 132 | eq_state_state_ext_read_data_4, |
| 133 | eq_state_state_ext_read_data_5, |
| 134 | eq_state_state_ext_read_data_6, |
| 135 | eq_state_state_ext_read_data_7, |
| 136 | eq_state_state_ext_read_data_8, |
| 137 | eq_state_state_ext_read_data_9, |
| 138 | eq_state_state_ext_read_data_10, |
| 139 | eq_state_state_ext_read_data_11, |
| 140 | eq_state_state_ext_read_data_12, |
| 141 | eq_state_state_ext_read_data_13, |
| 142 | eq_state_state_ext_read_data_14, |
| 143 | eq_state_state_ext_read_data_15, |
| 144 | eq_state_state_ext_read_data_16, |
| 145 | eq_state_state_ext_read_data_17, |
| 146 | eq_state_state_ext_read_data_18, |
| 147 | eq_state_state_ext_read_data_19, |
| 148 | eq_state_state_ext_read_data_20, |
| 149 | eq_state_state_ext_read_data_21, |
| 150 | eq_state_state_ext_read_data_22, |
| 151 | eq_state_state_ext_read_data_23, |
| 152 | eq_state_state_ext_read_data_24, |
| 153 | eq_state_state_ext_read_data_25, |
| 154 | eq_state_state_ext_read_data_26, |
| 155 | eq_state_state_ext_read_data_27, |
| 156 | eq_state_state_ext_read_data_28, |
| 157 | eq_state_state_ext_read_data_29, |
| 158 | eq_state_state_ext_read_data_30, |
| 159 | eq_state_state_ext_read_data_31, |
| 160 | eq_state_state_ext_read_data_32, |
| 161 | eq_state_state_ext_read_data_33, |
| 162 | eq_state_state_ext_read_data_34, |
| 163 | eq_state_state_ext_read_data_35, |
| 164 | eq_tail_overr_hw_ld_0, |
| 165 | eq_tail_overr_hw_ld_1, |
| 166 | eq_tail_overr_hw_ld_2, |
| 167 | eq_tail_overr_hw_ld_3, |
| 168 | eq_tail_overr_hw_ld_4, |
| 169 | eq_tail_overr_hw_ld_5, |
| 170 | eq_tail_overr_hw_ld_6, |
| 171 | eq_tail_overr_hw_ld_7, |
| 172 | eq_tail_overr_hw_ld_8, |
| 173 | eq_tail_overr_hw_ld_9, |
| 174 | eq_tail_overr_hw_ld_10, |
| 175 | eq_tail_overr_hw_ld_11, |
| 176 | eq_tail_overr_hw_ld_12, |
| 177 | eq_tail_overr_hw_ld_13, |
| 178 | eq_tail_overr_hw_ld_14, |
| 179 | eq_tail_overr_hw_ld_15, |
| 180 | eq_tail_overr_hw_ld_16, |
| 181 | eq_tail_overr_hw_ld_17, |
| 182 | eq_tail_overr_hw_ld_18, |
| 183 | eq_tail_overr_hw_ld_19, |
| 184 | eq_tail_overr_hw_ld_20, |
| 185 | eq_tail_overr_hw_ld_21, |
| 186 | eq_tail_overr_hw_ld_22, |
| 187 | eq_tail_overr_hw_ld_23, |
| 188 | eq_tail_overr_hw_ld_24, |
| 189 | eq_tail_overr_hw_ld_25, |
| 190 | eq_tail_overr_hw_ld_26, |
| 191 | eq_tail_overr_hw_ld_27, |
| 192 | eq_tail_overr_hw_ld_28, |
| 193 | eq_tail_overr_hw_ld_29, |
| 194 | eq_tail_overr_hw_ld_30, |
| 195 | eq_tail_overr_hw_ld_31, |
| 196 | eq_tail_overr_hw_ld_32, |
| 197 | eq_tail_overr_hw_ld_33, |
| 198 | eq_tail_overr_hw_ld_34, |
| 199 | eq_tail_overr_hw_ld_35, |
| 200 | eq_tail_overr_hw_write_0, |
| 201 | eq_tail_overr_hw_write_1, |
| 202 | eq_tail_overr_hw_write_2, |
| 203 | eq_tail_overr_hw_write_3, |
| 204 | eq_tail_overr_hw_write_4, |
| 205 | eq_tail_overr_hw_write_5, |
| 206 | eq_tail_overr_hw_write_6, |
| 207 | eq_tail_overr_hw_write_7, |
| 208 | eq_tail_overr_hw_write_8, |
| 209 | eq_tail_overr_hw_write_9, |
| 210 | eq_tail_overr_hw_write_10, |
| 211 | eq_tail_overr_hw_write_11, |
| 212 | eq_tail_overr_hw_write_12, |
| 213 | eq_tail_overr_hw_write_13, |
| 214 | eq_tail_overr_hw_write_14, |
| 215 | eq_tail_overr_hw_write_15, |
| 216 | eq_tail_overr_hw_write_16, |
| 217 | eq_tail_overr_hw_write_17, |
| 218 | eq_tail_overr_hw_write_18, |
| 219 | eq_tail_overr_hw_write_19, |
| 220 | eq_tail_overr_hw_write_20, |
| 221 | eq_tail_overr_hw_write_21, |
| 222 | eq_tail_overr_hw_write_22, |
| 223 | eq_tail_overr_hw_write_23, |
| 224 | eq_tail_overr_hw_write_24, |
| 225 | eq_tail_overr_hw_write_25, |
| 226 | eq_tail_overr_hw_write_26, |
| 227 | eq_tail_overr_hw_write_27, |
| 228 | eq_tail_overr_hw_write_28, |
| 229 | eq_tail_overr_hw_write_29, |
| 230 | eq_tail_overr_hw_write_30, |
| 231 | eq_tail_overr_hw_write_31, |
| 232 | eq_tail_overr_hw_write_32, |
| 233 | eq_tail_overr_hw_write_33, |
| 234 | eq_tail_overr_hw_write_34, |
| 235 | eq_tail_overr_hw_write_35, |
| 236 | eq_tail_tail_hw_ld_0, |
| 237 | eq_tail_tail_hw_ld_1, |
| 238 | eq_tail_tail_hw_ld_2, |
| 239 | eq_tail_tail_hw_ld_3, |
| 240 | eq_tail_tail_hw_ld_4, |
| 241 | eq_tail_tail_hw_ld_5, |
| 242 | eq_tail_tail_hw_ld_6, |
| 243 | eq_tail_tail_hw_ld_7, |
| 244 | eq_tail_tail_hw_ld_8, |
| 245 | eq_tail_tail_hw_ld_9, |
| 246 | eq_tail_tail_hw_ld_10, |
| 247 | eq_tail_tail_hw_ld_11, |
| 248 | eq_tail_tail_hw_ld_12, |
| 249 | eq_tail_tail_hw_ld_13, |
| 250 | eq_tail_tail_hw_ld_14, |
| 251 | eq_tail_tail_hw_ld_15, |
| 252 | eq_tail_tail_hw_ld_16, |
| 253 | eq_tail_tail_hw_ld_17, |
| 254 | eq_tail_tail_hw_ld_18, |
| 255 | eq_tail_tail_hw_ld_19, |
| 256 | eq_tail_tail_hw_ld_20, |
| 257 | eq_tail_tail_hw_ld_21, |
| 258 | eq_tail_tail_hw_ld_22, |
| 259 | eq_tail_tail_hw_ld_23, |
| 260 | eq_tail_tail_hw_ld_24, |
| 261 | eq_tail_tail_hw_ld_25, |
| 262 | eq_tail_tail_hw_ld_26, |
| 263 | eq_tail_tail_hw_ld_27, |
| 264 | eq_tail_tail_hw_ld_28, |
| 265 | eq_tail_tail_hw_ld_29, |
| 266 | eq_tail_tail_hw_ld_30, |
| 267 | eq_tail_tail_hw_ld_31, |
| 268 | eq_tail_tail_hw_ld_32, |
| 269 | eq_tail_tail_hw_ld_33, |
| 270 | eq_tail_tail_hw_ld_34, |
| 271 | eq_tail_tail_hw_ld_35, |
| 272 | eq_tail_tail_hw_write_0, |
| 273 | eq_tail_tail_hw_write_1, |
| 274 | eq_tail_tail_hw_write_2, |
| 275 | eq_tail_tail_hw_write_3, |
| 276 | eq_tail_tail_hw_write_4, |
| 277 | eq_tail_tail_hw_write_5, |
| 278 | eq_tail_tail_hw_write_6, |
| 279 | eq_tail_tail_hw_write_7, |
| 280 | eq_tail_tail_hw_write_8, |
| 281 | eq_tail_tail_hw_write_9, |
| 282 | eq_tail_tail_hw_write_10, |
| 283 | eq_tail_tail_hw_write_11, |
| 284 | eq_tail_tail_hw_write_12, |
| 285 | eq_tail_tail_hw_write_13, |
| 286 | eq_tail_tail_hw_write_14, |
| 287 | eq_tail_tail_hw_write_15, |
| 288 | eq_tail_tail_hw_write_16, |
| 289 | eq_tail_tail_hw_write_17, |
| 290 | eq_tail_tail_hw_write_18, |
| 291 | eq_tail_tail_hw_write_19, |
| 292 | eq_tail_tail_hw_write_20, |
| 293 | eq_tail_tail_hw_write_21, |
| 294 | eq_tail_tail_hw_write_22, |
| 295 | eq_tail_tail_hw_write_23, |
| 296 | eq_tail_tail_hw_write_24, |
| 297 | eq_tail_tail_hw_write_25, |
| 298 | eq_tail_tail_hw_write_26, |
| 299 | eq_tail_tail_hw_write_27, |
| 300 | eq_tail_tail_hw_write_28, |
| 301 | eq_tail_tail_hw_write_29, |
| 302 | eq_tail_tail_hw_write_30, |
| 303 | eq_tail_tail_hw_write_31, |
| 304 | eq_tail_tail_hw_write_32, |
| 305 | eq_tail_tail_hw_write_33, |
| 306 | eq_tail_tail_hw_write_34, |
| 307 | eq_tail_tail_hw_write_35, |
| 308 | eq_tail_tail_hw_read_0, |
| 309 | eq_tail_tail_hw_read_1, |
| 310 | eq_tail_tail_hw_read_2, |
| 311 | eq_tail_tail_hw_read_3, |
| 312 | eq_tail_tail_hw_read_4, |
| 313 | eq_tail_tail_hw_read_5, |
| 314 | eq_tail_tail_hw_read_6, |
| 315 | eq_tail_tail_hw_read_7, |
| 316 | eq_tail_tail_hw_read_8, |
| 317 | eq_tail_tail_hw_read_9, |
| 318 | eq_tail_tail_hw_read_10, |
| 319 | eq_tail_tail_hw_read_11, |
| 320 | eq_tail_tail_hw_read_12, |
| 321 | eq_tail_tail_hw_read_13, |
| 322 | eq_tail_tail_hw_read_14, |
| 323 | eq_tail_tail_hw_read_15, |
| 324 | eq_tail_tail_hw_read_16, |
| 325 | eq_tail_tail_hw_read_17, |
| 326 | eq_tail_tail_hw_read_18, |
| 327 | eq_tail_tail_hw_read_19, |
| 328 | eq_tail_tail_hw_read_20, |
| 329 | eq_tail_tail_hw_read_21, |
| 330 | eq_tail_tail_hw_read_22, |
| 331 | eq_tail_tail_hw_read_23, |
| 332 | eq_tail_tail_hw_read_24, |
| 333 | eq_tail_tail_hw_read_25, |
| 334 | eq_tail_tail_hw_read_26, |
| 335 | eq_tail_tail_hw_read_27, |
| 336 | eq_tail_tail_hw_read_28, |
| 337 | eq_tail_tail_hw_read_29, |
| 338 | eq_tail_tail_hw_read_30, |
| 339 | eq_tail_tail_hw_read_31, |
| 340 | eq_tail_tail_hw_read_32, |
| 341 | eq_tail_tail_hw_read_33, |
| 342 | eq_tail_tail_hw_read_34, |
| 343 | eq_tail_tail_hw_read_35, |
| 344 | eq_head_head_hw_read_0, |
| 345 | eq_head_head_hw_read_1, |
| 346 | eq_head_head_hw_read_2, |
| 347 | eq_head_head_hw_read_3, |
| 348 | eq_head_head_hw_read_4, |
| 349 | eq_head_head_hw_read_5, |
| 350 | eq_head_head_hw_read_6, |
| 351 | eq_head_head_hw_read_7, |
| 352 | eq_head_head_hw_read_8, |
| 353 | eq_head_head_hw_read_9, |
| 354 | eq_head_head_hw_read_10, |
| 355 | eq_head_head_hw_read_11, |
| 356 | eq_head_head_hw_read_12, |
| 357 | eq_head_head_hw_read_13, |
| 358 | eq_head_head_hw_read_14, |
| 359 | eq_head_head_hw_read_15, |
| 360 | eq_head_head_hw_read_16, |
| 361 | eq_head_head_hw_read_17, |
| 362 | eq_head_head_hw_read_18, |
| 363 | eq_head_head_hw_read_19, |
| 364 | eq_head_head_hw_read_20, |
| 365 | eq_head_head_hw_read_21, |
| 366 | eq_head_head_hw_read_22, |
| 367 | eq_head_head_hw_read_23, |
| 368 | eq_head_head_hw_read_24, |
| 369 | eq_head_head_hw_read_25, |
| 370 | eq_head_head_hw_read_26, |
| 371 | eq_head_head_hw_read_27, |
| 372 | eq_head_head_hw_read_28, |
| 373 | eq_head_head_hw_read_29, |
| 374 | eq_head_head_hw_read_30, |
| 375 | eq_head_head_hw_read_31, |
| 376 | eq_head_head_hw_read_32, |
| 377 | eq_head_head_hw_read_33, |
| 378 | eq_head_head_hw_read_34, |
| 379 | eq_head_head_hw_read_35 |
| 380 | ); |
| 381 | |
| 382 | //==================================================== |
| 383 | // Polarity declarations |
| 384 | //==================================================== |
| 385 | input clk; // Clock signal |
| 386 | input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus |
| 387 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 388 | input csrbus_wr; // Read/Write signal |
| 389 | input csrbus_valid; // Valid address |
| 390 | output csrbus_mapped; // Address is mapped |
| 391 | output csrbus_done; // Operation is done |
| 392 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus |
| 393 | input rst_l; // Reset signal |
| 394 | input [1:0] csrbus_src_bus; // Source bus |
| 395 | output csrbus_acc_vio; // Violation signal |
| 396 | input instance_id; // Instance ID |
| 397 | output ext_wr; // When one, csr operation is a write. When zero, operation is a |
| 398 | // read. |
| 399 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_INT_SLC] eq_base_address_address_hw_read; |
| 400 | // This signal provides the current value of eq_base_address_address. |
| 401 | output eq_ctrl_set_enoverr_ext_wr_data; // Provides SW write data for external |
| 402 | // register "eq_ctrl_set", field |
| 403 | // "enoverr" |
| 404 | output eq_ctrl_set_en_ext_wr_data; // Provides SW write data for external |
| 405 | // register "eq_ctrl_set", field "en" |
| 406 | output eq_ctrl_set_ext_select_0; // When set, register eq_ctrl_set is selected. |
| 407 | // This signal is a pulse. |
| 408 | output eq_ctrl_set_ext_select_1; // When set, register eq_ctrl_set is selected. |
| 409 | // This signal is a pulse. |
| 410 | output eq_ctrl_set_ext_select_2; // When set, register eq_ctrl_set is selected. |
| 411 | // This signal is a pulse. |
| 412 | output eq_ctrl_set_ext_select_3; // When set, register eq_ctrl_set is selected. |
| 413 | // This signal is a pulse. |
| 414 | output eq_ctrl_set_ext_select_4; // When set, register eq_ctrl_set is selected. |
| 415 | // This signal is a pulse. |
| 416 | output eq_ctrl_set_ext_select_5; // When set, register eq_ctrl_set is selected. |
| 417 | // This signal is a pulse. |
| 418 | output eq_ctrl_set_ext_select_6; // When set, register eq_ctrl_set is selected. |
| 419 | // This signal is a pulse. |
| 420 | output eq_ctrl_set_ext_select_7; // When set, register eq_ctrl_set is selected. |
| 421 | // This signal is a pulse. |
| 422 | output eq_ctrl_set_ext_select_8; // When set, register eq_ctrl_set is selected. |
| 423 | // This signal is a pulse. |
| 424 | output eq_ctrl_set_ext_select_9; // When set, register eq_ctrl_set is selected. |
| 425 | // This signal is a pulse. |
| 426 | output eq_ctrl_set_ext_select_10; // When set, register eq_ctrl_set is |
| 427 | // selected. This signal is a pulse. |
| 428 | output eq_ctrl_set_ext_select_11; // When set, register eq_ctrl_set is |
| 429 | // selected. This signal is a pulse. |
| 430 | output eq_ctrl_set_ext_select_12; // When set, register eq_ctrl_set is |
| 431 | // selected. This signal is a pulse. |
| 432 | output eq_ctrl_set_ext_select_13; // When set, register eq_ctrl_set is |
| 433 | // selected. This signal is a pulse. |
| 434 | output eq_ctrl_set_ext_select_14; // When set, register eq_ctrl_set is |
| 435 | // selected. This signal is a pulse. |
| 436 | output eq_ctrl_set_ext_select_15; // When set, register eq_ctrl_set is |
| 437 | // selected. This signal is a pulse. |
| 438 | output eq_ctrl_set_ext_select_16; // When set, register eq_ctrl_set is |
| 439 | // selected. This signal is a pulse. |
| 440 | output eq_ctrl_set_ext_select_17; // When set, register eq_ctrl_set is |
| 441 | // selected. This signal is a pulse. |
| 442 | output eq_ctrl_set_ext_select_18; // When set, register eq_ctrl_set is |
| 443 | // selected. This signal is a pulse. |
| 444 | output eq_ctrl_set_ext_select_19; // When set, register eq_ctrl_set is |
| 445 | // selected. This signal is a pulse. |
| 446 | output eq_ctrl_set_ext_select_20; // When set, register eq_ctrl_set is |
| 447 | // selected. This signal is a pulse. |
| 448 | output eq_ctrl_set_ext_select_21; // When set, register eq_ctrl_set is |
| 449 | // selected. This signal is a pulse. |
| 450 | output eq_ctrl_set_ext_select_22; // When set, register eq_ctrl_set is |
| 451 | // selected. This signal is a pulse. |
| 452 | output eq_ctrl_set_ext_select_23; // When set, register eq_ctrl_set is |
| 453 | // selected. This signal is a pulse. |
| 454 | output eq_ctrl_set_ext_select_24; // When set, register eq_ctrl_set is |
| 455 | // selected. This signal is a pulse. |
| 456 | output eq_ctrl_set_ext_select_25; // When set, register eq_ctrl_set is |
| 457 | // selected. This signal is a pulse. |
| 458 | output eq_ctrl_set_ext_select_26; // When set, register eq_ctrl_set is |
| 459 | // selected. This signal is a pulse. |
| 460 | output eq_ctrl_set_ext_select_27; // When set, register eq_ctrl_set is |
| 461 | // selected. This signal is a pulse. |
| 462 | output eq_ctrl_set_ext_select_28; // When set, register eq_ctrl_set is |
| 463 | // selected. This signal is a pulse. |
| 464 | output eq_ctrl_set_ext_select_29; // When set, register eq_ctrl_set is |
| 465 | // selected. This signal is a pulse. |
| 466 | output eq_ctrl_set_ext_select_30; // When set, register eq_ctrl_set is |
| 467 | // selected. This signal is a pulse. |
| 468 | output eq_ctrl_set_ext_select_31; // When set, register eq_ctrl_set is |
| 469 | // selected. This signal is a pulse. |
| 470 | output eq_ctrl_set_ext_select_32; // When set, register eq_ctrl_set is |
| 471 | // selected. This signal is a pulse. |
| 472 | output eq_ctrl_set_ext_select_33; // When set, register eq_ctrl_set is |
| 473 | // selected. This signal is a pulse. |
| 474 | output eq_ctrl_set_ext_select_34; // When set, register eq_ctrl_set is |
| 475 | // selected. This signal is a pulse. |
| 476 | output eq_ctrl_set_ext_select_35; // When set, register eq_ctrl_set is |
| 477 | // selected. This signal is a pulse. |
| 478 | output eq_ctrl_clr_coverr_ext_wr_data; // Provides SW write data for external |
| 479 | // register "eq_ctrl_clr", field |
| 480 | // "coverr" |
| 481 | output eq_ctrl_clr_e2i_ext_wr_data; // Provides SW write data for external |
| 482 | // register "eq_ctrl_clr", field "e2i" |
| 483 | output eq_ctrl_clr_dis_ext_wr_data; // Provides SW write data for external |
| 484 | // register "eq_ctrl_clr", field "dis" |
| 485 | output eq_ctrl_clr_ext_select_0; // When set, register eq_ctrl_clr is selected. |
| 486 | // This signal is a pulse. |
| 487 | output eq_ctrl_clr_ext_select_1; // When set, register eq_ctrl_clr is selected. |
| 488 | // This signal is a pulse. |
| 489 | output eq_ctrl_clr_ext_select_2; // When set, register eq_ctrl_clr is selected. |
| 490 | // This signal is a pulse. |
| 491 | output eq_ctrl_clr_ext_select_3; // When set, register eq_ctrl_clr is selected. |
| 492 | // This signal is a pulse. |
| 493 | output eq_ctrl_clr_ext_select_4; // When set, register eq_ctrl_clr is selected. |
| 494 | // This signal is a pulse. |
| 495 | output eq_ctrl_clr_ext_select_5; // When set, register eq_ctrl_clr is selected. |
| 496 | // This signal is a pulse. |
| 497 | output eq_ctrl_clr_ext_select_6; // When set, register eq_ctrl_clr is selected. |
| 498 | // This signal is a pulse. |
| 499 | output eq_ctrl_clr_ext_select_7; // When set, register eq_ctrl_clr is selected. |
| 500 | // This signal is a pulse. |
| 501 | output eq_ctrl_clr_ext_select_8; // When set, register eq_ctrl_clr is selected. |
| 502 | // This signal is a pulse. |
| 503 | output eq_ctrl_clr_ext_select_9; // When set, register eq_ctrl_clr is selected. |
| 504 | // This signal is a pulse. |
| 505 | output eq_ctrl_clr_ext_select_10; // When set, register eq_ctrl_clr is |
| 506 | // selected. This signal is a pulse. |
| 507 | output eq_ctrl_clr_ext_select_11; // When set, register eq_ctrl_clr is |
| 508 | // selected. This signal is a pulse. |
| 509 | output eq_ctrl_clr_ext_select_12; // When set, register eq_ctrl_clr is |
| 510 | // selected. This signal is a pulse. |
| 511 | output eq_ctrl_clr_ext_select_13; // When set, register eq_ctrl_clr is |
| 512 | // selected. This signal is a pulse. |
| 513 | output eq_ctrl_clr_ext_select_14; // When set, register eq_ctrl_clr is |
| 514 | // selected. This signal is a pulse. |
| 515 | output eq_ctrl_clr_ext_select_15; // When set, register eq_ctrl_clr is |
| 516 | // selected. This signal is a pulse. |
| 517 | output eq_ctrl_clr_ext_select_16; // When set, register eq_ctrl_clr is |
| 518 | // selected. This signal is a pulse. |
| 519 | output eq_ctrl_clr_ext_select_17; // When set, register eq_ctrl_clr is |
| 520 | // selected. This signal is a pulse. |
| 521 | output eq_ctrl_clr_ext_select_18; // When set, register eq_ctrl_clr is |
| 522 | // selected. This signal is a pulse. |
| 523 | output eq_ctrl_clr_ext_select_19; // When set, register eq_ctrl_clr is |
| 524 | // selected. This signal is a pulse. |
| 525 | output eq_ctrl_clr_ext_select_20; // When set, register eq_ctrl_clr is |
| 526 | // selected. This signal is a pulse. |
| 527 | output eq_ctrl_clr_ext_select_21; // When set, register eq_ctrl_clr is |
| 528 | // selected. This signal is a pulse. |
| 529 | output eq_ctrl_clr_ext_select_22; // When set, register eq_ctrl_clr is |
| 530 | // selected. This signal is a pulse. |
| 531 | output eq_ctrl_clr_ext_select_23; // When set, register eq_ctrl_clr is |
| 532 | // selected. This signal is a pulse. |
| 533 | output eq_ctrl_clr_ext_select_24; // When set, register eq_ctrl_clr is |
| 534 | // selected. This signal is a pulse. |
| 535 | output eq_ctrl_clr_ext_select_25; // When set, register eq_ctrl_clr is |
| 536 | // selected. This signal is a pulse. |
| 537 | output eq_ctrl_clr_ext_select_26; // When set, register eq_ctrl_clr is |
| 538 | // selected. This signal is a pulse. |
| 539 | output eq_ctrl_clr_ext_select_27; // When set, register eq_ctrl_clr is |
| 540 | // selected. This signal is a pulse. |
| 541 | output eq_ctrl_clr_ext_select_28; // When set, register eq_ctrl_clr is |
| 542 | // selected. This signal is a pulse. |
| 543 | output eq_ctrl_clr_ext_select_29; // When set, register eq_ctrl_clr is |
| 544 | // selected. This signal is a pulse. |
| 545 | output eq_ctrl_clr_ext_select_30; // When set, register eq_ctrl_clr is |
| 546 | // selected. This signal is a pulse. |
| 547 | output eq_ctrl_clr_ext_select_31; // When set, register eq_ctrl_clr is |
| 548 | // selected. This signal is a pulse. |
| 549 | output eq_ctrl_clr_ext_select_32; // When set, register eq_ctrl_clr is |
| 550 | // selected. This signal is a pulse. |
| 551 | output eq_ctrl_clr_ext_select_33; // When set, register eq_ctrl_clr is |
| 552 | // selected. This signal is a pulse. |
| 553 | output eq_ctrl_clr_ext_select_34; // When set, register eq_ctrl_clr is |
| 554 | // selected. This signal is a pulse. |
| 555 | output eq_ctrl_clr_ext_select_35; // When set, register eq_ctrl_clr is |
| 556 | // selected. This signal is a pulse. |
| 557 | input [2:0] eq_state_state_ext_read_data_0; // Ext read data (decode) |
| 558 | input [2:0] eq_state_state_ext_read_data_1; // Ext read data (decode) |
| 559 | input [2:0] eq_state_state_ext_read_data_2; // Ext read data (decode) |
| 560 | input [2:0] eq_state_state_ext_read_data_3; // Ext read data (decode) |
| 561 | input [2:0] eq_state_state_ext_read_data_4; // Ext read data (decode) |
| 562 | input [2:0] eq_state_state_ext_read_data_5; // Ext read data (decode) |
| 563 | input [2:0] eq_state_state_ext_read_data_6; // Ext read data (decode) |
| 564 | input [2:0] eq_state_state_ext_read_data_7; // Ext read data (decode) |
| 565 | input [2:0] eq_state_state_ext_read_data_8; // Ext read data (decode) |
| 566 | input [2:0] eq_state_state_ext_read_data_9; // Ext read data (decode) |
| 567 | input [2:0] eq_state_state_ext_read_data_10; // Ext read data (decode) |
| 568 | input [2:0] eq_state_state_ext_read_data_11; // Ext read data (decode) |
| 569 | input [2:0] eq_state_state_ext_read_data_12; // Ext read data (decode) |
| 570 | input [2:0] eq_state_state_ext_read_data_13; // Ext read data (decode) |
| 571 | input [2:0] eq_state_state_ext_read_data_14; // Ext read data (decode) |
| 572 | input [2:0] eq_state_state_ext_read_data_15; // Ext read data (decode) |
| 573 | input [2:0] eq_state_state_ext_read_data_16; // Ext read data (decode) |
| 574 | input [2:0] eq_state_state_ext_read_data_17; // Ext read data (decode) |
| 575 | input [2:0] eq_state_state_ext_read_data_18; // Ext read data (decode) |
| 576 | input [2:0] eq_state_state_ext_read_data_19; // Ext read data (decode) |
| 577 | input [2:0] eq_state_state_ext_read_data_20; // Ext read data (decode) |
| 578 | input [2:0] eq_state_state_ext_read_data_21; // Ext read data (decode) |
| 579 | input [2:0] eq_state_state_ext_read_data_22; // Ext read data (decode) |
| 580 | input [2:0] eq_state_state_ext_read_data_23; // Ext read data (decode) |
| 581 | input [2:0] eq_state_state_ext_read_data_24; // Ext read data (decode) |
| 582 | input [2:0] eq_state_state_ext_read_data_25; // Ext read data (decode) |
| 583 | input [2:0] eq_state_state_ext_read_data_26; // Ext read data (decode) |
| 584 | input [2:0] eq_state_state_ext_read_data_27; // Ext read data (decode) |
| 585 | input [2:0] eq_state_state_ext_read_data_28; // Ext read data (decode) |
| 586 | input [2:0] eq_state_state_ext_read_data_29; // Ext read data (decode) |
| 587 | input [2:0] eq_state_state_ext_read_data_30; // Ext read data (decode) |
| 588 | input [2:0] eq_state_state_ext_read_data_31; // Ext read data (decode) |
| 589 | input [2:0] eq_state_state_ext_read_data_32; // Ext read data (decode) |
| 590 | input [2:0] eq_state_state_ext_read_data_33; // Ext read data (decode) |
| 591 | input [2:0] eq_state_state_ext_read_data_34; // Ext read data (decode) |
| 592 | input [2:0] eq_state_state_ext_read_data_35; // Ext read data (decode) |
| 593 | input eq_tail_overr_hw_ld_0; // Hardware load enable for eq_tail_overr. When |
| 594 | // set, <hw write signal> will be loaded into |
| 595 | // eq_tail. |
| 596 | input eq_tail_overr_hw_ld_1; // Hardware load enable for eq_tail_overr. When |
| 597 | // set, <hw write signal> will be loaded into |
| 598 | // eq_tail. |
| 599 | input eq_tail_overr_hw_ld_2; // Hardware load enable for eq_tail_overr. When |
| 600 | // set, <hw write signal> will be loaded into |
| 601 | // eq_tail. |
| 602 | input eq_tail_overr_hw_ld_3; // Hardware load enable for eq_tail_overr. When |
| 603 | // set, <hw write signal> will be loaded into |
| 604 | // eq_tail. |
| 605 | input eq_tail_overr_hw_ld_4; // Hardware load enable for eq_tail_overr. When |
| 606 | // set, <hw write signal> will be loaded into |
| 607 | // eq_tail. |
| 608 | input eq_tail_overr_hw_ld_5; // Hardware load enable for eq_tail_overr. When |
| 609 | // set, <hw write signal> will be loaded into |
| 610 | // eq_tail. |
| 611 | input eq_tail_overr_hw_ld_6; // Hardware load enable for eq_tail_overr. When |
| 612 | // set, <hw write signal> will be loaded into |
| 613 | // eq_tail. |
| 614 | input eq_tail_overr_hw_ld_7; // Hardware load enable for eq_tail_overr. When |
| 615 | // set, <hw write signal> will be loaded into |
| 616 | // eq_tail. |
| 617 | input eq_tail_overr_hw_ld_8; // Hardware load enable for eq_tail_overr. When |
| 618 | // set, <hw write signal> will be loaded into |
| 619 | // eq_tail. |
| 620 | input eq_tail_overr_hw_ld_9; // Hardware load enable for eq_tail_overr. When |
| 621 | // set, <hw write signal> will be loaded into |
| 622 | // eq_tail. |
| 623 | input eq_tail_overr_hw_ld_10; // Hardware load enable for eq_tail_overr. When |
| 624 | // set, <hw write signal> will be loaded into |
| 625 | // eq_tail. |
| 626 | input eq_tail_overr_hw_ld_11; // Hardware load enable for eq_tail_overr. When |
| 627 | // set, <hw write signal> will be loaded into |
| 628 | // eq_tail. |
| 629 | input eq_tail_overr_hw_ld_12; // Hardware load enable for eq_tail_overr. When |
| 630 | // set, <hw write signal> will be loaded into |
| 631 | // eq_tail. |
| 632 | input eq_tail_overr_hw_ld_13; // Hardware load enable for eq_tail_overr. When |
| 633 | // set, <hw write signal> will be loaded into |
| 634 | // eq_tail. |
| 635 | input eq_tail_overr_hw_ld_14; // Hardware load enable for eq_tail_overr. When |
| 636 | // set, <hw write signal> will be loaded into |
| 637 | // eq_tail. |
| 638 | input eq_tail_overr_hw_ld_15; // Hardware load enable for eq_tail_overr. When |
| 639 | // set, <hw write signal> will be loaded into |
| 640 | // eq_tail. |
| 641 | input eq_tail_overr_hw_ld_16; // Hardware load enable for eq_tail_overr. When |
| 642 | // set, <hw write signal> will be loaded into |
| 643 | // eq_tail. |
| 644 | input eq_tail_overr_hw_ld_17; // Hardware load enable for eq_tail_overr. When |
| 645 | // set, <hw write signal> will be loaded into |
| 646 | // eq_tail. |
| 647 | input eq_tail_overr_hw_ld_18; // Hardware load enable for eq_tail_overr. When |
| 648 | // set, <hw write signal> will be loaded into |
| 649 | // eq_tail. |
| 650 | input eq_tail_overr_hw_ld_19; // Hardware load enable for eq_tail_overr. When |
| 651 | // set, <hw write signal> will be loaded into |
| 652 | // eq_tail. |
| 653 | input eq_tail_overr_hw_ld_20; // Hardware load enable for eq_tail_overr. When |
| 654 | // set, <hw write signal> will be loaded into |
| 655 | // eq_tail. |
| 656 | input eq_tail_overr_hw_ld_21; // Hardware load enable for eq_tail_overr. When |
| 657 | // set, <hw write signal> will be loaded into |
| 658 | // eq_tail. |
| 659 | input eq_tail_overr_hw_ld_22; // Hardware load enable for eq_tail_overr. When |
| 660 | // set, <hw write signal> will be loaded into |
| 661 | // eq_tail. |
| 662 | input eq_tail_overr_hw_ld_23; // Hardware load enable for eq_tail_overr. When |
| 663 | // set, <hw write signal> will be loaded into |
| 664 | // eq_tail. |
| 665 | input eq_tail_overr_hw_ld_24; // Hardware load enable for eq_tail_overr. When |
| 666 | // set, <hw write signal> will be loaded into |
| 667 | // eq_tail. |
| 668 | input eq_tail_overr_hw_ld_25; // Hardware load enable for eq_tail_overr. When |
| 669 | // set, <hw write signal> will be loaded into |
| 670 | // eq_tail. |
| 671 | input eq_tail_overr_hw_ld_26; // Hardware load enable for eq_tail_overr. When |
| 672 | // set, <hw write signal> will be loaded into |
| 673 | // eq_tail. |
| 674 | input eq_tail_overr_hw_ld_27; // Hardware load enable for eq_tail_overr. When |
| 675 | // set, <hw write signal> will be loaded into |
| 676 | // eq_tail. |
| 677 | input eq_tail_overr_hw_ld_28; // Hardware load enable for eq_tail_overr. When |
| 678 | // set, <hw write signal> will be loaded into |
| 679 | // eq_tail. |
| 680 | input eq_tail_overr_hw_ld_29; // Hardware load enable for eq_tail_overr. When |
| 681 | // set, <hw write signal> will be loaded into |
| 682 | // eq_tail. |
| 683 | input eq_tail_overr_hw_ld_30; // Hardware load enable for eq_tail_overr. When |
| 684 | // set, <hw write signal> will be loaded into |
| 685 | // eq_tail. |
| 686 | input eq_tail_overr_hw_ld_31; // Hardware load enable for eq_tail_overr. When |
| 687 | // set, <hw write signal> will be loaded into |
| 688 | // eq_tail. |
| 689 | input eq_tail_overr_hw_ld_32; // Hardware load enable for eq_tail_overr. When |
| 690 | // set, <hw write signal> will be loaded into |
| 691 | // eq_tail. |
| 692 | input eq_tail_overr_hw_ld_33; // Hardware load enable for eq_tail_overr. When |
| 693 | // set, <hw write signal> will be loaded into |
| 694 | // eq_tail. |
| 695 | input eq_tail_overr_hw_ld_34; // Hardware load enable for eq_tail_overr. When |
| 696 | // set, <hw write signal> will be loaded into |
| 697 | // eq_tail. |
| 698 | input eq_tail_overr_hw_ld_35; // Hardware load enable for eq_tail_overr. When |
| 699 | // set, <hw write signal> will be loaded into |
| 700 | // eq_tail. |
| 701 | input eq_tail_overr_hw_write_0; // data bus for hw loading of eq_tail_overr. |
| 702 | input eq_tail_overr_hw_write_1; // data bus for hw loading of eq_tail_overr. |
| 703 | input eq_tail_overr_hw_write_2; // data bus for hw loading of eq_tail_overr. |
| 704 | input eq_tail_overr_hw_write_3; // data bus for hw loading of eq_tail_overr. |
| 705 | input eq_tail_overr_hw_write_4; // data bus for hw loading of eq_tail_overr. |
| 706 | input eq_tail_overr_hw_write_5; // data bus for hw loading of eq_tail_overr. |
| 707 | input eq_tail_overr_hw_write_6; // data bus for hw loading of eq_tail_overr. |
| 708 | input eq_tail_overr_hw_write_7; // data bus for hw loading of eq_tail_overr. |
| 709 | input eq_tail_overr_hw_write_8; // data bus for hw loading of eq_tail_overr. |
| 710 | input eq_tail_overr_hw_write_9; // data bus for hw loading of eq_tail_overr. |
| 711 | input eq_tail_overr_hw_write_10; // data bus for hw loading of eq_tail_overr. |
| 712 | input eq_tail_overr_hw_write_11; // data bus for hw loading of eq_tail_overr. |
| 713 | input eq_tail_overr_hw_write_12; // data bus for hw loading of eq_tail_overr. |
| 714 | input eq_tail_overr_hw_write_13; // data bus for hw loading of eq_tail_overr. |
| 715 | input eq_tail_overr_hw_write_14; // data bus for hw loading of eq_tail_overr. |
| 716 | input eq_tail_overr_hw_write_15; // data bus for hw loading of eq_tail_overr. |
| 717 | input eq_tail_overr_hw_write_16; // data bus for hw loading of eq_tail_overr. |
| 718 | input eq_tail_overr_hw_write_17; // data bus for hw loading of eq_tail_overr. |
| 719 | input eq_tail_overr_hw_write_18; // data bus for hw loading of eq_tail_overr. |
| 720 | input eq_tail_overr_hw_write_19; // data bus for hw loading of eq_tail_overr. |
| 721 | input eq_tail_overr_hw_write_20; // data bus for hw loading of eq_tail_overr. |
| 722 | input eq_tail_overr_hw_write_21; // data bus for hw loading of eq_tail_overr. |
| 723 | input eq_tail_overr_hw_write_22; // data bus for hw loading of eq_tail_overr. |
| 724 | input eq_tail_overr_hw_write_23; // data bus for hw loading of eq_tail_overr. |
| 725 | input eq_tail_overr_hw_write_24; // data bus for hw loading of eq_tail_overr. |
| 726 | input eq_tail_overr_hw_write_25; // data bus for hw loading of eq_tail_overr. |
| 727 | input eq_tail_overr_hw_write_26; // data bus for hw loading of eq_tail_overr. |
| 728 | input eq_tail_overr_hw_write_27; // data bus for hw loading of eq_tail_overr. |
| 729 | input eq_tail_overr_hw_write_28; // data bus for hw loading of eq_tail_overr. |
| 730 | input eq_tail_overr_hw_write_29; // data bus for hw loading of eq_tail_overr. |
| 731 | input eq_tail_overr_hw_write_30; // data bus for hw loading of eq_tail_overr. |
| 732 | input eq_tail_overr_hw_write_31; // data bus for hw loading of eq_tail_overr. |
| 733 | input eq_tail_overr_hw_write_32; // data bus for hw loading of eq_tail_overr. |
| 734 | input eq_tail_overr_hw_write_33; // data bus for hw loading of eq_tail_overr. |
| 735 | input eq_tail_overr_hw_write_34; // data bus for hw loading of eq_tail_overr. |
| 736 | input eq_tail_overr_hw_write_35; // data bus for hw loading of eq_tail_overr. |
| 737 | input eq_tail_tail_hw_ld_0; // Hardware load enable for eq_tail_tail. When |
| 738 | // set, <hw write signal> will be loaded into |
| 739 | // eq_tail. |
| 740 | input eq_tail_tail_hw_ld_1; // Hardware load enable for eq_tail_tail. When |
| 741 | // set, <hw write signal> will be loaded into |
| 742 | // eq_tail. |
| 743 | input eq_tail_tail_hw_ld_2; // Hardware load enable for eq_tail_tail. When |
| 744 | // set, <hw write signal> will be loaded into |
| 745 | // eq_tail. |
| 746 | input eq_tail_tail_hw_ld_3; // Hardware load enable for eq_tail_tail. When |
| 747 | // set, <hw write signal> will be loaded into |
| 748 | // eq_tail. |
| 749 | input eq_tail_tail_hw_ld_4; // Hardware load enable for eq_tail_tail. When |
| 750 | // set, <hw write signal> will be loaded into |
| 751 | // eq_tail. |
| 752 | input eq_tail_tail_hw_ld_5; // Hardware load enable for eq_tail_tail. When |
| 753 | // set, <hw write signal> will be loaded into |
| 754 | // eq_tail. |
| 755 | input eq_tail_tail_hw_ld_6; // Hardware load enable for eq_tail_tail. When |
| 756 | // set, <hw write signal> will be loaded into |
| 757 | // eq_tail. |
| 758 | input eq_tail_tail_hw_ld_7; // Hardware load enable for eq_tail_tail. When |
| 759 | // set, <hw write signal> will be loaded into |
| 760 | // eq_tail. |
| 761 | input eq_tail_tail_hw_ld_8; // Hardware load enable for eq_tail_tail. When |
| 762 | // set, <hw write signal> will be loaded into |
| 763 | // eq_tail. |
| 764 | input eq_tail_tail_hw_ld_9; // Hardware load enable for eq_tail_tail. When |
| 765 | // set, <hw write signal> will be loaded into |
| 766 | // eq_tail. |
| 767 | input eq_tail_tail_hw_ld_10; // Hardware load enable for eq_tail_tail. When |
| 768 | // set, <hw write signal> will be loaded into |
| 769 | // eq_tail. |
| 770 | input eq_tail_tail_hw_ld_11; // Hardware load enable for eq_tail_tail. When |
| 771 | // set, <hw write signal> will be loaded into |
| 772 | // eq_tail. |
| 773 | input eq_tail_tail_hw_ld_12; // Hardware load enable for eq_tail_tail. When |
| 774 | // set, <hw write signal> will be loaded into |
| 775 | // eq_tail. |
| 776 | input eq_tail_tail_hw_ld_13; // Hardware load enable for eq_tail_tail. When |
| 777 | // set, <hw write signal> will be loaded into |
| 778 | // eq_tail. |
| 779 | input eq_tail_tail_hw_ld_14; // Hardware load enable for eq_tail_tail. When |
| 780 | // set, <hw write signal> will be loaded into |
| 781 | // eq_tail. |
| 782 | input eq_tail_tail_hw_ld_15; // Hardware load enable for eq_tail_tail. When |
| 783 | // set, <hw write signal> will be loaded into |
| 784 | // eq_tail. |
| 785 | input eq_tail_tail_hw_ld_16; // Hardware load enable for eq_tail_tail. When |
| 786 | // set, <hw write signal> will be loaded into |
| 787 | // eq_tail. |
| 788 | input eq_tail_tail_hw_ld_17; // Hardware load enable for eq_tail_tail. When |
| 789 | // set, <hw write signal> will be loaded into |
| 790 | // eq_tail. |
| 791 | input eq_tail_tail_hw_ld_18; // Hardware load enable for eq_tail_tail. When |
| 792 | // set, <hw write signal> will be loaded into |
| 793 | // eq_tail. |
| 794 | input eq_tail_tail_hw_ld_19; // Hardware load enable for eq_tail_tail. When |
| 795 | // set, <hw write signal> will be loaded into |
| 796 | // eq_tail. |
| 797 | input eq_tail_tail_hw_ld_20; // Hardware load enable for eq_tail_tail. When |
| 798 | // set, <hw write signal> will be loaded into |
| 799 | // eq_tail. |
| 800 | input eq_tail_tail_hw_ld_21; // Hardware load enable for eq_tail_tail. When |
| 801 | // set, <hw write signal> will be loaded into |
| 802 | // eq_tail. |
| 803 | input eq_tail_tail_hw_ld_22; // Hardware load enable for eq_tail_tail. When |
| 804 | // set, <hw write signal> will be loaded into |
| 805 | // eq_tail. |
| 806 | input eq_tail_tail_hw_ld_23; // Hardware load enable for eq_tail_tail. When |
| 807 | // set, <hw write signal> will be loaded into |
| 808 | // eq_tail. |
| 809 | input eq_tail_tail_hw_ld_24; // Hardware load enable for eq_tail_tail. When |
| 810 | // set, <hw write signal> will be loaded into |
| 811 | // eq_tail. |
| 812 | input eq_tail_tail_hw_ld_25; // Hardware load enable for eq_tail_tail. When |
| 813 | // set, <hw write signal> will be loaded into |
| 814 | // eq_tail. |
| 815 | input eq_tail_tail_hw_ld_26; // Hardware load enable for eq_tail_tail. When |
| 816 | // set, <hw write signal> will be loaded into |
| 817 | // eq_tail. |
| 818 | input eq_tail_tail_hw_ld_27; // Hardware load enable for eq_tail_tail. When |
| 819 | // set, <hw write signal> will be loaded into |
| 820 | // eq_tail. |
| 821 | input eq_tail_tail_hw_ld_28; // Hardware load enable for eq_tail_tail. When |
| 822 | // set, <hw write signal> will be loaded into |
| 823 | // eq_tail. |
| 824 | input eq_tail_tail_hw_ld_29; // Hardware load enable for eq_tail_tail. When |
| 825 | // set, <hw write signal> will be loaded into |
| 826 | // eq_tail. |
| 827 | input eq_tail_tail_hw_ld_30; // Hardware load enable for eq_tail_tail. When |
| 828 | // set, <hw write signal> will be loaded into |
| 829 | // eq_tail. |
| 830 | input eq_tail_tail_hw_ld_31; // Hardware load enable for eq_tail_tail. When |
| 831 | // set, <hw write signal> will be loaded into |
| 832 | // eq_tail. |
| 833 | input eq_tail_tail_hw_ld_32; // Hardware load enable for eq_tail_tail. When |
| 834 | // set, <hw write signal> will be loaded into |
| 835 | // eq_tail. |
| 836 | input eq_tail_tail_hw_ld_33; // Hardware load enable for eq_tail_tail. When |
| 837 | // set, <hw write signal> will be loaded into |
| 838 | // eq_tail. |
| 839 | input eq_tail_tail_hw_ld_34; // Hardware load enable for eq_tail_tail. When |
| 840 | // set, <hw write signal> will be loaded into |
| 841 | // eq_tail. |
| 842 | input eq_tail_tail_hw_ld_35; // Hardware load enable for eq_tail_tail. When |
| 843 | // set, <hw write signal> will be loaded into |
| 844 | // eq_tail. |
| 845 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_0; |
| 846 | // data bus for hw loading of eq_tail_tail. |
| 847 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_1; |
| 848 | // data bus for hw loading of eq_tail_tail. |
| 849 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_2; |
| 850 | // data bus for hw loading of eq_tail_tail. |
| 851 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_3; |
| 852 | // data bus for hw loading of eq_tail_tail. |
| 853 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_4; |
| 854 | // data bus for hw loading of eq_tail_tail. |
| 855 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_5; |
| 856 | // data bus for hw loading of eq_tail_tail. |
| 857 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_6; |
| 858 | // data bus for hw loading of eq_tail_tail. |
| 859 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_7; |
| 860 | // data bus for hw loading of eq_tail_tail. |
| 861 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_8; |
| 862 | // data bus for hw loading of eq_tail_tail. |
| 863 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_9; |
| 864 | // data bus for hw loading of eq_tail_tail. |
| 865 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_10; |
| 866 | // data bus for hw loading of eq_tail_tail. |
| 867 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_11; |
| 868 | // data bus for hw loading of eq_tail_tail. |
| 869 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_12; |
| 870 | // data bus for hw loading of eq_tail_tail. |
| 871 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_13; |
| 872 | // data bus for hw loading of eq_tail_tail. |
| 873 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_14; |
| 874 | // data bus for hw loading of eq_tail_tail. |
| 875 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_15; |
| 876 | // data bus for hw loading of eq_tail_tail. |
| 877 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_16; |
| 878 | // data bus for hw loading of eq_tail_tail. |
| 879 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_17; |
| 880 | // data bus for hw loading of eq_tail_tail. |
| 881 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_18; |
| 882 | // data bus for hw loading of eq_tail_tail. |
| 883 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_19; |
| 884 | // data bus for hw loading of eq_tail_tail. |
| 885 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_20; |
| 886 | // data bus for hw loading of eq_tail_tail. |
| 887 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_21; |
| 888 | // data bus for hw loading of eq_tail_tail. |
| 889 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_22; |
| 890 | // data bus for hw loading of eq_tail_tail. |
| 891 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_23; |
| 892 | // data bus for hw loading of eq_tail_tail. |
| 893 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_24; |
| 894 | // data bus for hw loading of eq_tail_tail. |
| 895 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_25; |
| 896 | // data bus for hw loading of eq_tail_tail. |
| 897 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_26; |
| 898 | // data bus for hw loading of eq_tail_tail. |
| 899 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_27; |
| 900 | // data bus for hw loading of eq_tail_tail. |
| 901 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_28; |
| 902 | // data bus for hw loading of eq_tail_tail. |
| 903 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_29; |
| 904 | // data bus for hw loading of eq_tail_tail. |
| 905 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_30; |
| 906 | // data bus for hw loading of eq_tail_tail. |
| 907 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_31; |
| 908 | // data bus for hw loading of eq_tail_tail. |
| 909 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_32; |
| 910 | // data bus for hw loading of eq_tail_tail. |
| 911 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_33; |
| 912 | // data bus for hw loading of eq_tail_tail. |
| 913 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_34; |
| 914 | // data bus for hw loading of eq_tail_tail. |
| 915 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_35; |
| 916 | // data bus for hw loading of eq_tail_tail. |
| 917 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_0; |
| 918 | // This signal provides the current value of eq_tail_tail. |
| 919 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_1; |
| 920 | // This signal provides the current value of eq_tail_tail. |
| 921 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_2; |
| 922 | // This signal provides the current value of eq_tail_tail. |
| 923 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_3; |
| 924 | // This signal provides the current value of eq_tail_tail. |
| 925 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_4; |
| 926 | // This signal provides the current value of eq_tail_tail. |
| 927 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_5; |
| 928 | // This signal provides the current value of eq_tail_tail. |
| 929 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_6; |
| 930 | // This signal provides the current value of eq_tail_tail. |
| 931 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_7; |
| 932 | // This signal provides the current value of eq_tail_tail. |
| 933 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_8; |
| 934 | // This signal provides the current value of eq_tail_tail. |
| 935 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_9; |
| 936 | // This signal provides the current value of eq_tail_tail. |
| 937 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_10; |
| 938 | // This signal provides the current value of eq_tail_tail. |
| 939 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_11; |
| 940 | // This signal provides the current value of eq_tail_tail. |
| 941 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_12; |
| 942 | // This signal provides the current value of eq_tail_tail. |
| 943 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_13; |
| 944 | // This signal provides the current value of eq_tail_tail. |
| 945 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_14; |
| 946 | // This signal provides the current value of eq_tail_tail. |
| 947 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_15; |
| 948 | // This signal provides the current value of eq_tail_tail. |
| 949 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_16; |
| 950 | // This signal provides the current value of eq_tail_tail. |
| 951 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_17; |
| 952 | // This signal provides the current value of eq_tail_tail. |
| 953 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_18; |
| 954 | // This signal provides the current value of eq_tail_tail. |
| 955 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_19; |
| 956 | // This signal provides the current value of eq_tail_tail. |
| 957 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_20; |
| 958 | // This signal provides the current value of eq_tail_tail. |
| 959 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_21; |
| 960 | // This signal provides the current value of eq_tail_tail. |
| 961 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_22; |
| 962 | // This signal provides the current value of eq_tail_tail. |
| 963 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_23; |
| 964 | // This signal provides the current value of eq_tail_tail. |
| 965 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_24; |
| 966 | // This signal provides the current value of eq_tail_tail. |
| 967 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_25; |
| 968 | // This signal provides the current value of eq_tail_tail. |
| 969 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_26; |
| 970 | // This signal provides the current value of eq_tail_tail. |
| 971 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_27; |
| 972 | // This signal provides the current value of eq_tail_tail. |
| 973 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_28; |
| 974 | // This signal provides the current value of eq_tail_tail. |
| 975 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_29; |
| 976 | // This signal provides the current value of eq_tail_tail. |
| 977 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_30; |
| 978 | // This signal provides the current value of eq_tail_tail. |
| 979 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_31; |
| 980 | // This signal provides the current value of eq_tail_tail. |
| 981 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_32; |
| 982 | // This signal provides the current value of eq_tail_tail. |
| 983 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_33; |
| 984 | // This signal provides the current value of eq_tail_tail. |
| 985 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_34; |
| 986 | // This signal provides the current value of eq_tail_tail. |
| 987 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_35; |
| 988 | // This signal provides the current value of eq_tail_tail. |
| 989 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_0; |
| 990 | // This signal provides the current value of eq_head_head. |
| 991 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_1; |
| 992 | // This signal provides the current value of eq_head_head. |
| 993 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_2; |
| 994 | // This signal provides the current value of eq_head_head. |
| 995 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_3; |
| 996 | // This signal provides the current value of eq_head_head. |
| 997 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_4; |
| 998 | // This signal provides the current value of eq_head_head. |
| 999 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_5; |
| 1000 | // This signal provides the current value of eq_head_head. |
| 1001 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_6; |
| 1002 | // This signal provides the current value of eq_head_head. |
| 1003 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_7; |
| 1004 | // This signal provides the current value of eq_head_head. |
| 1005 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_8; |
| 1006 | // This signal provides the current value of eq_head_head. |
| 1007 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_9; |
| 1008 | // This signal provides the current value of eq_head_head. |
| 1009 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_10; |
| 1010 | // This signal provides the current value of eq_head_head. |
| 1011 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_11; |
| 1012 | // This signal provides the current value of eq_head_head. |
| 1013 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_12; |
| 1014 | // This signal provides the current value of eq_head_head. |
| 1015 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_13; |
| 1016 | // This signal provides the current value of eq_head_head. |
| 1017 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_14; |
| 1018 | // This signal provides the current value of eq_head_head. |
| 1019 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_15; |
| 1020 | // This signal provides the current value of eq_head_head. |
| 1021 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_16; |
| 1022 | // This signal provides the current value of eq_head_head. |
| 1023 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_17; |
| 1024 | // This signal provides the current value of eq_head_head. |
| 1025 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_18; |
| 1026 | // This signal provides the current value of eq_head_head. |
| 1027 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_19; |
| 1028 | // This signal provides the current value of eq_head_head. |
| 1029 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_20; |
| 1030 | // This signal provides the current value of eq_head_head. |
| 1031 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_21; |
| 1032 | // This signal provides the current value of eq_head_head. |
| 1033 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_22; |
| 1034 | // This signal provides the current value of eq_head_head. |
| 1035 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_23; |
| 1036 | // This signal provides the current value of eq_head_head. |
| 1037 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_24; |
| 1038 | // This signal provides the current value of eq_head_head. |
| 1039 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_25; |
| 1040 | // This signal provides the current value of eq_head_head. |
| 1041 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_26; |
| 1042 | // This signal provides the current value of eq_head_head. |
| 1043 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_27; |
| 1044 | // This signal provides the current value of eq_head_head. |
| 1045 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_28; |
| 1046 | // This signal provides the current value of eq_head_head. |
| 1047 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_29; |
| 1048 | // This signal provides the current value of eq_head_head. |
| 1049 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_30; |
| 1050 | // This signal provides the current value of eq_head_head. |
| 1051 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_31; |
| 1052 | // This signal provides the current value of eq_head_head. |
| 1053 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_32; |
| 1054 | // This signal provides the current value of eq_head_head. |
| 1055 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_33; |
| 1056 | // This signal provides the current value of eq_head_head. |
| 1057 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_34; |
| 1058 | // This signal provides the current value of eq_head_head. |
| 1059 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_35; |
| 1060 | // This signal provides the current value of eq_head_head. |
| 1061 | |
| 1062 | //==================================================== |
| 1063 | // Type declarations |
| 1064 | //==================================================== |
| 1065 | wire clk; // Clock signal |
| 1066 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus |
| 1067 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 1068 | wire csrbus_wr; // Read/Write signal |
| 1069 | wire csrbus_valid; // Valid address |
| 1070 | wire csrbus_mapped; // Address is mapped |
| 1071 | wire csrbus_done; // Operation is done |
| 1072 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus |
| 1073 | wire rst_l; // Reset signal |
| 1074 | wire [1:0] csrbus_src_bus; // Source bus |
| 1075 | wire csrbus_acc_vio; // Violation signal |
| 1076 | wire instance_id; // Instance ID |
| 1077 | wire ext_wr; // When one, csr operation is a write. When zero, operation is a |
| 1078 | // read. |
| 1079 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_INT_SLC] eq_base_address_address_hw_read; |
| 1080 | // This signal provides the current value of eq_base_address_address. |
| 1081 | wire eq_ctrl_set_enoverr_ext_wr_data; // Provides SW write data for external |
| 1082 | // register "eq_ctrl_set", field |
| 1083 | // "enoverr" |
| 1084 | wire eq_ctrl_set_en_ext_wr_data; // Provides SW write data for external |
| 1085 | // register "eq_ctrl_set", field "en" |
| 1086 | wire eq_ctrl_set_ext_select_0; // When set, register eq_ctrl_set is selected. |
| 1087 | // This signal is a pulse. |
| 1088 | wire eq_ctrl_set_ext_select_1; // When set, register eq_ctrl_set is selected. |
| 1089 | // This signal is a pulse. |
| 1090 | wire eq_ctrl_set_ext_select_2; // When set, register eq_ctrl_set is selected. |
| 1091 | // This signal is a pulse. |
| 1092 | wire eq_ctrl_set_ext_select_3; // When set, register eq_ctrl_set is selected. |
| 1093 | // This signal is a pulse. |
| 1094 | wire eq_ctrl_set_ext_select_4; // When set, register eq_ctrl_set is selected. |
| 1095 | // This signal is a pulse. |
| 1096 | wire eq_ctrl_set_ext_select_5; // When set, register eq_ctrl_set is selected. |
| 1097 | // This signal is a pulse. |
| 1098 | wire eq_ctrl_set_ext_select_6; // When set, register eq_ctrl_set is selected. |
| 1099 | // This signal is a pulse. |
| 1100 | wire eq_ctrl_set_ext_select_7; // When set, register eq_ctrl_set is selected. |
| 1101 | // This signal is a pulse. |
| 1102 | wire eq_ctrl_set_ext_select_8; // When set, register eq_ctrl_set is selected. |
| 1103 | // This signal is a pulse. |
| 1104 | wire eq_ctrl_set_ext_select_9; // When set, register eq_ctrl_set is selected. |
| 1105 | // This signal is a pulse. |
| 1106 | wire eq_ctrl_set_ext_select_10; // When set, register eq_ctrl_set is selected. |
| 1107 | // This signal is a pulse. |
| 1108 | wire eq_ctrl_set_ext_select_11; // When set, register eq_ctrl_set is selected. |
| 1109 | // This signal is a pulse. |
| 1110 | wire eq_ctrl_set_ext_select_12; // When set, register eq_ctrl_set is selected. |
| 1111 | // This signal is a pulse. |
| 1112 | wire eq_ctrl_set_ext_select_13; // When set, register eq_ctrl_set is selected. |
| 1113 | // This signal is a pulse. |
| 1114 | wire eq_ctrl_set_ext_select_14; // When set, register eq_ctrl_set is selected. |
| 1115 | // This signal is a pulse. |
| 1116 | wire eq_ctrl_set_ext_select_15; // When set, register eq_ctrl_set is selected. |
| 1117 | // This signal is a pulse. |
| 1118 | wire eq_ctrl_set_ext_select_16; // When set, register eq_ctrl_set is selected. |
| 1119 | // This signal is a pulse. |
| 1120 | wire eq_ctrl_set_ext_select_17; // When set, register eq_ctrl_set is selected. |
| 1121 | // This signal is a pulse. |
| 1122 | wire eq_ctrl_set_ext_select_18; // When set, register eq_ctrl_set is selected. |
| 1123 | // This signal is a pulse. |
| 1124 | wire eq_ctrl_set_ext_select_19; // When set, register eq_ctrl_set is selected. |
| 1125 | // This signal is a pulse. |
| 1126 | wire eq_ctrl_set_ext_select_20; // When set, register eq_ctrl_set is selected. |
| 1127 | // This signal is a pulse. |
| 1128 | wire eq_ctrl_set_ext_select_21; // When set, register eq_ctrl_set is selected. |
| 1129 | // This signal is a pulse. |
| 1130 | wire eq_ctrl_set_ext_select_22; // When set, register eq_ctrl_set is selected. |
| 1131 | // This signal is a pulse. |
| 1132 | wire eq_ctrl_set_ext_select_23; // When set, register eq_ctrl_set is selected. |
| 1133 | // This signal is a pulse. |
| 1134 | wire eq_ctrl_set_ext_select_24; // When set, register eq_ctrl_set is selected. |
| 1135 | // This signal is a pulse. |
| 1136 | wire eq_ctrl_set_ext_select_25; // When set, register eq_ctrl_set is selected. |
| 1137 | // This signal is a pulse. |
| 1138 | wire eq_ctrl_set_ext_select_26; // When set, register eq_ctrl_set is selected. |
| 1139 | // This signal is a pulse. |
| 1140 | wire eq_ctrl_set_ext_select_27; // When set, register eq_ctrl_set is selected. |
| 1141 | // This signal is a pulse. |
| 1142 | wire eq_ctrl_set_ext_select_28; // When set, register eq_ctrl_set is selected. |
| 1143 | // This signal is a pulse. |
| 1144 | wire eq_ctrl_set_ext_select_29; // When set, register eq_ctrl_set is selected. |
| 1145 | // This signal is a pulse. |
| 1146 | wire eq_ctrl_set_ext_select_30; // When set, register eq_ctrl_set is selected. |
| 1147 | // This signal is a pulse. |
| 1148 | wire eq_ctrl_set_ext_select_31; // When set, register eq_ctrl_set is selected. |
| 1149 | // This signal is a pulse. |
| 1150 | wire eq_ctrl_set_ext_select_32; // When set, register eq_ctrl_set is selected. |
| 1151 | // This signal is a pulse. |
| 1152 | wire eq_ctrl_set_ext_select_33; // When set, register eq_ctrl_set is selected. |
| 1153 | // This signal is a pulse. |
| 1154 | wire eq_ctrl_set_ext_select_34; // When set, register eq_ctrl_set is selected. |
| 1155 | // This signal is a pulse. |
| 1156 | wire eq_ctrl_set_ext_select_35; // When set, register eq_ctrl_set is selected. |
| 1157 | // This signal is a pulse. |
| 1158 | wire eq_ctrl_clr_coverr_ext_wr_data; // Provides SW write data for external |
| 1159 | // register "eq_ctrl_clr", field "coverr" |
| 1160 | wire eq_ctrl_clr_e2i_ext_wr_data; // Provides SW write data for external |
| 1161 | // register "eq_ctrl_clr", field "e2i" |
| 1162 | wire eq_ctrl_clr_dis_ext_wr_data; // Provides SW write data for external |
| 1163 | // register "eq_ctrl_clr", field "dis" |
| 1164 | wire eq_ctrl_clr_ext_select_0; // When set, register eq_ctrl_clr is selected. |
| 1165 | // This signal is a pulse. |
| 1166 | wire eq_ctrl_clr_ext_select_1; // When set, register eq_ctrl_clr is selected. |
| 1167 | // This signal is a pulse. |
| 1168 | wire eq_ctrl_clr_ext_select_2; // When set, register eq_ctrl_clr is selected. |
| 1169 | // This signal is a pulse. |
| 1170 | wire eq_ctrl_clr_ext_select_3; // When set, register eq_ctrl_clr is selected. |
| 1171 | // This signal is a pulse. |
| 1172 | wire eq_ctrl_clr_ext_select_4; // When set, register eq_ctrl_clr is selected. |
| 1173 | // This signal is a pulse. |
| 1174 | wire eq_ctrl_clr_ext_select_5; // When set, register eq_ctrl_clr is selected. |
| 1175 | // This signal is a pulse. |
| 1176 | wire eq_ctrl_clr_ext_select_6; // When set, register eq_ctrl_clr is selected. |
| 1177 | // This signal is a pulse. |
| 1178 | wire eq_ctrl_clr_ext_select_7; // When set, register eq_ctrl_clr is selected. |
| 1179 | // This signal is a pulse. |
| 1180 | wire eq_ctrl_clr_ext_select_8; // When set, register eq_ctrl_clr is selected. |
| 1181 | // This signal is a pulse. |
| 1182 | wire eq_ctrl_clr_ext_select_9; // When set, register eq_ctrl_clr is selected. |
| 1183 | // This signal is a pulse. |
| 1184 | wire eq_ctrl_clr_ext_select_10; // When set, register eq_ctrl_clr is selected. |
| 1185 | // This signal is a pulse. |
| 1186 | wire eq_ctrl_clr_ext_select_11; // When set, register eq_ctrl_clr is selected. |
| 1187 | // This signal is a pulse. |
| 1188 | wire eq_ctrl_clr_ext_select_12; // When set, register eq_ctrl_clr is selected. |
| 1189 | // This signal is a pulse. |
| 1190 | wire eq_ctrl_clr_ext_select_13; // When set, register eq_ctrl_clr is selected. |
| 1191 | // This signal is a pulse. |
| 1192 | wire eq_ctrl_clr_ext_select_14; // When set, register eq_ctrl_clr is selected. |
| 1193 | // This signal is a pulse. |
| 1194 | wire eq_ctrl_clr_ext_select_15; // When set, register eq_ctrl_clr is selected. |
| 1195 | // This signal is a pulse. |
| 1196 | wire eq_ctrl_clr_ext_select_16; // When set, register eq_ctrl_clr is selected. |
| 1197 | // This signal is a pulse. |
| 1198 | wire eq_ctrl_clr_ext_select_17; // When set, register eq_ctrl_clr is selected. |
| 1199 | // This signal is a pulse. |
| 1200 | wire eq_ctrl_clr_ext_select_18; // When set, register eq_ctrl_clr is selected. |
| 1201 | // This signal is a pulse. |
| 1202 | wire eq_ctrl_clr_ext_select_19; // When set, register eq_ctrl_clr is selected. |
| 1203 | // This signal is a pulse. |
| 1204 | wire eq_ctrl_clr_ext_select_20; // When set, register eq_ctrl_clr is selected. |
| 1205 | // This signal is a pulse. |
| 1206 | wire eq_ctrl_clr_ext_select_21; // When set, register eq_ctrl_clr is selected. |
| 1207 | // This signal is a pulse. |
| 1208 | wire eq_ctrl_clr_ext_select_22; // When set, register eq_ctrl_clr is selected. |
| 1209 | // This signal is a pulse. |
| 1210 | wire eq_ctrl_clr_ext_select_23; // When set, register eq_ctrl_clr is selected. |
| 1211 | // This signal is a pulse. |
| 1212 | wire eq_ctrl_clr_ext_select_24; // When set, register eq_ctrl_clr is selected. |
| 1213 | // This signal is a pulse. |
| 1214 | wire eq_ctrl_clr_ext_select_25; // When set, register eq_ctrl_clr is selected. |
| 1215 | // This signal is a pulse. |
| 1216 | wire eq_ctrl_clr_ext_select_26; // When set, register eq_ctrl_clr is selected. |
| 1217 | // This signal is a pulse. |
| 1218 | wire eq_ctrl_clr_ext_select_27; // When set, register eq_ctrl_clr is selected. |
| 1219 | // This signal is a pulse. |
| 1220 | wire eq_ctrl_clr_ext_select_28; // When set, register eq_ctrl_clr is selected. |
| 1221 | // This signal is a pulse. |
| 1222 | wire eq_ctrl_clr_ext_select_29; // When set, register eq_ctrl_clr is selected. |
| 1223 | // This signal is a pulse. |
| 1224 | wire eq_ctrl_clr_ext_select_30; // When set, register eq_ctrl_clr is selected. |
| 1225 | // This signal is a pulse. |
| 1226 | wire eq_ctrl_clr_ext_select_31; // When set, register eq_ctrl_clr is selected. |
| 1227 | // This signal is a pulse. |
| 1228 | wire eq_ctrl_clr_ext_select_32; // When set, register eq_ctrl_clr is selected. |
| 1229 | // This signal is a pulse. |
| 1230 | wire eq_ctrl_clr_ext_select_33; // When set, register eq_ctrl_clr is selected. |
| 1231 | // This signal is a pulse. |
| 1232 | wire eq_ctrl_clr_ext_select_34; // When set, register eq_ctrl_clr is selected. |
| 1233 | // This signal is a pulse. |
| 1234 | wire eq_ctrl_clr_ext_select_35; // When set, register eq_ctrl_clr is selected. |
| 1235 | // This signal is a pulse. |
| 1236 | wire [2:0] eq_state_state_ext_read_data_0; // Ext read data (decode) |
| 1237 | wire [2:0] eq_state_state_ext_read_data_1; // Ext read data (decode) |
| 1238 | wire [2:0] eq_state_state_ext_read_data_2; // Ext read data (decode) |
| 1239 | wire [2:0] eq_state_state_ext_read_data_3; // Ext read data (decode) |
| 1240 | wire [2:0] eq_state_state_ext_read_data_4; // Ext read data (decode) |
| 1241 | wire [2:0] eq_state_state_ext_read_data_5; // Ext read data (decode) |
| 1242 | wire [2:0] eq_state_state_ext_read_data_6; // Ext read data (decode) |
| 1243 | wire [2:0] eq_state_state_ext_read_data_7; // Ext read data (decode) |
| 1244 | wire [2:0] eq_state_state_ext_read_data_8; // Ext read data (decode) |
| 1245 | wire [2:0] eq_state_state_ext_read_data_9; // Ext read data (decode) |
| 1246 | wire [2:0] eq_state_state_ext_read_data_10; // Ext read data (decode) |
| 1247 | wire [2:0] eq_state_state_ext_read_data_11; // Ext read data (decode) |
| 1248 | wire [2:0] eq_state_state_ext_read_data_12; // Ext read data (decode) |
| 1249 | wire [2:0] eq_state_state_ext_read_data_13; // Ext read data (decode) |
| 1250 | wire [2:0] eq_state_state_ext_read_data_14; // Ext read data (decode) |
| 1251 | wire [2:0] eq_state_state_ext_read_data_15; // Ext read data (decode) |
| 1252 | wire [2:0] eq_state_state_ext_read_data_16; // Ext read data (decode) |
| 1253 | wire [2:0] eq_state_state_ext_read_data_17; // Ext read data (decode) |
| 1254 | wire [2:0] eq_state_state_ext_read_data_18; // Ext read data (decode) |
| 1255 | wire [2:0] eq_state_state_ext_read_data_19; // Ext read data (decode) |
| 1256 | wire [2:0] eq_state_state_ext_read_data_20; // Ext read data (decode) |
| 1257 | wire [2:0] eq_state_state_ext_read_data_21; // Ext read data (decode) |
| 1258 | wire [2:0] eq_state_state_ext_read_data_22; // Ext read data (decode) |
| 1259 | wire [2:0] eq_state_state_ext_read_data_23; // Ext read data (decode) |
| 1260 | wire [2:0] eq_state_state_ext_read_data_24; // Ext read data (decode) |
| 1261 | wire [2:0] eq_state_state_ext_read_data_25; // Ext read data (decode) |
| 1262 | wire [2:0] eq_state_state_ext_read_data_26; // Ext read data (decode) |
| 1263 | wire [2:0] eq_state_state_ext_read_data_27; // Ext read data (decode) |
| 1264 | wire [2:0] eq_state_state_ext_read_data_28; // Ext read data (decode) |
| 1265 | wire [2:0] eq_state_state_ext_read_data_29; // Ext read data (decode) |
| 1266 | wire [2:0] eq_state_state_ext_read_data_30; // Ext read data (decode) |
| 1267 | wire [2:0] eq_state_state_ext_read_data_31; // Ext read data (decode) |
| 1268 | wire [2:0] eq_state_state_ext_read_data_32; // Ext read data (decode) |
| 1269 | wire [2:0] eq_state_state_ext_read_data_33; // Ext read data (decode) |
| 1270 | wire [2:0] eq_state_state_ext_read_data_34; // Ext read data (decode) |
| 1271 | wire [2:0] eq_state_state_ext_read_data_35; // Ext read data (decode) |
| 1272 | wire eq_tail_overr_hw_ld_0; // Hardware load enable for eq_tail_overr. When |
| 1273 | // set, <hw write signal> will be loaded into |
| 1274 | // eq_tail. |
| 1275 | wire eq_tail_overr_hw_ld_1; // Hardware load enable for eq_tail_overr. When |
| 1276 | // set, <hw write signal> will be loaded into |
| 1277 | // eq_tail. |
| 1278 | wire eq_tail_overr_hw_ld_2; // Hardware load enable for eq_tail_overr. When |
| 1279 | // set, <hw write signal> will be loaded into |
| 1280 | // eq_tail. |
| 1281 | wire eq_tail_overr_hw_ld_3; // Hardware load enable for eq_tail_overr. When |
| 1282 | // set, <hw write signal> will be loaded into |
| 1283 | // eq_tail. |
| 1284 | wire eq_tail_overr_hw_ld_4; // Hardware load enable for eq_tail_overr. When |
| 1285 | // set, <hw write signal> will be loaded into |
| 1286 | // eq_tail. |
| 1287 | wire eq_tail_overr_hw_ld_5; // Hardware load enable for eq_tail_overr. When |
| 1288 | // set, <hw write signal> will be loaded into |
| 1289 | // eq_tail. |
| 1290 | wire eq_tail_overr_hw_ld_6; // Hardware load enable for eq_tail_overr. When |
| 1291 | // set, <hw write signal> will be loaded into |
| 1292 | // eq_tail. |
| 1293 | wire eq_tail_overr_hw_ld_7; // Hardware load enable for eq_tail_overr. When |
| 1294 | // set, <hw write signal> will be loaded into |
| 1295 | // eq_tail. |
| 1296 | wire eq_tail_overr_hw_ld_8; // Hardware load enable for eq_tail_overr. When |
| 1297 | // set, <hw write signal> will be loaded into |
| 1298 | // eq_tail. |
| 1299 | wire eq_tail_overr_hw_ld_9; // Hardware load enable for eq_tail_overr. When |
| 1300 | // set, <hw write signal> will be loaded into |
| 1301 | // eq_tail. |
| 1302 | wire eq_tail_overr_hw_ld_10; // Hardware load enable for eq_tail_overr. When |
| 1303 | // set, <hw write signal> will be loaded into |
| 1304 | // eq_tail. |
| 1305 | wire eq_tail_overr_hw_ld_11; // Hardware load enable for eq_tail_overr. When |
| 1306 | // set, <hw write signal> will be loaded into |
| 1307 | // eq_tail. |
| 1308 | wire eq_tail_overr_hw_ld_12; // Hardware load enable for eq_tail_overr. When |
| 1309 | // set, <hw write signal> will be loaded into |
| 1310 | // eq_tail. |
| 1311 | wire eq_tail_overr_hw_ld_13; // Hardware load enable for eq_tail_overr. When |
| 1312 | // set, <hw write signal> will be loaded into |
| 1313 | // eq_tail. |
| 1314 | wire eq_tail_overr_hw_ld_14; // Hardware load enable for eq_tail_overr. When |
| 1315 | // set, <hw write signal> will be loaded into |
| 1316 | // eq_tail. |
| 1317 | wire eq_tail_overr_hw_ld_15; // Hardware load enable for eq_tail_overr. When |
| 1318 | // set, <hw write signal> will be loaded into |
| 1319 | // eq_tail. |
| 1320 | wire eq_tail_overr_hw_ld_16; // Hardware load enable for eq_tail_overr. When |
| 1321 | // set, <hw write signal> will be loaded into |
| 1322 | // eq_tail. |
| 1323 | wire eq_tail_overr_hw_ld_17; // Hardware load enable for eq_tail_overr. When |
| 1324 | // set, <hw write signal> will be loaded into |
| 1325 | // eq_tail. |
| 1326 | wire eq_tail_overr_hw_ld_18; // Hardware load enable for eq_tail_overr. When |
| 1327 | // set, <hw write signal> will be loaded into |
| 1328 | // eq_tail. |
| 1329 | wire eq_tail_overr_hw_ld_19; // Hardware load enable for eq_tail_overr. When |
| 1330 | // set, <hw write signal> will be loaded into |
| 1331 | // eq_tail. |
| 1332 | wire eq_tail_overr_hw_ld_20; // Hardware load enable for eq_tail_overr. When |
| 1333 | // set, <hw write signal> will be loaded into |
| 1334 | // eq_tail. |
| 1335 | wire eq_tail_overr_hw_ld_21; // Hardware load enable for eq_tail_overr. When |
| 1336 | // set, <hw write signal> will be loaded into |
| 1337 | // eq_tail. |
| 1338 | wire eq_tail_overr_hw_ld_22; // Hardware load enable for eq_tail_overr. When |
| 1339 | // set, <hw write signal> will be loaded into |
| 1340 | // eq_tail. |
| 1341 | wire eq_tail_overr_hw_ld_23; // Hardware load enable for eq_tail_overr. When |
| 1342 | // set, <hw write signal> will be loaded into |
| 1343 | // eq_tail. |
| 1344 | wire eq_tail_overr_hw_ld_24; // Hardware load enable for eq_tail_overr. When |
| 1345 | // set, <hw write signal> will be loaded into |
| 1346 | // eq_tail. |
| 1347 | wire eq_tail_overr_hw_ld_25; // Hardware load enable for eq_tail_overr. When |
| 1348 | // set, <hw write signal> will be loaded into |
| 1349 | // eq_tail. |
| 1350 | wire eq_tail_overr_hw_ld_26; // Hardware load enable for eq_tail_overr. When |
| 1351 | // set, <hw write signal> will be loaded into |
| 1352 | // eq_tail. |
| 1353 | wire eq_tail_overr_hw_ld_27; // Hardware load enable for eq_tail_overr. When |
| 1354 | // set, <hw write signal> will be loaded into |
| 1355 | // eq_tail. |
| 1356 | wire eq_tail_overr_hw_ld_28; // Hardware load enable for eq_tail_overr. When |
| 1357 | // set, <hw write signal> will be loaded into |
| 1358 | // eq_tail. |
| 1359 | wire eq_tail_overr_hw_ld_29; // Hardware load enable for eq_tail_overr. When |
| 1360 | // set, <hw write signal> will be loaded into |
| 1361 | // eq_tail. |
| 1362 | wire eq_tail_overr_hw_ld_30; // Hardware load enable for eq_tail_overr. When |
| 1363 | // set, <hw write signal> will be loaded into |
| 1364 | // eq_tail. |
| 1365 | wire eq_tail_overr_hw_ld_31; // Hardware load enable for eq_tail_overr. When |
| 1366 | // set, <hw write signal> will be loaded into |
| 1367 | // eq_tail. |
| 1368 | wire eq_tail_overr_hw_ld_32; // Hardware load enable for eq_tail_overr. When |
| 1369 | // set, <hw write signal> will be loaded into |
| 1370 | // eq_tail. |
| 1371 | wire eq_tail_overr_hw_ld_33; // Hardware load enable for eq_tail_overr. When |
| 1372 | // set, <hw write signal> will be loaded into |
| 1373 | // eq_tail. |
| 1374 | wire eq_tail_overr_hw_ld_34; // Hardware load enable for eq_tail_overr. When |
| 1375 | // set, <hw write signal> will be loaded into |
| 1376 | // eq_tail. |
| 1377 | wire eq_tail_overr_hw_ld_35; // Hardware load enable for eq_tail_overr. When |
| 1378 | // set, <hw write signal> will be loaded into |
| 1379 | // eq_tail. |
| 1380 | wire eq_tail_overr_hw_write_0; // data bus for hw loading of eq_tail_overr. |
| 1381 | wire eq_tail_overr_hw_write_1; // data bus for hw loading of eq_tail_overr. |
| 1382 | wire eq_tail_overr_hw_write_2; // data bus for hw loading of eq_tail_overr. |
| 1383 | wire eq_tail_overr_hw_write_3; // data bus for hw loading of eq_tail_overr. |
| 1384 | wire eq_tail_overr_hw_write_4; // data bus for hw loading of eq_tail_overr. |
| 1385 | wire eq_tail_overr_hw_write_5; // data bus for hw loading of eq_tail_overr. |
| 1386 | wire eq_tail_overr_hw_write_6; // data bus for hw loading of eq_tail_overr. |
| 1387 | wire eq_tail_overr_hw_write_7; // data bus for hw loading of eq_tail_overr. |
| 1388 | wire eq_tail_overr_hw_write_8; // data bus for hw loading of eq_tail_overr. |
| 1389 | wire eq_tail_overr_hw_write_9; // data bus for hw loading of eq_tail_overr. |
| 1390 | wire eq_tail_overr_hw_write_10; // data bus for hw loading of eq_tail_overr. |
| 1391 | wire eq_tail_overr_hw_write_11; // data bus for hw loading of eq_tail_overr. |
| 1392 | wire eq_tail_overr_hw_write_12; // data bus for hw loading of eq_tail_overr. |
| 1393 | wire eq_tail_overr_hw_write_13; // data bus for hw loading of eq_tail_overr. |
| 1394 | wire eq_tail_overr_hw_write_14; // data bus for hw loading of eq_tail_overr. |
| 1395 | wire eq_tail_overr_hw_write_15; // data bus for hw loading of eq_tail_overr. |
| 1396 | wire eq_tail_overr_hw_write_16; // data bus for hw loading of eq_tail_overr. |
| 1397 | wire eq_tail_overr_hw_write_17; // data bus for hw loading of eq_tail_overr. |
| 1398 | wire eq_tail_overr_hw_write_18; // data bus for hw loading of eq_tail_overr. |
| 1399 | wire eq_tail_overr_hw_write_19; // data bus for hw loading of eq_tail_overr. |
| 1400 | wire eq_tail_overr_hw_write_20; // data bus for hw loading of eq_tail_overr. |
| 1401 | wire eq_tail_overr_hw_write_21; // data bus for hw loading of eq_tail_overr. |
| 1402 | wire eq_tail_overr_hw_write_22; // data bus for hw loading of eq_tail_overr. |
| 1403 | wire eq_tail_overr_hw_write_23; // data bus for hw loading of eq_tail_overr. |
| 1404 | wire eq_tail_overr_hw_write_24; // data bus for hw loading of eq_tail_overr. |
| 1405 | wire eq_tail_overr_hw_write_25; // data bus for hw loading of eq_tail_overr. |
| 1406 | wire eq_tail_overr_hw_write_26; // data bus for hw loading of eq_tail_overr. |
| 1407 | wire eq_tail_overr_hw_write_27; // data bus for hw loading of eq_tail_overr. |
| 1408 | wire eq_tail_overr_hw_write_28; // data bus for hw loading of eq_tail_overr. |
| 1409 | wire eq_tail_overr_hw_write_29; // data bus for hw loading of eq_tail_overr. |
| 1410 | wire eq_tail_overr_hw_write_30; // data bus for hw loading of eq_tail_overr. |
| 1411 | wire eq_tail_overr_hw_write_31; // data bus for hw loading of eq_tail_overr. |
| 1412 | wire eq_tail_overr_hw_write_32; // data bus for hw loading of eq_tail_overr. |
| 1413 | wire eq_tail_overr_hw_write_33; // data bus for hw loading of eq_tail_overr. |
| 1414 | wire eq_tail_overr_hw_write_34; // data bus for hw loading of eq_tail_overr. |
| 1415 | wire eq_tail_overr_hw_write_35; // data bus for hw loading of eq_tail_overr. |
| 1416 | wire eq_tail_tail_hw_ld_0; // Hardware load enable for eq_tail_tail. When set, |
| 1417 | // <hw write signal> will be loaded into eq_tail. |
| 1418 | wire eq_tail_tail_hw_ld_1; // Hardware load enable for eq_tail_tail. When set, |
| 1419 | // <hw write signal> will be loaded into eq_tail. |
| 1420 | wire eq_tail_tail_hw_ld_2; // Hardware load enable for eq_tail_tail. When set, |
| 1421 | // <hw write signal> will be loaded into eq_tail. |
| 1422 | wire eq_tail_tail_hw_ld_3; // Hardware load enable for eq_tail_tail. When set, |
| 1423 | // <hw write signal> will be loaded into eq_tail. |
| 1424 | wire eq_tail_tail_hw_ld_4; // Hardware load enable for eq_tail_tail. When set, |
| 1425 | // <hw write signal> will be loaded into eq_tail. |
| 1426 | wire eq_tail_tail_hw_ld_5; // Hardware load enable for eq_tail_tail. When set, |
| 1427 | // <hw write signal> will be loaded into eq_tail. |
| 1428 | wire eq_tail_tail_hw_ld_6; // Hardware load enable for eq_tail_tail. When set, |
| 1429 | // <hw write signal> will be loaded into eq_tail. |
| 1430 | wire eq_tail_tail_hw_ld_7; // Hardware load enable for eq_tail_tail. When set, |
| 1431 | // <hw write signal> will be loaded into eq_tail. |
| 1432 | wire eq_tail_tail_hw_ld_8; // Hardware load enable for eq_tail_tail. When set, |
| 1433 | // <hw write signal> will be loaded into eq_tail. |
| 1434 | wire eq_tail_tail_hw_ld_9; // Hardware load enable for eq_tail_tail. When set, |
| 1435 | // <hw write signal> will be loaded into eq_tail. |
| 1436 | wire eq_tail_tail_hw_ld_10; // Hardware load enable for eq_tail_tail. When set, |
| 1437 | // <hw write signal> will be loaded into eq_tail. |
| 1438 | wire eq_tail_tail_hw_ld_11; // Hardware load enable for eq_tail_tail. When set, |
| 1439 | // <hw write signal> will be loaded into eq_tail. |
| 1440 | wire eq_tail_tail_hw_ld_12; // Hardware load enable for eq_tail_tail. When set, |
| 1441 | // <hw write signal> will be loaded into eq_tail. |
| 1442 | wire eq_tail_tail_hw_ld_13; // Hardware load enable for eq_tail_tail. When set, |
| 1443 | // <hw write signal> will be loaded into eq_tail. |
| 1444 | wire eq_tail_tail_hw_ld_14; // Hardware load enable for eq_tail_tail. When set, |
| 1445 | // <hw write signal> will be loaded into eq_tail. |
| 1446 | wire eq_tail_tail_hw_ld_15; // Hardware load enable for eq_tail_tail. When set, |
| 1447 | // <hw write signal> will be loaded into eq_tail. |
| 1448 | wire eq_tail_tail_hw_ld_16; // Hardware load enable for eq_tail_tail. When set, |
| 1449 | // <hw write signal> will be loaded into eq_tail. |
| 1450 | wire eq_tail_tail_hw_ld_17; // Hardware load enable for eq_tail_tail. When set, |
| 1451 | // <hw write signal> will be loaded into eq_tail. |
| 1452 | wire eq_tail_tail_hw_ld_18; // Hardware load enable for eq_tail_tail. When set, |
| 1453 | // <hw write signal> will be loaded into eq_tail. |
| 1454 | wire eq_tail_tail_hw_ld_19; // Hardware load enable for eq_tail_tail. When set, |
| 1455 | // <hw write signal> will be loaded into eq_tail. |
| 1456 | wire eq_tail_tail_hw_ld_20; // Hardware load enable for eq_tail_tail. When set, |
| 1457 | // <hw write signal> will be loaded into eq_tail. |
| 1458 | wire eq_tail_tail_hw_ld_21; // Hardware load enable for eq_tail_tail. When set, |
| 1459 | // <hw write signal> will be loaded into eq_tail. |
| 1460 | wire eq_tail_tail_hw_ld_22; // Hardware load enable for eq_tail_tail. When set, |
| 1461 | // <hw write signal> will be loaded into eq_tail. |
| 1462 | wire eq_tail_tail_hw_ld_23; // Hardware load enable for eq_tail_tail. When set, |
| 1463 | // <hw write signal> will be loaded into eq_tail. |
| 1464 | wire eq_tail_tail_hw_ld_24; // Hardware load enable for eq_tail_tail. When set, |
| 1465 | // <hw write signal> will be loaded into eq_tail. |
| 1466 | wire eq_tail_tail_hw_ld_25; // Hardware load enable for eq_tail_tail. When set, |
| 1467 | // <hw write signal> will be loaded into eq_tail. |
| 1468 | wire eq_tail_tail_hw_ld_26; // Hardware load enable for eq_tail_tail. When set, |
| 1469 | // <hw write signal> will be loaded into eq_tail. |
| 1470 | wire eq_tail_tail_hw_ld_27; // Hardware load enable for eq_tail_tail. When set, |
| 1471 | // <hw write signal> will be loaded into eq_tail. |
| 1472 | wire eq_tail_tail_hw_ld_28; // Hardware load enable for eq_tail_tail. When set, |
| 1473 | // <hw write signal> will be loaded into eq_tail. |
| 1474 | wire eq_tail_tail_hw_ld_29; // Hardware load enable for eq_tail_tail. When set, |
| 1475 | // <hw write signal> will be loaded into eq_tail. |
| 1476 | wire eq_tail_tail_hw_ld_30; // Hardware load enable for eq_tail_tail. When set, |
| 1477 | // <hw write signal> will be loaded into eq_tail. |
| 1478 | wire eq_tail_tail_hw_ld_31; // Hardware load enable for eq_tail_tail. When set, |
| 1479 | // <hw write signal> will be loaded into eq_tail. |
| 1480 | wire eq_tail_tail_hw_ld_32; // Hardware load enable for eq_tail_tail. When set, |
| 1481 | // <hw write signal> will be loaded into eq_tail. |
| 1482 | wire eq_tail_tail_hw_ld_33; // Hardware load enable for eq_tail_tail. When set, |
| 1483 | // <hw write signal> will be loaded into eq_tail. |
| 1484 | wire eq_tail_tail_hw_ld_34; // Hardware load enable for eq_tail_tail. When set, |
| 1485 | // <hw write signal> will be loaded into eq_tail. |
| 1486 | wire eq_tail_tail_hw_ld_35; // Hardware load enable for eq_tail_tail. When set, |
| 1487 | // <hw write signal> will be loaded into eq_tail. |
| 1488 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_0; |
| 1489 | // data bus for hw loading of eq_tail_tail. |
| 1490 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_1; |
| 1491 | // data bus for hw loading of eq_tail_tail. |
| 1492 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_2; |
| 1493 | // data bus for hw loading of eq_tail_tail. |
| 1494 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_3; |
| 1495 | // data bus for hw loading of eq_tail_tail. |
| 1496 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_4; |
| 1497 | // data bus for hw loading of eq_tail_tail. |
| 1498 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_5; |
| 1499 | // data bus for hw loading of eq_tail_tail. |
| 1500 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_6; |
| 1501 | // data bus for hw loading of eq_tail_tail. |
| 1502 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_7; |
| 1503 | // data bus for hw loading of eq_tail_tail. |
| 1504 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_8; |
| 1505 | // data bus for hw loading of eq_tail_tail. |
| 1506 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_9; |
| 1507 | // data bus for hw loading of eq_tail_tail. |
| 1508 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_10; |
| 1509 | // data bus for hw loading of eq_tail_tail. |
| 1510 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_11; |
| 1511 | // data bus for hw loading of eq_tail_tail. |
| 1512 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_12; |
| 1513 | // data bus for hw loading of eq_tail_tail. |
| 1514 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_13; |
| 1515 | // data bus for hw loading of eq_tail_tail. |
| 1516 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_14; |
| 1517 | // data bus for hw loading of eq_tail_tail. |
| 1518 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_15; |
| 1519 | // data bus for hw loading of eq_tail_tail. |
| 1520 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_16; |
| 1521 | // data bus for hw loading of eq_tail_tail. |
| 1522 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_17; |
| 1523 | // data bus for hw loading of eq_tail_tail. |
| 1524 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_18; |
| 1525 | // data bus for hw loading of eq_tail_tail. |
| 1526 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_19; |
| 1527 | // data bus for hw loading of eq_tail_tail. |
| 1528 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_20; |
| 1529 | // data bus for hw loading of eq_tail_tail. |
| 1530 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_21; |
| 1531 | // data bus for hw loading of eq_tail_tail. |
| 1532 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_22; |
| 1533 | // data bus for hw loading of eq_tail_tail. |
| 1534 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_23; |
| 1535 | // data bus for hw loading of eq_tail_tail. |
| 1536 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_24; |
| 1537 | // data bus for hw loading of eq_tail_tail. |
| 1538 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_25; |
| 1539 | // data bus for hw loading of eq_tail_tail. |
| 1540 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_26; |
| 1541 | // data bus for hw loading of eq_tail_tail. |
| 1542 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_27; |
| 1543 | // data bus for hw loading of eq_tail_tail. |
| 1544 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_28; |
| 1545 | // data bus for hw loading of eq_tail_tail. |
| 1546 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_29; |
| 1547 | // data bus for hw loading of eq_tail_tail. |
| 1548 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_30; |
| 1549 | // data bus for hw loading of eq_tail_tail. |
| 1550 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_31; |
| 1551 | // data bus for hw loading of eq_tail_tail. |
| 1552 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_32; |
| 1553 | // data bus for hw loading of eq_tail_tail. |
| 1554 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_33; |
| 1555 | // data bus for hw loading of eq_tail_tail. |
| 1556 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_34; |
| 1557 | // data bus for hw loading of eq_tail_tail. |
| 1558 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_35; |
| 1559 | // data bus for hw loading of eq_tail_tail. |
| 1560 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_0; |
| 1561 | // This signal provides the current value of eq_tail_tail. |
| 1562 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_1; |
| 1563 | // This signal provides the current value of eq_tail_tail. |
| 1564 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_2; |
| 1565 | // This signal provides the current value of eq_tail_tail. |
| 1566 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_3; |
| 1567 | // This signal provides the current value of eq_tail_tail. |
| 1568 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_4; |
| 1569 | // This signal provides the current value of eq_tail_tail. |
| 1570 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_5; |
| 1571 | // This signal provides the current value of eq_tail_tail. |
| 1572 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_6; |
| 1573 | // This signal provides the current value of eq_tail_tail. |
| 1574 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_7; |
| 1575 | // This signal provides the current value of eq_tail_tail. |
| 1576 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_8; |
| 1577 | // This signal provides the current value of eq_tail_tail. |
| 1578 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_9; |
| 1579 | // This signal provides the current value of eq_tail_tail. |
| 1580 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_10; |
| 1581 | // This signal provides the current value of eq_tail_tail. |
| 1582 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_11; |
| 1583 | // This signal provides the current value of eq_tail_tail. |
| 1584 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_12; |
| 1585 | // This signal provides the current value of eq_tail_tail. |
| 1586 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_13; |
| 1587 | // This signal provides the current value of eq_tail_tail. |
| 1588 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_14; |
| 1589 | // This signal provides the current value of eq_tail_tail. |
| 1590 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_15; |
| 1591 | // This signal provides the current value of eq_tail_tail. |
| 1592 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_16; |
| 1593 | // This signal provides the current value of eq_tail_tail. |
| 1594 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_17; |
| 1595 | // This signal provides the current value of eq_tail_tail. |
| 1596 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_18; |
| 1597 | // This signal provides the current value of eq_tail_tail. |
| 1598 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_19; |
| 1599 | // This signal provides the current value of eq_tail_tail. |
| 1600 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_20; |
| 1601 | // This signal provides the current value of eq_tail_tail. |
| 1602 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_21; |
| 1603 | // This signal provides the current value of eq_tail_tail. |
| 1604 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_22; |
| 1605 | // This signal provides the current value of eq_tail_tail. |
| 1606 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_23; |
| 1607 | // This signal provides the current value of eq_tail_tail. |
| 1608 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_24; |
| 1609 | // This signal provides the current value of eq_tail_tail. |
| 1610 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_25; |
| 1611 | // This signal provides the current value of eq_tail_tail. |
| 1612 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_26; |
| 1613 | // This signal provides the current value of eq_tail_tail. |
| 1614 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_27; |
| 1615 | // This signal provides the current value of eq_tail_tail. |
| 1616 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_28; |
| 1617 | // This signal provides the current value of eq_tail_tail. |
| 1618 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_29; |
| 1619 | // This signal provides the current value of eq_tail_tail. |
| 1620 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_30; |
| 1621 | // This signal provides the current value of eq_tail_tail. |
| 1622 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_31; |
| 1623 | // This signal provides the current value of eq_tail_tail. |
| 1624 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_32; |
| 1625 | // This signal provides the current value of eq_tail_tail. |
| 1626 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_33; |
| 1627 | // This signal provides the current value of eq_tail_tail. |
| 1628 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_34; |
| 1629 | // This signal provides the current value of eq_tail_tail. |
| 1630 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_35; |
| 1631 | // This signal provides the current value of eq_tail_tail. |
| 1632 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_0; |
| 1633 | // This signal provides the current value of eq_head_head. |
| 1634 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_1; |
| 1635 | // This signal provides the current value of eq_head_head. |
| 1636 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_2; |
| 1637 | // This signal provides the current value of eq_head_head. |
| 1638 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_3; |
| 1639 | // This signal provides the current value of eq_head_head. |
| 1640 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_4; |
| 1641 | // This signal provides the current value of eq_head_head. |
| 1642 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_5; |
| 1643 | // This signal provides the current value of eq_head_head. |
| 1644 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_6; |
| 1645 | // This signal provides the current value of eq_head_head. |
| 1646 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_7; |
| 1647 | // This signal provides the current value of eq_head_head. |
| 1648 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_8; |
| 1649 | // This signal provides the current value of eq_head_head. |
| 1650 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_9; |
| 1651 | // This signal provides the current value of eq_head_head. |
| 1652 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_10; |
| 1653 | // This signal provides the current value of eq_head_head. |
| 1654 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_11; |
| 1655 | // This signal provides the current value of eq_head_head. |
| 1656 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_12; |
| 1657 | // This signal provides the current value of eq_head_head. |
| 1658 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_13; |
| 1659 | // This signal provides the current value of eq_head_head. |
| 1660 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_14; |
| 1661 | // This signal provides the current value of eq_head_head. |
| 1662 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_15; |
| 1663 | // This signal provides the current value of eq_head_head. |
| 1664 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_16; |
| 1665 | // This signal provides the current value of eq_head_head. |
| 1666 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_17; |
| 1667 | // This signal provides the current value of eq_head_head. |
| 1668 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_18; |
| 1669 | // This signal provides the current value of eq_head_head. |
| 1670 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_19; |
| 1671 | // This signal provides the current value of eq_head_head. |
| 1672 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_20; |
| 1673 | // This signal provides the current value of eq_head_head. |
| 1674 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_21; |
| 1675 | // This signal provides the current value of eq_head_head. |
| 1676 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_22; |
| 1677 | // This signal provides the current value of eq_head_head. |
| 1678 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_23; |
| 1679 | // This signal provides the current value of eq_head_head. |
| 1680 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_24; |
| 1681 | // This signal provides the current value of eq_head_head. |
| 1682 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_25; |
| 1683 | // This signal provides the current value of eq_head_head. |
| 1684 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_26; |
| 1685 | // This signal provides the current value of eq_head_head. |
| 1686 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_27; |
| 1687 | // This signal provides the current value of eq_head_head. |
| 1688 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_28; |
| 1689 | // This signal provides the current value of eq_head_head. |
| 1690 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_29; |
| 1691 | // This signal provides the current value of eq_head_head. |
| 1692 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_30; |
| 1693 | // This signal provides the current value of eq_head_head. |
| 1694 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_31; |
| 1695 | // This signal provides the current value of eq_head_head. |
| 1696 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_32; |
| 1697 | // This signal provides the current value of eq_head_head. |
| 1698 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_33; |
| 1699 | // This signal provides the current value of eq_head_head. |
| 1700 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_34; |
| 1701 | // This signal provides the current value of eq_head_head. |
| 1702 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_35; |
| 1703 | // This signal provides the current value of eq_head_head. |
| 1704 | |
| 1705 | //==================================================== |
| 1706 | // Logic |
| 1707 | //==================================================== |
| 1708 | wire daemon_transaction_in_progress; |
| 1709 | wire daemon_csrbus_mapped; |
| 1710 | wire daemon_csrbus_valid; |
| 1711 | // vlint flag_dangling_net_within_module off |
| 1712 | // vlint flag_net_has_no_load off |
| 1713 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp; |
| 1714 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; |
| 1715 | // vlint flag_dangling_net_within_module on |
| 1716 | // vlint flag_net_has_no_load on |
| 1717 | wire daemon_csrbus_done; |
| 1718 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr; |
| 1719 | wire daemon_csrbus_wr_tmp; |
| 1720 | wire daemon_csrbus_wr; |
| 1721 | |
| 1722 | //summit modcovoff -bepgnv |
| 1723 | pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon ( |
| 1724 | .daemon_csrbus_valid (daemon_csrbus_valid), |
| 1725 | .daemon_csrbus_mapped (daemon_csrbus_mapped), |
| 1726 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp), |
| 1727 | .daemon_csrbus_done (daemon_csrbus_done), |
| 1728 | .daemon_csrbus_addr (daemon_csrbus_addr), |
| 1729 | .daemon_csrbus_wr (daemon_csrbus_wr_tmp), |
| 1730 | .daemon_transaction_in_progress (daemon_transaction_in_progress), |
| 1731 | // synopsys translate_off |
| 1732 | .clk(clk), |
| 1733 | .csrbus_read_data (csrbus_read_data), |
| 1734 | .rst_l (rst_l), |
| 1735 | // synopsys translate_on |
| 1736 | .csrbus_valid (csrbus_valid), |
| 1737 | .csrbus_mapped (csrbus_mapped), |
| 1738 | .csrbus_wr_data (csrbus_wr_data), |
| 1739 | .csrbus_done (csrbus_done), |
| 1740 | .csrbus_addr (csrbus_addr), |
| 1741 | .csrbus_wr (csrbus_wr) |
| 1742 | ); |
| 1743 | //summit modcovon -bepgnv |
| 1744 | |
| 1745 | //==================================================================== |
| 1746 | // Address decode |
| 1747 | //==================================================================== |
| 1748 | wire eq_base_address_select_pulse; |
| 1749 | wire eq_ctrl_set_select_0; |
| 1750 | wire eq_ctrl_set_select_1; |
| 1751 | wire eq_ctrl_set_select_2; |
| 1752 | wire eq_ctrl_set_select_3; |
| 1753 | wire eq_ctrl_set_select_4; |
| 1754 | wire eq_ctrl_set_select_5; |
| 1755 | wire eq_ctrl_set_select_6; |
| 1756 | wire eq_ctrl_set_select_7; |
| 1757 | wire eq_ctrl_set_select_8; |
| 1758 | wire eq_ctrl_set_select_9; |
| 1759 | wire eq_ctrl_set_select_10; |
| 1760 | wire eq_ctrl_set_select_11; |
| 1761 | wire eq_ctrl_set_select_12; |
| 1762 | wire eq_ctrl_set_select_13; |
| 1763 | wire eq_ctrl_set_select_14; |
| 1764 | wire eq_ctrl_set_select_15; |
| 1765 | wire eq_ctrl_set_select_16; |
| 1766 | wire eq_ctrl_set_select_17; |
| 1767 | wire eq_ctrl_set_select_18; |
| 1768 | wire eq_ctrl_set_select_19; |
| 1769 | wire eq_ctrl_set_select_20; |
| 1770 | wire eq_ctrl_set_select_21; |
| 1771 | wire eq_ctrl_set_select_22; |
| 1772 | wire eq_ctrl_set_select_23; |
| 1773 | wire eq_ctrl_set_select_24; |
| 1774 | wire eq_ctrl_set_select_25; |
| 1775 | wire eq_ctrl_set_select_26; |
| 1776 | wire eq_ctrl_set_select_27; |
| 1777 | wire eq_ctrl_set_select_28; |
| 1778 | wire eq_ctrl_set_select_29; |
| 1779 | wire eq_ctrl_set_select_30; |
| 1780 | wire eq_ctrl_set_select_31; |
| 1781 | wire eq_ctrl_set_select_32; |
| 1782 | wire eq_ctrl_set_select_33; |
| 1783 | wire eq_ctrl_set_select_34; |
| 1784 | wire eq_ctrl_set_select_35; |
| 1785 | wire eq_ctrl_clr_select_0; |
| 1786 | wire eq_ctrl_clr_select_1; |
| 1787 | wire eq_ctrl_clr_select_2; |
| 1788 | wire eq_ctrl_clr_select_3; |
| 1789 | wire eq_ctrl_clr_select_4; |
| 1790 | wire eq_ctrl_clr_select_5; |
| 1791 | wire eq_ctrl_clr_select_6; |
| 1792 | wire eq_ctrl_clr_select_7; |
| 1793 | wire eq_ctrl_clr_select_8; |
| 1794 | wire eq_ctrl_clr_select_9; |
| 1795 | wire eq_ctrl_clr_select_10; |
| 1796 | wire eq_ctrl_clr_select_11; |
| 1797 | wire eq_ctrl_clr_select_12; |
| 1798 | wire eq_ctrl_clr_select_13; |
| 1799 | wire eq_ctrl_clr_select_14; |
| 1800 | wire eq_ctrl_clr_select_15; |
| 1801 | wire eq_ctrl_clr_select_16; |
| 1802 | wire eq_ctrl_clr_select_17; |
| 1803 | wire eq_ctrl_clr_select_18; |
| 1804 | wire eq_ctrl_clr_select_19; |
| 1805 | wire eq_ctrl_clr_select_20; |
| 1806 | wire eq_ctrl_clr_select_21; |
| 1807 | wire eq_ctrl_clr_select_22; |
| 1808 | wire eq_ctrl_clr_select_23; |
| 1809 | wire eq_ctrl_clr_select_24; |
| 1810 | wire eq_ctrl_clr_select_25; |
| 1811 | wire eq_ctrl_clr_select_26; |
| 1812 | wire eq_ctrl_clr_select_27; |
| 1813 | wire eq_ctrl_clr_select_28; |
| 1814 | wire eq_ctrl_clr_select_29; |
| 1815 | wire eq_ctrl_clr_select_30; |
| 1816 | wire eq_ctrl_clr_select_31; |
| 1817 | wire eq_ctrl_clr_select_32; |
| 1818 | wire eq_ctrl_clr_select_33; |
| 1819 | wire eq_ctrl_clr_select_34; |
| 1820 | wire eq_ctrl_clr_select_35; |
| 1821 | wire eq_state_select_0; |
| 1822 | wire eq_state_select_1; |
| 1823 | wire eq_state_select_2; |
| 1824 | wire eq_state_select_3; |
| 1825 | wire eq_state_select_4; |
| 1826 | wire eq_state_select_5; |
| 1827 | wire eq_state_select_6; |
| 1828 | wire eq_state_select_7; |
| 1829 | wire eq_state_select_8; |
| 1830 | wire eq_state_select_9; |
| 1831 | wire eq_state_select_10; |
| 1832 | wire eq_state_select_11; |
| 1833 | wire eq_state_select_12; |
| 1834 | wire eq_state_select_13; |
| 1835 | wire eq_state_select_14; |
| 1836 | wire eq_state_select_15; |
| 1837 | wire eq_state_select_16; |
| 1838 | wire eq_state_select_17; |
| 1839 | wire eq_state_select_18; |
| 1840 | wire eq_state_select_19; |
| 1841 | wire eq_state_select_20; |
| 1842 | wire eq_state_select_21; |
| 1843 | wire eq_state_select_22; |
| 1844 | wire eq_state_select_23; |
| 1845 | wire eq_state_select_24; |
| 1846 | wire eq_state_select_25; |
| 1847 | wire eq_state_select_26; |
| 1848 | wire eq_state_select_27; |
| 1849 | wire eq_state_select_28; |
| 1850 | wire eq_state_select_29; |
| 1851 | wire eq_state_select_30; |
| 1852 | wire eq_state_select_31; |
| 1853 | wire eq_state_select_32; |
| 1854 | wire eq_state_select_33; |
| 1855 | wire eq_state_select_34; |
| 1856 | wire eq_state_select_35; |
| 1857 | wire eq_tail_select_pulse_0; |
| 1858 | wire eq_tail_select_pulse_1; |
| 1859 | wire eq_tail_select_pulse_2; |
| 1860 | wire eq_tail_select_pulse_3; |
| 1861 | wire eq_tail_select_pulse_4; |
| 1862 | wire eq_tail_select_pulse_5; |
| 1863 | wire eq_tail_select_pulse_6; |
| 1864 | wire eq_tail_select_pulse_7; |
| 1865 | wire eq_tail_select_pulse_8; |
| 1866 | wire eq_tail_select_pulse_9; |
| 1867 | wire eq_tail_select_pulse_10; |
| 1868 | wire eq_tail_select_pulse_11; |
| 1869 | wire eq_tail_select_pulse_12; |
| 1870 | wire eq_tail_select_pulse_13; |
| 1871 | wire eq_tail_select_pulse_14; |
| 1872 | wire eq_tail_select_pulse_15; |
| 1873 | wire eq_tail_select_pulse_16; |
| 1874 | wire eq_tail_select_pulse_17; |
| 1875 | wire eq_tail_select_pulse_18; |
| 1876 | wire eq_tail_select_pulse_19; |
| 1877 | wire eq_tail_select_pulse_20; |
| 1878 | wire eq_tail_select_pulse_21; |
| 1879 | wire eq_tail_select_pulse_22; |
| 1880 | wire eq_tail_select_pulse_23; |
| 1881 | wire eq_tail_select_pulse_24; |
| 1882 | wire eq_tail_select_pulse_25; |
| 1883 | wire eq_tail_select_pulse_26; |
| 1884 | wire eq_tail_select_pulse_27; |
| 1885 | wire eq_tail_select_pulse_28; |
| 1886 | wire eq_tail_select_pulse_29; |
| 1887 | wire eq_tail_select_pulse_30; |
| 1888 | wire eq_tail_select_pulse_31; |
| 1889 | wire eq_tail_select_pulse_32; |
| 1890 | wire eq_tail_select_pulse_33; |
| 1891 | wire eq_tail_select_pulse_34; |
| 1892 | wire eq_tail_select_pulse_35; |
| 1893 | wire eq_head_select_pulse_0; |
| 1894 | wire eq_head_select_pulse_1; |
| 1895 | wire eq_head_select_pulse_2; |
| 1896 | wire eq_head_select_pulse_3; |
| 1897 | wire eq_head_select_pulse_4; |
| 1898 | wire eq_head_select_pulse_5; |
| 1899 | wire eq_head_select_pulse_6; |
| 1900 | wire eq_head_select_pulse_7; |
| 1901 | wire eq_head_select_pulse_8; |
| 1902 | wire eq_head_select_pulse_9; |
| 1903 | wire eq_head_select_pulse_10; |
| 1904 | wire eq_head_select_pulse_11; |
| 1905 | wire eq_head_select_pulse_12; |
| 1906 | wire eq_head_select_pulse_13; |
| 1907 | wire eq_head_select_pulse_14; |
| 1908 | wire eq_head_select_pulse_15; |
| 1909 | wire eq_head_select_pulse_16; |
| 1910 | wire eq_head_select_pulse_17; |
| 1911 | wire eq_head_select_pulse_18; |
| 1912 | wire eq_head_select_pulse_19; |
| 1913 | wire eq_head_select_pulse_20; |
| 1914 | wire eq_head_select_pulse_21; |
| 1915 | wire eq_head_select_pulse_22; |
| 1916 | wire eq_head_select_pulse_23; |
| 1917 | wire eq_head_select_pulse_24; |
| 1918 | wire eq_head_select_pulse_25; |
| 1919 | wire eq_head_select_pulse_26; |
| 1920 | wire eq_head_select_pulse_27; |
| 1921 | wire eq_head_select_pulse_28; |
| 1922 | wire eq_head_select_pulse_29; |
| 1923 | wire eq_head_select_pulse_30; |
| 1924 | wire eq_head_select_pulse_31; |
| 1925 | wire eq_head_select_pulse_32; |
| 1926 | wire eq_head_select_pulse_33; |
| 1927 | wire eq_head_select_pulse_34; |
| 1928 | wire eq_head_select_pulse_35; |
| 1929 | |
| 1930 | dmu_imu_eqs_addr_decode dmu_imu_eqs_addr_decode |
| 1931 | ( |
| 1932 | .clk (clk), |
| 1933 | .rst_l (rst_l), |
| 1934 | .daemon_csrbus_valid (daemon_csrbus_valid), |
| 1935 | .daemon_csrbus_addr (daemon_csrbus_addr), |
| 1936 | .csrbus_src_bus (csrbus_src_bus), |
| 1937 | .daemon_csrbus_wr (daemon_csrbus_wr_tmp), |
| 1938 | .daemon_csrbus_wr_out (daemon_csrbus_wr), |
| 1939 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp), |
| 1940 | .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data), |
| 1941 | .daemon_csrbus_mapped (daemon_csrbus_mapped), |
| 1942 | .csrbus_acc_vio (csrbus_acc_vio), |
| 1943 | .daemon_transaction_in_progress (daemon_transaction_in_progress), |
| 1944 | .instance_id (instance_id), |
| 1945 | .daemon_csrbus_done (daemon_csrbus_done), |
| 1946 | .eq_base_address_select_pulse (eq_base_address_select_pulse), |
| 1947 | .eq_ctrl_set_select_0 (eq_ctrl_set_select_0), |
| 1948 | .eq_ctrl_set_select_1 (eq_ctrl_set_select_1), |
| 1949 | .eq_ctrl_set_select_2 (eq_ctrl_set_select_2), |
| 1950 | .eq_ctrl_set_select_3 (eq_ctrl_set_select_3), |
| 1951 | .eq_ctrl_set_select_4 (eq_ctrl_set_select_4), |
| 1952 | .eq_ctrl_set_select_5 (eq_ctrl_set_select_5), |
| 1953 | .eq_ctrl_set_select_6 (eq_ctrl_set_select_6), |
| 1954 | .eq_ctrl_set_select_7 (eq_ctrl_set_select_7), |
| 1955 | .eq_ctrl_set_select_8 (eq_ctrl_set_select_8), |
| 1956 | .eq_ctrl_set_select_9 (eq_ctrl_set_select_9), |
| 1957 | .eq_ctrl_set_select_10 (eq_ctrl_set_select_10), |
| 1958 | .eq_ctrl_set_select_11 (eq_ctrl_set_select_11), |
| 1959 | .eq_ctrl_set_select_12 (eq_ctrl_set_select_12), |
| 1960 | .eq_ctrl_set_select_13 (eq_ctrl_set_select_13), |
| 1961 | .eq_ctrl_set_select_14 (eq_ctrl_set_select_14), |
| 1962 | .eq_ctrl_set_select_15 (eq_ctrl_set_select_15), |
| 1963 | .eq_ctrl_set_select_16 (eq_ctrl_set_select_16), |
| 1964 | .eq_ctrl_set_select_17 (eq_ctrl_set_select_17), |
| 1965 | .eq_ctrl_set_select_18 (eq_ctrl_set_select_18), |
| 1966 | .eq_ctrl_set_select_19 (eq_ctrl_set_select_19), |
| 1967 | .eq_ctrl_set_select_20 (eq_ctrl_set_select_20), |
| 1968 | .eq_ctrl_set_select_21 (eq_ctrl_set_select_21), |
| 1969 | .eq_ctrl_set_select_22 (eq_ctrl_set_select_22), |
| 1970 | .eq_ctrl_set_select_23 (eq_ctrl_set_select_23), |
| 1971 | .eq_ctrl_set_select_24 (eq_ctrl_set_select_24), |
| 1972 | .eq_ctrl_set_select_25 (eq_ctrl_set_select_25), |
| 1973 | .eq_ctrl_set_select_26 (eq_ctrl_set_select_26), |
| 1974 | .eq_ctrl_set_select_27 (eq_ctrl_set_select_27), |
| 1975 | .eq_ctrl_set_select_28 (eq_ctrl_set_select_28), |
| 1976 | .eq_ctrl_set_select_29 (eq_ctrl_set_select_29), |
| 1977 | .eq_ctrl_set_select_30 (eq_ctrl_set_select_30), |
| 1978 | .eq_ctrl_set_select_31 (eq_ctrl_set_select_31), |
| 1979 | .eq_ctrl_set_select_32 (eq_ctrl_set_select_32), |
| 1980 | .eq_ctrl_set_select_33 (eq_ctrl_set_select_33), |
| 1981 | .eq_ctrl_set_select_34 (eq_ctrl_set_select_34), |
| 1982 | .eq_ctrl_set_select_35 (eq_ctrl_set_select_35), |
| 1983 | .eq_ctrl_clr_select_0 (eq_ctrl_clr_select_0), |
| 1984 | .eq_ctrl_clr_select_1 (eq_ctrl_clr_select_1), |
| 1985 | .eq_ctrl_clr_select_2 (eq_ctrl_clr_select_2), |
| 1986 | .eq_ctrl_clr_select_3 (eq_ctrl_clr_select_3), |
| 1987 | .eq_ctrl_clr_select_4 (eq_ctrl_clr_select_4), |
| 1988 | .eq_ctrl_clr_select_5 (eq_ctrl_clr_select_5), |
| 1989 | .eq_ctrl_clr_select_6 (eq_ctrl_clr_select_6), |
| 1990 | .eq_ctrl_clr_select_7 (eq_ctrl_clr_select_7), |
| 1991 | .eq_ctrl_clr_select_8 (eq_ctrl_clr_select_8), |
| 1992 | .eq_ctrl_clr_select_9 (eq_ctrl_clr_select_9), |
| 1993 | .eq_ctrl_clr_select_10 (eq_ctrl_clr_select_10), |
| 1994 | .eq_ctrl_clr_select_11 (eq_ctrl_clr_select_11), |
| 1995 | .eq_ctrl_clr_select_12 (eq_ctrl_clr_select_12), |
| 1996 | .eq_ctrl_clr_select_13 (eq_ctrl_clr_select_13), |
| 1997 | .eq_ctrl_clr_select_14 (eq_ctrl_clr_select_14), |
| 1998 | .eq_ctrl_clr_select_15 (eq_ctrl_clr_select_15), |
| 1999 | .eq_ctrl_clr_select_16 (eq_ctrl_clr_select_16), |
| 2000 | .eq_ctrl_clr_select_17 (eq_ctrl_clr_select_17), |
| 2001 | .eq_ctrl_clr_select_18 (eq_ctrl_clr_select_18), |
| 2002 | .eq_ctrl_clr_select_19 (eq_ctrl_clr_select_19), |
| 2003 | .eq_ctrl_clr_select_20 (eq_ctrl_clr_select_20), |
| 2004 | .eq_ctrl_clr_select_21 (eq_ctrl_clr_select_21), |
| 2005 | .eq_ctrl_clr_select_22 (eq_ctrl_clr_select_22), |
| 2006 | .eq_ctrl_clr_select_23 (eq_ctrl_clr_select_23), |
| 2007 | .eq_ctrl_clr_select_24 (eq_ctrl_clr_select_24), |
| 2008 | .eq_ctrl_clr_select_25 (eq_ctrl_clr_select_25), |
| 2009 | .eq_ctrl_clr_select_26 (eq_ctrl_clr_select_26), |
| 2010 | .eq_ctrl_clr_select_27 (eq_ctrl_clr_select_27), |
| 2011 | .eq_ctrl_clr_select_28 (eq_ctrl_clr_select_28), |
| 2012 | .eq_ctrl_clr_select_29 (eq_ctrl_clr_select_29), |
| 2013 | .eq_ctrl_clr_select_30 (eq_ctrl_clr_select_30), |
| 2014 | .eq_ctrl_clr_select_31 (eq_ctrl_clr_select_31), |
| 2015 | .eq_ctrl_clr_select_32 (eq_ctrl_clr_select_32), |
| 2016 | .eq_ctrl_clr_select_33 (eq_ctrl_clr_select_33), |
| 2017 | .eq_ctrl_clr_select_34 (eq_ctrl_clr_select_34), |
| 2018 | .eq_ctrl_clr_select_35 (eq_ctrl_clr_select_35), |
| 2019 | .eq_state_select_0 (eq_state_select_0), |
| 2020 | .eq_state_select_1 (eq_state_select_1), |
| 2021 | .eq_state_select_2 (eq_state_select_2), |
| 2022 | .eq_state_select_3 (eq_state_select_3), |
| 2023 | .eq_state_select_4 (eq_state_select_4), |
| 2024 | .eq_state_select_5 (eq_state_select_5), |
| 2025 | .eq_state_select_6 (eq_state_select_6), |
| 2026 | .eq_state_select_7 (eq_state_select_7), |
| 2027 | .eq_state_select_8 (eq_state_select_8), |
| 2028 | .eq_state_select_9 (eq_state_select_9), |
| 2029 | .eq_state_select_10 (eq_state_select_10), |
| 2030 | .eq_state_select_11 (eq_state_select_11), |
| 2031 | .eq_state_select_12 (eq_state_select_12), |
| 2032 | .eq_state_select_13 (eq_state_select_13), |
| 2033 | .eq_state_select_14 (eq_state_select_14), |
| 2034 | .eq_state_select_15 (eq_state_select_15), |
| 2035 | .eq_state_select_16 (eq_state_select_16), |
| 2036 | .eq_state_select_17 (eq_state_select_17), |
| 2037 | .eq_state_select_18 (eq_state_select_18), |
| 2038 | .eq_state_select_19 (eq_state_select_19), |
| 2039 | .eq_state_select_20 (eq_state_select_20), |
| 2040 | .eq_state_select_21 (eq_state_select_21), |
| 2041 | .eq_state_select_22 (eq_state_select_22), |
| 2042 | .eq_state_select_23 (eq_state_select_23), |
| 2043 | .eq_state_select_24 (eq_state_select_24), |
| 2044 | .eq_state_select_25 (eq_state_select_25), |
| 2045 | .eq_state_select_26 (eq_state_select_26), |
| 2046 | .eq_state_select_27 (eq_state_select_27), |
| 2047 | .eq_state_select_28 (eq_state_select_28), |
| 2048 | .eq_state_select_29 (eq_state_select_29), |
| 2049 | .eq_state_select_30 (eq_state_select_30), |
| 2050 | .eq_state_select_31 (eq_state_select_31), |
| 2051 | .eq_state_select_32 (eq_state_select_32), |
| 2052 | .eq_state_select_33 (eq_state_select_33), |
| 2053 | .eq_state_select_34 (eq_state_select_34), |
| 2054 | .eq_state_select_35 (eq_state_select_35), |
| 2055 | .eq_tail_select_pulse_0 (eq_tail_select_pulse_0), |
| 2056 | .eq_tail_select_pulse_1 (eq_tail_select_pulse_1), |
| 2057 | .eq_tail_select_pulse_2 (eq_tail_select_pulse_2), |
| 2058 | .eq_tail_select_pulse_3 (eq_tail_select_pulse_3), |
| 2059 | .eq_tail_select_pulse_4 (eq_tail_select_pulse_4), |
| 2060 | .eq_tail_select_pulse_5 (eq_tail_select_pulse_5), |
| 2061 | .eq_tail_select_pulse_6 (eq_tail_select_pulse_6), |
| 2062 | .eq_tail_select_pulse_7 (eq_tail_select_pulse_7), |
| 2063 | .eq_tail_select_pulse_8 (eq_tail_select_pulse_8), |
| 2064 | .eq_tail_select_pulse_9 (eq_tail_select_pulse_9), |
| 2065 | .eq_tail_select_pulse_10 (eq_tail_select_pulse_10), |
| 2066 | .eq_tail_select_pulse_11 (eq_tail_select_pulse_11), |
| 2067 | .eq_tail_select_pulse_12 (eq_tail_select_pulse_12), |
| 2068 | .eq_tail_select_pulse_13 (eq_tail_select_pulse_13), |
| 2069 | .eq_tail_select_pulse_14 (eq_tail_select_pulse_14), |
| 2070 | .eq_tail_select_pulse_15 (eq_tail_select_pulse_15), |
| 2071 | .eq_tail_select_pulse_16 (eq_tail_select_pulse_16), |
| 2072 | .eq_tail_select_pulse_17 (eq_tail_select_pulse_17), |
| 2073 | .eq_tail_select_pulse_18 (eq_tail_select_pulse_18), |
| 2074 | .eq_tail_select_pulse_19 (eq_tail_select_pulse_19), |
| 2075 | .eq_tail_select_pulse_20 (eq_tail_select_pulse_20), |
| 2076 | .eq_tail_select_pulse_21 (eq_tail_select_pulse_21), |
| 2077 | .eq_tail_select_pulse_22 (eq_tail_select_pulse_22), |
| 2078 | .eq_tail_select_pulse_23 (eq_tail_select_pulse_23), |
| 2079 | .eq_tail_select_pulse_24 (eq_tail_select_pulse_24), |
| 2080 | .eq_tail_select_pulse_25 (eq_tail_select_pulse_25), |
| 2081 | .eq_tail_select_pulse_26 (eq_tail_select_pulse_26), |
| 2082 | .eq_tail_select_pulse_27 (eq_tail_select_pulse_27), |
| 2083 | .eq_tail_select_pulse_28 (eq_tail_select_pulse_28), |
| 2084 | .eq_tail_select_pulse_29 (eq_tail_select_pulse_29), |
| 2085 | .eq_tail_select_pulse_30 (eq_tail_select_pulse_30), |
| 2086 | .eq_tail_select_pulse_31 (eq_tail_select_pulse_31), |
| 2087 | .eq_tail_select_pulse_32 (eq_tail_select_pulse_32), |
| 2088 | .eq_tail_select_pulse_33 (eq_tail_select_pulse_33), |
| 2089 | .eq_tail_select_pulse_34 (eq_tail_select_pulse_34), |
| 2090 | .eq_tail_select_pulse_35 (eq_tail_select_pulse_35), |
| 2091 | .eq_head_select_pulse_0 (eq_head_select_pulse_0), |
| 2092 | .eq_head_select_pulse_1 (eq_head_select_pulse_1), |
| 2093 | .eq_head_select_pulse_2 (eq_head_select_pulse_2), |
| 2094 | .eq_head_select_pulse_3 (eq_head_select_pulse_3), |
| 2095 | .eq_head_select_pulse_4 (eq_head_select_pulse_4), |
| 2096 | .eq_head_select_pulse_5 (eq_head_select_pulse_5), |
| 2097 | .eq_head_select_pulse_6 (eq_head_select_pulse_6), |
| 2098 | .eq_head_select_pulse_7 (eq_head_select_pulse_7), |
| 2099 | .eq_head_select_pulse_8 (eq_head_select_pulse_8), |
| 2100 | .eq_head_select_pulse_9 (eq_head_select_pulse_9), |
| 2101 | .eq_head_select_pulse_10 (eq_head_select_pulse_10), |
| 2102 | .eq_head_select_pulse_11 (eq_head_select_pulse_11), |
| 2103 | .eq_head_select_pulse_12 (eq_head_select_pulse_12), |
| 2104 | .eq_head_select_pulse_13 (eq_head_select_pulse_13), |
| 2105 | .eq_head_select_pulse_14 (eq_head_select_pulse_14), |
| 2106 | .eq_head_select_pulse_15 (eq_head_select_pulse_15), |
| 2107 | .eq_head_select_pulse_16 (eq_head_select_pulse_16), |
| 2108 | .eq_head_select_pulse_17 (eq_head_select_pulse_17), |
| 2109 | .eq_head_select_pulse_18 (eq_head_select_pulse_18), |
| 2110 | .eq_head_select_pulse_19 (eq_head_select_pulse_19), |
| 2111 | .eq_head_select_pulse_20 (eq_head_select_pulse_20), |
| 2112 | .eq_head_select_pulse_21 (eq_head_select_pulse_21), |
| 2113 | .eq_head_select_pulse_22 (eq_head_select_pulse_22), |
| 2114 | .eq_head_select_pulse_23 (eq_head_select_pulse_23), |
| 2115 | .eq_head_select_pulse_24 (eq_head_select_pulse_24), |
| 2116 | .eq_head_select_pulse_25 (eq_head_select_pulse_25), |
| 2117 | .eq_head_select_pulse_26 (eq_head_select_pulse_26), |
| 2118 | .eq_head_select_pulse_27 (eq_head_select_pulse_27), |
| 2119 | .eq_head_select_pulse_28 (eq_head_select_pulse_28), |
| 2120 | .eq_head_select_pulse_29 (eq_head_select_pulse_29), |
| 2121 | .eq_head_select_pulse_30 (eq_head_select_pulse_30), |
| 2122 | .eq_head_select_pulse_31 (eq_head_select_pulse_31), |
| 2123 | .eq_head_select_pulse_32 (eq_head_select_pulse_32), |
| 2124 | .eq_head_select_pulse_33 (eq_head_select_pulse_33), |
| 2125 | .eq_head_select_pulse_34 (eq_head_select_pulse_34), |
| 2126 | .eq_head_select_pulse_35 (eq_head_select_pulse_35) |
| 2127 | ); |
| 2128 | |
| 2129 | //==================================================================== |
| 2130 | // OUTPUT: csrbus_read_data (pipelining) |
| 2131 | //==================================================================== |
| 2132 | //----- connecting wires |
| 2133 | wire stage_mux_only_rst_l; |
| 2134 | wire stage_mux_only_daemon_csrbus_wr; |
| 2135 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data; |
| 2136 | |
| 2137 | //----- Stage: 1 / Grp: default_grp (109 inputs / 1 outputs) |
| 2138 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out; |
| 2139 | wire default_grp_eq_base_address_select_pulse; |
| 2140 | wire default_grp_eq_ctrl_set_select_0; |
| 2141 | wire default_grp_eq_ctrl_set_select_1; |
| 2142 | wire default_grp_eq_ctrl_set_select_2; |
| 2143 | wire default_grp_eq_ctrl_set_select_3; |
| 2144 | wire default_grp_eq_ctrl_set_select_4; |
| 2145 | wire default_grp_eq_ctrl_set_select_5; |
| 2146 | wire default_grp_eq_ctrl_set_select_6; |
| 2147 | wire default_grp_eq_ctrl_set_select_7; |
| 2148 | wire default_grp_eq_ctrl_set_select_8; |
| 2149 | wire default_grp_eq_ctrl_set_select_9; |
| 2150 | wire default_grp_eq_ctrl_set_select_10; |
| 2151 | wire default_grp_eq_ctrl_set_select_11; |
| 2152 | wire default_grp_eq_ctrl_set_select_12; |
| 2153 | wire default_grp_eq_ctrl_set_select_13; |
| 2154 | wire default_grp_eq_ctrl_set_select_14; |
| 2155 | wire default_grp_eq_ctrl_set_select_15; |
| 2156 | wire default_grp_eq_ctrl_set_select_16; |
| 2157 | wire default_grp_eq_ctrl_set_select_17; |
| 2158 | wire default_grp_eq_ctrl_set_select_18; |
| 2159 | wire default_grp_eq_ctrl_set_select_19; |
| 2160 | wire default_grp_eq_ctrl_set_select_20; |
| 2161 | wire default_grp_eq_ctrl_set_select_21; |
| 2162 | wire default_grp_eq_ctrl_set_select_22; |
| 2163 | wire default_grp_eq_ctrl_set_select_23; |
| 2164 | wire default_grp_eq_ctrl_set_select_24; |
| 2165 | wire default_grp_eq_ctrl_set_select_25; |
| 2166 | wire default_grp_eq_ctrl_set_select_26; |
| 2167 | wire default_grp_eq_ctrl_set_select_27; |
| 2168 | wire default_grp_eq_ctrl_set_select_28; |
| 2169 | wire default_grp_eq_ctrl_set_select_29; |
| 2170 | wire default_grp_eq_ctrl_set_select_30; |
| 2171 | wire default_grp_eq_ctrl_set_select_31; |
| 2172 | wire default_grp_eq_ctrl_set_select_32; |
| 2173 | wire default_grp_eq_ctrl_set_select_33; |
| 2174 | wire default_grp_eq_ctrl_set_select_34; |
| 2175 | wire default_grp_eq_ctrl_set_select_35; |
| 2176 | wire default_grp_eq_ctrl_clr_select_0; |
| 2177 | wire default_grp_eq_ctrl_clr_select_1; |
| 2178 | wire default_grp_eq_ctrl_clr_select_2; |
| 2179 | wire default_grp_eq_ctrl_clr_select_3; |
| 2180 | wire default_grp_eq_ctrl_clr_select_4; |
| 2181 | wire default_grp_eq_ctrl_clr_select_5; |
| 2182 | wire default_grp_eq_ctrl_clr_select_6; |
| 2183 | wire default_grp_eq_ctrl_clr_select_7; |
| 2184 | wire default_grp_eq_ctrl_clr_select_8; |
| 2185 | wire default_grp_eq_ctrl_clr_select_9; |
| 2186 | wire default_grp_eq_ctrl_clr_select_10; |
| 2187 | wire default_grp_eq_ctrl_clr_select_11; |
| 2188 | wire default_grp_eq_ctrl_clr_select_12; |
| 2189 | wire default_grp_eq_ctrl_clr_select_13; |
| 2190 | wire default_grp_eq_ctrl_clr_select_14; |
| 2191 | wire default_grp_eq_ctrl_clr_select_15; |
| 2192 | wire default_grp_eq_ctrl_clr_select_16; |
| 2193 | wire default_grp_eq_ctrl_clr_select_17; |
| 2194 | wire default_grp_eq_ctrl_clr_select_18; |
| 2195 | wire default_grp_eq_ctrl_clr_select_19; |
| 2196 | wire default_grp_eq_ctrl_clr_select_20; |
| 2197 | wire default_grp_eq_ctrl_clr_select_21; |
| 2198 | wire default_grp_eq_ctrl_clr_select_22; |
| 2199 | wire default_grp_eq_ctrl_clr_select_23; |
| 2200 | wire default_grp_eq_ctrl_clr_select_24; |
| 2201 | wire default_grp_eq_ctrl_clr_select_25; |
| 2202 | wire default_grp_eq_ctrl_clr_select_26; |
| 2203 | wire default_grp_eq_ctrl_clr_select_27; |
| 2204 | wire default_grp_eq_ctrl_clr_select_28; |
| 2205 | wire default_grp_eq_ctrl_clr_select_29; |
| 2206 | wire default_grp_eq_ctrl_clr_select_30; |
| 2207 | wire default_grp_eq_ctrl_clr_select_31; |
| 2208 | wire default_grp_eq_ctrl_clr_select_32; |
| 2209 | wire default_grp_eq_ctrl_clr_select_33; |
| 2210 | wire default_grp_eq_ctrl_clr_select_34; |
| 2211 | wire default_grp_eq_ctrl_clr_select_35; |
| 2212 | wire default_grp_eq_state_select_0; |
| 2213 | wire default_grp_eq_state_select_1; |
| 2214 | wire default_grp_eq_state_select_2; |
| 2215 | wire default_grp_eq_state_select_3; |
| 2216 | wire default_grp_eq_state_select_4; |
| 2217 | wire default_grp_eq_state_select_5; |
| 2218 | wire default_grp_eq_state_select_6; |
| 2219 | wire default_grp_eq_state_select_7; |
| 2220 | wire default_grp_eq_state_select_8; |
| 2221 | wire default_grp_eq_state_select_9; |
| 2222 | wire default_grp_eq_state_select_10; |
| 2223 | wire default_grp_eq_state_select_11; |
| 2224 | wire default_grp_eq_state_select_12; |
| 2225 | wire default_grp_eq_state_select_13; |
| 2226 | wire default_grp_eq_state_select_14; |
| 2227 | wire default_grp_eq_state_select_15; |
| 2228 | wire default_grp_eq_state_select_16; |
| 2229 | wire default_grp_eq_state_select_17; |
| 2230 | wire default_grp_eq_state_select_18; |
| 2231 | wire default_grp_eq_state_select_19; |
| 2232 | wire default_grp_eq_state_select_20; |
| 2233 | wire default_grp_eq_state_select_21; |
| 2234 | wire default_grp_eq_state_select_22; |
| 2235 | wire default_grp_eq_state_select_23; |
| 2236 | wire default_grp_eq_state_select_24; |
| 2237 | wire default_grp_eq_state_select_25; |
| 2238 | wire default_grp_eq_state_select_26; |
| 2239 | wire default_grp_eq_state_select_27; |
| 2240 | wire default_grp_eq_state_select_28; |
| 2241 | wire default_grp_eq_state_select_29; |
| 2242 | wire default_grp_eq_state_select_30; |
| 2243 | wire default_grp_eq_state_select_31; |
| 2244 | wire default_grp_eq_state_select_32; |
| 2245 | wire default_grp_eq_state_select_33; |
| 2246 | wire default_grp_eq_state_select_34; |
| 2247 | wire default_grp_eq_state_select_35; |
| 2248 | wire default_grp_eq_tail_select_pulse_0; |
| 2249 | wire default_grp_eq_tail_select_pulse_1; |
| 2250 | wire default_grp_eq_tail_select_pulse_2; |
| 2251 | wire default_grp_eq_tail_select_pulse_3; |
| 2252 | wire default_grp_eq_tail_select_pulse_4; |
| 2253 | wire default_grp_eq_tail_select_pulse_5; |
| 2254 | wire default_grp_eq_tail_select_pulse_6; |
| 2255 | wire default_grp_eq_tail_select_pulse_7; |
| 2256 | wire default_grp_eq_tail_select_pulse_8; |
| 2257 | wire default_grp_eq_tail_select_pulse_9; |
| 2258 | wire default_grp_eq_tail_select_pulse_10; |
| 2259 | wire default_grp_eq_tail_select_pulse_11; |
| 2260 | wire default_grp_eq_tail_select_pulse_12; |
| 2261 | wire default_grp_eq_tail_select_pulse_13; |
| 2262 | wire default_grp_eq_tail_select_pulse_14; |
| 2263 | wire default_grp_eq_tail_select_pulse_15; |
| 2264 | wire default_grp_eq_tail_select_pulse_16; |
| 2265 | wire default_grp_eq_tail_select_pulse_17; |
| 2266 | wire default_grp_eq_tail_select_pulse_18; |
| 2267 | wire default_grp_eq_tail_select_pulse_19; |
| 2268 | wire default_grp_eq_tail_select_pulse_20; |
| 2269 | wire default_grp_eq_tail_select_pulse_21; |
| 2270 | wire default_grp_eq_tail_select_pulse_22; |
| 2271 | wire default_grp_eq_tail_select_pulse_23; |
| 2272 | wire default_grp_eq_tail_select_pulse_24; |
| 2273 | wire default_grp_eq_tail_select_pulse_25; |
| 2274 | wire default_grp_eq_tail_select_pulse_26; |
| 2275 | wire default_grp_eq_tail_select_pulse_27; |
| 2276 | wire default_grp_eq_tail_select_pulse_28; |
| 2277 | wire default_grp_eq_tail_select_pulse_29; |
| 2278 | wire default_grp_eq_tail_select_pulse_30; |
| 2279 | wire default_grp_eq_tail_select_pulse_31; |
| 2280 | wire default_grp_eq_tail_select_pulse_32; |
| 2281 | wire default_grp_eq_tail_select_pulse_33; |
| 2282 | wire default_grp_eq_tail_select_pulse_34; |
| 2283 | wire default_grp_eq_tail_select_pulse_35; |
| 2284 | wire default_grp_eq_head_select_pulse_0; |
| 2285 | wire default_grp_eq_head_select_pulse_1; |
| 2286 | wire default_grp_eq_head_select_pulse_2; |
| 2287 | wire default_grp_eq_head_select_pulse_3; |
| 2288 | wire default_grp_eq_head_select_pulse_4; |
| 2289 | wire default_grp_eq_head_select_pulse_5; |
| 2290 | wire default_grp_eq_head_select_pulse_6; |
| 2291 | wire default_grp_eq_head_select_pulse_7; |
| 2292 | wire default_grp_eq_head_select_pulse_8; |
| 2293 | wire default_grp_eq_head_select_pulse_9; |
| 2294 | wire default_grp_eq_head_select_pulse_10; |
| 2295 | wire default_grp_eq_head_select_pulse_11; |
| 2296 | wire default_grp_eq_head_select_pulse_12; |
| 2297 | wire default_grp_eq_head_select_pulse_13; |
| 2298 | wire default_grp_eq_head_select_pulse_14; |
| 2299 | wire default_grp_eq_head_select_pulse_15; |
| 2300 | wire default_grp_eq_head_select_pulse_16; |
| 2301 | wire default_grp_eq_head_select_pulse_17; |
| 2302 | wire default_grp_eq_head_select_pulse_18; |
| 2303 | wire default_grp_eq_head_select_pulse_19; |
| 2304 | wire default_grp_eq_head_select_pulse_20; |
| 2305 | wire default_grp_eq_head_select_pulse_21; |
| 2306 | wire default_grp_eq_head_select_pulse_22; |
| 2307 | wire default_grp_eq_head_select_pulse_23; |
| 2308 | wire default_grp_eq_head_select_pulse_24; |
| 2309 | wire default_grp_eq_head_select_pulse_25; |
| 2310 | wire default_grp_eq_head_select_pulse_26; |
| 2311 | wire default_grp_eq_head_select_pulse_27; |
| 2312 | wire default_grp_eq_head_select_pulse_28; |
| 2313 | wire default_grp_eq_head_select_pulse_29; |
| 2314 | wire default_grp_eq_head_select_pulse_30; |
| 2315 | wire default_grp_eq_head_select_pulse_31; |
| 2316 | wire default_grp_eq_head_select_pulse_32; |
| 2317 | wire default_grp_eq_head_select_pulse_33; |
| 2318 | wire default_grp_eq_head_select_pulse_34; |
| 2319 | wire default_grp_eq_head_select_pulse_35; |
| 2320 | |
| 2321 | dmu_imu_eqs_default_grp dmu_imu_eqs_default_grp |
| 2322 | ( |
| 2323 | .clk (clk), |
| 2324 | .eq_base_address_address_hw_read (eq_base_address_address_hw_read), |
| 2325 | .eq_base_address_select_pulse (default_grp_eq_base_address_select_pulse), |
| 2326 | .eq_ctrl_set_ext_select_0 (eq_ctrl_set_ext_select_0), |
| 2327 | .eq_ctrl_set_ext_select_1 (eq_ctrl_set_ext_select_1), |
| 2328 | .eq_ctrl_set_ext_select_2 (eq_ctrl_set_ext_select_2), |
| 2329 | .eq_ctrl_set_ext_select_3 (eq_ctrl_set_ext_select_3), |
| 2330 | .eq_ctrl_set_ext_select_4 (eq_ctrl_set_ext_select_4), |
| 2331 | .eq_ctrl_set_ext_select_5 (eq_ctrl_set_ext_select_5), |
| 2332 | .eq_ctrl_set_ext_select_6 (eq_ctrl_set_ext_select_6), |
| 2333 | .eq_ctrl_set_ext_select_7 (eq_ctrl_set_ext_select_7), |
| 2334 | .eq_ctrl_set_ext_select_8 (eq_ctrl_set_ext_select_8), |
| 2335 | .eq_ctrl_set_ext_select_9 (eq_ctrl_set_ext_select_9), |
| 2336 | .eq_ctrl_set_ext_select_10 (eq_ctrl_set_ext_select_10), |
| 2337 | .eq_ctrl_set_ext_select_11 (eq_ctrl_set_ext_select_11), |
| 2338 | .eq_ctrl_set_ext_select_12 (eq_ctrl_set_ext_select_12), |
| 2339 | .eq_ctrl_set_ext_select_13 (eq_ctrl_set_ext_select_13), |
| 2340 | .eq_ctrl_set_ext_select_14 (eq_ctrl_set_ext_select_14), |
| 2341 | .eq_ctrl_set_ext_select_15 (eq_ctrl_set_ext_select_15), |
| 2342 | .eq_ctrl_set_ext_select_16 (eq_ctrl_set_ext_select_16), |
| 2343 | .eq_ctrl_set_ext_select_17 (eq_ctrl_set_ext_select_17), |
| 2344 | .eq_ctrl_set_ext_select_18 (eq_ctrl_set_ext_select_18), |
| 2345 | .eq_ctrl_set_ext_select_19 (eq_ctrl_set_ext_select_19), |
| 2346 | .eq_ctrl_set_ext_select_20 (eq_ctrl_set_ext_select_20), |
| 2347 | .eq_ctrl_set_ext_select_21 (eq_ctrl_set_ext_select_21), |
| 2348 | .eq_ctrl_set_ext_select_22 (eq_ctrl_set_ext_select_22), |
| 2349 | .eq_ctrl_set_ext_select_23 (eq_ctrl_set_ext_select_23), |
| 2350 | .eq_ctrl_set_ext_select_24 (eq_ctrl_set_ext_select_24), |
| 2351 | .eq_ctrl_set_ext_select_25 (eq_ctrl_set_ext_select_25), |
| 2352 | .eq_ctrl_set_ext_select_26 (eq_ctrl_set_ext_select_26), |
| 2353 | .eq_ctrl_set_ext_select_27 (eq_ctrl_set_ext_select_27), |
| 2354 | .eq_ctrl_set_ext_select_28 (eq_ctrl_set_ext_select_28), |
| 2355 | .eq_ctrl_set_ext_select_29 (eq_ctrl_set_ext_select_29), |
| 2356 | .eq_ctrl_set_ext_select_30 (eq_ctrl_set_ext_select_30), |
| 2357 | .eq_ctrl_set_ext_select_31 (eq_ctrl_set_ext_select_31), |
| 2358 | .eq_ctrl_set_ext_select_32 (eq_ctrl_set_ext_select_32), |
| 2359 | .eq_ctrl_set_ext_select_33 (eq_ctrl_set_ext_select_33), |
| 2360 | .eq_ctrl_set_ext_select_34 (eq_ctrl_set_ext_select_34), |
| 2361 | .eq_ctrl_set_ext_select_35 (eq_ctrl_set_ext_select_35), |
| 2362 | .eq_ctrl_set_select_0 (default_grp_eq_ctrl_set_select_0), |
| 2363 | .eq_ctrl_set_select_1 (default_grp_eq_ctrl_set_select_1), |
| 2364 | .eq_ctrl_set_select_2 (default_grp_eq_ctrl_set_select_2), |
| 2365 | .eq_ctrl_set_select_3 (default_grp_eq_ctrl_set_select_3), |
| 2366 | .eq_ctrl_set_select_4 (default_grp_eq_ctrl_set_select_4), |
| 2367 | .eq_ctrl_set_select_5 (default_grp_eq_ctrl_set_select_5), |
| 2368 | .eq_ctrl_set_select_6 (default_grp_eq_ctrl_set_select_6), |
| 2369 | .eq_ctrl_set_select_7 (default_grp_eq_ctrl_set_select_7), |
| 2370 | .eq_ctrl_set_select_8 (default_grp_eq_ctrl_set_select_8), |
| 2371 | .eq_ctrl_set_select_9 (default_grp_eq_ctrl_set_select_9), |
| 2372 | .eq_ctrl_set_select_10 (default_grp_eq_ctrl_set_select_10), |
| 2373 | .eq_ctrl_set_select_11 (default_grp_eq_ctrl_set_select_11), |
| 2374 | .eq_ctrl_set_select_12 (default_grp_eq_ctrl_set_select_12), |
| 2375 | .eq_ctrl_set_select_13 (default_grp_eq_ctrl_set_select_13), |
| 2376 | .eq_ctrl_set_select_14 (default_grp_eq_ctrl_set_select_14), |
| 2377 | .eq_ctrl_set_select_15 (default_grp_eq_ctrl_set_select_15), |
| 2378 | .eq_ctrl_set_select_16 (default_grp_eq_ctrl_set_select_16), |
| 2379 | .eq_ctrl_set_select_17 (default_grp_eq_ctrl_set_select_17), |
| 2380 | .eq_ctrl_set_select_18 (default_grp_eq_ctrl_set_select_18), |
| 2381 | .eq_ctrl_set_select_19 (default_grp_eq_ctrl_set_select_19), |
| 2382 | .eq_ctrl_set_select_20 (default_grp_eq_ctrl_set_select_20), |
| 2383 | .eq_ctrl_set_select_21 (default_grp_eq_ctrl_set_select_21), |
| 2384 | .eq_ctrl_set_select_22 (default_grp_eq_ctrl_set_select_22), |
| 2385 | .eq_ctrl_set_select_23 (default_grp_eq_ctrl_set_select_23), |
| 2386 | .eq_ctrl_set_select_24 (default_grp_eq_ctrl_set_select_24), |
| 2387 | .eq_ctrl_set_select_25 (default_grp_eq_ctrl_set_select_25), |
| 2388 | .eq_ctrl_set_select_26 (default_grp_eq_ctrl_set_select_26), |
| 2389 | .eq_ctrl_set_select_27 (default_grp_eq_ctrl_set_select_27), |
| 2390 | .eq_ctrl_set_select_28 (default_grp_eq_ctrl_set_select_28), |
| 2391 | .eq_ctrl_set_select_29 (default_grp_eq_ctrl_set_select_29), |
| 2392 | .eq_ctrl_set_select_30 (default_grp_eq_ctrl_set_select_30), |
| 2393 | .eq_ctrl_set_select_31 (default_grp_eq_ctrl_set_select_31), |
| 2394 | .eq_ctrl_set_select_32 (default_grp_eq_ctrl_set_select_32), |
| 2395 | .eq_ctrl_set_select_33 (default_grp_eq_ctrl_set_select_33), |
| 2396 | .eq_ctrl_set_select_34 (default_grp_eq_ctrl_set_select_34), |
| 2397 | .eq_ctrl_set_select_35 (default_grp_eq_ctrl_set_select_35), |
| 2398 | .eq_ctrl_set_enoverr_ext_wr_data (eq_ctrl_set_enoverr_ext_wr_data), |
| 2399 | .eq_ctrl_set_en_ext_wr_data (eq_ctrl_set_en_ext_wr_data), |
| 2400 | .eq_ctrl_clr_ext_select_0 (eq_ctrl_clr_ext_select_0), |
| 2401 | .eq_ctrl_clr_ext_select_1 (eq_ctrl_clr_ext_select_1), |
| 2402 | .eq_ctrl_clr_ext_select_2 (eq_ctrl_clr_ext_select_2), |
| 2403 | .eq_ctrl_clr_ext_select_3 (eq_ctrl_clr_ext_select_3), |
| 2404 | .eq_ctrl_clr_ext_select_4 (eq_ctrl_clr_ext_select_4), |
| 2405 | .eq_ctrl_clr_ext_select_5 (eq_ctrl_clr_ext_select_5), |
| 2406 | .eq_ctrl_clr_ext_select_6 (eq_ctrl_clr_ext_select_6), |
| 2407 | .eq_ctrl_clr_ext_select_7 (eq_ctrl_clr_ext_select_7), |
| 2408 | .eq_ctrl_clr_ext_select_8 (eq_ctrl_clr_ext_select_8), |
| 2409 | .eq_ctrl_clr_ext_select_9 (eq_ctrl_clr_ext_select_9), |
| 2410 | .eq_ctrl_clr_ext_select_10 (eq_ctrl_clr_ext_select_10), |
| 2411 | .eq_ctrl_clr_ext_select_11 (eq_ctrl_clr_ext_select_11), |
| 2412 | .eq_ctrl_clr_ext_select_12 (eq_ctrl_clr_ext_select_12), |
| 2413 | .eq_ctrl_clr_ext_select_13 (eq_ctrl_clr_ext_select_13), |
| 2414 | .eq_ctrl_clr_ext_select_14 (eq_ctrl_clr_ext_select_14), |
| 2415 | .eq_ctrl_clr_ext_select_15 (eq_ctrl_clr_ext_select_15), |
| 2416 | .eq_ctrl_clr_ext_select_16 (eq_ctrl_clr_ext_select_16), |
| 2417 | .eq_ctrl_clr_ext_select_17 (eq_ctrl_clr_ext_select_17), |
| 2418 | .eq_ctrl_clr_ext_select_18 (eq_ctrl_clr_ext_select_18), |
| 2419 | .eq_ctrl_clr_ext_select_19 (eq_ctrl_clr_ext_select_19), |
| 2420 | .eq_ctrl_clr_ext_select_20 (eq_ctrl_clr_ext_select_20), |
| 2421 | .eq_ctrl_clr_ext_select_21 (eq_ctrl_clr_ext_select_21), |
| 2422 | .eq_ctrl_clr_ext_select_22 (eq_ctrl_clr_ext_select_22), |
| 2423 | .eq_ctrl_clr_ext_select_23 (eq_ctrl_clr_ext_select_23), |
| 2424 | .eq_ctrl_clr_ext_select_24 (eq_ctrl_clr_ext_select_24), |
| 2425 | .eq_ctrl_clr_ext_select_25 (eq_ctrl_clr_ext_select_25), |
| 2426 | .eq_ctrl_clr_ext_select_26 (eq_ctrl_clr_ext_select_26), |
| 2427 | .eq_ctrl_clr_ext_select_27 (eq_ctrl_clr_ext_select_27), |
| 2428 | .eq_ctrl_clr_ext_select_28 (eq_ctrl_clr_ext_select_28), |
| 2429 | .eq_ctrl_clr_ext_select_29 (eq_ctrl_clr_ext_select_29), |
| 2430 | .eq_ctrl_clr_ext_select_30 (eq_ctrl_clr_ext_select_30), |
| 2431 | .eq_ctrl_clr_ext_select_31 (eq_ctrl_clr_ext_select_31), |
| 2432 | .eq_ctrl_clr_ext_select_32 (eq_ctrl_clr_ext_select_32), |
| 2433 | .eq_ctrl_clr_ext_select_33 (eq_ctrl_clr_ext_select_33), |
| 2434 | .eq_ctrl_clr_ext_select_34 (eq_ctrl_clr_ext_select_34), |
| 2435 | .eq_ctrl_clr_ext_select_35 (eq_ctrl_clr_ext_select_35), |
| 2436 | .eq_ctrl_clr_select_0 (default_grp_eq_ctrl_clr_select_0), |
| 2437 | .eq_ctrl_clr_select_1 (default_grp_eq_ctrl_clr_select_1), |
| 2438 | .eq_ctrl_clr_select_2 (default_grp_eq_ctrl_clr_select_2), |
| 2439 | .eq_ctrl_clr_select_3 (default_grp_eq_ctrl_clr_select_3), |
| 2440 | .eq_ctrl_clr_select_4 (default_grp_eq_ctrl_clr_select_4), |
| 2441 | .eq_ctrl_clr_select_5 (default_grp_eq_ctrl_clr_select_5), |
| 2442 | .eq_ctrl_clr_select_6 (default_grp_eq_ctrl_clr_select_6), |
| 2443 | .eq_ctrl_clr_select_7 (default_grp_eq_ctrl_clr_select_7), |
| 2444 | .eq_ctrl_clr_select_8 (default_grp_eq_ctrl_clr_select_8), |
| 2445 | .eq_ctrl_clr_select_9 (default_grp_eq_ctrl_clr_select_9), |
| 2446 | .eq_ctrl_clr_select_10 (default_grp_eq_ctrl_clr_select_10), |
| 2447 | .eq_ctrl_clr_select_11 (default_grp_eq_ctrl_clr_select_11), |
| 2448 | .eq_ctrl_clr_select_12 (default_grp_eq_ctrl_clr_select_12), |
| 2449 | .eq_ctrl_clr_select_13 (default_grp_eq_ctrl_clr_select_13), |
| 2450 | .eq_ctrl_clr_select_14 (default_grp_eq_ctrl_clr_select_14), |
| 2451 | .eq_ctrl_clr_select_15 (default_grp_eq_ctrl_clr_select_15), |
| 2452 | .eq_ctrl_clr_select_16 (default_grp_eq_ctrl_clr_select_16), |
| 2453 | .eq_ctrl_clr_select_17 (default_grp_eq_ctrl_clr_select_17), |
| 2454 | .eq_ctrl_clr_select_18 (default_grp_eq_ctrl_clr_select_18), |
| 2455 | .eq_ctrl_clr_select_19 (default_grp_eq_ctrl_clr_select_19), |
| 2456 | .eq_ctrl_clr_select_20 (default_grp_eq_ctrl_clr_select_20), |
| 2457 | .eq_ctrl_clr_select_21 (default_grp_eq_ctrl_clr_select_21), |
| 2458 | .eq_ctrl_clr_select_22 (default_grp_eq_ctrl_clr_select_22), |
| 2459 | .eq_ctrl_clr_select_23 (default_grp_eq_ctrl_clr_select_23), |
| 2460 | .eq_ctrl_clr_select_24 (default_grp_eq_ctrl_clr_select_24), |
| 2461 | .eq_ctrl_clr_select_25 (default_grp_eq_ctrl_clr_select_25), |
| 2462 | .eq_ctrl_clr_select_26 (default_grp_eq_ctrl_clr_select_26), |
| 2463 | .eq_ctrl_clr_select_27 (default_grp_eq_ctrl_clr_select_27), |
| 2464 | .eq_ctrl_clr_select_28 (default_grp_eq_ctrl_clr_select_28), |
| 2465 | .eq_ctrl_clr_select_29 (default_grp_eq_ctrl_clr_select_29), |
| 2466 | .eq_ctrl_clr_select_30 (default_grp_eq_ctrl_clr_select_30), |
| 2467 | .eq_ctrl_clr_select_31 (default_grp_eq_ctrl_clr_select_31), |
| 2468 | .eq_ctrl_clr_select_32 (default_grp_eq_ctrl_clr_select_32), |
| 2469 | .eq_ctrl_clr_select_33 (default_grp_eq_ctrl_clr_select_33), |
| 2470 | .eq_ctrl_clr_select_34 (default_grp_eq_ctrl_clr_select_34), |
| 2471 | .eq_ctrl_clr_select_35 (default_grp_eq_ctrl_clr_select_35), |
| 2472 | .eq_ctrl_clr_coverr_ext_wr_data (eq_ctrl_clr_coverr_ext_wr_data), |
| 2473 | .eq_ctrl_clr_e2i_ext_wr_data (eq_ctrl_clr_e2i_ext_wr_data), |
| 2474 | .eq_ctrl_clr_dis_ext_wr_data (eq_ctrl_clr_dis_ext_wr_data), |
| 2475 | .eq_state_select_0 (default_grp_eq_state_select_0), |
| 2476 | .eq_state_select_1 (default_grp_eq_state_select_1), |
| 2477 | .eq_state_select_2 (default_grp_eq_state_select_2), |
| 2478 | .eq_state_select_3 (default_grp_eq_state_select_3), |
| 2479 | .eq_state_select_4 (default_grp_eq_state_select_4), |
| 2480 | .eq_state_select_5 (default_grp_eq_state_select_5), |
| 2481 | .eq_state_select_6 (default_grp_eq_state_select_6), |
| 2482 | .eq_state_select_7 (default_grp_eq_state_select_7), |
| 2483 | .eq_state_select_8 (default_grp_eq_state_select_8), |
| 2484 | .eq_state_select_9 (default_grp_eq_state_select_9), |
| 2485 | .eq_state_select_10 (default_grp_eq_state_select_10), |
| 2486 | .eq_state_select_11 (default_grp_eq_state_select_11), |
| 2487 | .eq_state_select_12 (default_grp_eq_state_select_12), |
| 2488 | .eq_state_select_13 (default_grp_eq_state_select_13), |
| 2489 | .eq_state_select_14 (default_grp_eq_state_select_14), |
| 2490 | .eq_state_select_15 (default_grp_eq_state_select_15), |
| 2491 | .eq_state_select_16 (default_grp_eq_state_select_16), |
| 2492 | .eq_state_select_17 (default_grp_eq_state_select_17), |
| 2493 | .eq_state_select_18 (default_grp_eq_state_select_18), |
| 2494 | .eq_state_select_19 (default_grp_eq_state_select_19), |
| 2495 | .eq_state_select_20 (default_grp_eq_state_select_20), |
| 2496 | .eq_state_select_21 (default_grp_eq_state_select_21), |
| 2497 | .eq_state_select_22 (default_grp_eq_state_select_22), |
| 2498 | .eq_state_select_23 (default_grp_eq_state_select_23), |
| 2499 | .eq_state_select_24 (default_grp_eq_state_select_24), |
| 2500 | .eq_state_select_25 (default_grp_eq_state_select_25), |
| 2501 | .eq_state_select_26 (default_grp_eq_state_select_26), |
| 2502 | .eq_state_select_27 (default_grp_eq_state_select_27), |
| 2503 | .eq_state_select_28 (default_grp_eq_state_select_28), |
| 2504 | .eq_state_select_29 (default_grp_eq_state_select_29), |
| 2505 | .eq_state_select_30 (default_grp_eq_state_select_30), |
| 2506 | .eq_state_select_31 (default_grp_eq_state_select_31), |
| 2507 | .eq_state_select_32 (default_grp_eq_state_select_32), |
| 2508 | .eq_state_select_33 (default_grp_eq_state_select_33), |
| 2509 | .eq_state_select_34 (default_grp_eq_state_select_34), |
| 2510 | .eq_state_select_35 (default_grp_eq_state_select_35), |
| 2511 | .eq_state_ext_read_data_0 |
| 2512 | ( |
| 2513 | { |
| 2514 | 61'b0, |
| 2515 | eq_state_state_ext_read_data_0 |
| 2516 | }), |
| 2517 | .eq_state_ext_read_data_1 |
| 2518 | ( |
| 2519 | { |
| 2520 | 61'b0, |
| 2521 | eq_state_state_ext_read_data_1 |
| 2522 | }), |
| 2523 | .eq_state_ext_read_data_2 |
| 2524 | ( |
| 2525 | { |
| 2526 | 61'b0, |
| 2527 | eq_state_state_ext_read_data_2 |
| 2528 | }), |
| 2529 | .eq_state_ext_read_data_3 |
| 2530 | ( |
| 2531 | { |
| 2532 | 61'b0, |
| 2533 | eq_state_state_ext_read_data_3 |
| 2534 | }), |
| 2535 | .eq_state_ext_read_data_4 |
| 2536 | ( |
| 2537 | { |
| 2538 | 61'b0, |
| 2539 | eq_state_state_ext_read_data_4 |
| 2540 | }), |
| 2541 | .eq_state_ext_read_data_5 |
| 2542 | ( |
| 2543 | { |
| 2544 | 61'b0, |
| 2545 | eq_state_state_ext_read_data_5 |
| 2546 | }), |
| 2547 | .eq_state_ext_read_data_6 |
| 2548 | ( |
| 2549 | { |
| 2550 | 61'b0, |
| 2551 | eq_state_state_ext_read_data_6 |
| 2552 | }), |
| 2553 | .eq_state_ext_read_data_7 |
| 2554 | ( |
| 2555 | { |
| 2556 | 61'b0, |
| 2557 | eq_state_state_ext_read_data_7 |
| 2558 | }), |
| 2559 | .eq_state_ext_read_data_8 |
| 2560 | ( |
| 2561 | { |
| 2562 | 61'b0, |
| 2563 | eq_state_state_ext_read_data_8 |
| 2564 | }), |
| 2565 | .eq_state_ext_read_data_9 |
| 2566 | ( |
| 2567 | { |
| 2568 | 61'b0, |
| 2569 | eq_state_state_ext_read_data_9 |
| 2570 | }), |
| 2571 | .eq_state_ext_read_data_10 |
| 2572 | ( |
| 2573 | { |
| 2574 | 61'b0, |
| 2575 | eq_state_state_ext_read_data_10 |
| 2576 | }), |
| 2577 | .eq_state_ext_read_data_11 |
| 2578 | ( |
| 2579 | { |
| 2580 | 61'b0, |
| 2581 | eq_state_state_ext_read_data_11 |
| 2582 | }), |
| 2583 | .eq_state_ext_read_data_12 |
| 2584 | ( |
| 2585 | { |
| 2586 | 61'b0, |
| 2587 | eq_state_state_ext_read_data_12 |
| 2588 | }), |
| 2589 | .eq_state_ext_read_data_13 |
| 2590 | ( |
| 2591 | { |
| 2592 | 61'b0, |
| 2593 | eq_state_state_ext_read_data_13 |
| 2594 | }), |
| 2595 | .eq_state_ext_read_data_14 |
| 2596 | ( |
| 2597 | { |
| 2598 | 61'b0, |
| 2599 | eq_state_state_ext_read_data_14 |
| 2600 | }), |
| 2601 | .eq_state_ext_read_data_15 |
| 2602 | ( |
| 2603 | { |
| 2604 | 61'b0, |
| 2605 | eq_state_state_ext_read_data_15 |
| 2606 | }), |
| 2607 | .eq_state_ext_read_data_16 |
| 2608 | ( |
| 2609 | { |
| 2610 | 61'b0, |
| 2611 | eq_state_state_ext_read_data_16 |
| 2612 | }), |
| 2613 | .eq_state_ext_read_data_17 |
| 2614 | ( |
| 2615 | { |
| 2616 | 61'b0, |
| 2617 | eq_state_state_ext_read_data_17 |
| 2618 | }), |
| 2619 | .eq_state_ext_read_data_18 |
| 2620 | ( |
| 2621 | { |
| 2622 | 61'b0, |
| 2623 | eq_state_state_ext_read_data_18 |
| 2624 | }), |
| 2625 | .eq_state_ext_read_data_19 |
| 2626 | ( |
| 2627 | { |
| 2628 | 61'b0, |
| 2629 | eq_state_state_ext_read_data_19 |
| 2630 | }), |
| 2631 | .eq_state_ext_read_data_20 |
| 2632 | ( |
| 2633 | { |
| 2634 | 61'b0, |
| 2635 | eq_state_state_ext_read_data_20 |
| 2636 | }), |
| 2637 | .eq_state_ext_read_data_21 |
| 2638 | ( |
| 2639 | { |
| 2640 | 61'b0, |
| 2641 | eq_state_state_ext_read_data_21 |
| 2642 | }), |
| 2643 | .eq_state_ext_read_data_22 |
| 2644 | ( |
| 2645 | { |
| 2646 | 61'b0, |
| 2647 | eq_state_state_ext_read_data_22 |
| 2648 | }), |
| 2649 | .eq_state_ext_read_data_23 |
| 2650 | ( |
| 2651 | { |
| 2652 | 61'b0, |
| 2653 | eq_state_state_ext_read_data_23 |
| 2654 | }), |
| 2655 | .eq_state_ext_read_data_24 |
| 2656 | ( |
| 2657 | { |
| 2658 | 61'b0, |
| 2659 | eq_state_state_ext_read_data_24 |
| 2660 | }), |
| 2661 | .eq_state_ext_read_data_25 |
| 2662 | ( |
| 2663 | { |
| 2664 | 61'b0, |
| 2665 | eq_state_state_ext_read_data_25 |
| 2666 | }), |
| 2667 | .eq_state_ext_read_data_26 |
| 2668 | ( |
| 2669 | { |
| 2670 | 61'b0, |
| 2671 | eq_state_state_ext_read_data_26 |
| 2672 | }), |
| 2673 | .eq_state_ext_read_data_27 |
| 2674 | ( |
| 2675 | { |
| 2676 | 61'b0, |
| 2677 | eq_state_state_ext_read_data_27 |
| 2678 | }), |
| 2679 | .eq_state_ext_read_data_28 |
| 2680 | ( |
| 2681 | { |
| 2682 | 61'b0, |
| 2683 | eq_state_state_ext_read_data_28 |
| 2684 | }), |
| 2685 | .eq_state_ext_read_data_29 |
| 2686 | ( |
| 2687 | { |
| 2688 | 61'b0, |
| 2689 | eq_state_state_ext_read_data_29 |
| 2690 | }), |
| 2691 | .eq_state_ext_read_data_30 |
| 2692 | ( |
| 2693 | { |
| 2694 | 61'b0, |
| 2695 | eq_state_state_ext_read_data_30 |
| 2696 | }), |
| 2697 | .eq_state_ext_read_data_31 |
| 2698 | ( |
| 2699 | { |
| 2700 | 61'b0, |
| 2701 | eq_state_state_ext_read_data_31 |
| 2702 | }), |
| 2703 | .eq_state_ext_read_data_32 |
| 2704 | ( |
| 2705 | { |
| 2706 | 61'b0, |
| 2707 | eq_state_state_ext_read_data_32 |
| 2708 | }), |
| 2709 | .eq_state_ext_read_data_33 |
| 2710 | ( |
| 2711 | { |
| 2712 | 61'b0, |
| 2713 | eq_state_state_ext_read_data_33 |
| 2714 | }), |
| 2715 | .eq_state_ext_read_data_34 |
| 2716 | ( |
| 2717 | { |
| 2718 | 61'b0, |
| 2719 | eq_state_state_ext_read_data_34 |
| 2720 | }), |
| 2721 | .eq_state_ext_read_data_35 |
| 2722 | ( |
| 2723 | { |
| 2724 | 61'b0, |
| 2725 | eq_state_state_ext_read_data_35 |
| 2726 | }), |
| 2727 | .eq_tail_overr_hw_ld_0 (eq_tail_overr_hw_ld_0), |
| 2728 | .eq_tail_overr_hw_write_0 (eq_tail_overr_hw_write_0), |
| 2729 | .eq_tail_tail_hw_ld_0 (eq_tail_tail_hw_ld_0), |
| 2730 | .eq_tail_tail_hw_write_0 (eq_tail_tail_hw_write_0), |
| 2731 | .eq_tail_tail_hw_read_0 (eq_tail_tail_hw_read_0), |
| 2732 | .eq_tail_overr_hw_ld_1 (eq_tail_overr_hw_ld_1), |
| 2733 | .eq_tail_overr_hw_write_1 (eq_tail_overr_hw_write_1), |
| 2734 | .eq_tail_tail_hw_ld_1 (eq_tail_tail_hw_ld_1), |
| 2735 | .eq_tail_tail_hw_write_1 (eq_tail_tail_hw_write_1), |
| 2736 | .eq_tail_tail_hw_read_1 (eq_tail_tail_hw_read_1), |
| 2737 | .eq_tail_overr_hw_ld_2 (eq_tail_overr_hw_ld_2), |
| 2738 | .eq_tail_overr_hw_write_2 (eq_tail_overr_hw_write_2), |
| 2739 | .eq_tail_tail_hw_ld_2 (eq_tail_tail_hw_ld_2), |
| 2740 | .eq_tail_tail_hw_write_2 (eq_tail_tail_hw_write_2), |
| 2741 | .eq_tail_tail_hw_read_2 (eq_tail_tail_hw_read_2), |
| 2742 | .eq_tail_overr_hw_ld_3 (eq_tail_overr_hw_ld_3), |
| 2743 | .eq_tail_overr_hw_write_3 (eq_tail_overr_hw_write_3), |
| 2744 | .eq_tail_tail_hw_ld_3 (eq_tail_tail_hw_ld_3), |
| 2745 | .eq_tail_tail_hw_write_3 (eq_tail_tail_hw_write_3), |
| 2746 | .eq_tail_tail_hw_read_3 (eq_tail_tail_hw_read_3), |
| 2747 | .eq_tail_overr_hw_ld_4 (eq_tail_overr_hw_ld_4), |
| 2748 | .eq_tail_overr_hw_write_4 (eq_tail_overr_hw_write_4), |
| 2749 | .eq_tail_tail_hw_ld_4 (eq_tail_tail_hw_ld_4), |
| 2750 | .eq_tail_tail_hw_write_4 (eq_tail_tail_hw_write_4), |
| 2751 | .eq_tail_tail_hw_read_4 (eq_tail_tail_hw_read_4), |
| 2752 | .eq_tail_overr_hw_ld_5 (eq_tail_overr_hw_ld_5), |
| 2753 | .eq_tail_overr_hw_write_5 (eq_tail_overr_hw_write_5), |
| 2754 | .eq_tail_tail_hw_ld_5 (eq_tail_tail_hw_ld_5), |
| 2755 | .eq_tail_tail_hw_write_5 (eq_tail_tail_hw_write_5), |
| 2756 | .eq_tail_tail_hw_read_5 (eq_tail_tail_hw_read_5), |
| 2757 | .eq_tail_overr_hw_ld_6 (eq_tail_overr_hw_ld_6), |
| 2758 | .eq_tail_overr_hw_write_6 (eq_tail_overr_hw_write_6), |
| 2759 | .eq_tail_tail_hw_ld_6 (eq_tail_tail_hw_ld_6), |
| 2760 | .eq_tail_tail_hw_write_6 (eq_tail_tail_hw_write_6), |
| 2761 | .eq_tail_tail_hw_read_6 (eq_tail_tail_hw_read_6), |
| 2762 | .eq_tail_overr_hw_ld_7 (eq_tail_overr_hw_ld_7), |
| 2763 | .eq_tail_overr_hw_write_7 (eq_tail_overr_hw_write_7), |
| 2764 | .eq_tail_tail_hw_ld_7 (eq_tail_tail_hw_ld_7), |
| 2765 | .eq_tail_tail_hw_write_7 (eq_tail_tail_hw_write_7), |
| 2766 | .eq_tail_tail_hw_read_7 (eq_tail_tail_hw_read_7), |
| 2767 | .eq_tail_overr_hw_ld_8 (eq_tail_overr_hw_ld_8), |
| 2768 | .eq_tail_overr_hw_write_8 (eq_tail_overr_hw_write_8), |
| 2769 | .eq_tail_tail_hw_ld_8 (eq_tail_tail_hw_ld_8), |
| 2770 | .eq_tail_tail_hw_write_8 (eq_tail_tail_hw_write_8), |
| 2771 | .eq_tail_tail_hw_read_8 (eq_tail_tail_hw_read_8), |
| 2772 | .eq_tail_overr_hw_ld_9 (eq_tail_overr_hw_ld_9), |
| 2773 | .eq_tail_overr_hw_write_9 (eq_tail_overr_hw_write_9), |
| 2774 | .eq_tail_tail_hw_ld_9 (eq_tail_tail_hw_ld_9), |
| 2775 | .eq_tail_tail_hw_write_9 (eq_tail_tail_hw_write_9), |
| 2776 | .eq_tail_tail_hw_read_9 (eq_tail_tail_hw_read_9), |
| 2777 | .eq_tail_overr_hw_ld_10 (eq_tail_overr_hw_ld_10), |
| 2778 | .eq_tail_overr_hw_write_10 (eq_tail_overr_hw_write_10), |
| 2779 | .eq_tail_tail_hw_ld_10 (eq_tail_tail_hw_ld_10), |
| 2780 | .eq_tail_tail_hw_write_10 (eq_tail_tail_hw_write_10), |
| 2781 | .eq_tail_tail_hw_read_10 (eq_tail_tail_hw_read_10), |
| 2782 | .eq_tail_overr_hw_ld_11 (eq_tail_overr_hw_ld_11), |
| 2783 | .eq_tail_overr_hw_write_11 (eq_tail_overr_hw_write_11), |
| 2784 | .eq_tail_tail_hw_ld_11 (eq_tail_tail_hw_ld_11), |
| 2785 | .eq_tail_tail_hw_write_11 (eq_tail_tail_hw_write_11), |
| 2786 | .eq_tail_tail_hw_read_11 (eq_tail_tail_hw_read_11), |
| 2787 | .eq_tail_overr_hw_ld_12 (eq_tail_overr_hw_ld_12), |
| 2788 | .eq_tail_overr_hw_write_12 (eq_tail_overr_hw_write_12), |
| 2789 | .eq_tail_tail_hw_ld_12 (eq_tail_tail_hw_ld_12), |
| 2790 | .eq_tail_tail_hw_write_12 (eq_tail_tail_hw_write_12), |
| 2791 | .eq_tail_tail_hw_read_12 (eq_tail_tail_hw_read_12), |
| 2792 | .eq_tail_overr_hw_ld_13 (eq_tail_overr_hw_ld_13), |
| 2793 | .eq_tail_overr_hw_write_13 (eq_tail_overr_hw_write_13), |
| 2794 | .eq_tail_tail_hw_ld_13 (eq_tail_tail_hw_ld_13), |
| 2795 | .eq_tail_tail_hw_write_13 (eq_tail_tail_hw_write_13), |
| 2796 | .eq_tail_tail_hw_read_13 (eq_tail_tail_hw_read_13), |
| 2797 | .eq_tail_overr_hw_ld_14 (eq_tail_overr_hw_ld_14), |
| 2798 | .eq_tail_overr_hw_write_14 (eq_tail_overr_hw_write_14), |
| 2799 | .eq_tail_tail_hw_ld_14 (eq_tail_tail_hw_ld_14), |
| 2800 | .eq_tail_tail_hw_write_14 (eq_tail_tail_hw_write_14), |
| 2801 | .eq_tail_tail_hw_read_14 (eq_tail_tail_hw_read_14), |
| 2802 | .eq_tail_overr_hw_ld_15 (eq_tail_overr_hw_ld_15), |
| 2803 | .eq_tail_overr_hw_write_15 (eq_tail_overr_hw_write_15), |
| 2804 | .eq_tail_tail_hw_ld_15 (eq_tail_tail_hw_ld_15), |
| 2805 | .eq_tail_tail_hw_write_15 (eq_tail_tail_hw_write_15), |
| 2806 | .eq_tail_tail_hw_read_15 (eq_tail_tail_hw_read_15), |
| 2807 | .eq_tail_overr_hw_ld_16 (eq_tail_overr_hw_ld_16), |
| 2808 | .eq_tail_overr_hw_write_16 (eq_tail_overr_hw_write_16), |
| 2809 | .eq_tail_tail_hw_ld_16 (eq_tail_tail_hw_ld_16), |
| 2810 | .eq_tail_tail_hw_write_16 (eq_tail_tail_hw_write_16), |
| 2811 | .eq_tail_tail_hw_read_16 (eq_tail_tail_hw_read_16), |
| 2812 | .eq_tail_overr_hw_ld_17 (eq_tail_overr_hw_ld_17), |
| 2813 | .eq_tail_overr_hw_write_17 (eq_tail_overr_hw_write_17), |
| 2814 | .eq_tail_tail_hw_ld_17 (eq_tail_tail_hw_ld_17), |
| 2815 | .eq_tail_tail_hw_write_17 (eq_tail_tail_hw_write_17), |
| 2816 | .eq_tail_tail_hw_read_17 (eq_tail_tail_hw_read_17), |
| 2817 | .eq_tail_overr_hw_ld_18 (eq_tail_overr_hw_ld_18), |
| 2818 | .eq_tail_overr_hw_write_18 (eq_tail_overr_hw_write_18), |
| 2819 | .eq_tail_tail_hw_ld_18 (eq_tail_tail_hw_ld_18), |
| 2820 | .eq_tail_tail_hw_write_18 (eq_tail_tail_hw_write_18), |
| 2821 | .eq_tail_tail_hw_read_18 (eq_tail_tail_hw_read_18), |
| 2822 | .eq_tail_overr_hw_ld_19 (eq_tail_overr_hw_ld_19), |
| 2823 | .eq_tail_overr_hw_write_19 (eq_tail_overr_hw_write_19), |
| 2824 | .eq_tail_tail_hw_ld_19 (eq_tail_tail_hw_ld_19), |
| 2825 | .eq_tail_tail_hw_write_19 (eq_tail_tail_hw_write_19), |
| 2826 | .eq_tail_tail_hw_read_19 (eq_tail_tail_hw_read_19), |
| 2827 | .eq_tail_overr_hw_ld_20 (eq_tail_overr_hw_ld_20), |
| 2828 | .eq_tail_overr_hw_write_20 (eq_tail_overr_hw_write_20), |
| 2829 | .eq_tail_tail_hw_ld_20 (eq_tail_tail_hw_ld_20), |
| 2830 | .eq_tail_tail_hw_write_20 (eq_tail_tail_hw_write_20), |
| 2831 | .eq_tail_tail_hw_read_20 (eq_tail_tail_hw_read_20), |
| 2832 | .eq_tail_overr_hw_ld_21 (eq_tail_overr_hw_ld_21), |
| 2833 | .eq_tail_overr_hw_write_21 (eq_tail_overr_hw_write_21), |
| 2834 | .eq_tail_tail_hw_ld_21 (eq_tail_tail_hw_ld_21), |
| 2835 | .eq_tail_tail_hw_write_21 (eq_tail_tail_hw_write_21), |
| 2836 | .eq_tail_tail_hw_read_21 (eq_tail_tail_hw_read_21), |
| 2837 | .eq_tail_overr_hw_ld_22 (eq_tail_overr_hw_ld_22), |
| 2838 | .eq_tail_overr_hw_write_22 (eq_tail_overr_hw_write_22), |
| 2839 | .eq_tail_tail_hw_ld_22 (eq_tail_tail_hw_ld_22), |
| 2840 | .eq_tail_tail_hw_write_22 (eq_tail_tail_hw_write_22), |
| 2841 | .eq_tail_tail_hw_read_22 (eq_tail_tail_hw_read_22), |
| 2842 | .eq_tail_overr_hw_ld_23 (eq_tail_overr_hw_ld_23), |
| 2843 | .eq_tail_overr_hw_write_23 (eq_tail_overr_hw_write_23), |
| 2844 | .eq_tail_tail_hw_ld_23 (eq_tail_tail_hw_ld_23), |
| 2845 | .eq_tail_tail_hw_write_23 (eq_tail_tail_hw_write_23), |
| 2846 | .eq_tail_tail_hw_read_23 (eq_tail_tail_hw_read_23), |
| 2847 | .eq_tail_overr_hw_ld_24 (eq_tail_overr_hw_ld_24), |
| 2848 | .eq_tail_overr_hw_write_24 (eq_tail_overr_hw_write_24), |
| 2849 | .eq_tail_tail_hw_ld_24 (eq_tail_tail_hw_ld_24), |
| 2850 | .eq_tail_tail_hw_write_24 (eq_tail_tail_hw_write_24), |
| 2851 | .eq_tail_tail_hw_read_24 (eq_tail_tail_hw_read_24), |
| 2852 | .eq_tail_overr_hw_ld_25 (eq_tail_overr_hw_ld_25), |
| 2853 | .eq_tail_overr_hw_write_25 (eq_tail_overr_hw_write_25), |
| 2854 | .eq_tail_tail_hw_ld_25 (eq_tail_tail_hw_ld_25), |
| 2855 | .eq_tail_tail_hw_write_25 (eq_tail_tail_hw_write_25), |
| 2856 | .eq_tail_tail_hw_read_25 (eq_tail_tail_hw_read_25), |
| 2857 | .eq_tail_overr_hw_ld_26 (eq_tail_overr_hw_ld_26), |
| 2858 | .eq_tail_overr_hw_write_26 (eq_tail_overr_hw_write_26), |
| 2859 | .eq_tail_tail_hw_ld_26 (eq_tail_tail_hw_ld_26), |
| 2860 | .eq_tail_tail_hw_write_26 (eq_tail_tail_hw_write_26), |
| 2861 | .eq_tail_tail_hw_read_26 (eq_tail_tail_hw_read_26), |
| 2862 | .eq_tail_overr_hw_ld_27 (eq_tail_overr_hw_ld_27), |
| 2863 | .eq_tail_overr_hw_write_27 (eq_tail_overr_hw_write_27), |
| 2864 | .eq_tail_tail_hw_ld_27 (eq_tail_tail_hw_ld_27), |
| 2865 | .eq_tail_tail_hw_write_27 (eq_tail_tail_hw_write_27), |
| 2866 | .eq_tail_tail_hw_read_27 (eq_tail_tail_hw_read_27), |
| 2867 | .eq_tail_overr_hw_ld_28 (eq_tail_overr_hw_ld_28), |
| 2868 | .eq_tail_overr_hw_write_28 (eq_tail_overr_hw_write_28), |
| 2869 | .eq_tail_tail_hw_ld_28 (eq_tail_tail_hw_ld_28), |
| 2870 | .eq_tail_tail_hw_write_28 (eq_tail_tail_hw_write_28), |
| 2871 | .eq_tail_tail_hw_read_28 (eq_tail_tail_hw_read_28), |
| 2872 | .eq_tail_overr_hw_ld_29 (eq_tail_overr_hw_ld_29), |
| 2873 | .eq_tail_overr_hw_write_29 (eq_tail_overr_hw_write_29), |
| 2874 | .eq_tail_tail_hw_ld_29 (eq_tail_tail_hw_ld_29), |
| 2875 | .eq_tail_tail_hw_write_29 (eq_tail_tail_hw_write_29), |
| 2876 | .eq_tail_tail_hw_read_29 (eq_tail_tail_hw_read_29), |
| 2877 | .eq_tail_overr_hw_ld_30 (eq_tail_overr_hw_ld_30), |
| 2878 | .eq_tail_overr_hw_write_30 (eq_tail_overr_hw_write_30), |
| 2879 | .eq_tail_tail_hw_ld_30 (eq_tail_tail_hw_ld_30), |
| 2880 | .eq_tail_tail_hw_write_30 (eq_tail_tail_hw_write_30), |
| 2881 | .eq_tail_tail_hw_read_30 (eq_tail_tail_hw_read_30), |
| 2882 | .eq_tail_overr_hw_ld_31 (eq_tail_overr_hw_ld_31), |
| 2883 | .eq_tail_overr_hw_write_31 (eq_tail_overr_hw_write_31), |
| 2884 | .eq_tail_tail_hw_ld_31 (eq_tail_tail_hw_ld_31), |
| 2885 | .eq_tail_tail_hw_write_31 (eq_tail_tail_hw_write_31), |
| 2886 | .eq_tail_tail_hw_read_31 (eq_tail_tail_hw_read_31), |
| 2887 | .eq_tail_overr_hw_ld_32 (eq_tail_overr_hw_ld_32), |
| 2888 | .eq_tail_overr_hw_write_32 (eq_tail_overr_hw_write_32), |
| 2889 | .eq_tail_tail_hw_ld_32 (eq_tail_tail_hw_ld_32), |
| 2890 | .eq_tail_tail_hw_write_32 (eq_tail_tail_hw_write_32), |
| 2891 | .eq_tail_tail_hw_read_32 (eq_tail_tail_hw_read_32), |
| 2892 | .eq_tail_overr_hw_ld_33 (eq_tail_overr_hw_ld_33), |
| 2893 | .eq_tail_overr_hw_write_33 (eq_tail_overr_hw_write_33), |
| 2894 | .eq_tail_tail_hw_ld_33 (eq_tail_tail_hw_ld_33), |
| 2895 | .eq_tail_tail_hw_write_33 (eq_tail_tail_hw_write_33), |
| 2896 | .eq_tail_tail_hw_read_33 (eq_tail_tail_hw_read_33), |
| 2897 | .eq_tail_overr_hw_ld_34 (eq_tail_overr_hw_ld_34), |
| 2898 | .eq_tail_overr_hw_write_34 (eq_tail_overr_hw_write_34), |
| 2899 | .eq_tail_tail_hw_ld_34 (eq_tail_tail_hw_ld_34), |
| 2900 | .eq_tail_tail_hw_write_34 (eq_tail_tail_hw_write_34), |
| 2901 | .eq_tail_tail_hw_read_34 (eq_tail_tail_hw_read_34), |
| 2902 | .eq_tail_overr_hw_ld_35 (eq_tail_overr_hw_ld_35), |
| 2903 | .eq_tail_overr_hw_write_35 (eq_tail_overr_hw_write_35), |
| 2904 | .eq_tail_tail_hw_ld_35 (eq_tail_tail_hw_ld_35), |
| 2905 | .eq_tail_tail_hw_write_35 (eq_tail_tail_hw_write_35), |
| 2906 | .eq_tail_tail_hw_read_35 (eq_tail_tail_hw_read_35), |
| 2907 | .eq_tail_select_pulse_0 (default_grp_eq_tail_select_pulse_0), |
| 2908 | .eq_tail_select_pulse_1 (default_grp_eq_tail_select_pulse_1), |
| 2909 | .eq_tail_select_pulse_2 (default_grp_eq_tail_select_pulse_2), |
| 2910 | .eq_tail_select_pulse_3 (default_grp_eq_tail_select_pulse_3), |
| 2911 | .eq_tail_select_pulse_4 (default_grp_eq_tail_select_pulse_4), |
| 2912 | .eq_tail_select_pulse_5 (default_grp_eq_tail_select_pulse_5), |
| 2913 | .eq_tail_select_pulse_6 (default_grp_eq_tail_select_pulse_6), |
| 2914 | .eq_tail_select_pulse_7 (default_grp_eq_tail_select_pulse_7), |
| 2915 | .eq_tail_select_pulse_8 (default_grp_eq_tail_select_pulse_8), |
| 2916 | .eq_tail_select_pulse_9 (default_grp_eq_tail_select_pulse_9), |
| 2917 | .eq_tail_select_pulse_10 (default_grp_eq_tail_select_pulse_10), |
| 2918 | .eq_tail_select_pulse_11 (default_grp_eq_tail_select_pulse_11), |
| 2919 | .eq_tail_select_pulse_12 (default_grp_eq_tail_select_pulse_12), |
| 2920 | .eq_tail_select_pulse_13 (default_grp_eq_tail_select_pulse_13), |
| 2921 | .eq_tail_select_pulse_14 (default_grp_eq_tail_select_pulse_14), |
| 2922 | .eq_tail_select_pulse_15 (default_grp_eq_tail_select_pulse_15), |
| 2923 | .eq_tail_select_pulse_16 (default_grp_eq_tail_select_pulse_16), |
| 2924 | .eq_tail_select_pulse_17 (default_grp_eq_tail_select_pulse_17), |
| 2925 | .eq_tail_select_pulse_18 (default_grp_eq_tail_select_pulse_18), |
| 2926 | .eq_tail_select_pulse_19 (default_grp_eq_tail_select_pulse_19), |
| 2927 | .eq_tail_select_pulse_20 (default_grp_eq_tail_select_pulse_20), |
| 2928 | .eq_tail_select_pulse_21 (default_grp_eq_tail_select_pulse_21), |
| 2929 | .eq_tail_select_pulse_22 (default_grp_eq_tail_select_pulse_22), |
| 2930 | .eq_tail_select_pulse_23 (default_grp_eq_tail_select_pulse_23), |
| 2931 | .eq_tail_select_pulse_24 (default_grp_eq_tail_select_pulse_24), |
| 2932 | .eq_tail_select_pulse_25 (default_grp_eq_tail_select_pulse_25), |
| 2933 | .eq_tail_select_pulse_26 (default_grp_eq_tail_select_pulse_26), |
| 2934 | .eq_tail_select_pulse_27 (default_grp_eq_tail_select_pulse_27), |
| 2935 | .eq_tail_select_pulse_28 (default_grp_eq_tail_select_pulse_28), |
| 2936 | .eq_tail_select_pulse_29 (default_grp_eq_tail_select_pulse_29), |
| 2937 | .eq_tail_select_pulse_30 (default_grp_eq_tail_select_pulse_30), |
| 2938 | .eq_tail_select_pulse_31 (default_grp_eq_tail_select_pulse_31), |
| 2939 | .eq_tail_select_pulse_32 (default_grp_eq_tail_select_pulse_32), |
| 2940 | .eq_tail_select_pulse_33 (default_grp_eq_tail_select_pulse_33), |
| 2941 | .eq_tail_select_pulse_34 (default_grp_eq_tail_select_pulse_34), |
| 2942 | .eq_tail_select_pulse_35 (default_grp_eq_tail_select_pulse_35), |
| 2943 | .eq_head_head_hw_read_0 (eq_head_head_hw_read_0), |
| 2944 | .eq_head_head_hw_read_1 (eq_head_head_hw_read_1), |
| 2945 | .eq_head_head_hw_read_2 (eq_head_head_hw_read_2), |
| 2946 | .eq_head_head_hw_read_3 (eq_head_head_hw_read_3), |
| 2947 | .eq_head_head_hw_read_4 (eq_head_head_hw_read_4), |
| 2948 | .eq_head_head_hw_read_5 (eq_head_head_hw_read_5), |
| 2949 | .eq_head_head_hw_read_6 (eq_head_head_hw_read_6), |
| 2950 | .eq_head_head_hw_read_7 (eq_head_head_hw_read_7), |
| 2951 | .eq_head_head_hw_read_8 (eq_head_head_hw_read_8), |
| 2952 | .eq_head_head_hw_read_9 (eq_head_head_hw_read_9), |
| 2953 | .eq_head_head_hw_read_10 (eq_head_head_hw_read_10), |
| 2954 | .eq_head_head_hw_read_11 (eq_head_head_hw_read_11), |
| 2955 | .eq_head_head_hw_read_12 (eq_head_head_hw_read_12), |
| 2956 | .eq_head_head_hw_read_13 (eq_head_head_hw_read_13), |
| 2957 | .eq_head_head_hw_read_14 (eq_head_head_hw_read_14), |
| 2958 | .eq_head_head_hw_read_15 (eq_head_head_hw_read_15), |
| 2959 | .eq_head_head_hw_read_16 (eq_head_head_hw_read_16), |
| 2960 | .eq_head_head_hw_read_17 (eq_head_head_hw_read_17), |
| 2961 | .eq_head_head_hw_read_18 (eq_head_head_hw_read_18), |
| 2962 | .eq_head_head_hw_read_19 (eq_head_head_hw_read_19), |
| 2963 | .eq_head_head_hw_read_20 (eq_head_head_hw_read_20), |
| 2964 | .eq_head_head_hw_read_21 (eq_head_head_hw_read_21), |
| 2965 | .eq_head_head_hw_read_22 (eq_head_head_hw_read_22), |
| 2966 | .eq_head_head_hw_read_23 (eq_head_head_hw_read_23), |
| 2967 | .eq_head_head_hw_read_24 (eq_head_head_hw_read_24), |
| 2968 | .eq_head_head_hw_read_25 (eq_head_head_hw_read_25), |
| 2969 | .eq_head_head_hw_read_26 (eq_head_head_hw_read_26), |
| 2970 | .eq_head_head_hw_read_27 (eq_head_head_hw_read_27), |
| 2971 | .eq_head_head_hw_read_28 (eq_head_head_hw_read_28), |
| 2972 | .eq_head_head_hw_read_29 (eq_head_head_hw_read_29), |
| 2973 | .eq_head_head_hw_read_30 (eq_head_head_hw_read_30), |
| 2974 | .eq_head_head_hw_read_31 (eq_head_head_hw_read_31), |
| 2975 | .eq_head_head_hw_read_32 (eq_head_head_hw_read_32), |
| 2976 | .eq_head_head_hw_read_33 (eq_head_head_hw_read_33), |
| 2977 | .eq_head_head_hw_read_34 (eq_head_head_hw_read_34), |
| 2978 | .eq_head_head_hw_read_35 (eq_head_head_hw_read_35), |
| 2979 | .eq_head_select_pulse_0 (default_grp_eq_head_select_pulse_0), |
| 2980 | .eq_head_select_pulse_1 (default_grp_eq_head_select_pulse_1), |
| 2981 | .eq_head_select_pulse_2 (default_grp_eq_head_select_pulse_2), |
| 2982 | .eq_head_select_pulse_3 (default_grp_eq_head_select_pulse_3), |
| 2983 | .eq_head_select_pulse_4 (default_grp_eq_head_select_pulse_4), |
| 2984 | .eq_head_select_pulse_5 (default_grp_eq_head_select_pulse_5), |
| 2985 | .eq_head_select_pulse_6 (default_grp_eq_head_select_pulse_6), |
| 2986 | .eq_head_select_pulse_7 (default_grp_eq_head_select_pulse_7), |
| 2987 | .eq_head_select_pulse_8 (default_grp_eq_head_select_pulse_8), |
| 2988 | .eq_head_select_pulse_9 (default_grp_eq_head_select_pulse_9), |
| 2989 | .eq_head_select_pulse_10 (default_grp_eq_head_select_pulse_10), |
| 2990 | .eq_head_select_pulse_11 (default_grp_eq_head_select_pulse_11), |
| 2991 | .eq_head_select_pulse_12 (default_grp_eq_head_select_pulse_12), |
| 2992 | .eq_head_select_pulse_13 (default_grp_eq_head_select_pulse_13), |
| 2993 | .eq_head_select_pulse_14 (default_grp_eq_head_select_pulse_14), |
| 2994 | .eq_head_select_pulse_15 (default_grp_eq_head_select_pulse_15), |
| 2995 | .eq_head_select_pulse_16 (default_grp_eq_head_select_pulse_16), |
| 2996 | .eq_head_select_pulse_17 (default_grp_eq_head_select_pulse_17), |
| 2997 | .eq_head_select_pulse_18 (default_grp_eq_head_select_pulse_18), |
| 2998 | .eq_head_select_pulse_19 (default_grp_eq_head_select_pulse_19), |
| 2999 | .eq_head_select_pulse_20 (default_grp_eq_head_select_pulse_20), |
| 3000 | .eq_head_select_pulse_21 (default_grp_eq_head_select_pulse_21), |
| 3001 | .eq_head_select_pulse_22 (default_grp_eq_head_select_pulse_22), |
| 3002 | .eq_head_select_pulse_23 (default_grp_eq_head_select_pulse_23), |
| 3003 | .eq_head_select_pulse_24 (default_grp_eq_head_select_pulse_24), |
| 3004 | .eq_head_select_pulse_25 (default_grp_eq_head_select_pulse_25), |
| 3005 | .eq_head_select_pulse_26 (default_grp_eq_head_select_pulse_26), |
| 3006 | .eq_head_select_pulse_27 (default_grp_eq_head_select_pulse_27), |
| 3007 | .eq_head_select_pulse_28 (default_grp_eq_head_select_pulse_28), |
| 3008 | .eq_head_select_pulse_29 (default_grp_eq_head_select_pulse_29), |
| 3009 | .eq_head_select_pulse_30 (default_grp_eq_head_select_pulse_30), |
| 3010 | .eq_head_select_pulse_31 (default_grp_eq_head_select_pulse_31), |
| 3011 | .eq_head_select_pulse_32 (default_grp_eq_head_select_pulse_32), |
| 3012 | .eq_head_select_pulse_33 (default_grp_eq_head_select_pulse_33), |
| 3013 | .eq_head_select_pulse_34 (default_grp_eq_head_select_pulse_34), |
| 3014 | .eq_head_select_pulse_35 (default_grp_eq_head_select_pulse_35), |
| 3015 | .rst_l (stage_mux_only_rst_l), |
| 3016 | .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr), |
| 3017 | .daemon_csrbus_wr_out (ext_wr), |
| 3018 | .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data), |
| 3019 | .read_data_0_out (default_grp_read_data_0_out) |
| 3020 | ); |
| 3021 | |
| 3022 | //----- Stage: 2 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only) |
| 3023 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out; |
| 3024 | |
| 3025 | dmu_imu_eqs_stage_mux_only dmu_imu_eqs_stage_mux_only |
| 3026 | ( |
| 3027 | .clk (clk), |
| 3028 | .read_data_0 (default_grp_read_data_0_out), |
| 3029 | .eq_base_address_select_pulse (eq_base_address_select_pulse), |
| 3030 | .eq_base_address_select_pulse_out (default_grp_eq_base_address_select_pulse), |
| 3031 | .eq_ctrl_set_select_0 (eq_ctrl_set_select_0), |
| 3032 | .eq_ctrl_set_select_0_out (default_grp_eq_ctrl_set_select_0), |
| 3033 | .eq_ctrl_set_select_1 (eq_ctrl_set_select_1), |
| 3034 | .eq_ctrl_set_select_1_out (default_grp_eq_ctrl_set_select_1), |
| 3035 | .eq_ctrl_set_select_2 (eq_ctrl_set_select_2), |
| 3036 | .eq_ctrl_set_select_2_out (default_grp_eq_ctrl_set_select_2), |
| 3037 | .eq_ctrl_set_select_3 (eq_ctrl_set_select_3), |
| 3038 | .eq_ctrl_set_select_3_out (default_grp_eq_ctrl_set_select_3), |
| 3039 | .eq_ctrl_set_select_4 (eq_ctrl_set_select_4), |
| 3040 | .eq_ctrl_set_select_4_out (default_grp_eq_ctrl_set_select_4), |
| 3041 | .eq_ctrl_set_select_5 (eq_ctrl_set_select_5), |
| 3042 | .eq_ctrl_set_select_5_out (default_grp_eq_ctrl_set_select_5), |
| 3043 | .eq_ctrl_set_select_6 (eq_ctrl_set_select_6), |
| 3044 | .eq_ctrl_set_select_6_out (default_grp_eq_ctrl_set_select_6), |
| 3045 | .eq_ctrl_set_select_7 (eq_ctrl_set_select_7), |
| 3046 | .eq_ctrl_set_select_7_out (default_grp_eq_ctrl_set_select_7), |
| 3047 | .eq_ctrl_set_select_8 (eq_ctrl_set_select_8), |
| 3048 | .eq_ctrl_set_select_8_out (default_grp_eq_ctrl_set_select_8), |
| 3049 | .eq_ctrl_set_select_9 (eq_ctrl_set_select_9), |
| 3050 | .eq_ctrl_set_select_9_out (default_grp_eq_ctrl_set_select_9), |
| 3051 | .eq_ctrl_set_select_10 (eq_ctrl_set_select_10), |
| 3052 | .eq_ctrl_set_select_10_out (default_grp_eq_ctrl_set_select_10), |
| 3053 | .eq_ctrl_set_select_11 (eq_ctrl_set_select_11), |
| 3054 | .eq_ctrl_set_select_11_out (default_grp_eq_ctrl_set_select_11), |
| 3055 | .eq_ctrl_set_select_12 (eq_ctrl_set_select_12), |
| 3056 | .eq_ctrl_set_select_12_out (default_grp_eq_ctrl_set_select_12), |
| 3057 | .eq_ctrl_set_select_13 (eq_ctrl_set_select_13), |
| 3058 | .eq_ctrl_set_select_13_out (default_grp_eq_ctrl_set_select_13), |
| 3059 | .eq_ctrl_set_select_14 (eq_ctrl_set_select_14), |
| 3060 | .eq_ctrl_set_select_14_out (default_grp_eq_ctrl_set_select_14), |
| 3061 | .eq_ctrl_set_select_15 (eq_ctrl_set_select_15), |
| 3062 | .eq_ctrl_set_select_15_out (default_grp_eq_ctrl_set_select_15), |
| 3063 | .eq_ctrl_set_select_16 (eq_ctrl_set_select_16), |
| 3064 | .eq_ctrl_set_select_16_out (default_grp_eq_ctrl_set_select_16), |
| 3065 | .eq_ctrl_set_select_17 (eq_ctrl_set_select_17), |
| 3066 | .eq_ctrl_set_select_17_out (default_grp_eq_ctrl_set_select_17), |
| 3067 | .eq_ctrl_set_select_18 (eq_ctrl_set_select_18), |
| 3068 | .eq_ctrl_set_select_18_out (default_grp_eq_ctrl_set_select_18), |
| 3069 | .eq_ctrl_set_select_19 (eq_ctrl_set_select_19), |
| 3070 | .eq_ctrl_set_select_19_out (default_grp_eq_ctrl_set_select_19), |
| 3071 | .eq_ctrl_set_select_20 (eq_ctrl_set_select_20), |
| 3072 | .eq_ctrl_set_select_20_out (default_grp_eq_ctrl_set_select_20), |
| 3073 | .eq_ctrl_set_select_21 (eq_ctrl_set_select_21), |
| 3074 | .eq_ctrl_set_select_21_out (default_grp_eq_ctrl_set_select_21), |
| 3075 | .eq_ctrl_set_select_22 (eq_ctrl_set_select_22), |
| 3076 | .eq_ctrl_set_select_22_out (default_grp_eq_ctrl_set_select_22), |
| 3077 | .eq_ctrl_set_select_23 (eq_ctrl_set_select_23), |
| 3078 | .eq_ctrl_set_select_23_out (default_grp_eq_ctrl_set_select_23), |
| 3079 | .eq_ctrl_set_select_24 (eq_ctrl_set_select_24), |
| 3080 | .eq_ctrl_set_select_24_out (default_grp_eq_ctrl_set_select_24), |
| 3081 | .eq_ctrl_set_select_25 (eq_ctrl_set_select_25), |
| 3082 | .eq_ctrl_set_select_25_out (default_grp_eq_ctrl_set_select_25), |
| 3083 | .eq_ctrl_set_select_26 (eq_ctrl_set_select_26), |
| 3084 | .eq_ctrl_set_select_26_out (default_grp_eq_ctrl_set_select_26), |
| 3085 | .eq_ctrl_set_select_27 (eq_ctrl_set_select_27), |
| 3086 | .eq_ctrl_set_select_27_out (default_grp_eq_ctrl_set_select_27), |
| 3087 | .eq_ctrl_set_select_28 (eq_ctrl_set_select_28), |
| 3088 | .eq_ctrl_set_select_28_out (default_grp_eq_ctrl_set_select_28), |
| 3089 | .eq_ctrl_set_select_29 (eq_ctrl_set_select_29), |
| 3090 | .eq_ctrl_set_select_29_out (default_grp_eq_ctrl_set_select_29), |
| 3091 | .eq_ctrl_set_select_30 (eq_ctrl_set_select_30), |
| 3092 | .eq_ctrl_set_select_30_out (default_grp_eq_ctrl_set_select_30), |
| 3093 | .eq_ctrl_set_select_31 (eq_ctrl_set_select_31), |
| 3094 | .eq_ctrl_set_select_31_out (default_grp_eq_ctrl_set_select_31), |
| 3095 | .eq_ctrl_set_select_32 (eq_ctrl_set_select_32), |
| 3096 | .eq_ctrl_set_select_32_out (default_grp_eq_ctrl_set_select_32), |
| 3097 | .eq_ctrl_set_select_33 (eq_ctrl_set_select_33), |
| 3098 | .eq_ctrl_set_select_33_out (default_grp_eq_ctrl_set_select_33), |
| 3099 | .eq_ctrl_set_select_34 (eq_ctrl_set_select_34), |
| 3100 | .eq_ctrl_set_select_34_out (default_grp_eq_ctrl_set_select_34), |
| 3101 | .eq_ctrl_set_select_35 (eq_ctrl_set_select_35), |
| 3102 | .eq_ctrl_set_select_35_out (default_grp_eq_ctrl_set_select_35), |
| 3103 | .eq_ctrl_clr_select_0 (eq_ctrl_clr_select_0), |
| 3104 | .eq_ctrl_clr_select_0_out (default_grp_eq_ctrl_clr_select_0), |
| 3105 | .eq_ctrl_clr_select_1 (eq_ctrl_clr_select_1), |
| 3106 | .eq_ctrl_clr_select_1_out (default_grp_eq_ctrl_clr_select_1), |
| 3107 | .eq_ctrl_clr_select_2 (eq_ctrl_clr_select_2), |
| 3108 | .eq_ctrl_clr_select_2_out (default_grp_eq_ctrl_clr_select_2), |
| 3109 | .eq_ctrl_clr_select_3 (eq_ctrl_clr_select_3), |
| 3110 | .eq_ctrl_clr_select_3_out (default_grp_eq_ctrl_clr_select_3), |
| 3111 | .eq_ctrl_clr_select_4 (eq_ctrl_clr_select_4), |
| 3112 | .eq_ctrl_clr_select_4_out (default_grp_eq_ctrl_clr_select_4), |
| 3113 | .eq_ctrl_clr_select_5 (eq_ctrl_clr_select_5), |
| 3114 | .eq_ctrl_clr_select_5_out (default_grp_eq_ctrl_clr_select_5), |
| 3115 | .eq_ctrl_clr_select_6 (eq_ctrl_clr_select_6), |
| 3116 | .eq_ctrl_clr_select_6_out (default_grp_eq_ctrl_clr_select_6), |
| 3117 | .eq_ctrl_clr_select_7 (eq_ctrl_clr_select_7), |
| 3118 | .eq_ctrl_clr_select_7_out (default_grp_eq_ctrl_clr_select_7), |
| 3119 | .eq_ctrl_clr_select_8 (eq_ctrl_clr_select_8), |
| 3120 | .eq_ctrl_clr_select_8_out (default_grp_eq_ctrl_clr_select_8), |
| 3121 | .eq_ctrl_clr_select_9 (eq_ctrl_clr_select_9), |
| 3122 | .eq_ctrl_clr_select_9_out (default_grp_eq_ctrl_clr_select_9), |
| 3123 | .eq_ctrl_clr_select_10 (eq_ctrl_clr_select_10), |
| 3124 | .eq_ctrl_clr_select_10_out (default_grp_eq_ctrl_clr_select_10), |
| 3125 | .eq_ctrl_clr_select_11 (eq_ctrl_clr_select_11), |
| 3126 | .eq_ctrl_clr_select_11_out (default_grp_eq_ctrl_clr_select_11), |
| 3127 | .eq_ctrl_clr_select_12 (eq_ctrl_clr_select_12), |
| 3128 | .eq_ctrl_clr_select_12_out (default_grp_eq_ctrl_clr_select_12), |
| 3129 | .eq_ctrl_clr_select_13 (eq_ctrl_clr_select_13), |
| 3130 | .eq_ctrl_clr_select_13_out (default_grp_eq_ctrl_clr_select_13), |
| 3131 | .eq_ctrl_clr_select_14 (eq_ctrl_clr_select_14), |
| 3132 | .eq_ctrl_clr_select_14_out (default_grp_eq_ctrl_clr_select_14), |
| 3133 | .eq_ctrl_clr_select_15 (eq_ctrl_clr_select_15), |
| 3134 | .eq_ctrl_clr_select_15_out (default_grp_eq_ctrl_clr_select_15), |
| 3135 | .eq_ctrl_clr_select_16 (eq_ctrl_clr_select_16), |
| 3136 | .eq_ctrl_clr_select_16_out (default_grp_eq_ctrl_clr_select_16), |
| 3137 | .eq_ctrl_clr_select_17 (eq_ctrl_clr_select_17), |
| 3138 | .eq_ctrl_clr_select_17_out (default_grp_eq_ctrl_clr_select_17), |
| 3139 | .eq_ctrl_clr_select_18 (eq_ctrl_clr_select_18), |
| 3140 | .eq_ctrl_clr_select_18_out (default_grp_eq_ctrl_clr_select_18), |
| 3141 | .eq_ctrl_clr_select_19 (eq_ctrl_clr_select_19), |
| 3142 | .eq_ctrl_clr_select_19_out (default_grp_eq_ctrl_clr_select_19), |
| 3143 | .eq_ctrl_clr_select_20 (eq_ctrl_clr_select_20), |
| 3144 | .eq_ctrl_clr_select_20_out (default_grp_eq_ctrl_clr_select_20), |
| 3145 | .eq_ctrl_clr_select_21 (eq_ctrl_clr_select_21), |
| 3146 | .eq_ctrl_clr_select_21_out (default_grp_eq_ctrl_clr_select_21), |
| 3147 | .eq_ctrl_clr_select_22 (eq_ctrl_clr_select_22), |
| 3148 | .eq_ctrl_clr_select_22_out (default_grp_eq_ctrl_clr_select_22), |
| 3149 | .eq_ctrl_clr_select_23 (eq_ctrl_clr_select_23), |
| 3150 | .eq_ctrl_clr_select_23_out (default_grp_eq_ctrl_clr_select_23), |
| 3151 | .eq_ctrl_clr_select_24 (eq_ctrl_clr_select_24), |
| 3152 | .eq_ctrl_clr_select_24_out (default_grp_eq_ctrl_clr_select_24), |
| 3153 | .eq_ctrl_clr_select_25 (eq_ctrl_clr_select_25), |
| 3154 | .eq_ctrl_clr_select_25_out (default_grp_eq_ctrl_clr_select_25), |
| 3155 | .eq_ctrl_clr_select_26 (eq_ctrl_clr_select_26), |
| 3156 | .eq_ctrl_clr_select_26_out (default_grp_eq_ctrl_clr_select_26), |
| 3157 | .eq_ctrl_clr_select_27 (eq_ctrl_clr_select_27), |
| 3158 | .eq_ctrl_clr_select_27_out (default_grp_eq_ctrl_clr_select_27), |
| 3159 | .eq_ctrl_clr_select_28 (eq_ctrl_clr_select_28), |
| 3160 | .eq_ctrl_clr_select_28_out (default_grp_eq_ctrl_clr_select_28), |
| 3161 | .eq_ctrl_clr_select_29 (eq_ctrl_clr_select_29), |
| 3162 | .eq_ctrl_clr_select_29_out (default_grp_eq_ctrl_clr_select_29), |
| 3163 | .eq_ctrl_clr_select_30 (eq_ctrl_clr_select_30), |
| 3164 | .eq_ctrl_clr_select_30_out (default_grp_eq_ctrl_clr_select_30), |
| 3165 | .eq_ctrl_clr_select_31 (eq_ctrl_clr_select_31), |
| 3166 | .eq_ctrl_clr_select_31_out (default_grp_eq_ctrl_clr_select_31), |
| 3167 | .eq_ctrl_clr_select_32 (eq_ctrl_clr_select_32), |
| 3168 | .eq_ctrl_clr_select_32_out (default_grp_eq_ctrl_clr_select_32), |
| 3169 | .eq_ctrl_clr_select_33 (eq_ctrl_clr_select_33), |
| 3170 | .eq_ctrl_clr_select_33_out (default_grp_eq_ctrl_clr_select_33), |
| 3171 | .eq_ctrl_clr_select_34 (eq_ctrl_clr_select_34), |
| 3172 | .eq_ctrl_clr_select_34_out (default_grp_eq_ctrl_clr_select_34), |
| 3173 | .eq_ctrl_clr_select_35 (eq_ctrl_clr_select_35), |
| 3174 | .eq_ctrl_clr_select_35_out (default_grp_eq_ctrl_clr_select_35), |
| 3175 | .eq_state_select_0 (eq_state_select_0), |
| 3176 | .eq_state_select_0_out (default_grp_eq_state_select_0), |
| 3177 | .eq_state_select_1 (eq_state_select_1), |
| 3178 | .eq_state_select_1_out (default_grp_eq_state_select_1), |
| 3179 | .eq_state_select_2 (eq_state_select_2), |
| 3180 | .eq_state_select_2_out (default_grp_eq_state_select_2), |
| 3181 | .eq_state_select_3 (eq_state_select_3), |
| 3182 | .eq_state_select_3_out (default_grp_eq_state_select_3), |
| 3183 | .eq_state_select_4 (eq_state_select_4), |
| 3184 | .eq_state_select_4_out (default_grp_eq_state_select_4), |
| 3185 | .eq_state_select_5 (eq_state_select_5), |
| 3186 | .eq_state_select_5_out (default_grp_eq_state_select_5), |
| 3187 | .eq_state_select_6 (eq_state_select_6), |
| 3188 | .eq_state_select_6_out (default_grp_eq_state_select_6), |
| 3189 | .eq_state_select_7 (eq_state_select_7), |
| 3190 | .eq_state_select_7_out (default_grp_eq_state_select_7), |
| 3191 | .eq_state_select_8 (eq_state_select_8), |
| 3192 | .eq_state_select_8_out (default_grp_eq_state_select_8), |
| 3193 | .eq_state_select_9 (eq_state_select_9), |
| 3194 | .eq_state_select_9_out (default_grp_eq_state_select_9), |
| 3195 | .eq_state_select_10 (eq_state_select_10), |
| 3196 | .eq_state_select_10_out (default_grp_eq_state_select_10), |
| 3197 | .eq_state_select_11 (eq_state_select_11), |
| 3198 | .eq_state_select_11_out (default_grp_eq_state_select_11), |
| 3199 | .eq_state_select_12 (eq_state_select_12), |
| 3200 | .eq_state_select_12_out (default_grp_eq_state_select_12), |
| 3201 | .eq_state_select_13 (eq_state_select_13), |
| 3202 | .eq_state_select_13_out (default_grp_eq_state_select_13), |
| 3203 | .eq_state_select_14 (eq_state_select_14), |
| 3204 | .eq_state_select_14_out (default_grp_eq_state_select_14), |
| 3205 | .eq_state_select_15 (eq_state_select_15), |
| 3206 | .eq_state_select_15_out (default_grp_eq_state_select_15), |
| 3207 | .eq_state_select_16 (eq_state_select_16), |
| 3208 | .eq_state_select_16_out (default_grp_eq_state_select_16), |
| 3209 | .eq_state_select_17 (eq_state_select_17), |
| 3210 | .eq_state_select_17_out (default_grp_eq_state_select_17), |
| 3211 | .eq_state_select_18 (eq_state_select_18), |
| 3212 | .eq_state_select_18_out (default_grp_eq_state_select_18), |
| 3213 | .eq_state_select_19 (eq_state_select_19), |
| 3214 | .eq_state_select_19_out (default_grp_eq_state_select_19), |
| 3215 | .eq_state_select_20 (eq_state_select_20), |
| 3216 | .eq_state_select_20_out (default_grp_eq_state_select_20), |
| 3217 | .eq_state_select_21 (eq_state_select_21), |
| 3218 | .eq_state_select_21_out (default_grp_eq_state_select_21), |
| 3219 | .eq_state_select_22 (eq_state_select_22), |
| 3220 | .eq_state_select_22_out (default_grp_eq_state_select_22), |
| 3221 | .eq_state_select_23 (eq_state_select_23), |
| 3222 | .eq_state_select_23_out (default_grp_eq_state_select_23), |
| 3223 | .eq_state_select_24 (eq_state_select_24), |
| 3224 | .eq_state_select_24_out (default_grp_eq_state_select_24), |
| 3225 | .eq_state_select_25 (eq_state_select_25), |
| 3226 | .eq_state_select_25_out (default_grp_eq_state_select_25), |
| 3227 | .eq_state_select_26 (eq_state_select_26), |
| 3228 | .eq_state_select_26_out (default_grp_eq_state_select_26), |
| 3229 | .eq_state_select_27 (eq_state_select_27), |
| 3230 | .eq_state_select_27_out (default_grp_eq_state_select_27), |
| 3231 | .eq_state_select_28 (eq_state_select_28), |
| 3232 | .eq_state_select_28_out (default_grp_eq_state_select_28), |
| 3233 | .eq_state_select_29 (eq_state_select_29), |
| 3234 | .eq_state_select_29_out (default_grp_eq_state_select_29), |
| 3235 | .eq_state_select_30 (eq_state_select_30), |
| 3236 | .eq_state_select_30_out (default_grp_eq_state_select_30), |
| 3237 | .eq_state_select_31 (eq_state_select_31), |
| 3238 | .eq_state_select_31_out (default_grp_eq_state_select_31), |
| 3239 | .eq_state_select_32 (eq_state_select_32), |
| 3240 | .eq_state_select_32_out (default_grp_eq_state_select_32), |
| 3241 | .eq_state_select_33 (eq_state_select_33), |
| 3242 | .eq_state_select_33_out (default_grp_eq_state_select_33), |
| 3243 | .eq_state_select_34 (eq_state_select_34), |
| 3244 | .eq_state_select_34_out (default_grp_eq_state_select_34), |
| 3245 | .eq_state_select_35 (eq_state_select_35), |
| 3246 | .eq_state_select_35_out (default_grp_eq_state_select_35), |
| 3247 | .eq_tail_select_pulse_0 (eq_tail_select_pulse_0), |
| 3248 | .eq_tail_select_pulse_0_out (default_grp_eq_tail_select_pulse_0), |
| 3249 | .eq_tail_select_pulse_1 (eq_tail_select_pulse_1), |
| 3250 | .eq_tail_select_pulse_1_out (default_grp_eq_tail_select_pulse_1), |
| 3251 | .eq_tail_select_pulse_2 (eq_tail_select_pulse_2), |
| 3252 | .eq_tail_select_pulse_2_out (default_grp_eq_tail_select_pulse_2), |
| 3253 | .eq_tail_select_pulse_3 (eq_tail_select_pulse_3), |
| 3254 | .eq_tail_select_pulse_3_out (default_grp_eq_tail_select_pulse_3), |
| 3255 | .eq_tail_select_pulse_4 (eq_tail_select_pulse_4), |
| 3256 | .eq_tail_select_pulse_4_out (default_grp_eq_tail_select_pulse_4), |
| 3257 | .eq_tail_select_pulse_5 (eq_tail_select_pulse_5), |
| 3258 | .eq_tail_select_pulse_5_out (default_grp_eq_tail_select_pulse_5), |
| 3259 | .eq_tail_select_pulse_6 (eq_tail_select_pulse_6), |
| 3260 | .eq_tail_select_pulse_6_out (default_grp_eq_tail_select_pulse_6), |
| 3261 | .eq_tail_select_pulse_7 (eq_tail_select_pulse_7), |
| 3262 | .eq_tail_select_pulse_7_out (default_grp_eq_tail_select_pulse_7), |
| 3263 | .eq_tail_select_pulse_8 (eq_tail_select_pulse_8), |
| 3264 | .eq_tail_select_pulse_8_out (default_grp_eq_tail_select_pulse_8), |
| 3265 | .eq_tail_select_pulse_9 (eq_tail_select_pulse_9), |
| 3266 | .eq_tail_select_pulse_9_out (default_grp_eq_tail_select_pulse_9), |
| 3267 | .eq_tail_select_pulse_10 (eq_tail_select_pulse_10), |
| 3268 | .eq_tail_select_pulse_10_out (default_grp_eq_tail_select_pulse_10), |
| 3269 | .eq_tail_select_pulse_11 (eq_tail_select_pulse_11), |
| 3270 | .eq_tail_select_pulse_11_out (default_grp_eq_tail_select_pulse_11), |
| 3271 | .eq_tail_select_pulse_12 (eq_tail_select_pulse_12), |
| 3272 | .eq_tail_select_pulse_12_out (default_grp_eq_tail_select_pulse_12), |
| 3273 | .eq_tail_select_pulse_13 (eq_tail_select_pulse_13), |
| 3274 | .eq_tail_select_pulse_13_out (default_grp_eq_tail_select_pulse_13), |
| 3275 | .eq_tail_select_pulse_14 (eq_tail_select_pulse_14), |
| 3276 | .eq_tail_select_pulse_14_out (default_grp_eq_tail_select_pulse_14), |
| 3277 | .eq_tail_select_pulse_15 (eq_tail_select_pulse_15), |
| 3278 | .eq_tail_select_pulse_15_out (default_grp_eq_tail_select_pulse_15), |
| 3279 | .eq_tail_select_pulse_16 (eq_tail_select_pulse_16), |
| 3280 | .eq_tail_select_pulse_16_out (default_grp_eq_tail_select_pulse_16), |
| 3281 | .eq_tail_select_pulse_17 (eq_tail_select_pulse_17), |
| 3282 | .eq_tail_select_pulse_17_out (default_grp_eq_tail_select_pulse_17), |
| 3283 | .eq_tail_select_pulse_18 (eq_tail_select_pulse_18), |
| 3284 | .eq_tail_select_pulse_18_out (default_grp_eq_tail_select_pulse_18), |
| 3285 | .eq_tail_select_pulse_19 (eq_tail_select_pulse_19), |
| 3286 | .eq_tail_select_pulse_19_out (default_grp_eq_tail_select_pulse_19), |
| 3287 | .eq_tail_select_pulse_20 (eq_tail_select_pulse_20), |
| 3288 | .eq_tail_select_pulse_20_out (default_grp_eq_tail_select_pulse_20), |
| 3289 | .eq_tail_select_pulse_21 (eq_tail_select_pulse_21), |
| 3290 | .eq_tail_select_pulse_21_out (default_grp_eq_tail_select_pulse_21), |
| 3291 | .eq_tail_select_pulse_22 (eq_tail_select_pulse_22), |
| 3292 | .eq_tail_select_pulse_22_out (default_grp_eq_tail_select_pulse_22), |
| 3293 | .eq_tail_select_pulse_23 (eq_tail_select_pulse_23), |
| 3294 | .eq_tail_select_pulse_23_out (default_grp_eq_tail_select_pulse_23), |
| 3295 | .eq_tail_select_pulse_24 (eq_tail_select_pulse_24), |
| 3296 | .eq_tail_select_pulse_24_out (default_grp_eq_tail_select_pulse_24), |
| 3297 | .eq_tail_select_pulse_25 (eq_tail_select_pulse_25), |
| 3298 | .eq_tail_select_pulse_25_out (default_grp_eq_tail_select_pulse_25), |
| 3299 | .eq_tail_select_pulse_26 (eq_tail_select_pulse_26), |
| 3300 | .eq_tail_select_pulse_26_out (default_grp_eq_tail_select_pulse_26), |
| 3301 | .eq_tail_select_pulse_27 (eq_tail_select_pulse_27), |
| 3302 | .eq_tail_select_pulse_27_out (default_grp_eq_tail_select_pulse_27), |
| 3303 | .eq_tail_select_pulse_28 (eq_tail_select_pulse_28), |
| 3304 | .eq_tail_select_pulse_28_out (default_grp_eq_tail_select_pulse_28), |
| 3305 | .eq_tail_select_pulse_29 (eq_tail_select_pulse_29), |
| 3306 | .eq_tail_select_pulse_29_out (default_grp_eq_tail_select_pulse_29), |
| 3307 | .eq_tail_select_pulse_30 (eq_tail_select_pulse_30), |
| 3308 | .eq_tail_select_pulse_30_out (default_grp_eq_tail_select_pulse_30), |
| 3309 | .eq_tail_select_pulse_31 (eq_tail_select_pulse_31), |
| 3310 | .eq_tail_select_pulse_31_out (default_grp_eq_tail_select_pulse_31), |
| 3311 | .eq_tail_select_pulse_32 (eq_tail_select_pulse_32), |
| 3312 | .eq_tail_select_pulse_32_out (default_grp_eq_tail_select_pulse_32), |
| 3313 | .eq_tail_select_pulse_33 (eq_tail_select_pulse_33), |
| 3314 | .eq_tail_select_pulse_33_out (default_grp_eq_tail_select_pulse_33), |
| 3315 | .eq_tail_select_pulse_34 (eq_tail_select_pulse_34), |
| 3316 | .eq_tail_select_pulse_34_out (default_grp_eq_tail_select_pulse_34), |
| 3317 | .eq_tail_select_pulse_35 (eq_tail_select_pulse_35), |
| 3318 | .eq_tail_select_pulse_35_out (default_grp_eq_tail_select_pulse_35), |
| 3319 | .eq_head_select_pulse_0 (eq_head_select_pulse_0), |
| 3320 | .eq_head_select_pulse_0_out (default_grp_eq_head_select_pulse_0), |
| 3321 | .eq_head_select_pulse_1 (eq_head_select_pulse_1), |
| 3322 | .eq_head_select_pulse_1_out (default_grp_eq_head_select_pulse_1), |
| 3323 | .eq_head_select_pulse_2 (eq_head_select_pulse_2), |
| 3324 | .eq_head_select_pulse_2_out (default_grp_eq_head_select_pulse_2), |
| 3325 | .eq_head_select_pulse_3 (eq_head_select_pulse_3), |
| 3326 | .eq_head_select_pulse_3_out (default_grp_eq_head_select_pulse_3), |
| 3327 | .eq_head_select_pulse_4 (eq_head_select_pulse_4), |
| 3328 | .eq_head_select_pulse_4_out (default_grp_eq_head_select_pulse_4), |
| 3329 | .eq_head_select_pulse_5 (eq_head_select_pulse_5), |
| 3330 | .eq_head_select_pulse_5_out (default_grp_eq_head_select_pulse_5), |
| 3331 | .eq_head_select_pulse_6 (eq_head_select_pulse_6), |
| 3332 | .eq_head_select_pulse_6_out (default_grp_eq_head_select_pulse_6), |
| 3333 | .eq_head_select_pulse_7 (eq_head_select_pulse_7), |
| 3334 | .eq_head_select_pulse_7_out (default_grp_eq_head_select_pulse_7), |
| 3335 | .eq_head_select_pulse_8 (eq_head_select_pulse_8), |
| 3336 | .eq_head_select_pulse_8_out (default_grp_eq_head_select_pulse_8), |
| 3337 | .eq_head_select_pulse_9 (eq_head_select_pulse_9), |
| 3338 | .eq_head_select_pulse_9_out (default_grp_eq_head_select_pulse_9), |
| 3339 | .eq_head_select_pulse_10 (eq_head_select_pulse_10), |
| 3340 | .eq_head_select_pulse_10_out (default_grp_eq_head_select_pulse_10), |
| 3341 | .eq_head_select_pulse_11 (eq_head_select_pulse_11), |
| 3342 | .eq_head_select_pulse_11_out (default_grp_eq_head_select_pulse_11), |
| 3343 | .eq_head_select_pulse_12 (eq_head_select_pulse_12), |
| 3344 | .eq_head_select_pulse_12_out (default_grp_eq_head_select_pulse_12), |
| 3345 | .eq_head_select_pulse_13 (eq_head_select_pulse_13), |
| 3346 | .eq_head_select_pulse_13_out (default_grp_eq_head_select_pulse_13), |
| 3347 | .eq_head_select_pulse_14 (eq_head_select_pulse_14), |
| 3348 | .eq_head_select_pulse_14_out (default_grp_eq_head_select_pulse_14), |
| 3349 | .eq_head_select_pulse_15 (eq_head_select_pulse_15), |
| 3350 | .eq_head_select_pulse_15_out (default_grp_eq_head_select_pulse_15), |
| 3351 | .eq_head_select_pulse_16 (eq_head_select_pulse_16), |
| 3352 | .eq_head_select_pulse_16_out (default_grp_eq_head_select_pulse_16), |
| 3353 | .eq_head_select_pulse_17 (eq_head_select_pulse_17), |
| 3354 | .eq_head_select_pulse_17_out (default_grp_eq_head_select_pulse_17), |
| 3355 | .eq_head_select_pulse_18 (eq_head_select_pulse_18), |
| 3356 | .eq_head_select_pulse_18_out (default_grp_eq_head_select_pulse_18), |
| 3357 | .eq_head_select_pulse_19 (eq_head_select_pulse_19), |
| 3358 | .eq_head_select_pulse_19_out (default_grp_eq_head_select_pulse_19), |
| 3359 | .eq_head_select_pulse_20 (eq_head_select_pulse_20), |
| 3360 | .eq_head_select_pulse_20_out (default_grp_eq_head_select_pulse_20), |
| 3361 | .eq_head_select_pulse_21 (eq_head_select_pulse_21), |
| 3362 | .eq_head_select_pulse_21_out (default_grp_eq_head_select_pulse_21), |
| 3363 | .eq_head_select_pulse_22 (eq_head_select_pulse_22), |
| 3364 | .eq_head_select_pulse_22_out (default_grp_eq_head_select_pulse_22), |
| 3365 | .eq_head_select_pulse_23 (eq_head_select_pulse_23), |
| 3366 | .eq_head_select_pulse_23_out (default_grp_eq_head_select_pulse_23), |
| 3367 | .eq_head_select_pulse_24 (eq_head_select_pulse_24), |
| 3368 | .eq_head_select_pulse_24_out (default_grp_eq_head_select_pulse_24), |
| 3369 | .eq_head_select_pulse_25 (eq_head_select_pulse_25), |
| 3370 | .eq_head_select_pulse_25_out (default_grp_eq_head_select_pulse_25), |
| 3371 | .eq_head_select_pulse_26 (eq_head_select_pulse_26), |
| 3372 | .eq_head_select_pulse_26_out (default_grp_eq_head_select_pulse_26), |
| 3373 | .eq_head_select_pulse_27 (eq_head_select_pulse_27), |
| 3374 | .eq_head_select_pulse_27_out (default_grp_eq_head_select_pulse_27), |
| 3375 | .eq_head_select_pulse_28 (eq_head_select_pulse_28), |
| 3376 | .eq_head_select_pulse_28_out (default_grp_eq_head_select_pulse_28), |
| 3377 | .eq_head_select_pulse_29 (eq_head_select_pulse_29), |
| 3378 | .eq_head_select_pulse_29_out (default_grp_eq_head_select_pulse_29), |
| 3379 | .eq_head_select_pulse_30 (eq_head_select_pulse_30), |
| 3380 | .eq_head_select_pulse_30_out (default_grp_eq_head_select_pulse_30), |
| 3381 | .eq_head_select_pulse_31 (eq_head_select_pulse_31), |
| 3382 | .eq_head_select_pulse_31_out (default_grp_eq_head_select_pulse_31), |
| 3383 | .eq_head_select_pulse_32 (eq_head_select_pulse_32), |
| 3384 | .eq_head_select_pulse_32_out (default_grp_eq_head_select_pulse_32), |
| 3385 | .eq_head_select_pulse_33 (eq_head_select_pulse_33), |
| 3386 | .eq_head_select_pulse_33_out (default_grp_eq_head_select_pulse_33), |
| 3387 | .eq_head_select_pulse_34 (eq_head_select_pulse_34), |
| 3388 | .eq_head_select_pulse_34_out (default_grp_eq_head_select_pulse_34), |
| 3389 | .eq_head_select_pulse_35 (eq_head_select_pulse_35), |
| 3390 | .eq_head_select_pulse_35_out (default_grp_eq_head_select_pulse_35), |
| 3391 | .daemon_csrbus_wr_in (daemon_csrbus_wr), |
| 3392 | .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr), |
| 3393 | .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data), |
| 3394 | .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data), |
| 3395 | .read_data_0_out (stage_mux_only_read_data_0_out), |
| 3396 | .rst_l (rst_l), |
| 3397 | .rst_l_out (stage_mux_only_rst_l) |
| 3398 | ); |
| 3399 | |
| 3400 | //----- OUTPUT: csrbus_read_data |
| 3401 | assign csrbus_read_data = stage_mux_only_read_data_0_out; |
| 3402 | |
| 3403 | endmodule // dmu_imu_eqs_csr |