| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | por_l, |
| 42 | |
| 43 | // DMC Block Level Input Interrupt Signals |
| 44 | |
| 45 | mm2im_int, |
| 46 | y2k_int_l, |
| 47 | |
| 48 | // IMU sub-block Level Input Interrupt Signals |
| 49 | |
| 50 | rds2ics_msi_mal_error, |
| 51 | rds2ics_msi_par_error, |
| 52 | rds2ics_pmeack_mes_not_en_error, |
| 53 | rds2ics_pmpme_mes_not_en_error, |
| 54 | rds2ics_fatal_mes_not_en_error, |
| 55 | rds2ics_nonfatal_mes_not_en_error, |
| 56 | rds2ics_cor_mes_not_en_error, |
| 57 | rds2ics_msi_not_en_error, |
| 58 | rds2ics_error_data, |
| 59 | |
| 60 | eqs2ics_eq_over_error, |
| 61 | eqs2ics_error_data, |
| 62 | |
| 63 | scs2ics_eq_not_en_error, |
| 64 | scs2ics_error_data, |
| 65 | |
| 66 | // DMC/PEC Core Level Output Interrupt Signals |
| 67 | |
| 68 | ics2iss_mondo_62_int_l, |
| 69 | ics2iss_mondo_63_int_l, |
| 70 | |
| 71 | // TMU Static CSR Signals |
| 72 | |
| 73 | im2tm_msi32_addr_reg, |
| 74 | im2tm_msi64_addr_reg, |
| 75 | im2rm_mem64_offset_reg, |
| 76 | |
| 77 | |
| 78 | // CSR Bus Signals |
| 79 | |
| 80 | csrbus_valid, |
| 81 | csrbus_done, |
| 82 | csrbus_mapped, |
| 83 | csrbus_wr_data, |
| 84 | csrbus_wr, |
| 85 | csrbus_read_data, |
| 86 | csrbus_addr, |
| 87 | csrbus_src_bus, |
| 88 | csrbus_acc_vio, |
| 89 | |
| 90 | // Static ID |
| 91 | j2d_instance_id, |
| 92 | |
| 93 | //Perf Counters |
| 94 | |
| 95 | ors2ics_perf_eq_mondos, |
| 96 | ors2ics_perf_mondos, |
| 97 | ors2ics_perf_msi, |
| 98 | ors2ics_perf_eq_wr, |
| 99 | |
| 100 | rss2ics_perf_mondo_nacks, |
| 101 | |
| 102 | // for N2 debug |
| 103 | dmu_dbg_err_event, |
| 104 | |
| 105 | // for N2 pio stall enable for bug 107207 |
| 106 | im2crm_bc_stall_en, |
| 107 | im2crm_ilu_stall_en |
| 108 | |
| 109 | ); |
| 110 | |
| 111 | |
| 112 | //############################################################################ |
| 113 | // PORT DECLARATIONS |
| 114 | //############################################################################ |
| 115 | |
| 116 | |
| 117 | //------------------------------------------------------------------------ |
| 118 | // Clock and Reset Signals |
| 119 | //------------------------------------------------------------------------ |
| 120 | input clk; |
| 121 | input rst_l; |
| 122 | input por_l; |
| 123 | |
| 124 | |
| 125 | //------------------------------------------------------------------------ |
| 126 | // DMC Block Level Input Interrupt Signals |
| 127 | //------------------------------------------------------------------------ |
| 128 | |
| 129 | input mm2im_int; // MMU Interrupt signal active high |
| 130 | input y2k_int_l; // PEC core Int signal active low |
| 131 | |
| 132 | |
| 133 | //------------------------------------------------------------------------ |
| 134 | // IMU sub-block Level Input Interrupt Signals |
| 135 | //------------------------------------------------------------------------ |
| 136 | |
| 137 | input rds2ics_msi_mal_error; |
| 138 | input rds2ics_msi_par_error; |
| 139 | input rds2ics_pmeack_mes_not_en_error; |
| 140 | input rds2ics_pmpme_mes_not_en_error; |
| 141 | input rds2ics_fatal_mes_not_en_error; |
| 142 | input rds2ics_nonfatal_mes_not_en_error; |
| 143 | input rds2ics_cor_mes_not_en_error; |
| 144 | input rds2ics_msi_not_en_error; |
| 145 | input [63:0] rds2ics_error_data; |
| 146 | |
| 147 | input eqs2ics_eq_over_error; |
| 148 | input [63:0] eqs2ics_error_data; |
| 149 | |
| 150 | input scs2ics_eq_not_en_error; |
| 151 | input [63:0] scs2ics_error_data; |
| 152 | |
| 153 | |
| 154 | //------------------------------------------------------------------------ |
| 155 | // DMC/PEC Core Level Output Interrupt Signals |
| 156 | //------------------------------------------------------------------------ |
| 157 | |
| 158 | output ics2iss_mondo_62_int_l; |
| 159 | output ics2iss_mondo_63_int_l; |
| 160 | |
| 161 | |
| 162 | //------------------------------------------------------------------------ |
| 163 | // TMU Static CSR Signals |
| 164 | //------------------------------------------------------------------------ |
| 165 | |
| 166 | output [15:0] im2tm_msi32_addr_reg; |
| 167 | output [47:0] im2tm_msi64_addr_reg; |
| 168 | output [39:0] im2rm_mem64_offset_reg; |
| 169 | |
| 170 | |
| 171 | //------------------------------------------------------------------------ |
| 172 | // PIO INTERFACE |
| 173 | //------------------------------------------------------------------------ |
| 174 | input csrbus_valid; |
| 175 | output csrbus_done; |
| 176 | output csrbus_mapped; |
| 177 | |
| 178 | input [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_wr_data; |
| 179 | input csrbus_wr; |
| 180 | |
| 181 | output [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_read_data; |
| 182 | |
| 183 | input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] csrbus_addr; |
| 184 | |
| 185 | input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] csrbus_src_bus; |
| 186 | output csrbus_acc_vio; |
| 187 | |
| 188 | |
| 189 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; |
| 190 | |
| 191 | //------------------------------------------------------------------------ |
| 192 | // Perf Counters |
| 193 | //------------------------------------------------------------------------ |
| 194 | input ors2ics_perf_eq_mondos; |
| 195 | input ors2ics_perf_mondos; |
| 196 | input ors2ics_perf_msi; |
| 197 | input ors2ics_perf_eq_wr; |
| 198 | |
| 199 | input rss2ics_perf_mondo_nacks; |
| 200 | //------------------------------------------------------------------------ |
| 201 | // for N2 debug |
| 202 | //------------------------------------------------------------------------ |
| 203 | output dmu_dbg_err_event; |
| 204 | |
| 205 | //------------------------------------------------------------------------ |
| 206 | // for N2 stall fix enables for bug 107207 |
| 207 | //------------------------------------------------------------------------ |
| 208 | output im2crm_bc_stall_en; |
| 209 | output im2crm_ilu_stall_en; |
| 210 | |
| 211 | //############################################################################ |
| 212 | // SIGNAL DECLARATIONS |
| 213 | //############################################################################ |
| 214 | |
| 215 | //************************************************** |
| 216 | // Wires |
| 217 | //************************************************** |
| 218 | |
| 219 | wire imu_mask; |
| 220 | wire mmu_mask; |
| 221 | wire dmc_mask; |
| 222 | |
| 223 | wire im2im_int; |
| 224 | |
| 225 | wire imu_block_int; |
| 226 | wire mmu_block_int; |
| 227 | |
| 228 | wire dmc_core_int_l; |
| 229 | wire dmc_core_int; |
| 230 | |
| 231 | wire pec_core_int_l; |
| 232 | wire pec_core_int; |
| 233 | |
| 234 | reg [4:0] spare_error; |
| 235 | wire [7:0] spare_control_load; |
| 236 | wire [7:0] spare_control; |
| 237 | wire [7:0] spare_status; |
| 238 | //------------------------------------------- |
| 239 | // Log Enable Wires |
| 240 | //------------------------------------------- |
| 241 | |
| 242 | wire [4:0] spare_error_log_en; |
| 243 | wire eq_over_error_log_en; |
| 244 | wire eq_not_en_error_log_en; |
| 245 | wire msi_mal_error_log_en; |
| 246 | wire msi_par_error_log_en; |
| 247 | wire pmeack_mes_not_en_error_log_en; |
| 248 | wire pmpme_mes_not_en_error_log_en; |
| 249 | wire fatal_mes_not_en_error_log_en; |
| 250 | wire nonfatal_mes_not_en_error_log_en; |
| 251 | wire cor_mes_not_en_error_log_en; |
| 252 | wire msi_not_en_error_log_en; |
| 253 | |
| 254 | //------------------------------------------- |
| 255 | // INT Enable Primary Wires |
| 256 | //------------------------------------------- |
| 257 | |
| 258 | wire [4:0] spare_error_p_int_en; |
| 259 | wire eq_over_error_p_int_en; |
| 260 | wire eq_not_en_error_p_int_en; |
| 261 | wire msi_mal_error_p_int_en; |
| 262 | wire msi_par_error_p_int_en; |
| 263 | wire pmeack_mes_not_en_error_p_int_en; |
| 264 | wire pmpme_mes_not_en_error_p_int_en; |
| 265 | wire fatal_mes_not_en_error_p_int_en; |
| 266 | wire nonfatal_mes_not_en_error_p_int_en; |
| 267 | wire cor_mes_not_en_error_p_int_en; |
| 268 | wire msi_not_en_error_p_int_en; |
| 269 | |
| 270 | //------------------------------------------- |
| 271 | // INT Enable Secondary Wires |
| 272 | //------------------------------------------- |
| 273 | |
| 274 | wire [4:0] spare_error_s_int_en; |
| 275 | wire eq_over_error_s_int_en; |
| 276 | wire eq_not_en_error_s_int_en; |
| 277 | wire msi_mal_error_s_int_en; |
| 278 | wire msi_par_error_s_int_en; |
| 279 | wire pmeack_mes_not_en_error_s_int_en; |
| 280 | wire pmpme_mes_not_en_error_s_int_en; |
| 281 | wire fatal_mes_not_en_error_s_int_en; |
| 282 | wire nonfatal_mes_not_en_error_s_int_en; |
| 283 | wire cor_mes_not_en_error_s_int_en; |
| 284 | wire msi_not_en_error_s_int_en; |
| 285 | |
| 286 | |
| 287 | |
| 288 | //------------------------------------------- |
| 289 | // Anded Error and Log Enable Wires |
| 290 | //------------------------------------------- |
| 291 | |
| 292 | wire [4:0] log_spare_error; |
| 293 | wire log_eq_over_error; |
| 294 | wire log_eq_not_en_error; |
| 295 | wire log_msi_mal_error; |
| 296 | wire log_msi_par_error; |
| 297 | wire log_pmeack_mes_not_en_error; |
| 298 | wire log_pmpme_mes_not_en_error; |
| 299 | wire log_fatal_mes_not_en_error; |
| 300 | wire log_nonfatal_mes_not_en_error; |
| 301 | wire log_cor_mes_not_en_error; |
| 302 | wire log_msi_not_en_error; |
| 303 | |
| 304 | //------------------------------------------- |
| 305 | // Set wire for Primary Logged Error Stat |
| 306 | //------------------------------------------- |
| 307 | |
| 308 | wire [4:0] set_p_logged_spare; |
| 309 | wire set_p_logged_eq_over; |
| 310 | wire set_p_logged_eq_not_en; |
| 311 | wire set_p_logged_msi_mal; |
| 312 | wire set_p_logged_msi_par; |
| 313 | wire set_p_logged_pmeack_mes_not_en; |
| 314 | wire set_p_logged_pmpme_mes_not_en; |
| 315 | wire set_p_logged_fatal_mes_not_en; |
| 316 | wire set_p_logged_nonfatal_mes_not_en; |
| 317 | wire set_p_logged_cor_mes_not_en; |
| 318 | wire set_p_logged_msi_not_en; |
| 319 | |
| 320 | //------------------------------------------- |
| 321 | // Set wire for Sec Logged Error Stat |
| 322 | //------------------------------------------- |
| 323 | |
| 324 | wire [4:0] set_s_logged_spare; |
| 325 | wire set_s_logged_eq_over; |
| 326 | wire set_s_logged_eq_not_en; |
| 327 | wire set_s_logged_msi_mal; |
| 328 | wire set_s_logged_msi_par; |
| 329 | wire set_s_logged_pmeack_mes_not_en; |
| 330 | wire set_s_logged_pmpme_mes_not_en; |
| 331 | wire set_s_logged_fatal_mes_not_en; |
| 332 | wire set_s_logged_nonfatal_mes_not_en; |
| 333 | wire set_s_logged_cor_mes_not_en; |
| 334 | wire set_s_logged_msi_not_en; |
| 335 | |
| 336 | |
| 337 | //------------------------------------------- |
| 338 | //Read Port wire Primary Logged Error Stat |
| 339 | //------------------------------------------- |
| 340 | |
| 341 | wire [4:0] logged_p_spare_reg; |
| 342 | wire logged_p_eq_over_reg; |
| 343 | wire logged_p_eq_not_en_reg; |
| 344 | wire logged_p_msi_mal_reg; |
| 345 | wire logged_p_msi_par_reg; |
| 346 | wire logged_p_pmeack_mes_not_en_reg; |
| 347 | wire logged_p_pmpme_mes_not_en_reg; |
| 348 | wire logged_p_fatal_mes_not_en_reg; |
| 349 | wire logged_p_nonfatal_mes_not_en_reg; |
| 350 | wire logged_p_cor_mes_not_en_reg; |
| 351 | wire logged_p_msi_not_en_reg; |
| 352 | |
| 353 | //------------------------------------------- |
| 354 | //Read Port wire Sec Logged Error Stat |
| 355 | //------------------------------------------- |
| 356 | |
| 357 | wire [4:0] logged_s_spare_reg; |
| 358 | wire logged_s_eq_over_reg; |
| 359 | wire logged_s_eq_not_en_reg; |
| 360 | wire logged_s_msi_mal_reg; |
| 361 | wire logged_s_msi_par_reg; |
| 362 | wire logged_s_pmeack_mes_not_en_reg; |
| 363 | wire logged_s_pmpme_mes_not_en_reg; |
| 364 | wire logged_s_fatal_mes_not_en_reg; |
| 365 | wire logged_s_nonfatal_mes_not_en_reg; |
| 366 | wire logged_s_cor_mes_not_en_reg; |
| 367 | wire logged_s_msi_not_en_reg; |
| 368 | |
| 369 | //------------------------------------------- |
| 370 | // Set wire for Primary Enabled Err Stat Reg |
| 371 | //------------------------------------------- |
| 372 | |
| 373 | wire [4:0] enabled_p_spare; |
| 374 | wire enabled_p_eq_over; |
| 375 | wire enabled_p_eq_not_en; |
| 376 | wire enabled_p_msi_mal; |
| 377 | wire enabled_p_msi_par; |
| 378 | wire enabled_p_pmeack_mes_not_en; |
| 379 | wire enabled_p_pmpme_mes_not_en; |
| 380 | wire enabled_p_fatal_mes_not_en; |
| 381 | wire enabled_p_nonfatal_mes_not_en; |
| 382 | wire enabled_p_cor_mes_not_en; |
| 383 | wire enabled_p_msi_not_en; |
| 384 | |
| 385 | //------------------------------------------- |
| 386 | // Set wire for Sec Enabled Err Stat Reg |
| 387 | //------------------------------------------- |
| 388 | |
| 389 | wire [4:0] enabled_s_spare; |
| 390 | wire enabled_s_eq_over; |
| 391 | wire enabled_s_eq_not_en; |
| 392 | wire enabled_s_msi_mal; |
| 393 | wire enabled_s_msi_par; |
| 394 | wire enabled_s_pmeack_mes_not_en; |
| 395 | wire enabled_s_pmpme_mes_not_en; |
| 396 | wire enabled_s_fatal_mes_not_en; |
| 397 | wire enabled_s_nonfatal_mes_not_en; |
| 398 | wire enabled_s_cor_mes_not_en; |
| 399 | wire enabled_s_msi_not_en; |
| 400 | |
| 401 | wire rds_group_p_error_set; |
| 402 | wire scs_group_p_error_set; |
| 403 | wire eqs_group_p_error_set; |
| 404 | |
| 405 | wire load_rds_logging_reg; |
| 406 | wire load_scs_logging_reg; |
| 407 | wire load_eqs_logging_reg; |
| 408 | |
| 409 | |
| 410 | //-------------------------------------------- |
| 411 | // Perf Counters |
| 412 | //-------------------------------------------- |
| 413 | wire [`FIRE_PRF_ADDR_BITS] prfc_sel1_hw_read; |
| 414 | wire [`FIRE_PRF_ADDR_BITS] prfc_sel0_hw_read; |
| 415 | |
| 416 | wire [`FIRE_PRF_DATA_BITS] prf0_cnt_hw_read; |
| 417 | wire [`FIRE_PRF_DATA_BITS] prf1_cnt_hw_read; |
| 418 | |
| 419 | wire [`FIRE_PRF_DATA_BITS] prf0_cnt_hw_write; |
| 420 | wire [`FIRE_PRF_DATA_BITS] prf1_cnt_hw_write; |
| 421 | |
| 422 | wire [`FIRE_PRF_DATA_BITS] inc_cnt0; |
| 423 | wire [`FIRE_PRF_DATA_BITS] inc_cnt1; |
| 424 | |
| 425 | //************************************************** |
| 426 | // Registers that Are Not Flops |
| 427 | //************************************************** |
| 428 | |
| 429 | |
| 430 | //************************************************** |
| 431 | // Registers that Are Flops |
| 432 | //************************************************** |
| 433 | reg [`FIRE_PRF_ADDR_BITS] prf_sel [0:1]; |
| 434 | reg [1:0] prf_inc; |
| 435 | |
| 436 | reg [7:0] spare_control_load_reg; |
| 437 | reg [7:0] spare_control_reg; |
| 438 | reg [7:0] spare_status_reg; |
| 439 | |
| 440 | integer i; |
| 441 | //############################################################################ |
| 442 | // ZERO IN CHECKERS |
| 443 | //############################################################################ |
| 444 | |
| 445 | |
| 446 | |
| 447 | //############################################################################ |
| 448 | // COMBINATIONAL LOGIC FOR DMC ERRORS |
| 449 | //############################################################################ |
| 450 | |
| 451 | //---------------------------------- |
| 452 | // IMU Block Level Interrupt Signals |
| 453 | // |
| 454 | // Consentrate All Error Signals |
| 455 | //---------------------------------- |
| 456 | |
| 457 | assign im2im_int = enabled_p_spare[0] | |
| 458 | enabled_s_spare[0] | |
| 459 | enabled_p_spare[1] | |
| 460 | enabled_s_spare[1] | |
| 461 | enabled_p_spare[2] | |
| 462 | enabled_s_spare[2] | |
| 463 | enabled_p_spare[3] | |
| 464 | enabled_s_spare[3] | |
| 465 | enabled_p_spare[4] | |
| 466 | enabled_s_spare[4] | |
| 467 | enabled_p_eq_over | |
| 468 | enabled_p_eq_not_en | |
| 469 | enabled_p_msi_mal | |
| 470 | enabled_p_msi_par | |
| 471 | enabled_p_pmeack_mes_not_en | |
| 472 | enabled_p_pmpme_mes_not_en | |
| 473 | enabled_p_fatal_mes_not_en | |
| 474 | enabled_p_nonfatal_mes_not_en | |
| 475 | enabled_p_cor_mes_not_en | |
| 476 | enabled_p_msi_not_en | |
| 477 | enabled_s_eq_over | |
| 478 | enabled_s_eq_not_en | |
| 479 | enabled_s_msi_mal | |
| 480 | enabled_s_msi_par | |
| 481 | enabled_s_pmeack_mes_not_en | |
| 482 | enabled_s_pmpme_mes_not_en | |
| 483 | enabled_s_fatal_mes_not_en | |
| 484 | enabled_s_nonfatal_mes_not_en | |
| 485 | enabled_s_cor_mes_not_en | |
| 486 | enabled_s_msi_not_en; |
| 487 | |
| 488 | //---------------------------------- |
| 489 | // IMU Block Level Interrupt Signal |
| 490 | // |
| 491 | // - Active High |
| 492 | // - Anded with IMU Block mask |
| 493 | // - Anded with DMC Core Mask |
| 494 | //---------------------------------- |
| 495 | |
| 496 | assign imu_block_int = imu_mask & dmc_mask & im2im_int; |
| 497 | |
| 498 | //--------------------------------- |
| 499 | // MMU Block Level Interrupt Signal |
| 500 | // |
| 501 | // - Active High |
| 502 | // - Anded with MMU Block mask |
| 503 | // - Anded with DMC Core Mask |
| 504 | //---------------------------------- |
| 505 | |
| 506 | assign mmu_block_int = mmu_mask & dmc_mask & mm2im_int; |
| 507 | |
| 508 | |
| 509 | |
| 510 | //--------------------------------- |
| 511 | // DMC Core Level Interrupt Signal |
| 512 | // |
| 513 | // - Active Low |
| 514 | // - Ored Block level signals |
| 515 | // - Inverted |
| 516 | //---------------------------------- |
| 517 | |
| 518 | assign dmc_core_int_l = ~(mmu_block_int | imu_block_int); |
| 519 | // assign dmc_core_int = ~dmc_core_int_l; |
| 520 | |
| 521 | //--------------------------------- |
| 522 | // PEC Core Level Interrupt Signal |
| 523 | // |
| 524 | // - Active Low |
| 525 | // - Ored Block level signals |
| 526 | // - From Pec |
| 527 | //---------------------------------- |
| 528 | |
| 529 | assign pec_core_int_l = y2k_int_l; |
| 530 | // assign pec_core_int = ~pec_core_int_l; |
| 531 | |
| 532 | //--------------------------------- |
| 533 | // Mondo 62 Interrupt Signal |
| 534 | // |
| 535 | // - Active Low |
| 536 | // - Anded core level signals |
| 537 | //---------------------------------- |
| 538 | assign ics2iss_mondo_62_int_l = dmc_core_int_l; |
| 539 | assign ics2iss_mondo_63_int_l = pec_core_int_l; |
| 540 | |
| 541 | // for N2 debug |
| 542 | wire debug_trig_en; |
| 543 | assign dmu_dbg_err_event = debug_trig_en & (~(dmc_core_int_l & pec_core_int_l)); |
| 544 | //############################################################################ |
| 545 | // COMBINATIONAL LOGIC FOR IMU ERRORS |
| 546 | //############################################################################ |
| 547 | |
| 548 | |
| 549 | |
| 550 | //----------------------------------------------------- |
| 551 | // Determine if the Detected Error needs to be logged |
| 552 | // |
| 553 | // - Take Error Signal and AND with Log Enable |
| 554 | //------------------------------------------------------ |
| 555 | |
| 556 | //--------------------------- |
| 557 | // Tie off Spare |
| 558 | //--------------------------- |
| 559 | |
| 560 | //--------------------------------------------------------- |
| 561 | // Tie Off spare Errors |
| 562 | // |
| 563 | // Makingthem a Flop so the error logic doesn't get optimized out |
| 564 | // |
| 565 | // Also leaving reset in so can possibly use these as spare flops later |
| 566 | //---------------------------------------------------------- |
| 567 | |
| 568 | always @(posedge clk) |
| 569 | begin |
| 570 | if (!rst_l) |
| 571 | spare_error <= 5'b0; |
| 572 | else |
| 573 | spare_error <= 5'b0; |
| 574 | end |
| 575 | assign log_spare_error[0] = spare_error[0] & spare_error_log_en[0]; |
| 576 | assign log_spare_error[1] = spare_error[1] & spare_error_log_en[1]; |
| 577 | assign log_spare_error[2] = spare_error[2] & spare_error_log_en[2]; |
| 578 | assign log_spare_error[3] = spare_error[3] & spare_error_log_en[3]; |
| 579 | assign log_spare_error[4] = spare_error[4] & spare_error_log_en[4]; |
| 580 | assign log_eq_over_error = eqs2ics_eq_over_error & eq_over_error_log_en; |
| 581 | assign log_eq_not_en_error = scs2ics_eq_not_en_error & eq_not_en_error_log_en; |
| 582 | assign log_msi_mal_error = rds2ics_msi_mal_error & msi_mal_error_log_en; |
| 583 | assign log_msi_par_error = rds2ics_msi_par_error & msi_par_error_log_en; |
| 584 | assign log_pmeack_mes_not_en_error = rds2ics_pmeack_mes_not_en_error & pmeack_mes_not_en_error_log_en; |
| 585 | assign log_pmpme_mes_not_en_error = rds2ics_pmpme_mes_not_en_error & pmpme_mes_not_en_error_log_en; |
| 586 | assign log_fatal_mes_not_en_error = rds2ics_fatal_mes_not_en_error & fatal_mes_not_en_error_log_en; |
| 587 | assign log_nonfatal_mes_not_en_error = rds2ics_nonfatal_mes_not_en_error & nonfatal_mes_not_en_error_log_en; |
| 588 | assign log_cor_mes_not_en_error = rds2ics_cor_mes_not_en_error & cor_mes_not_en_error_log_en; |
| 589 | assign log_msi_not_en_error = rds2ics_msi_not_en_error & msi_not_en_error_log_en; |
| 590 | |
| 591 | |
| 592 | //------------------------------------------------------ |
| 593 | // Grouping the four errors from rds into one group |
| 594 | //------------------------------------------------------ |
| 595 | |
| 596 | //----------- |
| 597 | // RDS |
| 598 | //----------- |
| 599 | assign rds_group_p_error_set = logged_p_spare_reg[0] | |
| 600 | logged_p_spare_reg[1] | |
| 601 | logged_p_msi_mal_reg | |
| 602 | logged_p_msi_par_reg | |
| 603 | logged_p_pmeack_mes_not_en_reg | |
| 604 | logged_p_pmpme_mes_not_en_reg | |
| 605 | logged_p_fatal_mes_not_en_reg | |
| 606 | logged_p_nonfatal_mes_not_en_reg | |
| 607 | logged_p_cor_mes_not_en_reg | |
| 608 | logged_p_msi_not_en_reg; |
| 609 | |
| 610 | assign load_rds_logging_reg = ~rds_group_p_error_set; |
| 611 | |
| 612 | |
| 613 | //---------- |
| 614 | // SCS |
| 615 | //---------- |
| 616 | |
| 617 | assign scs_group_p_error_set = logged_p_spare_reg[2] | |
| 618 | logged_p_eq_not_en_reg; |
| 619 | |
| 620 | assign load_scs_logging_reg = ~logged_p_eq_not_en_reg; |
| 621 | |
| 622 | //---------- |
| 623 | // SCS |
| 624 | //---------- |
| 625 | |
| 626 | assign eqs_group_p_error_set = logged_p_spare_reg[3] | |
| 627 | logged_p_eq_over_reg; |
| 628 | |
| 629 | assign load_eqs_logging_reg = ~logged_p_eq_over_reg; |
| 630 | |
| 631 | //----------------------------------------------------- |
| 632 | // Determine if the Primary Error Needs to be loaded |
| 633 | // for Logged Error Status Register |
| 634 | // |
| 635 | // - Since we are using a set register always set the |
| 636 | // the primary bit on error detection |
| 637 | // |
| 638 | // - log_*****_error |
| 639 | // |
| 640 | //------------------------------------------------------ |
| 641 | assign set_p_logged_spare[0] = log_spare_error[0] & ~rds_group_p_error_set; |
| 642 | assign set_p_logged_spare[1] = log_spare_error[1] & ~rds_group_p_error_set; |
| 643 | |
| 644 | assign set_p_logged_spare[2] = log_spare_error[2] & ~scs_group_p_error_set; |
| 645 | assign set_p_logged_spare[3] = log_spare_error[3] & ~eqs_group_p_error_set; |
| 646 | assign set_p_logged_spare[4] = log_spare_error[4]; |
| 647 | |
| 648 | assign set_p_logged_eq_over = log_eq_over_error & ~eqs_group_p_error_set; |
| 649 | assign set_p_logged_eq_not_en = log_eq_not_en_error & ~scs_group_p_error_set; |
| 650 | |
| 651 | assign set_p_logged_msi_mal = log_msi_mal_error & ~rds_group_p_error_set; |
| 652 | assign set_p_logged_msi_par = log_msi_par_error & ~rds_group_p_error_set; |
| 653 | assign set_p_logged_pmeack_mes_not_en = log_pmeack_mes_not_en_error & ~rds_group_p_error_set; |
| 654 | assign set_p_logged_pmpme_mes_not_en = log_pmpme_mes_not_en_error & ~rds_group_p_error_set; |
| 655 | assign set_p_logged_fatal_mes_not_en = log_fatal_mes_not_en_error & ~rds_group_p_error_set; |
| 656 | assign set_p_logged_nonfatal_mes_not_en = log_nonfatal_mes_not_en_error & ~rds_group_p_error_set; |
| 657 | assign set_p_logged_cor_mes_not_en = log_cor_mes_not_en_error & ~rds_group_p_error_set; |
| 658 | assign set_p_logged_msi_not_en = log_msi_not_en_error & ~rds_group_p_error_set; |
| 659 | |
| 660 | |
| 661 | //----------------------------------------------------- |
| 662 | // Determine if the Secondary Error Needs to be loaded |
| 663 | // for Logged Error Status Register |
| 664 | // |
| 665 | // - Since we are using a set register always set the |
| 666 | // the secondary bit on error detection only if |
| 667 | // first is already set. |
| 668 | // |
| 669 | // |
| 670 | // - log_*****_error & p_logged_***** |
| 671 | // |
| 672 | //------------------------------------------------------ |
| 673 | |
| 674 | assign set_s_logged_spare[0] = log_spare_error[0] & rds_group_p_error_set; |
| 675 | assign set_s_logged_spare[1] = log_spare_error[1] & rds_group_p_error_set; |
| 676 | |
| 677 | assign set_s_logged_spare[2] = log_spare_error[2] & scs_group_p_error_set; |
| 678 | assign set_s_logged_spare[3] = log_spare_error[3] & eqs_group_p_error_set; |
| 679 | assign set_s_logged_spare[4] = log_spare_error[4] & logged_p_spare_reg[4]; |
| 680 | |
| 681 | assign set_s_logged_eq_over = log_eq_over_error & eqs_group_p_error_set; |
| 682 | assign set_s_logged_eq_not_en = log_eq_not_en_error & scs_group_p_error_set; |
| 683 | |
| 684 | assign set_s_logged_msi_mal = log_msi_mal_error & rds_group_p_error_set; |
| 685 | assign set_s_logged_msi_par = log_msi_par_error & rds_group_p_error_set; |
| 686 | assign set_s_logged_pmeack_mes_not_en = log_pmeack_mes_not_en_error & rds_group_p_error_set; |
| 687 | assign set_s_logged_pmpme_mes_not_en = log_pmpme_mes_not_en_error & rds_group_p_error_set; |
| 688 | assign set_s_logged_fatal_mes_not_en = log_fatal_mes_not_en_error & rds_group_p_error_set; |
| 689 | assign set_s_logged_nonfatal_mes_not_en = log_nonfatal_mes_not_en_error & rds_group_p_error_set; |
| 690 | assign set_s_logged_cor_mes_not_en = log_cor_mes_not_en_error & rds_group_p_error_set; |
| 691 | assign set_s_logged_msi_not_en = log_msi_not_en_error & rds_group_p_error_set; |
| 692 | |
| 693 | |
| 694 | //----------------------------------------------------- |
| 695 | // Determine if the Primary Error Needs to be loaded |
| 696 | // for Enabled Error Status Register |
| 697 | // |
| 698 | // - Since we are using a set register always set the |
| 699 | // the primary bit on error detection |
| 700 | // |
| 701 | // - loggged_p_*****_reg & ****_p_int_en |
| 702 | // |
| 703 | //------------------------------------------------------ |
| 704 | |
| 705 | assign enabled_p_spare[0] = logged_p_spare_reg[0] & spare_error_p_int_en[0] ; |
| 706 | assign enabled_p_spare[1] = logged_p_spare_reg[1] & spare_error_p_int_en[1] ; |
| 707 | assign enabled_p_spare[2] = logged_p_spare_reg[2] & spare_error_p_int_en[2] ; |
| 708 | assign enabled_p_spare[3] = logged_p_spare_reg[3] & spare_error_p_int_en[3] ; |
| 709 | assign enabled_p_spare[4] = logged_p_spare_reg[4] & spare_error_p_int_en[4] ; |
| 710 | |
| 711 | assign enabled_p_eq_over = logged_p_eq_over_reg & eq_over_error_p_int_en; |
| 712 | assign enabled_p_eq_not_en = logged_p_eq_not_en_reg & eq_not_en_error_p_int_en; |
| 713 | assign enabled_p_msi_mal = logged_p_msi_mal_reg & msi_mal_error_p_int_en; |
| 714 | assign enabled_p_msi_par = logged_p_msi_par_reg & msi_par_error_p_int_en; |
| 715 | assign enabled_p_pmeack_mes_not_en = logged_p_pmeack_mes_not_en_reg & pmeack_mes_not_en_error_p_int_en; |
| 716 | assign enabled_p_pmpme_mes_not_en = logged_p_pmpme_mes_not_en_reg & pmpme_mes_not_en_error_p_int_en; |
| 717 | assign enabled_p_fatal_mes_not_en = logged_p_fatal_mes_not_en_reg & fatal_mes_not_en_error_p_int_en; |
| 718 | assign enabled_p_nonfatal_mes_not_en = logged_p_nonfatal_mes_not_en_reg & nonfatal_mes_not_en_error_p_int_en; |
| 719 | assign enabled_p_cor_mes_not_en = logged_p_cor_mes_not_en_reg & cor_mes_not_en_error_p_int_en; |
| 720 | assign enabled_p_msi_not_en = logged_p_msi_not_en_reg & msi_not_en_error_p_int_en; |
| 721 | |
| 722 | |
| 723 | |
| 724 | //----------------------------------------------------- |
| 725 | // Determine if the Seconday Error Needs to be loaded |
| 726 | // for Enabled Error Status Register |
| 727 | // |
| 728 | // - Since we are using a set register always set the |
| 729 | // the primary bit on error detection |
| 730 | // |
| 731 | // - loggged_p_*****_reg & ****_p_int_en |
| 732 | // |
| 733 | //------------------------------------------------------ |
| 734 | |
| 735 | assign enabled_s_spare[0] = logged_s_spare_reg[0] & spare_error_s_int_en[0] ; |
| 736 | assign enabled_s_spare[1] = logged_s_spare_reg[1] & spare_error_s_int_en[1] ; |
| 737 | assign enabled_s_spare[2] = logged_s_spare_reg[2] & spare_error_s_int_en[2] ; |
| 738 | assign enabled_s_spare[3] = logged_s_spare_reg[3] & spare_error_s_int_en[3] ; |
| 739 | assign enabled_s_spare[4] = logged_s_spare_reg[4] & spare_error_s_int_en[4] ; |
| 740 | |
| 741 | assign enabled_s_eq_over = logged_s_eq_over_reg & eq_over_error_s_int_en; |
| 742 | assign enabled_s_eq_not_en = logged_s_eq_not_en_reg & eq_not_en_error_s_int_en; |
| 743 | assign enabled_s_msi_mal = logged_s_msi_mal_reg & msi_mal_error_s_int_en; |
| 744 | assign enabled_s_msi_par = logged_s_msi_par_reg & msi_par_error_s_int_en; |
| 745 | assign enabled_s_pmeack_mes_not_en = logged_s_pmeack_mes_not_en_reg & pmeack_mes_not_en_error_s_int_en; |
| 746 | assign enabled_s_pmpme_mes_not_en = logged_s_pmpme_mes_not_en_reg & pmpme_mes_not_en_error_s_int_en; |
| 747 | assign enabled_s_fatal_mes_not_en = logged_s_fatal_mes_not_en_reg & fatal_mes_not_en_error_s_int_en; |
| 748 | assign enabled_s_nonfatal_mes_not_en = logged_s_nonfatal_mes_not_en_reg & nonfatal_mes_not_en_error_s_int_en; |
| 749 | assign enabled_s_cor_mes_not_en = logged_s_cor_mes_not_en_reg & cor_mes_not_en_error_s_int_en; |
| 750 | assign enabled_s_msi_not_en = logged_s_msi_not_en_reg & msi_not_en_error_s_int_en; |
| 751 | |
| 752 | //---------------------------------------------------------------------------- |
| 753 | // Performance Counters |
| 754 | //---------------------------------------------------------------------------- |
| 755 | assign inc_cnt0 = prf0_cnt_hw_read + 1; |
| 756 | assign inc_cnt1 = prf1_cnt_hw_read + 1; |
| 757 | |
| 758 | always @ (prfc_sel0_hw_read or prfc_sel1_hw_read) begin |
| 759 | prf_sel[0] = prfc_sel0_hw_read; |
| 760 | prf_sel[1] = prfc_sel1_hw_read; |
| 761 | end |
| 762 | |
| 763 | always @ (prf_sel[0] or prf_sel[1] or ors2ics_perf_mondos or ors2ics_perf_msi or |
| 764 | rss2ics_perf_mondo_nacks or ors2ics_perf_eq_wr or ors2ics_perf_eq_mondos) |
| 765 | |
| 766 | begin |
| 767 | for (i = 0; i < 2; i = i + 1) begin |
| 768 | case (prf_sel[i]) // synopsys infer_mux |
| 769 | 8'h00 : prf_inc[i] = 1'b0; |
| 770 | 8'h01 : prf_inc[i] = 1'b1; |
| 771 | 8'h02 : prf_inc[i] = ors2ics_perf_mondos; |
| 772 | 8'h03 : prf_inc[i] = ors2ics_perf_msi; |
| 773 | 8'h04 : prf_inc[i] = rss2ics_perf_mondo_nacks; |
| 774 | 8'h05 : prf_inc[i] = ors2ics_perf_eq_wr; |
| 775 | 8'h06 : prf_inc[i] = ors2ics_perf_eq_mondos; |
| 776 | 8'h07 : prf_inc[i] = 0; |
| 777 | 8'h08 : prf_inc[i] = 0; |
| 778 | 8'h09 : prf_inc[i] = 0; |
| 779 | 8'h0a : prf_inc[i] = 0; |
| 780 | |
| 781 | default : prf_inc[i] = 1'b0; |
| 782 | endcase |
| 783 | end |
| 784 | end |
| 785 | |
| 786 | assign prf0_cnt_hw_write = prf_inc[0] ? inc_cnt0 : prf0_cnt_hw_read; |
| 787 | assign prf1_cnt_hw_write = prf_inc[1] ? inc_cnt1 : prf1_cnt_hw_read; |
| 788 | |
| 789 | |
| 790 | //----------------------------------------------------- |
| 791 | // Spare Control and Status Registers for ECO's |
| 792 | // |
| 793 | //----------------------------------------------------- |
| 794 | |
| 795 | always @ (posedge clk) |
| 796 | begin |
| 797 | if (!rst_l ) begin |
| 798 | spare_control_load_reg <= 8'b0; |
| 799 | spare_control_reg <= 8'b0; |
| 800 | spare_status_reg <= 8'b0; |
| 801 | end |
| 802 | else begin |
| 803 | spare_control_load_reg <= spare_control_load; |
| 804 | spare_control_reg <= spare_control; |
| 805 | spare_status_reg[7:2] <= spare_status[7:2]; |
| 806 | spare_status_reg[1:0] <= 2'b0; |
| 807 | end |
| 808 | end |
| 809 | |
| 810 | //############################################################################ |
| 811 | // MODULE INSTANTIATIONS |
| 812 | //############################################################################ |
| 813 | |
| 814 | //--------------------------------- |
| 815 | // DCM Instanciation |
| 816 | //---------------------------------- |
| 817 | |
| 818 | dmu_imu_ics_csr csr ( |
| 819 | .clk (clk), |
| 820 | .csrbus_addr (csrbus_addr), |
| 821 | .csrbus_wr_data (csrbus_wr_data), |
| 822 | .csrbus_wr (csrbus_wr), |
| 823 | .csrbus_valid (csrbus_valid), |
| 824 | .csrbus_mapped (csrbus_mapped), |
| 825 | .csrbus_done (csrbus_done), |
| 826 | .csrbus_read_data (csrbus_read_data), |
| 827 | .por_l (por_l), |
| 828 | .rst_l (rst_l), |
| 829 | |
| 830 | .csrbus_src_bus (csrbus_src_bus), |
| 831 | .csrbus_acc_vio (csrbus_acc_vio), |
| 832 | .instance_id (j2d_instance_id), |
| 833 | |
| 834 | // .multi_core_error_status_reg_pec_ext_read_data (pec_core_int), |
| 835 | // .multi_core_error_status_reg_dmc_ext_read_data (dmc_core_int), |
| 836 | |
| 837 | |
| 838 | // HW READ ONLY PORT of LOG Enable Registers |
| 839 | .imu_error_log_en_reg_spare_log_en_hw_read(spare_error_log_en), |
| 840 | .imu_error_log_en_reg_eq_over_log_en_hw_read(eq_over_error_log_en), |
| 841 | .imu_error_log_en_reg_eq_not_en_log_en_hw_read(eq_not_en_error_log_en), |
| 842 | .imu_error_log_en_reg_msi_mal_err_log_en_hw_read(msi_mal_error_log_en), |
| 843 | .imu_error_log_en_reg_msi_par_err_log_en_hw_read(msi_par_error_log_en), |
| 844 | .imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read(pmeack_mes_not_en_error_log_en), |
| 845 | .imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read(pmpme_mes_not_en_error_log_en), |
| 846 | .imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read(fatal_mes_not_en_error_log_en), |
| 847 | .imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read(nonfatal_mes_not_en_error_log_en), |
| 848 | .imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read(cor_mes_not_en_error_log_en), |
| 849 | .imu_error_log_en_reg_msi_not_en_log_en_hw_read(msi_not_en_error_log_en), |
| 850 | |
| 851 | // HW READ ONLY PORT of INT Enable regs (Secondary) |
| 852 | .imu_int_en_reg_spare_s_int_en_hw_read(spare_error_s_int_en), |
| 853 | .imu_int_en_reg_eq_over_s_int_en_hw_read(eq_over_error_s_int_en), |
| 854 | .imu_int_en_reg_eq_not_en_s_int_en_hw_read(eq_not_en_error_s_int_en), |
| 855 | .imu_int_en_reg_msi_mal_err_s_int_en_hw_read(msi_mal_error_s_int_en), |
| 856 | .imu_int_en_reg_msi_par_err_s_int_en_hw_read(msi_par_error_s_int_en), |
| 857 | .imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read(pmeack_mes_not_en_error_s_int_en), |
| 858 | .imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read(pmpme_mes_not_en_error_s_int_en), |
| 859 | .imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read(fatal_mes_not_en_error_s_int_en), |
| 860 | .imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read(nonfatal_mes_not_en_error_s_int_en), |
| 861 | .imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read(cor_mes_not_en_error_s_int_en), |
| 862 | .imu_int_en_reg_msi_not_en_s_int_en_hw_read(msi_not_en_error_s_int_en), |
| 863 | |
| 864 | |
| 865 | // HW READ ONLY PORT of INT Enable regs (Primary) |
| 866 | |
| 867 | .imu_int_en_reg_spare_p_int_en_hw_read(spare_error_p_int_en), |
| 868 | .imu_int_en_reg_eq_over_p_int_en_hw_read(eq_over_error_p_int_en), |
| 869 | .imu_int_en_reg_eq_not_en_p_int_en_hw_read(eq_not_en_error_p_int_en), |
| 870 | .imu_int_en_reg_msi_mal_err_p_int_en_hw_read(msi_mal_error_p_int_en), |
| 871 | .imu_int_en_reg_msi_par_err_p_int_en_hw_read(msi_par_error_p_int_en), |
| 872 | .imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read(pmeack_mes_not_en_error_p_int_en), |
| 873 | .imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read(pmpme_mes_not_en_error_p_int_en), |
| 874 | .imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read(fatal_mes_not_en_error_p_int_en), |
| 875 | .imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read(nonfatal_mes_not_en_error_p_int_en), |
| 876 | .imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read(cor_mes_not_en_error_p_int_en), |
| 877 | .imu_int_en_reg_msi_not_en_p_int_en_hw_read(msi_not_en_error_p_int_en), |
| 878 | |
| 879 | // HW READ PORT of Enabled Error Status regs (Secondary) |
| 880 | |
| 881 | .imu_enabled_error_status_reg_spare_s_ext_read_data(enabled_s_spare), |
| 882 | .imu_enabled_error_status_reg_eq_over_s_ext_read_data(enabled_s_eq_over), |
| 883 | .imu_enabled_error_status_reg_eq_not_en_s_ext_read_data(enabled_s_eq_not_en), |
| 884 | .imu_enabled_error_status_reg_msi_mal_err_s_ext_read_data(enabled_s_msi_mal), |
| 885 | .imu_enabled_error_status_reg_msi_par_err_s_ext_read_data(enabled_s_msi_par), |
| 886 | .imu_enabled_error_status_reg_pmeack_mes_not_en_s_ext_read_data(enabled_s_pmeack_mes_not_en), |
| 887 | .imu_enabled_error_status_reg_pmpme_mes_not_en_s_ext_read_data(enabled_s_pmpme_mes_not_en), |
| 888 | .imu_enabled_error_status_reg_fatal_mes_not_en_s_ext_read_data(enabled_s_fatal_mes_not_en), |
| 889 | .imu_enabled_error_status_reg_nonfatal_mes_not_en_s_ext_read_data(enabled_s_nonfatal_mes_not_en), |
| 890 | .imu_enabled_error_status_reg_cor_mes_not_en_s_ext_read_data(enabled_s_cor_mes_not_en), |
| 891 | .imu_enabled_error_status_reg_msi_not_en_s_ext_read_data(enabled_s_msi_not_en), |
| 892 | |
| 893 | |
| 894 | // HW READ PORT of Enabled Error Status regs (Primary) |
| 895 | .imu_enabled_error_status_reg_spare_p_ext_read_data(enabled_p_spare), |
| 896 | .imu_enabled_error_status_reg_eq_over_p_ext_read_data(enabled_p_eq_over), |
| 897 | .imu_enabled_error_status_reg_eq_not_en_p_ext_read_data(enabled_p_eq_not_en), |
| 898 | .imu_enabled_error_status_reg_msi_mal_err_p_ext_read_data(enabled_p_msi_mal), |
| 899 | .imu_enabled_error_status_reg_msi_par_err_p_ext_read_data(enabled_p_msi_par), |
| 900 | .imu_enabled_error_status_reg_pmeack_mes_not_en_p_ext_read_data(enabled_p_pmeack_mes_not_en), |
| 901 | .imu_enabled_error_status_reg_pmpme_mes_not_en_p_ext_read_data(enabled_p_pmpme_mes_not_en), |
| 902 | .imu_enabled_error_status_reg_fatal_mes_not_en_p_ext_read_data(enabled_p_fatal_mes_not_en), |
| 903 | .imu_enabled_error_status_reg_nonfatal_mes_not_en_p_ext_read_data(enabled_p_nonfatal_mes_not_en), |
| 904 | .imu_enabled_error_status_reg_cor_mes_not_en_p_ext_read_data(enabled_p_cor_mes_not_en), |
| 905 | .imu_enabled_error_status_reg_msi_not_en_p_ext_read_data(enabled_p_msi_not_en), |
| 906 | |
| 907 | // READ and SET Ports of the Logged Error Status regs (Secondary) |
| 908 | .imu_logged_error_status_reg_spare_s_hw_set(set_s_logged_spare), |
| 909 | .imu_logged_error_status_reg_spare_s_hw_read(logged_s_spare_reg), |
| 910 | |
| 911 | .imu_logged_error_status_reg_eq_over_s_hw_set(set_s_logged_eq_over), |
| 912 | .imu_logged_error_status_reg_eq_over_s_hw_read(logged_s_eq_over_reg), |
| 913 | |
| 914 | .imu_logged_error_status_reg_eq_not_en_s_hw_set(set_s_logged_eq_not_en), |
| 915 | .imu_logged_error_status_reg_eq_not_en_s_hw_read(logged_s_eq_not_en_reg), |
| 916 | |
| 917 | .imu_logged_error_status_reg_msi_mal_err_s_hw_set(set_s_logged_msi_mal), |
| 918 | .imu_logged_error_status_reg_msi_mal_err_s_hw_read(logged_s_msi_mal_reg), |
| 919 | |
| 920 | .imu_logged_error_status_reg_msi_par_err_s_hw_set(set_s_logged_msi_par), |
| 921 | .imu_logged_error_status_reg_msi_par_err_s_hw_read(logged_s_msi_par_reg), |
| 922 | |
| 923 | .imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set(set_s_logged_pmeack_mes_not_en), |
| 924 | .imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read(logged_s_pmeack_mes_not_en_reg), |
| 925 | |
| 926 | .imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set(set_s_logged_pmpme_mes_not_en), |
| 927 | .imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read(logged_s_pmpme_mes_not_en_reg), |
| 928 | |
| 929 | .imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set(set_s_logged_fatal_mes_not_en), |
| 930 | .imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read(logged_s_fatal_mes_not_en_reg), |
| 931 | |
| 932 | .imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set(set_s_logged_nonfatal_mes_not_en), |
| 933 | .imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read(logged_s_nonfatal_mes_not_en_reg), |
| 934 | |
| 935 | .imu_logged_error_status_reg_cor_mes_not_en_s_hw_set(set_s_logged_cor_mes_not_en), |
| 936 | .imu_logged_error_status_reg_cor_mes_not_en_s_hw_read(logged_s_cor_mes_not_en_reg), |
| 937 | |
| 938 | .imu_logged_error_status_reg_msi_not_en_s_hw_set(set_s_logged_msi_not_en), |
| 939 | .imu_logged_error_status_reg_msi_not_en_s_hw_read(logged_s_msi_not_en_reg), |
| 940 | |
| 941 | |
| 942 | // READ and SET Ports of the Logged Error Status regs (Primary) |
| 943 | |
| 944 | .imu_logged_error_status_reg_spare_p_hw_set(set_p_logged_spare), |
| 945 | .imu_logged_error_status_reg_spare_p_hw_read(logged_p_spare_reg), |
| 946 | |
| 947 | .imu_logged_error_status_reg_eq_over_p_hw_set(set_p_logged_eq_over), |
| 948 | .imu_logged_error_status_reg_eq_over_p_hw_read(logged_p_eq_over_reg), |
| 949 | |
| 950 | .imu_logged_error_status_reg_eq_not_en_p_hw_set(set_p_logged_eq_not_en), |
| 951 | .imu_logged_error_status_reg_eq_not_en_p_hw_read(logged_p_eq_not_en_reg), |
| 952 | |
| 953 | .imu_logged_error_status_reg_msi_mal_err_p_hw_set(set_p_logged_msi_mal), |
| 954 | .imu_logged_error_status_reg_msi_mal_err_p_hw_read(logged_p_msi_mal_reg), |
| 955 | |
| 956 | .imu_logged_error_status_reg_msi_par_err_p_hw_set(set_p_logged_msi_par), |
| 957 | .imu_logged_error_status_reg_msi_par_err_p_hw_read(logged_p_msi_par_reg), |
| 958 | |
| 959 | .imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set(set_p_logged_pmeack_mes_not_en), |
| 960 | .imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read(logged_p_pmeack_mes_not_en_reg), |
| 961 | |
| 962 | .imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set(set_p_logged_pmpme_mes_not_en), |
| 963 | .imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read(logged_p_pmpme_mes_not_en_reg), |
| 964 | |
| 965 | .imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set(set_p_logged_fatal_mes_not_en), |
| 966 | .imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read(logged_p_fatal_mes_not_en_reg), |
| 967 | |
| 968 | .imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set(set_p_logged_nonfatal_mes_not_en), |
| 969 | .imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read(logged_p_nonfatal_mes_not_en_reg), |
| 970 | |
| 971 | .imu_logged_error_status_reg_cor_mes_not_en_p_hw_set(set_p_logged_cor_mes_not_en), |
| 972 | .imu_logged_error_status_reg_cor_mes_not_en_p_hw_read(logged_p_cor_mes_not_en_reg), |
| 973 | |
| 974 | .imu_logged_error_status_reg_msi_not_en_p_hw_set(set_p_logged_msi_not_en), |
| 975 | .imu_logged_error_status_reg_msi_not_en_p_hw_read(logged_p_msi_not_en_reg), |
| 976 | |
| 977 | .imu_rds_error_log_reg_hw_ld(load_rds_logging_reg), |
| 978 | .imu_rds_error_log_reg_hw_write(rds2ics_error_data), |
| 979 | |
| 980 | .imu_scs_error_log_reg_hw_ld(load_scs_logging_reg), |
| 981 | .imu_scs_error_log_reg_hw_write(scs2ics_error_data), |
| 982 | |
| 983 | .imu_eqs_error_log_reg_hw_ld(load_eqs_logging_reg), |
| 984 | .imu_eqs_error_log_reg_hw_write(eqs2ics_error_data), |
| 985 | |
| 986 | .dmc_interrupt_mask_reg_dmc_hw_read (dmc_mask), |
| 987 | .dmc_interrupt_mask_reg_debug_trig_en_hw_read (debug_trig_en), |
| 988 | .dmc_interrupt_mask_reg_mmu_hw_read (mmu_mask), |
| 989 | .dmc_interrupt_mask_reg_imu_hw_read (imu_mask), |
| 990 | .dmc_interrupt_status_reg_mmu_ext_read_data (mmu_block_int), |
| 991 | .dmc_interrupt_status_reg_imu_ext_read_data (imu_block_int), |
| 992 | .imu_perf_cntrl_sel1_hw_read (prfc_sel1_hw_read), |
| 993 | .imu_perf_cntrl_sel0_hw_read (prfc_sel0_hw_read), |
| 994 | .imu_perf_cnt0_cnt_hw_write (prf0_cnt_hw_write), |
| 995 | .imu_perf_cnt0_cnt_hw_read (prf0_cnt_hw_read), |
| 996 | .imu_perf_cnt1_cnt_hw_write (prf1_cnt_hw_write), |
| 997 | .imu_perf_cnt1_cnt_hw_read (prf1_cnt_hw_read), |
| 998 | .msi_32_addr_reg_addr_hw_read (im2tm_msi32_addr_reg), |
| 999 | .msi_64_addr_reg_addr_hw_read (im2tm_msi64_addr_reg), |
| 1000 | .mem_64_pcie_offset_reg_addr_hw_read (im2rm_mem64_offset_reg), |
| 1001 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_ld(spare_status_reg[7]), |
| 1002 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_write(spare_control_load_reg[7]), |
| 1003 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_read(spare_control_load[7]), |
| 1004 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_ld(spare_status_reg[6]), |
| 1005 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_write(spare_control_load_reg[6]), |
| 1006 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_read(spare_control_load[6]), |
| 1007 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_ld(spare_status_reg[5]), |
| 1008 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_write(spare_control_load_reg[5]), |
| 1009 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_read(spare_control_load[5]), |
| 1010 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_ld(spare_status_reg[4]), |
| 1011 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_write(spare_control_load_reg[4]), |
| 1012 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_read(spare_control_load[4]), |
| 1013 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_ld(spare_status_reg[3]), |
| 1014 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_write(spare_control_load_reg[3]), |
| 1015 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_read(spare_control_load[3]), |
| 1016 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_ld(spare_status_reg[2]), |
| 1017 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_write(spare_control_load_reg[2]), |
| 1018 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_read(spare_control_load[2]), |
| 1019 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_ld(spare_status_reg[1]), |
| 1020 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_write(spare_control_load_reg[1]), |
| 1021 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_read(spare_control_load[1]), |
| 1022 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_ld(spare_status_reg[0]), |
| 1023 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_write(spare_control_load_reg[0]), |
| 1024 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_read(spare_control_load[0]), |
| 1025 | .mem_64_pcie_offset_reg_spare_control_hw_write(spare_control_reg), |
| 1026 | .mem_64_pcie_offset_reg_spare_control_hw_read(spare_control), |
| 1027 | .mem_64_pcie_offset_reg_spare_status_hw_read(spare_status) |
| 1028 | ); |
| 1029 | |
| 1030 | |
| 1031 | //BP n2 12-19-05 use 2 of the spare bits in the above register , these control |
| 1032 | // 2 different solutions to the lockup issue, see bug 107207, ie. since the |
| 1033 | // egress pipe merges the dma rd completions and pio requests into the cr2rm fifo |
| 1034 | // there could be cases where the pio's back up and stall the dma rd's from completing |
| 1035 | // these 2 bits control 2 different solutions for the same thing, but since we are |
| 1036 | // close to freezing we are putting both in, just in case, they can both be disabled |
| 1037 | // or enabled |
| 1038 | assign im2crm_bc_stall_en = spare_status[0]; // stall statemachine enable |
| 1039 | assign im2crm_ilu_stall_en = spare_status[1]; // stall statemachine enable from ilu |
| 1040 | |
| 1041 | |
| 1042 | |
| 1043 | endmodule |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |