| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_eqs_error_log_reg_entry.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_csr_imu_eqs_error_log_reg_entry |
| 36 | ( |
| 37 | // synopsys translate_off |
| 38 | omni_ld, |
| 39 | omni_data, |
| 40 | // synopsys translate_on |
| 41 | clk, |
| 42 | por_l, |
| 43 | w_ld, |
| 44 | csrbus_wr_data, |
| 45 | imu_eqs_error_log_reg_csrbus_read_data, |
| 46 | imu_eqs_error_log_reg_hw_ld, |
| 47 | imu_eqs_error_log_reg_hw_write |
| 48 | ); |
| 49 | |
| 50 | //==================================================================== |
| 51 | // Polarity declarations |
| 52 | //==================================================================== |
| 53 | // synopsys translate_off |
| 54 | input omni_ld; // Omni load |
| 55 | // vlint flag_input_port_not_connected off |
| 56 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH - 1:0] omni_data; |
| 57 | // Omni write data |
| 58 | // synopsys translate_on |
| 59 | // vlint flag_input_port_not_connected on |
| 60 | input clk; // Clock signal |
| 61 | input por_l; // Reset signal |
| 62 | input w_ld; // SW load |
| 63 | // vlint flag_input_port_not_connected off |
| 64 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 65 | // vlint flag_input_port_not_connected on |
| 66 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_csrbus_read_data; |
| 67 | // SW read data |
| 68 | input imu_eqs_error_log_reg_hw_ld; // Hardware load enable for |
| 69 | // imu_eqs_error_log_reg. When set, <hw |
| 70 | // write signal> will be loaded into |
| 71 | // imu_eqs_error_log_reg. |
| 72 | // vlint flag_input_port_not_connected off |
| 73 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH -1:0] imu_eqs_error_log_reg_hw_write; |
| 74 | // data bus for hw loading of imu_eqs_error_log_reg. |
| 75 | // vlint flag_input_port_not_connected on |
| 76 | |
| 77 | //==================================================================== |
| 78 | // Type declarations |
| 79 | //==================================================================== |
| 80 | // synopsys translate_off |
| 81 | wire omni_ld; // Omni load |
| 82 | // vlint flag_dangling_net_within_module off |
| 83 | // vlint flag_net_has_no_load off |
| 84 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH - 1:0] omni_data; |
| 85 | // Omni write data |
| 86 | // synopsys translate_on |
| 87 | // vlint flag_dangling_net_within_module on |
| 88 | // vlint flag_net_has_no_load on |
| 89 | wire clk; // Clock signal |
| 90 | wire por_l; // Reset signal |
| 91 | wire w_ld; // SW load |
| 92 | // vlint flag_dangling_net_within_module off |
| 93 | // vlint flag_net_has_no_load off |
| 94 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 95 | // vlint flag_dangling_net_within_module on |
| 96 | // vlint flag_net_has_no_load on |
| 97 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_csrbus_read_data; |
| 98 | // SW read data |
| 99 | wire imu_eqs_error_log_reg_hw_ld; // Hardware load enable for |
| 100 | // imu_eqs_error_log_reg. When set, <hw write |
| 101 | // signal> will be loaded into |
| 102 | // imu_eqs_error_log_reg. |
| 103 | // vlint flag_dangling_net_within_module off |
| 104 | // vlint flag_net_has_no_load off |
| 105 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH -1:0] imu_eqs_error_log_reg_hw_write; |
| 106 | // data bus for hw loading of imu_eqs_error_log_reg. |
| 107 | // vlint flag_dangling_net_within_module on |
| 108 | // vlint flag_net_has_no_load on |
| 109 | |
| 110 | //==================================================================== |
| 111 | // Logic |
| 112 | //==================================================================== |
| 113 | |
| 114 | //----- Reset values |
| 115 | // verilint 531 off |
| 116 | wire [5:0] reset_eq_num = 6'b0; |
| 117 | // verilint 531 on |
| 118 | |
| 119 | //----- Active high reset wires |
| 120 | wire por_l_active_high = ~por_l; |
| 121 | |
| 122 | //==================================================== |
| 123 | // Instantiation of flops |
| 124 | //==================================================== |
| 125 | |
| 126 | // bit 0 |
| 127 | csr_sw csr_sw_0 |
| 128 | ( |
| 129 | // synopsys translate_off |
| 130 | .omni_ld (omni_ld), |
| 131 | .omni_data (omni_data[0]), |
| 132 | .omni_rw_alias (1'b1), |
| 133 | .omni_rw1c_alias (1'b0), |
| 134 | .omni_rw1s_alias (1'b0), |
| 135 | // synopsys translate_on |
| 136 | .rst (por_l_active_high), |
| 137 | .rst_val (reset_eq_num[0]), |
| 138 | .csr_ld (w_ld), |
| 139 | .csr_data (csrbus_wr_data[0]), |
| 140 | .rw_alias (1'b1), |
| 141 | .rw1c_alias (1'b0), |
| 142 | .rw1s_alias (1'b0), |
| 143 | .hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 144 | .hw_data (imu_eqs_error_log_reg_hw_write[0]), |
| 145 | .cp (clk), |
| 146 | .q (imu_eqs_error_log_reg_csrbus_read_data[0]) |
| 147 | ); |
| 148 | |
| 149 | // bit 1 |
| 150 | csr_sw csr_sw_1 |
| 151 | ( |
| 152 | // synopsys translate_off |
| 153 | .omni_ld (omni_ld), |
| 154 | .omni_data (omni_data[1]), |
| 155 | .omni_rw_alias (1'b1), |
| 156 | .omni_rw1c_alias (1'b0), |
| 157 | .omni_rw1s_alias (1'b0), |
| 158 | // synopsys translate_on |
| 159 | .rst (por_l_active_high), |
| 160 | .rst_val (reset_eq_num[1]), |
| 161 | .csr_ld (w_ld), |
| 162 | .csr_data (csrbus_wr_data[1]), |
| 163 | .rw_alias (1'b1), |
| 164 | .rw1c_alias (1'b0), |
| 165 | .rw1s_alias (1'b0), |
| 166 | .hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 167 | .hw_data (imu_eqs_error_log_reg_hw_write[1]), |
| 168 | .cp (clk), |
| 169 | .q (imu_eqs_error_log_reg_csrbus_read_data[1]) |
| 170 | ); |
| 171 | |
| 172 | // bit 2 |
| 173 | csr_sw csr_sw_2 |
| 174 | ( |
| 175 | // synopsys translate_off |
| 176 | .omni_ld (omni_ld), |
| 177 | .omni_data (omni_data[2]), |
| 178 | .omni_rw_alias (1'b1), |
| 179 | .omni_rw1c_alias (1'b0), |
| 180 | .omni_rw1s_alias (1'b0), |
| 181 | // synopsys translate_on |
| 182 | .rst (por_l_active_high), |
| 183 | .rst_val (reset_eq_num[2]), |
| 184 | .csr_ld (w_ld), |
| 185 | .csr_data (csrbus_wr_data[2]), |
| 186 | .rw_alias (1'b1), |
| 187 | .rw1c_alias (1'b0), |
| 188 | .rw1s_alias (1'b0), |
| 189 | .hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 190 | .hw_data (imu_eqs_error_log_reg_hw_write[2]), |
| 191 | .cp (clk), |
| 192 | .q (imu_eqs_error_log_reg_csrbus_read_data[2]) |
| 193 | ); |
| 194 | |
| 195 | // bit 3 |
| 196 | csr_sw csr_sw_3 |
| 197 | ( |
| 198 | // synopsys translate_off |
| 199 | .omni_ld (omni_ld), |
| 200 | .omni_data (omni_data[3]), |
| 201 | .omni_rw_alias (1'b1), |
| 202 | .omni_rw1c_alias (1'b0), |
| 203 | .omni_rw1s_alias (1'b0), |
| 204 | // synopsys translate_on |
| 205 | .rst (por_l_active_high), |
| 206 | .rst_val (reset_eq_num[3]), |
| 207 | .csr_ld (w_ld), |
| 208 | .csr_data (csrbus_wr_data[3]), |
| 209 | .rw_alias (1'b1), |
| 210 | .rw1c_alias (1'b0), |
| 211 | .rw1s_alias (1'b0), |
| 212 | .hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 213 | .hw_data (imu_eqs_error_log_reg_hw_write[3]), |
| 214 | .cp (clk), |
| 215 | .q (imu_eqs_error_log_reg_csrbus_read_data[3]) |
| 216 | ); |
| 217 | |
| 218 | // bit 4 |
| 219 | csr_sw csr_sw_4 |
| 220 | ( |
| 221 | // synopsys translate_off |
| 222 | .omni_ld (omni_ld), |
| 223 | .omni_data (omni_data[4]), |
| 224 | .omni_rw_alias (1'b1), |
| 225 | .omni_rw1c_alias (1'b0), |
| 226 | .omni_rw1s_alias (1'b0), |
| 227 | // synopsys translate_on |
| 228 | .rst (por_l_active_high), |
| 229 | .rst_val (reset_eq_num[4]), |
| 230 | .csr_ld (w_ld), |
| 231 | .csr_data (csrbus_wr_data[4]), |
| 232 | .rw_alias (1'b1), |
| 233 | .rw1c_alias (1'b0), |
| 234 | .rw1s_alias (1'b0), |
| 235 | .hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 236 | .hw_data (imu_eqs_error_log_reg_hw_write[4]), |
| 237 | .cp (clk), |
| 238 | .q (imu_eqs_error_log_reg_csrbus_read_data[4]) |
| 239 | ); |
| 240 | |
| 241 | // bit 5 |
| 242 | csr_sw csr_sw_5 |
| 243 | ( |
| 244 | // synopsys translate_off |
| 245 | .omni_ld (omni_ld), |
| 246 | .omni_data (omni_data[5]), |
| 247 | .omni_rw_alias (1'b1), |
| 248 | .omni_rw1c_alias (1'b0), |
| 249 | .omni_rw1s_alias (1'b0), |
| 250 | // synopsys translate_on |
| 251 | .rst (por_l_active_high), |
| 252 | .rst_val (reset_eq_num[5]), |
| 253 | .csr_ld (w_ld), |
| 254 | .csr_data (csrbus_wr_data[5]), |
| 255 | .rw_alias (1'b1), |
| 256 | .rw1c_alias (1'b0), |
| 257 | .rw1s_alias (1'b0), |
| 258 | .hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 259 | .hw_data (imu_eqs_error_log_reg_hw_write[5]), |
| 260 | .cp (clk), |
| 261 | .q (imu_eqs_error_log_reg_csrbus_read_data[5]) |
| 262 | ); |
| 263 | |
| 264 | assign imu_eqs_error_log_reg_csrbus_read_data[6] = 1'b0; // bit 6 |
| 265 | assign imu_eqs_error_log_reg_csrbus_read_data[7] = 1'b0; // bit 7 |
| 266 | assign imu_eqs_error_log_reg_csrbus_read_data[8] = 1'b0; // bit 8 |
| 267 | assign imu_eqs_error_log_reg_csrbus_read_data[9] = 1'b0; // bit 9 |
| 268 | assign imu_eqs_error_log_reg_csrbus_read_data[10] = 1'b0; // bit 10 |
| 269 | assign imu_eqs_error_log_reg_csrbus_read_data[11] = 1'b0; // bit 11 |
| 270 | assign imu_eqs_error_log_reg_csrbus_read_data[12] = 1'b0; // bit 12 |
| 271 | assign imu_eqs_error_log_reg_csrbus_read_data[13] = 1'b0; // bit 13 |
| 272 | assign imu_eqs_error_log_reg_csrbus_read_data[14] = 1'b0; // bit 14 |
| 273 | assign imu_eqs_error_log_reg_csrbus_read_data[15] = 1'b0; // bit 15 |
| 274 | assign imu_eqs_error_log_reg_csrbus_read_data[16] = 1'b0; // bit 16 |
| 275 | assign imu_eqs_error_log_reg_csrbus_read_data[17] = 1'b0; // bit 17 |
| 276 | assign imu_eqs_error_log_reg_csrbus_read_data[18] = 1'b0; // bit 18 |
| 277 | assign imu_eqs_error_log_reg_csrbus_read_data[19] = 1'b0; // bit 19 |
| 278 | assign imu_eqs_error_log_reg_csrbus_read_data[20] = 1'b0; // bit 20 |
| 279 | assign imu_eqs_error_log_reg_csrbus_read_data[21] = 1'b0; // bit 21 |
| 280 | assign imu_eqs_error_log_reg_csrbus_read_data[22] = 1'b0; // bit 22 |
| 281 | assign imu_eqs_error_log_reg_csrbus_read_data[23] = 1'b0; // bit 23 |
| 282 | assign imu_eqs_error_log_reg_csrbus_read_data[24] = 1'b0; // bit 24 |
| 283 | assign imu_eqs_error_log_reg_csrbus_read_data[25] = 1'b0; // bit 25 |
| 284 | assign imu_eqs_error_log_reg_csrbus_read_data[26] = 1'b0; // bit 26 |
| 285 | assign imu_eqs_error_log_reg_csrbus_read_data[27] = 1'b0; // bit 27 |
| 286 | assign imu_eqs_error_log_reg_csrbus_read_data[28] = 1'b0; // bit 28 |
| 287 | assign imu_eqs_error_log_reg_csrbus_read_data[29] = 1'b0; // bit 29 |
| 288 | assign imu_eqs_error_log_reg_csrbus_read_data[30] = 1'b0; // bit 30 |
| 289 | assign imu_eqs_error_log_reg_csrbus_read_data[31] = 1'b0; // bit 31 |
| 290 | assign imu_eqs_error_log_reg_csrbus_read_data[32] = 1'b0; // bit 32 |
| 291 | assign imu_eqs_error_log_reg_csrbus_read_data[33] = 1'b0; // bit 33 |
| 292 | assign imu_eqs_error_log_reg_csrbus_read_data[34] = 1'b0; // bit 34 |
| 293 | assign imu_eqs_error_log_reg_csrbus_read_data[35] = 1'b0; // bit 35 |
| 294 | assign imu_eqs_error_log_reg_csrbus_read_data[36] = 1'b0; // bit 36 |
| 295 | assign imu_eqs_error_log_reg_csrbus_read_data[37] = 1'b0; // bit 37 |
| 296 | assign imu_eqs_error_log_reg_csrbus_read_data[38] = 1'b0; // bit 38 |
| 297 | assign imu_eqs_error_log_reg_csrbus_read_data[39] = 1'b0; // bit 39 |
| 298 | assign imu_eqs_error_log_reg_csrbus_read_data[40] = 1'b0; // bit 40 |
| 299 | assign imu_eqs_error_log_reg_csrbus_read_data[41] = 1'b0; // bit 41 |
| 300 | assign imu_eqs_error_log_reg_csrbus_read_data[42] = 1'b0; // bit 42 |
| 301 | assign imu_eqs_error_log_reg_csrbus_read_data[43] = 1'b0; // bit 43 |
| 302 | assign imu_eqs_error_log_reg_csrbus_read_data[44] = 1'b0; // bit 44 |
| 303 | assign imu_eqs_error_log_reg_csrbus_read_data[45] = 1'b0; // bit 45 |
| 304 | assign imu_eqs_error_log_reg_csrbus_read_data[46] = 1'b0; // bit 46 |
| 305 | assign imu_eqs_error_log_reg_csrbus_read_data[47] = 1'b0; // bit 47 |
| 306 | assign imu_eqs_error_log_reg_csrbus_read_data[48] = 1'b0; // bit 48 |
| 307 | assign imu_eqs_error_log_reg_csrbus_read_data[49] = 1'b0; // bit 49 |
| 308 | assign imu_eqs_error_log_reg_csrbus_read_data[50] = 1'b0; // bit 50 |
| 309 | assign imu_eqs_error_log_reg_csrbus_read_data[51] = 1'b0; // bit 51 |
| 310 | assign imu_eqs_error_log_reg_csrbus_read_data[52] = 1'b0; // bit 52 |
| 311 | assign imu_eqs_error_log_reg_csrbus_read_data[53] = 1'b0; // bit 53 |
| 312 | assign imu_eqs_error_log_reg_csrbus_read_data[54] = 1'b0; // bit 54 |
| 313 | assign imu_eqs_error_log_reg_csrbus_read_data[55] = 1'b0; // bit 55 |
| 314 | assign imu_eqs_error_log_reg_csrbus_read_data[56] = 1'b0; // bit 56 |
| 315 | assign imu_eqs_error_log_reg_csrbus_read_data[57] = 1'b0; // bit 57 |
| 316 | assign imu_eqs_error_log_reg_csrbus_read_data[58] = 1'b0; // bit 58 |
| 317 | assign imu_eqs_error_log_reg_csrbus_read_data[59] = 1'b0; // bit 59 |
| 318 | assign imu_eqs_error_log_reg_csrbus_read_data[60] = 1'b0; // bit 60 |
| 319 | assign imu_eqs_error_log_reg_csrbus_read_data[61] = 1'b0; // bit 61 |
| 320 | assign imu_eqs_error_log_reg_csrbus_read_data[62] = 1'b0; // bit 62 |
| 321 | assign imu_eqs_error_log_reg_csrbus_read_data[63] = 1'b0; // bit 63 |
| 322 | |
| 323 | endmodule // dmu_imu_ics_csr_imu_eqs_error_log_reg_entry |