| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_rds_error_log_reg_entry.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_csr_imu_rds_error_log_reg_entry |
| 36 | ( |
| 37 | // synopsys translate_off |
| 38 | omni_ld, |
| 39 | omni_data, |
| 40 | // synopsys translate_on |
| 41 | clk, |
| 42 | por_l, |
| 43 | w_ld, |
| 44 | csrbus_wr_data, |
| 45 | imu_rds_error_log_reg_csrbus_read_data, |
| 46 | imu_rds_error_log_reg_hw_ld, |
| 47 | imu_rds_error_log_reg_hw_write |
| 48 | ); |
| 49 | |
| 50 | //==================================================================== |
| 51 | // Polarity declarations |
| 52 | //==================================================================== |
| 53 | // synopsys translate_off |
| 54 | input omni_ld; // Omni load |
| 55 | // vlint flag_input_port_not_connected off |
| 56 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH - 1:0] omni_data; |
| 57 | // Omni write data |
| 58 | // synopsys translate_on |
| 59 | // vlint flag_input_port_not_connected on |
| 60 | input clk; // Clock signal |
| 61 | input por_l; // Reset signal |
| 62 | input w_ld; // SW load |
| 63 | // vlint flag_input_port_not_connected off |
| 64 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 65 | // vlint flag_input_port_not_connected on |
| 66 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_csrbus_read_data; |
| 67 | // SW read data |
| 68 | input imu_rds_error_log_reg_hw_ld; // Hardware load enable for |
| 69 | // imu_rds_error_log_reg. When set, <hw |
| 70 | // write signal> will be loaded into |
| 71 | // imu_rds_error_log_reg. |
| 72 | // vlint flag_input_port_not_connected off |
| 73 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH -1:0] imu_rds_error_log_reg_hw_write; |
| 74 | // data bus for hw loading of imu_rds_error_log_reg. |
| 75 | // vlint flag_input_port_not_connected on |
| 76 | |
| 77 | //==================================================================== |
| 78 | // Type declarations |
| 79 | //==================================================================== |
| 80 | // synopsys translate_off |
| 81 | wire omni_ld; // Omni load |
| 82 | // vlint flag_dangling_net_within_module off |
| 83 | // vlint flag_net_has_no_load off |
| 84 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH - 1:0] omni_data; |
| 85 | // Omni write data |
| 86 | // synopsys translate_on |
| 87 | // vlint flag_dangling_net_within_module on |
| 88 | // vlint flag_net_has_no_load on |
| 89 | wire clk; // Clock signal |
| 90 | wire por_l; // Reset signal |
| 91 | wire w_ld; // SW load |
| 92 | // vlint flag_dangling_net_within_module off |
| 93 | // vlint flag_net_has_no_load off |
| 94 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 95 | // vlint flag_dangling_net_within_module on |
| 96 | // vlint flag_net_has_no_load on |
| 97 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_csrbus_read_data; |
| 98 | // SW read data |
| 99 | wire imu_rds_error_log_reg_hw_ld; // Hardware load enable for |
| 100 | // imu_rds_error_log_reg. When set, <hw write |
| 101 | // signal> will be loaded into |
| 102 | // imu_rds_error_log_reg. |
| 103 | // vlint flag_dangling_net_within_module off |
| 104 | // vlint flag_net_has_no_load off |
| 105 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH -1:0] imu_rds_error_log_reg_hw_write; |
| 106 | // data bus for hw loading of imu_rds_error_log_reg. |
| 107 | // vlint flag_dangling_net_within_module on |
| 108 | // vlint flag_net_has_no_load on |
| 109 | |
| 110 | //==================================================================== |
| 111 | // Logic |
| 112 | //==================================================================== |
| 113 | |
| 114 | //----- Reset values |
| 115 | // verilint 531 off |
| 116 | wire [5:0] reset_type = 6'b0; |
| 117 | wire [9:0] reset_length = 10'b0; |
| 118 | wire [15:0] reset_req_id = 16'b0; |
| 119 | wire [7:0] reset_tlp_tag = 8'b0; |
| 120 | wire [7:0] reset_be_mess_code = 8'b0; |
| 121 | wire [15:0] reset_msi_data = 16'b0; |
| 122 | // verilint 531 on |
| 123 | |
| 124 | //----- Active high reset wires |
| 125 | wire por_l_active_high = ~por_l; |
| 126 | |
| 127 | //==================================================== |
| 128 | // Instantiation of flops |
| 129 | //==================================================== |
| 130 | |
| 131 | // bit 0 |
| 132 | csr_sw csr_sw_0 |
| 133 | ( |
| 134 | // synopsys translate_off |
| 135 | .omni_ld (omni_ld), |
| 136 | .omni_data (omni_data[0]), |
| 137 | .omni_rw_alias (1'b1), |
| 138 | .omni_rw1c_alias (1'b0), |
| 139 | .omni_rw1s_alias (1'b0), |
| 140 | // synopsys translate_on |
| 141 | .rst (por_l_active_high), |
| 142 | .rst_val (reset_msi_data[0]), |
| 143 | .csr_ld (w_ld), |
| 144 | .csr_data (csrbus_wr_data[0]), |
| 145 | .rw_alias (1'b1), |
| 146 | .rw1c_alias (1'b0), |
| 147 | .rw1s_alias (1'b0), |
| 148 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 149 | .hw_data (imu_rds_error_log_reg_hw_write[0]), |
| 150 | .cp (clk), |
| 151 | .q (imu_rds_error_log_reg_csrbus_read_data[0]) |
| 152 | ); |
| 153 | |
| 154 | // bit 1 |
| 155 | csr_sw csr_sw_1 |
| 156 | ( |
| 157 | // synopsys translate_off |
| 158 | .omni_ld (omni_ld), |
| 159 | .omni_data (omni_data[1]), |
| 160 | .omni_rw_alias (1'b1), |
| 161 | .omni_rw1c_alias (1'b0), |
| 162 | .omni_rw1s_alias (1'b0), |
| 163 | // synopsys translate_on |
| 164 | .rst (por_l_active_high), |
| 165 | .rst_val (reset_msi_data[1]), |
| 166 | .csr_ld (w_ld), |
| 167 | .csr_data (csrbus_wr_data[1]), |
| 168 | .rw_alias (1'b1), |
| 169 | .rw1c_alias (1'b0), |
| 170 | .rw1s_alias (1'b0), |
| 171 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 172 | .hw_data (imu_rds_error_log_reg_hw_write[1]), |
| 173 | .cp (clk), |
| 174 | .q (imu_rds_error_log_reg_csrbus_read_data[1]) |
| 175 | ); |
| 176 | |
| 177 | // bit 2 |
| 178 | csr_sw csr_sw_2 |
| 179 | ( |
| 180 | // synopsys translate_off |
| 181 | .omni_ld (omni_ld), |
| 182 | .omni_data (omni_data[2]), |
| 183 | .omni_rw_alias (1'b1), |
| 184 | .omni_rw1c_alias (1'b0), |
| 185 | .omni_rw1s_alias (1'b0), |
| 186 | // synopsys translate_on |
| 187 | .rst (por_l_active_high), |
| 188 | .rst_val (reset_msi_data[2]), |
| 189 | .csr_ld (w_ld), |
| 190 | .csr_data (csrbus_wr_data[2]), |
| 191 | .rw_alias (1'b1), |
| 192 | .rw1c_alias (1'b0), |
| 193 | .rw1s_alias (1'b0), |
| 194 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 195 | .hw_data (imu_rds_error_log_reg_hw_write[2]), |
| 196 | .cp (clk), |
| 197 | .q (imu_rds_error_log_reg_csrbus_read_data[2]) |
| 198 | ); |
| 199 | |
| 200 | // bit 3 |
| 201 | csr_sw csr_sw_3 |
| 202 | ( |
| 203 | // synopsys translate_off |
| 204 | .omni_ld (omni_ld), |
| 205 | .omni_data (omni_data[3]), |
| 206 | .omni_rw_alias (1'b1), |
| 207 | .omni_rw1c_alias (1'b0), |
| 208 | .omni_rw1s_alias (1'b0), |
| 209 | // synopsys translate_on |
| 210 | .rst (por_l_active_high), |
| 211 | .rst_val (reset_msi_data[3]), |
| 212 | .csr_ld (w_ld), |
| 213 | .csr_data (csrbus_wr_data[3]), |
| 214 | .rw_alias (1'b1), |
| 215 | .rw1c_alias (1'b0), |
| 216 | .rw1s_alias (1'b0), |
| 217 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 218 | .hw_data (imu_rds_error_log_reg_hw_write[3]), |
| 219 | .cp (clk), |
| 220 | .q (imu_rds_error_log_reg_csrbus_read_data[3]) |
| 221 | ); |
| 222 | |
| 223 | // bit 4 |
| 224 | csr_sw csr_sw_4 |
| 225 | ( |
| 226 | // synopsys translate_off |
| 227 | .omni_ld (omni_ld), |
| 228 | .omni_data (omni_data[4]), |
| 229 | .omni_rw_alias (1'b1), |
| 230 | .omni_rw1c_alias (1'b0), |
| 231 | .omni_rw1s_alias (1'b0), |
| 232 | // synopsys translate_on |
| 233 | .rst (por_l_active_high), |
| 234 | .rst_val (reset_msi_data[4]), |
| 235 | .csr_ld (w_ld), |
| 236 | .csr_data (csrbus_wr_data[4]), |
| 237 | .rw_alias (1'b1), |
| 238 | .rw1c_alias (1'b0), |
| 239 | .rw1s_alias (1'b0), |
| 240 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 241 | .hw_data (imu_rds_error_log_reg_hw_write[4]), |
| 242 | .cp (clk), |
| 243 | .q (imu_rds_error_log_reg_csrbus_read_data[4]) |
| 244 | ); |
| 245 | |
| 246 | // bit 5 |
| 247 | csr_sw csr_sw_5 |
| 248 | ( |
| 249 | // synopsys translate_off |
| 250 | .omni_ld (omni_ld), |
| 251 | .omni_data (omni_data[5]), |
| 252 | .omni_rw_alias (1'b1), |
| 253 | .omni_rw1c_alias (1'b0), |
| 254 | .omni_rw1s_alias (1'b0), |
| 255 | // synopsys translate_on |
| 256 | .rst (por_l_active_high), |
| 257 | .rst_val (reset_msi_data[5]), |
| 258 | .csr_ld (w_ld), |
| 259 | .csr_data (csrbus_wr_data[5]), |
| 260 | .rw_alias (1'b1), |
| 261 | .rw1c_alias (1'b0), |
| 262 | .rw1s_alias (1'b0), |
| 263 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 264 | .hw_data (imu_rds_error_log_reg_hw_write[5]), |
| 265 | .cp (clk), |
| 266 | .q (imu_rds_error_log_reg_csrbus_read_data[5]) |
| 267 | ); |
| 268 | |
| 269 | // bit 6 |
| 270 | csr_sw csr_sw_6 |
| 271 | ( |
| 272 | // synopsys translate_off |
| 273 | .omni_ld (omni_ld), |
| 274 | .omni_data (omni_data[6]), |
| 275 | .omni_rw_alias (1'b1), |
| 276 | .omni_rw1c_alias (1'b0), |
| 277 | .omni_rw1s_alias (1'b0), |
| 278 | // synopsys translate_on |
| 279 | .rst (por_l_active_high), |
| 280 | .rst_val (reset_msi_data[6]), |
| 281 | .csr_ld (w_ld), |
| 282 | .csr_data (csrbus_wr_data[6]), |
| 283 | .rw_alias (1'b1), |
| 284 | .rw1c_alias (1'b0), |
| 285 | .rw1s_alias (1'b0), |
| 286 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 287 | .hw_data (imu_rds_error_log_reg_hw_write[6]), |
| 288 | .cp (clk), |
| 289 | .q (imu_rds_error_log_reg_csrbus_read_data[6]) |
| 290 | ); |
| 291 | |
| 292 | // bit 7 |
| 293 | csr_sw csr_sw_7 |
| 294 | ( |
| 295 | // synopsys translate_off |
| 296 | .omni_ld (omni_ld), |
| 297 | .omni_data (omni_data[7]), |
| 298 | .omni_rw_alias (1'b1), |
| 299 | .omni_rw1c_alias (1'b0), |
| 300 | .omni_rw1s_alias (1'b0), |
| 301 | // synopsys translate_on |
| 302 | .rst (por_l_active_high), |
| 303 | .rst_val (reset_msi_data[7]), |
| 304 | .csr_ld (w_ld), |
| 305 | .csr_data (csrbus_wr_data[7]), |
| 306 | .rw_alias (1'b1), |
| 307 | .rw1c_alias (1'b0), |
| 308 | .rw1s_alias (1'b0), |
| 309 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 310 | .hw_data (imu_rds_error_log_reg_hw_write[7]), |
| 311 | .cp (clk), |
| 312 | .q (imu_rds_error_log_reg_csrbus_read_data[7]) |
| 313 | ); |
| 314 | |
| 315 | // bit 8 |
| 316 | csr_sw csr_sw_8 |
| 317 | ( |
| 318 | // synopsys translate_off |
| 319 | .omni_ld (omni_ld), |
| 320 | .omni_data (omni_data[8]), |
| 321 | .omni_rw_alias (1'b1), |
| 322 | .omni_rw1c_alias (1'b0), |
| 323 | .omni_rw1s_alias (1'b0), |
| 324 | // synopsys translate_on |
| 325 | .rst (por_l_active_high), |
| 326 | .rst_val (reset_msi_data[8]), |
| 327 | .csr_ld (w_ld), |
| 328 | .csr_data (csrbus_wr_data[8]), |
| 329 | .rw_alias (1'b1), |
| 330 | .rw1c_alias (1'b0), |
| 331 | .rw1s_alias (1'b0), |
| 332 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 333 | .hw_data (imu_rds_error_log_reg_hw_write[8]), |
| 334 | .cp (clk), |
| 335 | .q (imu_rds_error_log_reg_csrbus_read_data[8]) |
| 336 | ); |
| 337 | |
| 338 | // bit 9 |
| 339 | csr_sw csr_sw_9 |
| 340 | ( |
| 341 | // synopsys translate_off |
| 342 | .omni_ld (omni_ld), |
| 343 | .omni_data (omni_data[9]), |
| 344 | .omni_rw_alias (1'b1), |
| 345 | .omni_rw1c_alias (1'b0), |
| 346 | .omni_rw1s_alias (1'b0), |
| 347 | // synopsys translate_on |
| 348 | .rst (por_l_active_high), |
| 349 | .rst_val (reset_msi_data[9]), |
| 350 | .csr_ld (w_ld), |
| 351 | .csr_data (csrbus_wr_data[9]), |
| 352 | .rw_alias (1'b1), |
| 353 | .rw1c_alias (1'b0), |
| 354 | .rw1s_alias (1'b0), |
| 355 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 356 | .hw_data (imu_rds_error_log_reg_hw_write[9]), |
| 357 | .cp (clk), |
| 358 | .q (imu_rds_error_log_reg_csrbus_read_data[9]) |
| 359 | ); |
| 360 | |
| 361 | // bit 10 |
| 362 | csr_sw csr_sw_10 |
| 363 | ( |
| 364 | // synopsys translate_off |
| 365 | .omni_ld (omni_ld), |
| 366 | .omni_data (omni_data[10]), |
| 367 | .omni_rw_alias (1'b1), |
| 368 | .omni_rw1c_alias (1'b0), |
| 369 | .omni_rw1s_alias (1'b0), |
| 370 | // synopsys translate_on |
| 371 | .rst (por_l_active_high), |
| 372 | .rst_val (reset_msi_data[10]), |
| 373 | .csr_ld (w_ld), |
| 374 | .csr_data (csrbus_wr_data[10]), |
| 375 | .rw_alias (1'b1), |
| 376 | .rw1c_alias (1'b0), |
| 377 | .rw1s_alias (1'b0), |
| 378 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 379 | .hw_data (imu_rds_error_log_reg_hw_write[10]), |
| 380 | .cp (clk), |
| 381 | .q (imu_rds_error_log_reg_csrbus_read_data[10]) |
| 382 | ); |
| 383 | |
| 384 | // bit 11 |
| 385 | csr_sw csr_sw_11 |
| 386 | ( |
| 387 | // synopsys translate_off |
| 388 | .omni_ld (omni_ld), |
| 389 | .omni_data (omni_data[11]), |
| 390 | .omni_rw_alias (1'b1), |
| 391 | .omni_rw1c_alias (1'b0), |
| 392 | .omni_rw1s_alias (1'b0), |
| 393 | // synopsys translate_on |
| 394 | .rst (por_l_active_high), |
| 395 | .rst_val (reset_msi_data[11]), |
| 396 | .csr_ld (w_ld), |
| 397 | .csr_data (csrbus_wr_data[11]), |
| 398 | .rw_alias (1'b1), |
| 399 | .rw1c_alias (1'b0), |
| 400 | .rw1s_alias (1'b0), |
| 401 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 402 | .hw_data (imu_rds_error_log_reg_hw_write[11]), |
| 403 | .cp (clk), |
| 404 | .q (imu_rds_error_log_reg_csrbus_read_data[11]) |
| 405 | ); |
| 406 | |
| 407 | // bit 12 |
| 408 | csr_sw csr_sw_12 |
| 409 | ( |
| 410 | // synopsys translate_off |
| 411 | .omni_ld (omni_ld), |
| 412 | .omni_data (omni_data[12]), |
| 413 | .omni_rw_alias (1'b1), |
| 414 | .omni_rw1c_alias (1'b0), |
| 415 | .omni_rw1s_alias (1'b0), |
| 416 | // synopsys translate_on |
| 417 | .rst (por_l_active_high), |
| 418 | .rst_val (reset_msi_data[12]), |
| 419 | .csr_ld (w_ld), |
| 420 | .csr_data (csrbus_wr_data[12]), |
| 421 | .rw_alias (1'b1), |
| 422 | .rw1c_alias (1'b0), |
| 423 | .rw1s_alias (1'b0), |
| 424 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 425 | .hw_data (imu_rds_error_log_reg_hw_write[12]), |
| 426 | .cp (clk), |
| 427 | .q (imu_rds_error_log_reg_csrbus_read_data[12]) |
| 428 | ); |
| 429 | |
| 430 | // bit 13 |
| 431 | csr_sw csr_sw_13 |
| 432 | ( |
| 433 | // synopsys translate_off |
| 434 | .omni_ld (omni_ld), |
| 435 | .omni_data (omni_data[13]), |
| 436 | .omni_rw_alias (1'b1), |
| 437 | .omni_rw1c_alias (1'b0), |
| 438 | .omni_rw1s_alias (1'b0), |
| 439 | // synopsys translate_on |
| 440 | .rst (por_l_active_high), |
| 441 | .rst_val (reset_msi_data[13]), |
| 442 | .csr_ld (w_ld), |
| 443 | .csr_data (csrbus_wr_data[13]), |
| 444 | .rw_alias (1'b1), |
| 445 | .rw1c_alias (1'b0), |
| 446 | .rw1s_alias (1'b0), |
| 447 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 448 | .hw_data (imu_rds_error_log_reg_hw_write[13]), |
| 449 | .cp (clk), |
| 450 | .q (imu_rds_error_log_reg_csrbus_read_data[13]) |
| 451 | ); |
| 452 | |
| 453 | // bit 14 |
| 454 | csr_sw csr_sw_14 |
| 455 | ( |
| 456 | // synopsys translate_off |
| 457 | .omni_ld (omni_ld), |
| 458 | .omni_data (omni_data[14]), |
| 459 | .omni_rw_alias (1'b1), |
| 460 | .omni_rw1c_alias (1'b0), |
| 461 | .omni_rw1s_alias (1'b0), |
| 462 | // synopsys translate_on |
| 463 | .rst (por_l_active_high), |
| 464 | .rst_val (reset_msi_data[14]), |
| 465 | .csr_ld (w_ld), |
| 466 | .csr_data (csrbus_wr_data[14]), |
| 467 | .rw_alias (1'b1), |
| 468 | .rw1c_alias (1'b0), |
| 469 | .rw1s_alias (1'b0), |
| 470 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 471 | .hw_data (imu_rds_error_log_reg_hw_write[14]), |
| 472 | .cp (clk), |
| 473 | .q (imu_rds_error_log_reg_csrbus_read_data[14]) |
| 474 | ); |
| 475 | |
| 476 | // bit 15 |
| 477 | csr_sw csr_sw_15 |
| 478 | ( |
| 479 | // synopsys translate_off |
| 480 | .omni_ld (omni_ld), |
| 481 | .omni_data (omni_data[15]), |
| 482 | .omni_rw_alias (1'b1), |
| 483 | .omni_rw1c_alias (1'b0), |
| 484 | .omni_rw1s_alias (1'b0), |
| 485 | // synopsys translate_on |
| 486 | .rst (por_l_active_high), |
| 487 | .rst_val (reset_msi_data[15]), |
| 488 | .csr_ld (w_ld), |
| 489 | .csr_data (csrbus_wr_data[15]), |
| 490 | .rw_alias (1'b1), |
| 491 | .rw1c_alias (1'b0), |
| 492 | .rw1s_alias (1'b0), |
| 493 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 494 | .hw_data (imu_rds_error_log_reg_hw_write[15]), |
| 495 | .cp (clk), |
| 496 | .q (imu_rds_error_log_reg_csrbus_read_data[15]) |
| 497 | ); |
| 498 | |
| 499 | // bit 16 |
| 500 | csr_sw csr_sw_16 |
| 501 | ( |
| 502 | // synopsys translate_off |
| 503 | .omni_ld (omni_ld), |
| 504 | .omni_data (omni_data[16]), |
| 505 | .omni_rw_alias (1'b1), |
| 506 | .omni_rw1c_alias (1'b0), |
| 507 | .omni_rw1s_alias (1'b0), |
| 508 | // synopsys translate_on |
| 509 | .rst (por_l_active_high), |
| 510 | .rst_val (reset_be_mess_code[0]), |
| 511 | .csr_ld (w_ld), |
| 512 | .csr_data (csrbus_wr_data[16]), |
| 513 | .rw_alias (1'b1), |
| 514 | .rw1c_alias (1'b0), |
| 515 | .rw1s_alias (1'b0), |
| 516 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 517 | .hw_data (imu_rds_error_log_reg_hw_write[16]), |
| 518 | .cp (clk), |
| 519 | .q (imu_rds_error_log_reg_csrbus_read_data[16]) |
| 520 | ); |
| 521 | |
| 522 | // bit 17 |
| 523 | csr_sw csr_sw_17 |
| 524 | ( |
| 525 | // synopsys translate_off |
| 526 | .omni_ld (omni_ld), |
| 527 | .omni_data (omni_data[17]), |
| 528 | .omni_rw_alias (1'b1), |
| 529 | .omni_rw1c_alias (1'b0), |
| 530 | .omni_rw1s_alias (1'b0), |
| 531 | // synopsys translate_on |
| 532 | .rst (por_l_active_high), |
| 533 | .rst_val (reset_be_mess_code[1]), |
| 534 | .csr_ld (w_ld), |
| 535 | .csr_data (csrbus_wr_data[17]), |
| 536 | .rw_alias (1'b1), |
| 537 | .rw1c_alias (1'b0), |
| 538 | .rw1s_alias (1'b0), |
| 539 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 540 | .hw_data (imu_rds_error_log_reg_hw_write[17]), |
| 541 | .cp (clk), |
| 542 | .q (imu_rds_error_log_reg_csrbus_read_data[17]) |
| 543 | ); |
| 544 | |
| 545 | // bit 18 |
| 546 | csr_sw csr_sw_18 |
| 547 | ( |
| 548 | // synopsys translate_off |
| 549 | .omni_ld (omni_ld), |
| 550 | .omni_data (omni_data[18]), |
| 551 | .omni_rw_alias (1'b1), |
| 552 | .omni_rw1c_alias (1'b0), |
| 553 | .omni_rw1s_alias (1'b0), |
| 554 | // synopsys translate_on |
| 555 | .rst (por_l_active_high), |
| 556 | .rst_val (reset_be_mess_code[2]), |
| 557 | .csr_ld (w_ld), |
| 558 | .csr_data (csrbus_wr_data[18]), |
| 559 | .rw_alias (1'b1), |
| 560 | .rw1c_alias (1'b0), |
| 561 | .rw1s_alias (1'b0), |
| 562 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 563 | .hw_data (imu_rds_error_log_reg_hw_write[18]), |
| 564 | .cp (clk), |
| 565 | .q (imu_rds_error_log_reg_csrbus_read_data[18]) |
| 566 | ); |
| 567 | |
| 568 | // bit 19 |
| 569 | csr_sw csr_sw_19 |
| 570 | ( |
| 571 | // synopsys translate_off |
| 572 | .omni_ld (omni_ld), |
| 573 | .omni_data (omni_data[19]), |
| 574 | .omni_rw_alias (1'b1), |
| 575 | .omni_rw1c_alias (1'b0), |
| 576 | .omni_rw1s_alias (1'b0), |
| 577 | // synopsys translate_on |
| 578 | .rst (por_l_active_high), |
| 579 | .rst_val (reset_be_mess_code[3]), |
| 580 | .csr_ld (w_ld), |
| 581 | .csr_data (csrbus_wr_data[19]), |
| 582 | .rw_alias (1'b1), |
| 583 | .rw1c_alias (1'b0), |
| 584 | .rw1s_alias (1'b0), |
| 585 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 586 | .hw_data (imu_rds_error_log_reg_hw_write[19]), |
| 587 | .cp (clk), |
| 588 | .q (imu_rds_error_log_reg_csrbus_read_data[19]) |
| 589 | ); |
| 590 | |
| 591 | // bit 20 |
| 592 | csr_sw csr_sw_20 |
| 593 | ( |
| 594 | // synopsys translate_off |
| 595 | .omni_ld (omni_ld), |
| 596 | .omni_data (omni_data[20]), |
| 597 | .omni_rw_alias (1'b1), |
| 598 | .omni_rw1c_alias (1'b0), |
| 599 | .omni_rw1s_alias (1'b0), |
| 600 | // synopsys translate_on |
| 601 | .rst (por_l_active_high), |
| 602 | .rst_val (reset_be_mess_code[4]), |
| 603 | .csr_ld (w_ld), |
| 604 | .csr_data (csrbus_wr_data[20]), |
| 605 | .rw_alias (1'b1), |
| 606 | .rw1c_alias (1'b0), |
| 607 | .rw1s_alias (1'b0), |
| 608 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 609 | .hw_data (imu_rds_error_log_reg_hw_write[20]), |
| 610 | .cp (clk), |
| 611 | .q (imu_rds_error_log_reg_csrbus_read_data[20]) |
| 612 | ); |
| 613 | |
| 614 | // bit 21 |
| 615 | csr_sw csr_sw_21 |
| 616 | ( |
| 617 | // synopsys translate_off |
| 618 | .omni_ld (omni_ld), |
| 619 | .omni_data (omni_data[21]), |
| 620 | .omni_rw_alias (1'b1), |
| 621 | .omni_rw1c_alias (1'b0), |
| 622 | .omni_rw1s_alias (1'b0), |
| 623 | // synopsys translate_on |
| 624 | .rst (por_l_active_high), |
| 625 | .rst_val (reset_be_mess_code[5]), |
| 626 | .csr_ld (w_ld), |
| 627 | .csr_data (csrbus_wr_data[21]), |
| 628 | .rw_alias (1'b1), |
| 629 | .rw1c_alias (1'b0), |
| 630 | .rw1s_alias (1'b0), |
| 631 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 632 | .hw_data (imu_rds_error_log_reg_hw_write[21]), |
| 633 | .cp (clk), |
| 634 | .q (imu_rds_error_log_reg_csrbus_read_data[21]) |
| 635 | ); |
| 636 | |
| 637 | // bit 22 |
| 638 | csr_sw csr_sw_22 |
| 639 | ( |
| 640 | // synopsys translate_off |
| 641 | .omni_ld (omni_ld), |
| 642 | .omni_data (omni_data[22]), |
| 643 | .omni_rw_alias (1'b1), |
| 644 | .omni_rw1c_alias (1'b0), |
| 645 | .omni_rw1s_alias (1'b0), |
| 646 | // synopsys translate_on |
| 647 | .rst (por_l_active_high), |
| 648 | .rst_val (reset_be_mess_code[6]), |
| 649 | .csr_ld (w_ld), |
| 650 | .csr_data (csrbus_wr_data[22]), |
| 651 | .rw_alias (1'b1), |
| 652 | .rw1c_alias (1'b0), |
| 653 | .rw1s_alias (1'b0), |
| 654 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 655 | .hw_data (imu_rds_error_log_reg_hw_write[22]), |
| 656 | .cp (clk), |
| 657 | .q (imu_rds_error_log_reg_csrbus_read_data[22]) |
| 658 | ); |
| 659 | |
| 660 | // bit 23 |
| 661 | csr_sw csr_sw_23 |
| 662 | ( |
| 663 | // synopsys translate_off |
| 664 | .omni_ld (omni_ld), |
| 665 | .omni_data (omni_data[23]), |
| 666 | .omni_rw_alias (1'b1), |
| 667 | .omni_rw1c_alias (1'b0), |
| 668 | .omni_rw1s_alias (1'b0), |
| 669 | // synopsys translate_on |
| 670 | .rst (por_l_active_high), |
| 671 | .rst_val (reset_be_mess_code[7]), |
| 672 | .csr_ld (w_ld), |
| 673 | .csr_data (csrbus_wr_data[23]), |
| 674 | .rw_alias (1'b1), |
| 675 | .rw1c_alias (1'b0), |
| 676 | .rw1s_alias (1'b0), |
| 677 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 678 | .hw_data (imu_rds_error_log_reg_hw_write[23]), |
| 679 | .cp (clk), |
| 680 | .q (imu_rds_error_log_reg_csrbus_read_data[23]) |
| 681 | ); |
| 682 | |
| 683 | // bit 24 |
| 684 | csr_sw csr_sw_24 |
| 685 | ( |
| 686 | // synopsys translate_off |
| 687 | .omni_ld (omni_ld), |
| 688 | .omni_data (omni_data[24]), |
| 689 | .omni_rw_alias (1'b1), |
| 690 | .omni_rw1c_alias (1'b0), |
| 691 | .omni_rw1s_alias (1'b0), |
| 692 | // synopsys translate_on |
| 693 | .rst (por_l_active_high), |
| 694 | .rst_val (reset_tlp_tag[0]), |
| 695 | .csr_ld (w_ld), |
| 696 | .csr_data (csrbus_wr_data[24]), |
| 697 | .rw_alias (1'b1), |
| 698 | .rw1c_alias (1'b0), |
| 699 | .rw1s_alias (1'b0), |
| 700 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 701 | .hw_data (imu_rds_error_log_reg_hw_write[24]), |
| 702 | .cp (clk), |
| 703 | .q (imu_rds_error_log_reg_csrbus_read_data[24]) |
| 704 | ); |
| 705 | |
| 706 | // bit 25 |
| 707 | csr_sw csr_sw_25 |
| 708 | ( |
| 709 | // synopsys translate_off |
| 710 | .omni_ld (omni_ld), |
| 711 | .omni_data (omni_data[25]), |
| 712 | .omni_rw_alias (1'b1), |
| 713 | .omni_rw1c_alias (1'b0), |
| 714 | .omni_rw1s_alias (1'b0), |
| 715 | // synopsys translate_on |
| 716 | .rst (por_l_active_high), |
| 717 | .rst_val (reset_tlp_tag[1]), |
| 718 | .csr_ld (w_ld), |
| 719 | .csr_data (csrbus_wr_data[25]), |
| 720 | .rw_alias (1'b1), |
| 721 | .rw1c_alias (1'b0), |
| 722 | .rw1s_alias (1'b0), |
| 723 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 724 | .hw_data (imu_rds_error_log_reg_hw_write[25]), |
| 725 | .cp (clk), |
| 726 | .q (imu_rds_error_log_reg_csrbus_read_data[25]) |
| 727 | ); |
| 728 | |
| 729 | // bit 26 |
| 730 | csr_sw csr_sw_26 |
| 731 | ( |
| 732 | // synopsys translate_off |
| 733 | .omni_ld (omni_ld), |
| 734 | .omni_data (omni_data[26]), |
| 735 | .omni_rw_alias (1'b1), |
| 736 | .omni_rw1c_alias (1'b0), |
| 737 | .omni_rw1s_alias (1'b0), |
| 738 | // synopsys translate_on |
| 739 | .rst (por_l_active_high), |
| 740 | .rst_val (reset_tlp_tag[2]), |
| 741 | .csr_ld (w_ld), |
| 742 | .csr_data (csrbus_wr_data[26]), |
| 743 | .rw_alias (1'b1), |
| 744 | .rw1c_alias (1'b0), |
| 745 | .rw1s_alias (1'b0), |
| 746 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 747 | .hw_data (imu_rds_error_log_reg_hw_write[26]), |
| 748 | .cp (clk), |
| 749 | .q (imu_rds_error_log_reg_csrbus_read_data[26]) |
| 750 | ); |
| 751 | |
| 752 | // bit 27 |
| 753 | csr_sw csr_sw_27 |
| 754 | ( |
| 755 | // synopsys translate_off |
| 756 | .omni_ld (omni_ld), |
| 757 | .omni_data (omni_data[27]), |
| 758 | .omni_rw_alias (1'b1), |
| 759 | .omni_rw1c_alias (1'b0), |
| 760 | .omni_rw1s_alias (1'b0), |
| 761 | // synopsys translate_on |
| 762 | .rst (por_l_active_high), |
| 763 | .rst_val (reset_tlp_tag[3]), |
| 764 | .csr_ld (w_ld), |
| 765 | .csr_data (csrbus_wr_data[27]), |
| 766 | .rw_alias (1'b1), |
| 767 | .rw1c_alias (1'b0), |
| 768 | .rw1s_alias (1'b0), |
| 769 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 770 | .hw_data (imu_rds_error_log_reg_hw_write[27]), |
| 771 | .cp (clk), |
| 772 | .q (imu_rds_error_log_reg_csrbus_read_data[27]) |
| 773 | ); |
| 774 | |
| 775 | // bit 28 |
| 776 | csr_sw csr_sw_28 |
| 777 | ( |
| 778 | // synopsys translate_off |
| 779 | .omni_ld (omni_ld), |
| 780 | .omni_data (omni_data[28]), |
| 781 | .omni_rw_alias (1'b1), |
| 782 | .omni_rw1c_alias (1'b0), |
| 783 | .omni_rw1s_alias (1'b0), |
| 784 | // synopsys translate_on |
| 785 | .rst (por_l_active_high), |
| 786 | .rst_val (reset_tlp_tag[4]), |
| 787 | .csr_ld (w_ld), |
| 788 | .csr_data (csrbus_wr_data[28]), |
| 789 | .rw_alias (1'b1), |
| 790 | .rw1c_alias (1'b0), |
| 791 | .rw1s_alias (1'b0), |
| 792 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 793 | .hw_data (imu_rds_error_log_reg_hw_write[28]), |
| 794 | .cp (clk), |
| 795 | .q (imu_rds_error_log_reg_csrbus_read_data[28]) |
| 796 | ); |
| 797 | |
| 798 | // bit 29 |
| 799 | csr_sw csr_sw_29 |
| 800 | ( |
| 801 | // synopsys translate_off |
| 802 | .omni_ld (omni_ld), |
| 803 | .omni_data (omni_data[29]), |
| 804 | .omni_rw_alias (1'b1), |
| 805 | .omni_rw1c_alias (1'b0), |
| 806 | .omni_rw1s_alias (1'b0), |
| 807 | // synopsys translate_on |
| 808 | .rst (por_l_active_high), |
| 809 | .rst_val (reset_tlp_tag[5]), |
| 810 | .csr_ld (w_ld), |
| 811 | .csr_data (csrbus_wr_data[29]), |
| 812 | .rw_alias (1'b1), |
| 813 | .rw1c_alias (1'b0), |
| 814 | .rw1s_alias (1'b0), |
| 815 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 816 | .hw_data (imu_rds_error_log_reg_hw_write[29]), |
| 817 | .cp (clk), |
| 818 | .q (imu_rds_error_log_reg_csrbus_read_data[29]) |
| 819 | ); |
| 820 | |
| 821 | // bit 30 |
| 822 | csr_sw csr_sw_30 |
| 823 | ( |
| 824 | // synopsys translate_off |
| 825 | .omni_ld (omni_ld), |
| 826 | .omni_data (omni_data[30]), |
| 827 | .omni_rw_alias (1'b1), |
| 828 | .omni_rw1c_alias (1'b0), |
| 829 | .omni_rw1s_alias (1'b0), |
| 830 | // synopsys translate_on |
| 831 | .rst (por_l_active_high), |
| 832 | .rst_val (reset_tlp_tag[6]), |
| 833 | .csr_ld (w_ld), |
| 834 | .csr_data (csrbus_wr_data[30]), |
| 835 | .rw_alias (1'b1), |
| 836 | .rw1c_alias (1'b0), |
| 837 | .rw1s_alias (1'b0), |
| 838 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 839 | .hw_data (imu_rds_error_log_reg_hw_write[30]), |
| 840 | .cp (clk), |
| 841 | .q (imu_rds_error_log_reg_csrbus_read_data[30]) |
| 842 | ); |
| 843 | |
| 844 | // bit 31 |
| 845 | csr_sw csr_sw_31 |
| 846 | ( |
| 847 | // synopsys translate_off |
| 848 | .omni_ld (omni_ld), |
| 849 | .omni_data (omni_data[31]), |
| 850 | .omni_rw_alias (1'b1), |
| 851 | .omni_rw1c_alias (1'b0), |
| 852 | .omni_rw1s_alias (1'b0), |
| 853 | // synopsys translate_on |
| 854 | .rst (por_l_active_high), |
| 855 | .rst_val (reset_tlp_tag[7]), |
| 856 | .csr_ld (w_ld), |
| 857 | .csr_data (csrbus_wr_data[31]), |
| 858 | .rw_alias (1'b1), |
| 859 | .rw1c_alias (1'b0), |
| 860 | .rw1s_alias (1'b0), |
| 861 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 862 | .hw_data (imu_rds_error_log_reg_hw_write[31]), |
| 863 | .cp (clk), |
| 864 | .q (imu_rds_error_log_reg_csrbus_read_data[31]) |
| 865 | ); |
| 866 | |
| 867 | // bit 32 |
| 868 | csr_sw csr_sw_32 |
| 869 | ( |
| 870 | // synopsys translate_off |
| 871 | .omni_ld (omni_ld), |
| 872 | .omni_data (omni_data[32]), |
| 873 | .omni_rw_alias (1'b1), |
| 874 | .omni_rw1c_alias (1'b0), |
| 875 | .omni_rw1s_alias (1'b0), |
| 876 | // synopsys translate_on |
| 877 | .rst (por_l_active_high), |
| 878 | .rst_val (reset_req_id[0]), |
| 879 | .csr_ld (w_ld), |
| 880 | .csr_data (csrbus_wr_data[32]), |
| 881 | .rw_alias (1'b1), |
| 882 | .rw1c_alias (1'b0), |
| 883 | .rw1s_alias (1'b0), |
| 884 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 885 | .hw_data (imu_rds_error_log_reg_hw_write[32]), |
| 886 | .cp (clk), |
| 887 | .q (imu_rds_error_log_reg_csrbus_read_data[32]) |
| 888 | ); |
| 889 | |
| 890 | // bit 33 |
| 891 | csr_sw csr_sw_33 |
| 892 | ( |
| 893 | // synopsys translate_off |
| 894 | .omni_ld (omni_ld), |
| 895 | .omni_data (omni_data[33]), |
| 896 | .omni_rw_alias (1'b1), |
| 897 | .omni_rw1c_alias (1'b0), |
| 898 | .omni_rw1s_alias (1'b0), |
| 899 | // synopsys translate_on |
| 900 | .rst (por_l_active_high), |
| 901 | .rst_val (reset_req_id[1]), |
| 902 | .csr_ld (w_ld), |
| 903 | .csr_data (csrbus_wr_data[33]), |
| 904 | .rw_alias (1'b1), |
| 905 | .rw1c_alias (1'b0), |
| 906 | .rw1s_alias (1'b0), |
| 907 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 908 | .hw_data (imu_rds_error_log_reg_hw_write[33]), |
| 909 | .cp (clk), |
| 910 | .q (imu_rds_error_log_reg_csrbus_read_data[33]) |
| 911 | ); |
| 912 | |
| 913 | // bit 34 |
| 914 | csr_sw csr_sw_34 |
| 915 | ( |
| 916 | // synopsys translate_off |
| 917 | .omni_ld (omni_ld), |
| 918 | .omni_data (omni_data[34]), |
| 919 | .omni_rw_alias (1'b1), |
| 920 | .omni_rw1c_alias (1'b0), |
| 921 | .omni_rw1s_alias (1'b0), |
| 922 | // synopsys translate_on |
| 923 | .rst (por_l_active_high), |
| 924 | .rst_val (reset_req_id[2]), |
| 925 | .csr_ld (w_ld), |
| 926 | .csr_data (csrbus_wr_data[34]), |
| 927 | .rw_alias (1'b1), |
| 928 | .rw1c_alias (1'b0), |
| 929 | .rw1s_alias (1'b0), |
| 930 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 931 | .hw_data (imu_rds_error_log_reg_hw_write[34]), |
| 932 | .cp (clk), |
| 933 | .q (imu_rds_error_log_reg_csrbus_read_data[34]) |
| 934 | ); |
| 935 | |
| 936 | // bit 35 |
| 937 | csr_sw csr_sw_35 |
| 938 | ( |
| 939 | // synopsys translate_off |
| 940 | .omni_ld (omni_ld), |
| 941 | .omni_data (omni_data[35]), |
| 942 | .omni_rw_alias (1'b1), |
| 943 | .omni_rw1c_alias (1'b0), |
| 944 | .omni_rw1s_alias (1'b0), |
| 945 | // synopsys translate_on |
| 946 | .rst (por_l_active_high), |
| 947 | .rst_val (reset_req_id[3]), |
| 948 | .csr_ld (w_ld), |
| 949 | .csr_data (csrbus_wr_data[35]), |
| 950 | .rw_alias (1'b1), |
| 951 | .rw1c_alias (1'b0), |
| 952 | .rw1s_alias (1'b0), |
| 953 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 954 | .hw_data (imu_rds_error_log_reg_hw_write[35]), |
| 955 | .cp (clk), |
| 956 | .q (imu_rds_error_log_reg_csrbus_read_data[35]) |
| 957 | ); |
| 958 | |
| 959 | // bit 36 |
| 960 | csr_sw csr_sw_36 |
| 961 | ( |
| 962 | // synopsys translate_off |
| 963 | .omni_ld (omni_ld), |
| 964 | .omni_data (omni_data[36]), |
| 965 | .omni_rw_alias (1'b1), |
| 966 | .omni_rw1c_alias (1'b0), |
| 967 | .omni_rw1s_alias (1'b0), |
| 968 | // synopsys translate_on |
| 969 | .rst (por_l_active_high), |
| 970 | .rst_val (reset_req_id[4]), |
| 971 | .csr_ld (w_ld), |
| 972 | .csr_data (csrbus_wr_data[36]), |
| 973 | .rw_alias (1'b1), |
| 974 | .rw1c_alias (1'b0), |
| 975 | .rw1s_alias (1'b0), |
| 976 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 977 | .hw_data (imu_rds_error_log_reg_hw_write[36]), |
| 978 | .cp (clk), |
| 979 | .q (imu_rds_error_log_reg_csrbus_read_data[36]) |
| 980 | ); |
| 981 | |
| 982 | // bit 37 |
| 983 | csr_sw csr_sw_37 |
| 984 | ( |
| 985 | // synopsys translate_off |
| 986 | .omni_ld (omni_ld), |
| 987 | .omni_data (omni_data[37]), |
| 988 | .omni_rw_alias (1'b1), |
| 989 | .omni_rw1c_alias (1'b0), |
| 990 | .omni_rw1s_alias (1'b0), |
| 991 | // synopsys translate_on |
| 992 | .rst (por_l_active_high), |
| 993 | .rst_val (reset_req_id[5]), |
| 994 | .csr_ld (w_ld), |
| 995 | .csr_data (csrbus_wr_data[37]), |
| 996 | .rw_alias (1'b1), |
| 997 | .rw1c_alias (1'b0), |
| 998 | .rw1s_alias (1'b0), |
| 999 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1000 | .hw_data (imu_rds_error_log_reg_hw_write[37]), |
| 1001 | .cp (clk), |
| 1002 | .q (imu_rds_error_log_reg_csrbus_read_data[37]) |
| 1003 | ); |
| 1004 | |
| 1005 | // bit 38 |
| 1006 | csr_sw csr_sw_38 |
| 1007 | ( |
| 1008 | // synopsys translate_off |
| 1009 | .omni_ld (omni_ld), |
| 1010 | .omni_data (omni_data[38]), |
| 1011 | .omni_rw_alias (1'b1), |
| 1012 | .omni_rw1c_alias (1'b0), |
| 1013 | .omni_rw1s_alias (1'b0), |
| 1014 | // synopsys translate_on |
| 1015 | .rst (por_l_active_high), |
| 1016 | .rst_val (reset_req_id[6]), |
| 1017 | .csr_ld (w_ld), |
| 1018 | .csr_data (csrbus_wr_data[38]), |
| 1019 | .rw_alias (1'b1), |
| 1020 | .rw1c_alias (1'b0), |
| 1021 | .rw1s_alias (1'b0), |
| 1022 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1023 | .hw_data (imu_rds_error_log_reg_hw_write[38]), |
| 1024 | .cp (clk), |
| 1025 | .q (imu_rds_error_log_reg_csrbus_read_data[38]) |
| 1026 | ); |
| 1027 | |
| 1028 | // bit 39 |
| 1029 | csr_sw csr_sw_39 |
| 1030 | ( |
| 1031 | // synopsys translate_off |
| 1032 | .omni_ld (omni_ld), |
| 1033 | .omni_data (omni_data[39]), |
| 1034 | .omni_rw_alias (1'b1), |
| 1035 | .omni_rw1c_alias (1'b0), |
| 1036 | .omni_rw1s_alias (1'b0), |
| 1037 | // synopsys translate_on |
| 1038 | .rst (por_l_active_high), |
| 1039 | .rst_val (reset_req_id[7]), |
| 1040 | .csr_ld (w_ld), |
| 1041 | .csr_data (csrbus_wr_data[39]), |
| 1042 | .rw_alias (1'b1), |
| 1043 | .rw1c_alias (1'b0), |
| 1044 | .rw1s_alias (1'b0), |
| 1045 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1046 | .hw_data (imu_rds_error_log_reg_hw_write[39]), |
| 1047 | .cp (clk), |
| 1048 | .q (imu_rds_error_log_reg_csrbus_read_data[39]) |
| 1049 | ); |
| 1050 | |
| 1051 | // bit 40 |
| 1052 | csr_sw csr_sw_40 |
| 1053 | ( |
| 1054 | // synopsys translate_off |
| 1055 | .omni_ld (omni_ld), |
| 1056 | .omni_data (omni_data[40]), |
| 1057 | .omni_rw_alias (1'b1), |
| 1058 | .omni_rw1c_alias (1'b0), |
| 1059 | .omni_rw1s_alias (1'b0), |
| 1060 | // synopsys translate_on |
| 1061 | .rst (por_l_active_high), |
| 1062 | .rst_val (reset_req_id[8]), |
| 1063 | .csr_ld (w_ld), |
| 1064 | .csr_data (csrbus_wr_data[40]), |
| 1065 | .rw_alias (1'b1), |
| 1066 | .rw1c_alias (1'b0), |
| 1067 | .rw1s_alias (1'b0), |
| 1068 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1069 | .hw_data (imu_rds_error_log_reg_hw_write[40]), |
| 1070 | .cp (clk), |
| 1071 | .q (imu_rds_error_log_reg_csrbus_read_data[40]) |
| 1072 | ); |
| 1073 | |
| 1074 | // bit 41 |
| 1075 | csr_sw csr_sw_41 |
| 1076 | ( |
| 1077 | // synopsys translate_off |
| 1078 | .omni_ld (omni_ld), |
| 1079 | .omni_data (omni_data[41]), |
| 1080 | .omni_rw_alias (1'b1), |
| 1081 | .omni_rw1c_alias (1'b0), |
| 1082 | .omni_rw1s_alias (1'b0), |
| 1083 | // synopsys translate_on |
| 1084 | .rst (por_l_active_high), |
| 1085 | .rst_val (reset_req_id[9]), |
| 1086 | .csr_ld (w_ld), |
| 1087 | .csr_data (csrbus_wr_data[41]), |
| 1088 | .rw_alias (1'b1), |
| 1089 | .rw1c_alias (1'b0), |
| 1090 | .rw1s_alias (1'b0), |
| 1091 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1092 | .hw_data (imu_rds_error_log_reg_hw_write[41]), |
| 1093 | .cp (clk), |
| 1094 | .q (imu_rds_error_log_reg_csrbus_read_data[41]) |
| 1095 | ); |
| 1096 | |
| 1097 | // bit 42 |
| 1098 | csr_sw csr_sw_42 |
| 1099 | ( |
| 1100 | // synopsys translate_off |
| 1101 | .omni_ld (omni_ld), |
| 1102 | .omni_data (omni_data[42]), |
| 1103 | .omni_rw_alias (1'b1), |
| 1104 | .omni_rw1c_alias (1'b0), |
| 1105 | .omni_rw1s_alias (1'b0), |
| 1106 | // synopsys translate_on |
| 1107 | .rst (por_l_active_high), |
| 1108 | .rst_val (reset_req_id[10]), |
| 1109 | .csr_ld (w_ld), |
| 1110 | .csr_data (csrbus_wr_data[42]), |
| 1111 | .rw_alias (1'b1), |
| 1112 | .rw1c_alias (1'b0), |
| 1113 | .rw1s_alias (1'b0), |
| 1114 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1115 | .hw_data (imu_rds_error_log_reg_hw_write[42]), |
| 1116 | .cp (clk), |
| 1117 | .q (imu_rds_error_log_reg_csrbus_read_data[42]) |
| 1118 | ); |
| 1119 | |
| 1120 | // bit 43 |
| 1121 | csr_sw csr_sw_43 |
| 1122 | ( |
| 1123 | // synopsys translate_off |
| 1124 | .omni_ld (omni_ld), |
| 1125 | .omni_data (omni_data[43]), |
| 1126 | .omni_rw_alias (1'b1), |
| 1127 | .omni_rw1c_alias (1'b0), |
| 1128 | .omni_rw1s_alias (1'b0), |
| 1129 | // synopsys translate_on |
| 1130 | .rst (por_l_active_high), |
| 1131 | .rst_val (reset_req_id[11]), |
| 1132 | .csr_ld (w_ld), |
| 1133 | .csr_data (csrbus_wr_data[43]), |
| 1134 | .rw_alias (1'b1), |
| 1135 | .rw1c_alias (1'b0), |
| 1136 | .rw1s_alias (1'b0), |
| 1137 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1138 | .hw_data (imu_rds_error_log_reg_hw_write[43]), |
| 1139 | .cp (clk), |
| 1140 | .q (imu_rds_error_log_reg_csrbus_read_data[43]) |
| 1141 | ); |
| 1142 | |
| 1143 | // bit 44 |
| 1144 | csr_sw csr_sw_44 |
| 1145 | ( |
| 1146 | // synopsys translate_off |
| 1147 | .omni_ld (omni_ld), |
| 1148 | .omni_data (omni_data[44]), |
| 1149 | .omni_rw_alias (1'b1), |
| 1150 | .omni_rw1c_alias (1'b0), |
| 1151 | .omni_rw1s_alias (1'b0), |
| 1152 | // synopsys translate_on |
| 1153 | .rst (por_l_active_high), |
| 1154 | .rst_val (reset_req_id[12]), |
| 1155 | .csr_ld (w_ld), |
| 1156 | .csr_data (csrbus_wr_data[44]), |
| 1157 | .rw_alias (1'b1), |
| 1158 | .rw1c_alias (1'b0), |
| 1159 | .rw1s_alias (1'b0), |
| 1160 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1161 | .hw_data (imu_rds_error_log_reg_hw_write[44]), |
| 1162 | .cp (clk), |
| 1163 | .q (imu_rds_error_log_reg_csrbus_read_data[44]) |
| 1164 | ); |
| 1165 | |
| 1166 | // bit 45 |
| 1167 | csr_sw csr_sw_45 |
| 1168 | ( |
| 1169 | // synopsys translate_off |
| 1170 | .omni_ld (omni_ld), |
| 1171 | .omni_data (omni_data[45]), |
| 1172 | .omni_rw_alias (1'b1), |
| 1173 | .omni_rw1c_alias (1'b0), |
| 1174 | .omni_rw1s_alias (1'b0), |
| 1175 | // synopsys translate_on |
| 1176 | .rst (por_l_active_high), |
| 1177 | .rst_val (reset_req_id[13]), |
| 1178 | .csr_ld (w_ld), |
| 1179 | .csr_data (csrbus_wr_data[45]), |
| 1180 | .rw_alias (1'b1), |
| 1181 | .rw1c_alias (1'b0), |
| 1182 | .rw1s_alias (1'b0), |
| 1183 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1184 | .hw_data (imu_rds_error_log_reg_hw_write[45]), |
| 1185 | .cp (clk), |
| 1186 | .q (imu_rds_error_log_reg_csrbus_read_data[45]) |
| 1187 | ); |
| 1188 | |
| 1189 | // bit 46 |
| 1190 | csr_sw csr_sw_46 |
| 1191 | ( |
| 1192 | // synopsys translate_off |
| 1193 | .omni_ld (omni_ld), |
| 1194 | .omni_data (omni_data[46]), |
| 1195 | .omni_rw_alias (1'b1), |
| 1196 | .omni_rw1c_alias (1'b0), |
| 1197 | .omni_rw1s_alias (1'b0), |
| 1198 | // synopsys translate_on |
| 1199 | .rst (por_l_active_high), |
| 1200 | .rst_val (reset_req_id[14]), |
| 1201 | .csr_ld (w_ld), |
| 1202 | .csr_data (csrbus_wr_data[46]), |
| 1203 | .rw_alias (1'b1), |
| 1204 | .rw1c_alias (1'b0), |
| 1205 | .rw1s_alias (1'b0), |
| 1206 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1207 | .hw_data (imu_rds_error_log_reg_hw_write[46]), |
| 1208 | .cp (clk), |
| 1209 | .q (imu_rds_error_log_reg_csrbus_read_data[46]) |
| 1210 | ); |
| 1211 | |
| 1212 | // bit 47 |
| 1213 | csr_sw csr_sw_47 |
| 1214 | ( |
| 1215 | // synopsys translate_off |
| 1216 | .omni_ld (omni_ld), |
| 1217 | .omni_data (omni_data[47]), |
| 1218 | .omni_rw_alias (1'b1), |
| 1219 | .omni_rw1c_alias (1'b0), |
| 1220 | .omni_rw1s_alias (1'b0), |
| 1221 | // synopsys translate_on |
| 1222 | .rst (por_l_active_high), |
| 1223 | .rst_val (reset_req_id[15]), |
| 1224 | .csr_ld (w_ld), |
| 1225 | .csr_data (csrbus_wr_data[47]), |
| 1226 | .rw_alias (1'b1), |
| 1227 | .rw1c_alias (1'b0), |
| 1228 | .rw1s_alias (1'b0), |
| 1229 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1230 | .hw_data (imu_rds_error_log_reg_hw_write[47]), |
| 1231 | .cp (clk), |
| 1232 | .q (imu_rds_error_log_reg_csrbus_read_data[47]) |
| 1233 | ); |
| 1234 | |
| 1235 | // bit 48 |
| 1236 | csr_sw csr_sw_48 |
| 1237 | ( |
| 1238 | // synopsys translate_off |
| 1239 | .omni_ld (omni_ld), |
| 1240 | .omni_data (omni_data[48]), |
| 1241 | .omni_rw_alias (1'b1), |
| 1242 | .omni_rw1c_alias (1'b0), |
| 1243 | .omni_rw1s_alias (1'b0), |
| 1244 | // synopsys translate_on |
| 1245 | .rst (por_l_active_high), |
| 1246 | .rst_val (reset_length[0]), |
| 1247 | .csr_ld (w_ld), |
| 1248 | .csr_data (csrbus_wr_data[48]), |
| 1249 | .rw_alias (1'b1), |
| 1250 | .rw1c_alias (1'b0), |
| 1251 | .rw1s_alias (1'b0), |
| 1252 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1253 | .hw_data (imu_rds_error_log_reg_hw_write[48]), |
| 1254 | .cp (clk), |
| 1255 | .q (imu_rds_error_log_reg_csrbus_read_data[48]) |
| 1256 | ); |
| 1257 | |
| 1258 | // bit 49 |
| 1259 | csr_sw csr_sw_49 |
| 1260 | ( |
| 1261 | // synopsys translate_off |
| 1262 | .omni_ld (omni_ld), |
| 1263 | .omni_data (omni_data[49]), |
| 1264 | .omni_rw_alias (1'b1), |
| 1265 | .omni_rw1c_alias (1'b0), |
| 1266 | .omni_rw1s_alias (1'b0), |
| 1267 | // synopsys translate_on |
| 1268 | .rst (por_l_active_high), |
| 1269 | .rst_val (reset_length[1]), |
| 1270 | .csr_ld (w_ld), |
| 1271 | .csr_data (csrbus_wr_data[49]), |
| 1272 | .rw_alias (1'b1), |
| 1273 | .rw1c_alias (1'b0), |
| 1274 | .rw1s_alias (1'b0), |
| 1275 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1276 | .hw_data (imu_rds_error_log_reg_hw_write[49]), |
| 1277 | .cp (clk), |
| 1278 | .q (imu_rds_error_log_reg_csrbus_read_data[49]) |
| 1279 | ); |
| 1280 | |
| 1281 | // bit 50 |
| 1282 | csr_sw csr_sw_50 |
| 1283 | ( |
| 1284 | // synopsys translate_off |
| 1285 | .omni_ld (omni_ld), |
| 1286 | .omni_data (omni_data[50]), |
| 1287 | .omni_rw_alias (1'b1), |
| 1288 | .omni_rw1c_alias (1'b0), |
| 1289 | .omni_rw1s_alias (1'b0), |
| 1290 | // synopsys translate_on |
| 1291 | .rst (por_l_active_high), |
| 1292 | .rst_val (reset_length[2]), |
| 1293 | .csr_ld (w_ld), |
| 1294 | .csr_data (csrbus_wr_data[50]), |
| 1295 | .rw_alias (1'b1), |
| 1296 | .rw1c_alias (1'b0), |
| 1297 | .rw1s_alias (1'b0), |
| 1298 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1299 | .hw_data (imu_rds_error_log_reg_hw_write[50]), |
| 1300 | .cp (clk), |
| 1301 | .q (imu_rds_error_log_reg_csrbus_read_data[50]) |
| 1302 | ); |
| 1303 | |
| 1304 | // bit 51 |
| 1305 | csr_sw csr_sw_51 |
| 1306 | ( |
| 1307 | // synopsys translate_off |
| 1308 | .omni_ld (omni_ld), |
| 1309 | .omni_data (omni_data[51]), |
| 1310 | .omni_rw_alias (1'b1), |
| 1311 | .omni_rw1c_alias (1'b0), |
| 1312 | .omni_rw1s_alias (1'b0), |
| 1313 | // synopsys translate_on |
| 1314 | .rst (por_l_active_high), |
| 1315 | .rst_val (reset_length[3]), |
| 1316 | .csr_ld (w_ld), |
| 1317 | .csr_data (csrbus_wr_data[51]), |
| 1318 | .rw_alias (1'b1), |
| 1319 | .rw1c_alias (1'b0), |
| 1320 | .rw1s_alias (1'b0), |
| 1321 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1322 | .hw_data (imu_rds_error_log_reg_hw_write[51]), |
| 1323 | .cp (clk), |
| 1324 | .q (imu_rds_error_log_reg_csrbus_read_data[51]) |
| 1325 | ); |
| 1326 | |
| 1327 | // bit 52 |
| 1328 | csr_sw csr_sw_52 |
| 1329 | ( |
| 1330 | // synopsys translate_off |
| 1331 | .omni_ld (omni_ld), |
| 1332 | .omni_data (omni_data[52]), |
| 1333 | .omni_rw_alias (1'b1), |
| 1334 | .omni_rw1c_alias (1'b0), |
| 1335 | .omni_rw1s_alias (1'b0), |
| 1336 | // synopsys translate_on |
| 1337 | .rst (por_l_active_high), |
| 1338 | .rst_val (reset_length[4]), |
| 1339 | .csr_ld (w_ld), |
| 1340 | .csr_data (csrbus_wr_data[52]), |
| 1341 | .rw_alias (1'b1), |
| 1342 | .rw1c_alias (1'b0), |
| 1343 | .rw1s_alias (1'b0), |
| 1344 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1345 | .hw_data (imu_rds_error_log_reg_hw_write[52]), |
| 1346 | .cp (clk), |
| 1347 | .q (imu_rds_error_log_reg_csrbus_read_data[52]) |
| 1348 | ); |
| 1349 | |
| 1350 | // bit 53 |
| 1351 | csr_sw csr_sw_53 |
| 1352 | ( |
| 1353 | // synopsys translate_off |
| 1354 | .omni_ld (omni_ld), |
| 1355 | .omni_data (omni_data[53]), |
| 1356 | .omni_rw_alias (1'b1), |
| 1357 | .omni_rw1c_alias (1'b0), |
| 1358 | .omni_rw1s_alias (1'b0), |
| 1359 | // synopsys translate_on |
| 1360 | .rst (por_l_active_high), |
| 1361 | .rst_val (reset_length[5]), |
| 1362 | .csr_ld (w_ld), |
| 1363 | .csr_data (csrbus_wr_data[53]), |
| 1364 | .rw_alias (1'b1), |
| 1365 | .rw1c_alias (1'b0), |
| 1366 | .rw1s_alias (1'b0), |
| 1367 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1368 | .hw_data (imu_rds_error_log_reg_hw_write[53]), |
| 1369 | .cp (clk), |
| 1370 | .q (imu_rds_error_log_reg_csrbus_read_data[53]) |
| 1371 | ); |
| 1372 | |
| 1373 | // bit 54 |
| 1374 | csr_sw csr_sw_54 |
| 1375 | ( |
| 1376 | // synopsys translate_off |
| 1377 | .omni_ld (omni_ld), |
| 1378 | .omni_data (omni_data[54]), |
| 1379 | .omni_rw_alias (1'b1), |
| 1380 | .omni_rw1c_alias (1'b0), |
| 1381 | .omni_rw1s_alias (1'b0), |
| 1382 | // synopsys translate_on |
| 1383 | .rst (por_l_active_high), |
| 1384 | .rst_val (reset_length[6]), |
| 1385 | .csr_ld (w_ld), |
| 1386 | .csr_data (csrbus_wr_data[54]), |
| 1387 | .rw_alias (1'b1), |
| 1388 | .rw1c_alias (1'b0), |
| 1389 | .rw1s_alias (1'b0), |
| 1390 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1391 | .hw_data (imu_rds_error_log_reg_hw_write[54]), |
| 1392 | .cp (clk), |
| 1393 | .q (imu_rds_error_log_reg_csrbus_read_data[54]) |
| 1394 | ); |
| 1395 | |
| 1396 | // bit 55 |
| 1397 | csr_sw csr_sw_55 |
| 1398 | ( |
| 1399 | // synopsys translate_off |
| 1400 | .omni_ld (omni_ld), |
| 1401 | .omni_data (omni_data[55]), |
| 1402 | .omni_rw_alias (1'b1), |
| 1403 | .omni_rw1c_alias (1'b0), |
| 1404 | .omni_rw1s_alias (1'b0), |
| 1405 | // synopsys translate_on |
| 1406 | .rst (por_l_active_high), |
| 1407 | .rst_val (reset_length[7]), |
| 1408 | .csr_ld (w_ld), |
| 1409 | .csr_data (csrbus_wr_data[55]), |
| 1410 | .rw_alias (1'b1), |
| 1411 | .rw1c_alias (1'b0), |
| 1412 | .rw1s_alias (1'b0), |
| 1413 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1414 | .hw_data (imu_rds_error_log_reg_hw_write[55]), |
| 1415 | .cp (clk), |
| 1416 | .q (imu_rds_error_log_reg_csrbus_read_data[55]) |
| 1417 | ); |
| 1418 | |
| 1419 | // bit 56 |
| 1420 | csr_sw csr_sw_56 |
| 1421 | ( |
| 1422 | // synopsys translate_off |
| 1423 | .omni_ld (omni_ld), |
| 1424 | .omni_data (omni_data[56]), |
| 1425 | .omni_rw_alias (1'b1), |
| 1426 | .omni_rw1c_alias (1'b0), |
| 1427 | .omni_rw1s_alias (1'b0), |
| 1428 | // synopsys translate_on |
| 1429 | .rst (por_l_active_high), |
| 1430 | .rst_val (reset_length[8]), |
| 1431 | .csr_ld (w_ld), |
| 1432 | .csr_data (csrbus_wr_data[56]), |
| 1433 | .rw_alias (1'b1), |
| 1434 | .rw1c_alias (1'b0), |
| 1435 | .rw1s_alias (1'b0), |
| 1436 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1437 | .hw_data (imu_rds_error_log_reg_hw_write[56]), |
| 1438 | .cp (clk), |
| 1439 | .q (imu_rds_error_log_reg_csrbus_read_data[56]) |
| 1440 | ); |
| 1441 | |
| 1442 | // bit 57 |
| 1443 | csr_sw csr_sw_57 |
| 1444 | ( |
| 1445 | // synopsys translate_off |
| 1446 | .omni_ld (omni_ld), |
| 1447 | .omni_data (omni_data[57]), |
| 1448 | .omni_rw_alias (1'b1), |
| 1449 | .omni_rw1c_alias (1'b0), |
| 1450 | .omni_rw1s_alias (1'b0), |
| 1451 | // synopsys translate_on |
| 1452 | .rst (por_l_active_high), |
| 1453 | .rst_val (reset_length[9]), |
| 1454 | .csr_ld (w_ld), |
| 1455 | .csr_data (csrbus_wr_data[57]), |
| 1456 | .rw_alias (1'b1), |
| 1457 | .rw1c_alias (1'b0), |
| 1458 | .rw1s_alias (1'b0), |
| 1459 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1460 | .hw_data (imu_rds_error_log_reg_hw_write[57]), |
| 1461 | .cp (clk), |
| 1462 | .q (imu_rds_error_log_reg_csrbus_read_data[57]) |
| 1463 | ); |
| 1464 | |
| 1465 | // bit 58 |
| 1466 | csr_sw csr_sw_58 |
| 1467 | ( |
| 1468 | // synopsys translate_off |
| 1469 | .omni_ld (omni_ld), |
| 1470 | .omni_data (omni_data[58]), |
| 1471 | .omni_rw_alias (1'b1), |
| 1472 | .omni_rw1c_alias (1'b0), |
| 1473 | .omni_rw1s_alias (1'b0), |
| 1474 | // synopsys translate_on |
| 1475 | .rst (por_l_active_high), |
| 1476 | .rst_val (reset_type[0]), |
| 1477 | .csr_ld (w_ld), |
| 1478 | .csr_data (csrbus_wr_data[58]), |
| 1479 | .rw_alias (1'b1), |
| 1480 | .rw1c_alias (1'b0), |
| 1481 | .rw1s_alias (1'b0), |
| 1482 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1483 | .hw_data (imu_rds_error_log_reg_hw_write[58]), |
| 1484 | .cp (clk), |
| 1485 | .q (imu_rds_error_log_reg_csrbus_read_data[58]) |
| 1486 | ); |
| 1487 | |
| 1488 | // bit 59 |
| 1489 | csr_sw csr_sw_59 |
| 1490 | ( |
| 1491 | // synopsys translate_off |
| 1492 | .omni_ld (omni_ld), |
| 1493 | .omni_data (omni_data[59]), |
| 1494 | .omni_rw_alias (1'b1), |
| 1495 | .omni_rw1c_alias (1'b0), |
| 1496 | .omni_rw1s_alias (1'b0), |
| 1497 | // synopsys translate_on |
| 1498 | .rst (por_l_active_high), |
| 1499 | .rst_val (reset_type[1]), |
| 1500 | .csr_ld (w_ld), |
| 1501 | .csr_data (csrbus_wr_data[59]), |
| 1502 | .rw_alias (1'b1), |
| 1503 | .rw1c_alias (1'b0), |
| 1504 | .rw1s_alias (1'b0), |
| 1505 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1506 | .hw_data (imu_rds_error_log_reg_hw_write[59]), |
| 1507 | .cp (clk), |
| 1508 | .q (imu_rds_error_log_reg_csrbus_read_data[59]) |
| 1509 | ); |
| 1510 | |
| 1511 | // bit 60 |
| 1512 | csr_sw csr_sw_60 |
| 1513 | ( |
| 1514 | // synopsys translate_off |
| 1515 | .omni_ld (omni_ld), |
| 1516 | .omni_data (omni_data[60]), |
| 1517 | .omni_rw_alias (1'b1), |
| 1518 | .omni_rw1c_alias (1'b0), |
| 1519 | .omni_rw1s_alias (1'b0), |
| 1520 | // synopsys translate_on |
| 1521 | .rst (por_l_active_high), |
| 1522 | .rst_val (reset_type[2]), |
| 1523 | .csr_ld (w_ld), |
| 1524 | .csr_data (csrbus_wr_data[60]), |
| 1525 | .rw_alias (1'b1), |
| 1526 | .rw1c_alias (1'b0), |
| 1527 | .rw1s_alias (1'b0), |
| 1528 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1529 | .hw_data (imu_rds_error_log_reg_hw_write[60]), |
| 1530 | .cp (clk), |
| 1531 | .q (imu_rds_error_log_reg_csrbus_read_data[60]) |
| 1532 | ); |
| 1533 | |
| 1534 | // bit 61 |
| 1535 | csr_sw csr_sw_61 |
| 1536 | ( |
| 1537 | // synopsys translate_off |
| 1538 | .omni_ld (omni_ld), |
| 1539 | .omni_data (omni_data[61]), |
| 1540 | .omni_rw_alias (1'b1), |
| 1541 | .omni_rw1c_alias (1'b0), |
| 1542 | .omni_rw1s_alias (1'b0), |
| 1543 | // synopsys translate_on |
| 1544 | .rst (por_l_active_high), |
| 1545 | .rst_val (reset_type[3]), |
| 1546 | .csr_ld (w_ld), |
| 1547 | .csr_data (csrbus_wr_data[61]), |
| 1548 | .rw_alias (1'b1), |
| 1549 | .rw1c_alias (1'b0), |
| 1550 | .rw1s_alias (1'b0), |
| 1551 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1552 | .hw_data (imu_rds_error_log_reg_hw_write[61]), |
| 1553 | .cp (clk), |
| 1554 | .q (imu_rds_error_log_reg_csrbus_read_data[61]) |
| 1555 | ); |
| 1556 | |
| 1557 | // bit 62 |
| 1558 | csr_sw csr_sw_62 |
| 1559 | ( |
| 1560 | // synopsys translate_off |
| 1561 | .omni_ld (omni_ld), |
| 1562 | .omni_data (omni_data[62]), |
| 1563 | .omni_rw_alias (1'b1), |
| 1564 | .omni_rw1c_alias (1'b0), |
| 1565 | .omni_rw1s_alias (1'b0), |
| 1566 | // synopsys translate_on |
| 1567 | .rst (por_l_active_high), |
| 1568 | .rst_val (reset_type[4]), |
| 1569 | .csr_ld (w_ld), |
| 1570 | .csr_data (csrbus_wr_data[62]), |
| 1571 | .rw_alias (1'b1), |
| 1572 | .rw1c_alias (1'b0), |
| 1573 | .rw1s_alias (1'b0), |
| 1574 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1575 | .hw_data (imu_rds_error_log_reg_hw_write[62]), |
| 1576 | .cp (clk), |
| 1577 | .q (imu_rds_error_log_reg_csrbus_read_data[62]) |
| 1578 | ); |
| 1579 | |
| 1580 | // bit 63 |
| 1581 | csr_sw csr_sw_63 |
| 1582 | ( |
| 1583 | // synopsys translate_off |
| 1584 | .omni_ld (omni_ld), |
| 1585 | .omni_data (omni_data[63]), |
| 1586 | .omni_rw_alias (1'b1), |
| 1587 | .omni_rw1c_alias (1'b0), |
| 1588 | .omni_rw1s_alias (1'b0), |
| 1589 | // synopsys translate_on |
| 1590 | .rst (por_l_active_high), |
| 1591 | .rst_val (reset_type[5]), |
| 1592 | .csr_ld (w_ld), |
| 1593 | .csr_data (csrbus_wr_data[63]), |
| 1594 | .rw_alias (1'b1), |
| 1595 | .rw1c_alias (1'b0), |
| 1596 | .rw1s_alias (1'b0), |
| 1597 | .hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1598 | .hw_data (imu_rds_error_log_reg_hw_write[63]), |
| 1599 | .cp (clk), |
| 1600 | .q (imu_rds_error_log_reg_csrbus_read_data[63]) |
| 1601 | ); |
| 1602 | |
| 1603 | |
| 1604 | endmodule // dmu_imu_ics_csr_imu_rds_error_log_reg_entry |