| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_default_grp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_default_grp |
| 36 | ( |
| 37 | clk, |
| 38 | imu_error_log_en_reg_spare_log_en_hw_read, |
| 39 | imu_error_log_en_reg_eq_over_log_en_hw_read, |
| 40 | imu_error_log_en_reg_eq_not_en_log_en_hw_read, |
| 41 | imu_error_log_en_reg_msi_mal_err_log_en_hw_read, |
| 42 | imu_error_log_en_reg_msi_par_err_log_en_hw_read, |
| 43 | imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read, |
| 44 | imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read, |
| 45 | imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read, |
| 46 | imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read, |
| 47 | imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read, |
| 48 | imu_error_log_en_reg_msi_not_en_log_en_hw_read, |
| 49 | imu_error_log_en_reg_select_pulse, |
| 50 | imu_int_en_reg_spare_s_int_en_hw_read, |
| 51 | imu_int_en_reg_eq_over_s_int_en_hw_read, |
| 52 | imu_int_en_reg_eq_not_en_s_int_en_hw_read, |
| 53 | imu_int_en_reg_msi_mal_err_s_int_en_hw_read, |
| 54 | imu_int_en_reg_msi_par_err_s_int_en_hw_read, |
| 55 | imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read, |
| 56 | imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read, |
| 57 | imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read, |
| 58 | imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read, |
| 59 | imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read, |
| 60 | imu_int_en_reg_msi_not_en_s_int_en_hw_read, |
| 61 | imu_int_en_reg_spare_p_int_en_hw_read, |
| 62 | imu_int_en_reg_eq_over_p_int_en_hw_read, |
| 63 | imu_int_en_reg_eq_not_en_p_int_en_hw_read, |
| 64 | imu_int_en_reg_msi_mal_err_p_int_en_hw_read, |
| 65 | imu_int_en_reg_msi_par_err_p_int_en_hw_read, |
| 66 | imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read, |
| 67 | imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read, |
| 68 | imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read, |
| 69 | imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read, |
| 70 | imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read, |
| 71 | imu_int_en_reg_msi_not_en_p_int_en_hw_read, |
| 72 | imu_int_en_reg_select_pulse, |
| 73 | imu_enabled_error_status_reg_select, |
| 74 | imu_enabled_error_status_reg_ext_read_data, |
| 75 | imu_logged_error_status_reg_spare_s_hw_set, |
| 76 | imu_logged_error_status_reg_spare_s_hw_read, |
| 77 | imu_logged_error_status_reg_eq_over_s_hw_set, |
| 78 | imu_logged_error_status_reg_eq_over_s_hw_read, |
| 79 | imu_logged_error_status_reg_eq_not_en_s_hw_set, |
| 80 | imu_logged_error_status_reg_eq_not_en_s_hw_read, |
| 81 | imu_logged_error_status_reg_msi_mal_err_s_hw_set, |
| 82 | imu_logged_error_status_reg_msi_mal_err_s_hw_read, |
| 83 | imu_logged_error_status_reg_msi_par_err_s_hw_set, |
| 84 | imu_logged_error_status_reg_msi_par_err_s_hw_read, |
| 85 | imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set, |
| 86 | imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read, |
| 87 | imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set, |
| 88 | imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read, |
| 89 | imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set, |
| 90 | imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read, |
| 91 | imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set, |
| 92 | imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read, |
| 93 | imu_logged_error_status_reg_cor_mes_not_en_s_hw_set, |
| 94 | imu_logged_error_status_reg_cor_mes_not_en_s_hw_read, |
| 95 | imu_logged_error_status_reg_msi_not_en_s_hw_set, |
| 96 | imu_logged_error_status_reg_msi_not_en_s_hw_read, |
| 97 | imu_logged_error_status_reg_spare_p_hw_set, |
| 98 | imu_logged_error_status_reg_spare_p_hw_read, |
| 99 | imu_logged_error_status_reg_eq_over_p_hw_set, |
| 100 | imu_logged_error_status_reg_eq_over_p_hw_read, |
| 101 | imu_logged_error_status_reg_eq_not_en_p_hw_set, |
| 102 | imu_logged_error_status_reg_eq_not_en_p_hw_read, |
| 103 | imu_logged_error_status_reg_msi_mal_err_p_hw_set, |
| 104 | imu_logged_error_status_reg_msi_mal_err_p_hw_read, |
| 105 | imu_logged_error_status_reg_msi_par_err_p_hw_set, |
| 106 | imu_logged_error_status_reg_msi_par_err_p_hw_read, |
| 107 | imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set, |
| 108 | imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read, |
| 109 | imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set, |
| 110 | imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read, |
| 111 | imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set, |
| 112 | imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read, |
| 113 | imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set, |
| 114 | imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read, |
| 115 | imu_logged_error_status_reg_cor_mes_not_en_p_hw_set, |
| 116 | imu_logged_error_status_reg_cor_mes_not_en_p_hw_read, |
| 117 | imu_logged_error_status_reg_msi_not_en_p_hw_set, |
| 118 | imu_logged_error_status_reg_msi_not_en_p_hw_read, |
| 119 | imu_logged_error_status_reg_select_pulse, |
| 120 | imu_rds_error_log_reg_hw_ld, |
| 121 | imu_rds_error_log_reg_hw_write, |
| 122 | imu_rds_error_log_reg_select_pulse, |
| 123 | imu_scs_error_log_reg_hw_ld, |
| 124 | imu_scs_error_log_reg_hw_write, |
| 125 | imu_scs_error_log_reg_select_pulse, |
| 126 | imu_eqs_error_log_reg_hw_ld, |
| 127 | imu_eqs_error_log_reg_hw_write, |
| 128 | imu_eqs_error_log_reg_select_pulse, |
| 129 | dmc_interrupt_mask_reg_dmc_hw_read, |
| 130 | dmc_interrupt_mask_reg_debug_trig_en_hw_read, |
| 131 | dmc_interrupt_mask_reg_mmu_hw_read, |
| 132 | dmc_interrupt_mask_reg_imu_hw_read, |
| 133 | dmc_interrupt_mask_reg_select_pulse, |
| 134 | dmc_interrupt_status_reg_select, |
| 135 | dmc_interrupt_status_reg_ext_read_data, |
| 136 | imu_perf_cntrl_sel1_hw_read, |
| 137 | imu_perf_cntrl_sel0_hw_read, |
| 138 | imu_perf_cntrl_select_pulse, |
| 139 | imu_perf_cnt0_cnt_hw_write, |
| 140 | imu_perf_cnt0_cnt_hw_read, |
| 141 | imu_perf_cnt0_select_pulse, |
| 142 | imu_perf_cnt1_cnt_hw_write, |
| 143 | imu_perf_cnt1_cnt_hw_read, |
| 144 | imu_perf_cnt1_select_pulse, |
| 145 | msi_32_addr_reg_addr_hw_read, |
| 146 | msi_32_addr_reg_select_pulse, |
| 147 | msi_64_addr_reg_addr_hw_read, |
| 148 | msi_64_addr_reg_select_pulse, |
| 149 | mem_64_pcie_offset_reg_addr_hw_read, |
| 150 | mem_64_pcie_offset_reg_spare_control_load_7_hw_ld, |
| 151 | mem_64_pcie_offset_reg_spare_control_load_7_hw_write, |
| 152 | mem_64_pcie_offset_reg_spare_control_load_7_hw_read, |
| 153 | mem_64_pcie_offset_reg_spare_control_load_6_hw_ld, |
| 154 | mem_64_pcie_offset_reg_spare_control_load_6_hw_write, |
| 155 | mem_64_pcie_offset_reg_spare_control_load_6_hw_read, |
| 156 | mem_64_pcie_offset_reg_spare_control_load_5_hw_ld, |
| 157 | mem_64_pcie_offset_reg_spare_control_load_5_hw_write, |
| 158 | mem_64_pcie_offset_reg_spare_control_load_5_hw_read, |
| 159 | mem_64_pcie_offset_reg_spare_control_load_4_hw_ld, |
| 160 | mem_64_pcie_offset_reg_spare_control_load_4_hw_write, |
| 161 | mem_64_pcie_offset_reg_spare_control_load_4_hw_read, |
| 162 | mem_64_pcie_offset_reg_spare_control_load_3_hw_ld, |
| 163 | mem_64_pcie_offset_reg_spare_control_load_3_hw_write, |
| 164 | mem_64_pcie_offset_reg_spare_control_load_3_hw_read, |
| 165 | mem_64_pcie_offset_reg_spare_control_load_2_hw_ld, |
| 166 | mem_64_pcie_offset_reg_spare_control_load_2_hw_write, |
| 167 | mem_64_pcie_offset_reg_spare_control_load_2_hw_read, |
| 168 | mem_64_pcie_offset_reg_spare_control_load_1_hw_ld, |
| 169 | mem_64_pcie_offset_reg_spare_control_load_1_hw_write, |
| 170 | mem_64_pcie_offset_reg_spare_control_load_1_hw_read, |
| 171 | mem_64_pcie_offset_reg_spare_control_load_0_hw_ld, |
| 172 | mem_64_pcie_offset_reg_spare_control_load_0_hw_write, |
| 173 | mem_64_pcie_offset_reg_spare_control_load_0_hw_read, |
| 174 | mem_64_pcie_offset_reg_spare_control_hw_write, |
| 175 | mem_64_pcie_offset_reg_spare_control_hw_read, |
| 176 | mem_64_pcie_offset_reg_spare_status_hw_read, |
| 177 | mem_64_pcie_offset_reg_select_pulse, |
| 178 | imu_logged_error_status_reg_rw1c_alias, |
| 179 | imu_logged_error_status_reg_rw1s_alias, |
| 180 | rst_l, |
| 181 | por_l, |
| 182 | daemon_csrbus_wr_in, |
| 183 | daemon_csrbus_wr_data_in, |
| 184 | read_data_0_out |
| 185 | ); |
| 186 | |
| 187 | //==================================================== |
| 188 | // Polarity declarations |
| 189 | //==================================================== |
| 190 | input clk; // Clock signal |
| 191 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read; |
| 192 | // This signal provides the current value of |
| 193 | // imu_error_log_en_reg_spare_log_en. |
| 194 | output imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the |
| 195 | // current value of |
| 196 | // imu_error_log_en_reg_eq_over_log_en. |
| 197 | output imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides |
| 198 | // the current value of |
| 199 | // imu_error_log_en_reg_eq_not_en_log_en. |
| 200 | output imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides |
| 201 | // the current value of |
| 202 | // imu_error_log_en_reg_msi_mal_err_log_en. |
| 203 | output imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides |
| 204 | // the current value of |
| 205 | // imu_error_log_en_reg_msi_par_err_log_en. |
| 206 | output imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal |
| 207 | // provides the |
| 208 | // current value |
| 209 | // of |
| 210 | // imu_error_log_en_reg_pmeack_mes_not_en_log_en. |
| 211 | output imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal |
| 212 | // provides the |
| 213 | // current value |
| 214 | // of |
| 215 | // imu_error_log_en_reg_pmpme_mes_not_en_log_en. |
| 216 | output imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal |
| 217 | // provides the |
| 218 | // current value |
| 219 | // of |
| 220 | // imu_error_log_en_reg_fatal_mes_not_en_log_en. |
| 221 | output imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal |
| 222 | // provides the |
| 223 | // current |
| 224 | // value of |
| 225 | // imu_error_log_en_reg_nonfatal_mes_not_en_log_en. |
| 226 | output imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal |
| 227 | // provides the |
| 228 | // current value of |
| 229 | // imu_error_log_en_reg_cor_mes_not_en_log_en. |
| 230 | output imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides |
| 231 | // the current value of |
| 232 | // imu_error_log_en_reg_msi_not_en_log_en. |
| 233 | input imu_error_log_en_reg_select_pulse; // select |
| 234 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC] imu_int_en_reg_spare_s_int_en_hw_read; |
| 235 | // This signal provides the current value of imu_int_en_reg_spare_s_int_en. |
| 236 | output imu_int_en_reg_eq_over_s_int_en_hw_read; // This signal provides the |
| 237 | // current value of |
| 238 | // imu_int_en_reg_eq_over_s_int_en. |
| 239 | output imu_int_en_reg_eq_not_en_s_int_en_hw_read; // This signal provides the |
| 240 | // current value of |
| 241 | // imu_int_en_reg_eq_not_en_s_int_en. |
| 242 | output imu_int_en_reg_msi_mal_err_s_int_en_hw_read; // This signal provides the |
| 243 | // current value of |
| 244 | // imu_int_en_reg_msi_mal_err_s_int_en. |
| 245 | output imu_int_en_reg_msi_par_err_s_int_en_hw_read; // This signal provides the |
| 246 | // current value of |
| 247 | // imu_int_en_reg_msi_par_err_s_int_en. |
| 248 | output imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read; // This signal |
| 249 | // provides the |
| 250 | // current value of |
| 251 | // imu_int_en_reg_pmeack_mes_not_en_s_int_en. |
| 252 | output imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read; // This signal |
| 253 | // provides the |
| 254 | // current value of |
| 255 | // imu_int_en_reg_pmpme_mes_not_en_s_int_en. |
| 256 | output imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read; // This signal |
| 257 | // provides the |
| 258 | // current value of |
| 259 | // imu_int_en_reg_fatal_mes_not_en_s_int_en. |
| 260 | output imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read; // This signal |
| 261 | // provides the |
| 262 | // current value of |
| 263 | // imu_int_en_reg_nonfatal_mes_not_en_s_int_en. |
| 264 | output imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read; // This signal provides |
| 265 | // the current value of |
| 266 | // imu_int_en_reg_cor_mes_not_en_s_int_en. |
| 267 | output imu_int_en_reg_msi_not_en_s_int_en_hw_read; // This signal provides the |
| 268 | // current value of |
| 269 | // imu_int_en_reg_msi_not_en_s_int_en. |
| 270 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC] imu_int_en_reg_spare_p_int_en_hw_read; |
| 271 | // This signal provides the current value of imu_int_en_reg_spare_p_int_en. |
| 272 | output imu_int_en_reg_eq_over_p_int_en_hw_read; // This signal provides the |
| 273 | // current value of |
| 274 | // imu_int_en_reg_eq_over_p_int_en. |
| 275 | output imu_int_en_reg_eq_not_en_p_int_en_hw_read; // This signal provides the |
| 276 | // current value of |
| 277 | // imu_int_en_reg_eq_not_en_p_int_en. |
| 278 | output imu_int_en_reg_msi_mal_err_p_int_en_hw_read; // This signal provides the |
| 279 | // current value of |
| 280 | // imu_int_en_reg_msi_mal_err_p_int_en. |
| 281 | output imu_int_en_reg_msi_par_err_p_int_en_hw_read; // This signal provides the |
| 282 | // current value of |
| 283 | // imu_int_en_reg_msi_par_err_p_int_en. |
| 284 | output imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read; // This signal |
| 285 | // provides the |
| 286 | // current value of |
| 287 | // imu_int_en_reg_pmeack_mes_not_en_p_int_en. |
| 288 | output imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read; // This signal |
| 289 | // provides the |
| 290 | // current value of |
| 291 | // imu_int_en_reg_pmpme_mes_not_en_p_int_en. |
| 292 | output imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read; // This signal |
| 293 | // provides the |
| 294 | // current value of |
| 295 | // imu_int_en_reg_fatal_mes_not_en_p_int_en. |
| 296 | output imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read; // This signal |
| 297 | // provides the |
| 298 | // current value of |
| 299 | // imu_int_en_reg_nonfatal_mes_not_en_p_int_en. |
| 300 | output imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read; // This signal provides |
| 301 | // the current value of |
| 302 | // imu_int_en_reg_cor_mes_not_en_p_int_en. |
| 303 | output imu_int_en_reg_msi_not_en_p_int_en_hw_read; // This signal provides the |
| 304 | // current value of |
| 305 | // imu_int_en_reg_msi_not_en_p_int_en. |
| 306 | input imu_int_en_reg_select_pulse; // select |
| 307 | input imu_enabled_error_status_reg_select; // select |
| 308 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] imu_enabled_error_status_reg_ext_read_data; |
| 309 | // Read Data |
| 310 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC] |
| 311 | imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for |
| 312 | // imu_logged_error_status_reg_spare_s. |
| 313 | // When set |
| 314 | // imu_logged_error_status_reg |
| 315 | // will be set to one. |
| 316 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC] |
| 317 | imu_logged_error_status_reg_spare_s_hw_read; // This signal provides the |
| 318 | // current value of |
| 319 | // imu_logged_error_status_reg_spare_s. |
| 320 | input imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for |
| 321 | // imu_logged_error_status_reg_eq_over_s. |
| 322 | // When set |
| 323 | // imu_logged_error_status_reg |
| 324 | // will be set to one. |
| 325 | output imu_logged_error_status_reg_eq_over_s_hw_read; // This signal provides |
| 326 | // the current value of |
| 327 | // imu_logged_error_status_reg_eq_over_s. |
| 328 | input imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal |
| 329 | // for |
| 330 | // imu_logged_error_status_reg_eq_not_en_s. |
| 331 | // When set |
| 332 | // imu_logged_error_status_reg |
| 333 | // will be set to one. |
| 334 | output imu_logged_error_status_reg_eq_not_en_s_hw_read; // This signal provides |
| 335 | // the current value of |
| 336 | // imu_logged_error_status_reg_eq_not_en_s. |
| 337 | input imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal |
| 338 | // for |
| 339 | // imu_logged_error_status_reg_msi_mal_err_s. |
| 340 | // When set |
| 341 | // imu_logged_error_status_reg |
| 342 | // will be set to one. |
| 343 | output imu_logged_error_status_reg_msi_mal_err_s_hw_read; // This signal |
| 344 | // provides the |
| 345 | // current value of |
| 346 | // imu_logged_error_status_reg_msi_mal_err_s. |
| 347 | input imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal |
| 348 | // for |
| 349 | // imu_logged_error_status_reg_msi_par_err_s. |
| 350 | // When set |
| 351 | // imu_logged_error_status_reg |
| 352 | // will be set to one. |
| 353 | output imu_logged_error_status_reg_msi_par_err_s_hw_read; // This signal |
| 354 | // provides the |
| 355 | // current value of |
| 356 | // imu_logged_error_status_reg_msi_par_err_s. |
| 357 | input imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set |
| 358 | // signal for |
| 359 | // imu_logged_error_status_reg_pmeack_mes_not_en_s. |
| 360 | // When set |
| 361 | // imu_logged_error_status_reg |
| 362 | // will be set |
| 363 | // to one. |
| 364 | output imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read; // This signal |
| 365 | // provides the |
| 366 | // current |
| 367 | // value of |
| 368 | // imu_logged_error_status_reg_pmeack_mes_not_en_s. |
| 369 | input imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set |
| 370 | // signal for |
| 371 | // imu_logged_error_status_reg_pmpme_mes_not_en_s. |
| 372 | // When set |
| 373 | // imu_logged_error_status_reg |
| 374 | // will be set to |
| 375 | // one. |
| 376 | output imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read; // This signal |
| 377 | // provides the |
| 378 | // current value |
| 379 | // of |
| 380 | // imu_logged_error_status_reg_pmpme_mes_not_en_s. |
| 381 | input imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set |
| 382 | // signal for |
| 383 | // imu_logged_error_status_reg_fatal_mes_not_en_s. |
| 384 | // When set |
| 385 | // imu_logged_error_status_reg |
| 386 | // will be set to |
| 387 | // one. |
| 388 | output imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read; // This signal |
| 389 | // provides the |
| 390 | // current value |
| 391 | // of |
| 392 | // imu_logged_error_status_reg_fatal_mes_not_en_s. |
| 393 | input imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware |
| 394 | // set signal |
| 395 | // for |
| 396 | // imu_logged_error_status_reg_nonfatal_mes_not_en_s. |
| 397 | // When set |
| 398 | // imu_logged_error_status_reg |
| 399 | // will be set |
| 400 | // to one. |
| 401 | output imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read; |
| 402 | // This signal provides the current value of |
| 403 | // imu_logged_error_status_reg_nonfatal_mes_not_en_s. |
| 404 | input imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set |
| 405 | // signal for |
| 406 | // imu_logged_error_status_reg_cor_mes_not_en_s. |
| 407 | // When set |
| 408 | // imu_logged_error_status_reg |
| 409 | // will be set to |
| 410 | // one. |
| 411 | output imu_logged_error_status_reg_cor_mes_not_en_s_hw_read; // This signal |
| 412 | // provides the |
| 413 | // current value |
| 414 | // of |
| 415 | // imu_logged_error_status_reg_cor_mes_not_en_s. |
| 416 | input imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal |
| 417 | // for |
| 418 | // imu_logged_error_status_reg_msi_not_en_s. |
| 419 | // When set |
| 420 | // imu_logged_error_status_reg |
| 421 | // will be set to one. |
| 422 | output imu_logged_error_status_reg_msi_not_en_s_hw_read; // This signal |
| 423 | // provides the |
| 424 | // current value of |
| 425 | // imu_logged_error_status_reg_msi_not_en_s. |
| 426 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC] |
| 427 | imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for |
| 428 | // imu_logged_error_status_reg_spare_p. |
| 429 | // When set |
| 430 | // imu_logged_error_status_reg |
| 431 | // will be set to one. |
| 432 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC] |
| 433 | imu_logged_error_status_reg_spare_p_hw_read; // This signal provides the |
| 434 | // current value of |
| 435 | // imu_logged_error_status_reg_spare_p. |
| 436 | input imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for |
| 437 | // imu_logged_error_status_reg_eq_over_p. |
| 438 | // When set |
| 439 | // imu_logged_error_status_reg |
| 440 | // will be set to one. |
| 441 | output imu_logged_error_status_reg_eq_over_p_hw_read; // This signal provides |
| 442 | // the current value of |
| 443 | // imu_logged_error_status_reg_eq_over_p. |
| 444 | input imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal |
| 445 | // for |
| 446 | // imu_logged_error_status_reg_eq_not_en_p. |
| 447 | // When set |
| 448 | // imu_logged_error_status_reg |
| 449 | // will be set to one. |
| 450 | output imu_logged_error_status_reg_eq_not_en_p_hw_read; // This signal provides |
| 451 | // the current value of |
| 452 | // imu_logged_error_status_reg_eq_not_en_p. |
| 453 | input imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal |
| 454 | // for |
| 455 | // imu_logged_error_status_reg_msi_mal_err_p. |
| 456 | // When set |
| 457 | // imu_logged_error_status_reg |
| 458 | // will be set to one. |
| 459 | output imu_logged_error_status_reg_msi_mal_err_p_hw_read; // This signal |
| 460 | // provides the |
| 461 | // current value of |
| 462 | // imu_logged_error_status_reg_msi_mal_err_p. |
| 463 | input imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal |
| 464 | // for |
| 465 | // imu_logged_error_status_reg_msi_par_err_p. |
| 466 | // When set |
| 467 | // imu_logged_error_status_reg |
| 468 | // will be set to one. |
| 469 | output imu_logged_error_status_reg_msi_par_err_p_hw_read; // This signal |
| 470 | // provides the |
| 471 | // current value of |
| 472 | // imu_logged_error_status_reg_msi_par_err_p. |
| 473 | input imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set |
| 474 | // signal for |
| 475 | // imu_logged_error_status_reg_pmeack_mes_not_en_p. |
| 476 | // When set |
| 477 | // imu_logged_error_status_reg |
| 478 | // will be set |
| 479 | // to one. |
| 480 | output imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read; // This signal |
| 481 | // provides the |
| 482 | // current |
| 483 | // value of |
| 484 | // imu_logged_error_status_reg_pmeack_mes_not_en_p. |
| 485 | input imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set |
| 486 | // signal for |
| 487 | // imu_logged_error_status_reg_pmpme_mes_not_en_p. |
| 488 | // When set |
| 489 | // imu_logged_error_status_reg |
| 490 | // will be set to |
| 491 | // one. |
| 492 | output imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read; // This signal |
| 493 | // provides the |
| 494 | // current value |
| 495 | // of |
| 496 | // imu_logged_error_status_reg_pmpme_mes_not_en_p. |
| 497 | input imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set |
| 498 | // signal for |
| 499 | // imu_logged_error_status_reg_fatal_mes_not_en_p. |
| 500 | // When set |
| 501 | // imu_logged_error_status_reg |
| 502 | // will be set to |
| 503 | // one. |
| 504 | output imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read; // This signal |
| 505 | // provides the |
| 506 | // current value |
| 507 | // of |
| 508 | // imu_logged_error_status_reg_fatal_mes_not_en_p. |
| 509 | input imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware |
| 510 | // set signal |
| 511 | // for |
| 512 | // imu_logged_error_status_reg_nonfatal_mes_not_en_p. |
| 513 | // When set |
| 514 | // imu_logged_error_status_reg |
| 515 | // will be set |
| 516 | // to one. |
| 517 | output imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read; |
| 518 | // This signal provides the current value of |
| 519 | // imu_logged_error_status_reg_nonfatal_mes_not_en_p. |
| 520 | input imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set |
| 521 | // signal for |
| 522 | // imu_logged_error_status_reg_cor_mes_not_en_p. |
| 523 | // When set |
| 524 | // imu_logged_error_status_reg |
| 525 | // will be set to |
| 526 | // one. |
| 527 | output imu_logged_error_status_reg_cor_mes_not_en_p_hw_read; // This signal |
| 528 | // provides the |
| 529 | // current value |
| 530 | // of |
| 531 | // imu_logged_error_status_reg_cor_mes_not_en_p. |
| 532 | input imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal |
| 533 | // for |
| 534 | // imu_logged_error_status_reg_msi_not_en_p. |
| 535 | // When set |
| 536 | // imu_logged_error_status_reg |
| 537 | // will be set to one. |
| 538 | output imu_logged_error_status_reg_msi_not_en_p_hw_read; // This signal |
| 539 | // provides the |
| 540 | // current value of |
| 541 | // imu_logged_error_status_reg_msi_not_en_p. |
| 542 | input imu_logged_error_status_reg_select_pulse; // select |
| 543 | input imu_rds_error_log_reg_hw_ld; // Hardware load enable for |
| 544 | // imu_rds_error_log_reg. When set, <hw |
| 545 | // write signal> will be loaded into |
| 546 | // imu_rds_error_log_reg. |
| 547 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_hw_write; |
| 548 | // data bus for hw loading of imu_rds_error_log_reg. |
| 549 | input imu_rds_error_log_reg_select_pulse; // select |
| 550 | input imu_scs_error_log_reg_hw_ld; // Hardware load enable for |
| 551 | // imu_scs_error_log_reg. When set, <hw |
| 552 | // write signal> will be loaded into |
| 553 | // imu_scs_error_log_reg. |
| 554 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_hw_write; |
| 555 | // data bus for hw loading of imu_scs_error_log_reg. |
| 556 | input imu_scs_error_log_reg_select_pulse; // select |
| 557 | input imu_eqs_error_log_reg_hw_ld; // Hardware load enable for |
| 558 | // imu_eqs_error_log_reg. When set, <hw |
| 559 | // write signal> will be loaded into |
| 560 | // imu_eqs_error_log_reg. |
| 561 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_hw_write; |
| 562 | // data bus for hw loading of imu_eqs_error_log_reg. |
| 563 | input imu_eqs_error_log_reg_select_pulse; // select |
| 564 | output dmc_interrupt_mask_reg_dmc_hw_read; // This signal provides the current |
| 565 | // value of |
| 566 | // dmc_interrupt_mask_reg_dmc. |
| 567 | output dmc_interrupt_mask_reg_debug_trig_en_hw_read; // This signal provides |
| 568 | // the current value of |
| 569 | // dmc_interrupt_mask_reg_debug_trig_en. |
| 570 | output dmc_interrupt_mask_reg_mmu_hw_read; // This signal provides the current |
| 571 | // value of |
| 572 | // dmc_interrupt_mask_reg_mmu. |
| 573 | output dmc_interrupt_mask_reg_imu_hw_read; // This signal provides the current |
| 574 | // value of |
| 575 | // dmc_interrupt_mask_reg_imu. |
| 576 | input dmc_interrupt_mask_reg_select_pulse; // select |
| 577 | input dmc_interrupt_status_reg_select; // select |
| 578 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] dmc_interrupt_status_reg_ext_read_data; |
| 579 | // Read Data |
| 580 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC] imu_perf_cntrl_sel1_hw_read; |
| 581 | // This signal provides the current value of imu_perf_cntrl_sel1. |
| 582 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC] imu_perf_cntrl_sel0_hw_read; |
| 583 | // This signal provides the current value of imu_perf_cntrl_sel0. |
| 584 | input imu_perf_cntrl_select_pulse; // select |
| 585 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_write; |
| 586 | // data bus for hw loading of imu_perf_cnt0_cnt. |
| 587 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_read; |
| 588 | // This signal provides the current value of imu_perf_cnt0_cnt. |
| 589 | input imu_perf_cnt0_select_pulse; // select |
| 590 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_write; |
| 591 | // data bus for hw loading of imu_perf_cnt1_cnt. |
| 592 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_read; |
| 593 | // This signal provides the current value of imu_perf_cnt1_cnt. |
| 594 | input imu_perf_cnt1_select_pulse; // select |
| 595 | output [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_INT_SLC] msi_32_addr_reg_addr_hw_read; |
| 596 | // This signal provides the current value of msi_32_addr_reg_addr. |
| 597 | input msi_32_addr_reg_select_pulse; // select |
| 598 | output [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_INT_SLC] msi_64_addr_reg_addr_hw_read; |
| 599 | // This signal provides the current value of msi_64_addr_reg_addr. |
| 600 | input msi_64_addr_reg_select_pulse; // select |
| 601 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC] mem_64_pcie_offset_reg_addr_hw_read; |
| 602 | // This signal provides the current value of mem_64_pcie_offset_reg_addr. |
| 603 | input mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load |
| 604 | // enable for |
| 605 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 606 | // When set, <hw |
| 607 | // write signal> |
| 608 | // will be loaded |
| 609 | // into |
| 610 | // mem_64_pcie_offset_reg. |
| 611 | input mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw |
| 612 | // loading of |
| 613 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 614 | output mem_64_pcie_offset_reg_spare_control_load_7_hw_read; // This signal |
| 615 | // provides the |
| 616 | // current value of |
| 617 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 618 | input mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load |
| 619 | // enable for |
| 620 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 621 | // When set, <hw |
| 622 | // write signal> |
| 623 | // will be loaded |
| 624 | // into |
| 625 | // mem_64_pcie_offset_reg. |
| 626 | input mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw |
| 627 | // loading of |
| 628 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 629 | output mem_64_pcie_offset_reg_spare_control_load_6_hw_read; // This signal |
| 630 | // provides the |
| 631 | // current value of |
| 632 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 633 | input mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load |
| 634 | // enable for |
| 635 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 636 | // When set, <hw |
| 637 | // write signal> |
| 638 | // will be loaded |
| 639 | // into |
| 640 | // mem_64_pcie_offset_reg. |
| 641 | input mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw |
| 642 | // loading of |
| 643 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 644 | output mem_64_pcie_offset_reg_spare_control_load_5_hw_read; // This signal |
| 645 | // provides the |
| 646 | // current value of |
| 647 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 648 | input mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load |
| 649 | // enable for |
| 650 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 651 | // When set, <hw |
| 652 | // write signal> |
| 653 | // will be loaded |
| 654 | // into |
| 655 | // mem_64_pcie_offset_reg. |
| 656 | input mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw |
| 657 | // loading of |
| 658 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 659 | output mem_64_pcie_offset_reg_spare_control_load_4_hw_read; // This signal |
| 660 | // provides the |
| 661 | // current value of |
| 662 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 663 | input mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load |
| 664 | // enable for |
| 665 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 666 | // When set, <hw |
| 667 | // write signal> |
| 668 | // will be loaded |
| 669 | // into |
| 670 | // mem_64_pcie_offset_reg. |
| 671 | input mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw |
| 672 | // loading of |
| 673 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 674 | output mem_64_pcie_offset_reg_spare_control_load_3_hw_read; // This signal |
| 675 | // provides the |
| 676 | // current value of |
| 677 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 678 | input mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load |
| 679 | // enable for |
| 680 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 681 | // When set, <hw |
| 682 | // write signal> |
| 683 | // will be loaded |
| 684 | // into |
| 685 | // mem_64_pcie_offset_reg. |
| 686 | input mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw |
| 687 | // loading of |
| 688 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 689 | output mem_64_pcie_offset_reg_spare_control_load_2_hw_read; // This signal |
| 690 | // provides the |
| 691 | // current value of |
| 692 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 693 | input mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load |
| 694 | // enable for |
| 695 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 696 | // When set, <hw |
| 697 | // write signal> |
| 698 | // will be loaded |
| 699 | // into |
| 700 | // mem_64_pcie_offset_reg. |
| 701 | input mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw |
| 702 | // loading of |
| 703 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 704 | output mem_64_pcie_offset_reg_spare_control_load_1_hw_read; // This signal |
| 705 | // provides the |
| 706 | // current value of |
| 707 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 708 | input mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load |
| 709 | // enable for |
| 710 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 711 | // When set, <hw |
| 712 | // write signal> |
| 713 | // will be loaded |
| 714 | // into |
| 715 | // mem_64_pcie_offset_reg. |
| 716 | input mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw |
| 717 | // loading of |
| 718 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 719 | output mem_64_pcie_offset_reg_spare_control_load_0_hw_read; // This signal |
| 720 | // provides the |
| 721 | // current value of |
| 722 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 723 | input [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] |
| 724 | mem_64_pcie_offset_reg_spare_control_hw_write; // data bus for hw loading of |
| 725 | // mem_64_pcie_offset_reg_spare_control. |
| 726 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] |
| 727 | mem_64_pcie_offset_reg_spare_control_hw_read; // This signal provides the |
| 728 | // current value of |
| 729 | // mem_64_pcie_offset_reg_spare_control. |
| 730 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC] mem_64_pcie_offset_reg_spare_status_hw_read; |
| 731 | // This signal provides the current value of |
| 732 | // mem_64_pcie_offset_reg_spare_status. |
| 733 | input mem_64_pcie_offset_reg_select_pulse; // select |
| 734 | input imu_logged_error_status_reg_rw1c_alias; // SW load |
| 735 | input imu_logged_error_status_reg_rw1s_alias; // SW load |
| 736 | input rst_l; // HW reset |
| 737 | input por_l; // HW reset |
| 738 | input daemon_csrbus_wr_in; // csrbus_wr |
| 739 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 740 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 741 | |
| 742 | //==================================================== |
| 743 | // Type declarations |
| 744 | //==================================================== |
| 745 | wire clk; // Clock signal |
| 746 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read; |
| 747 | // This signal provides the current value of |
| 748 | // imu_error_log_en_reg_spare_log_en. |
| 749 | wire imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the |
| 750 | // current value of |
| 751 | // imu_error_log_en_reg_eq_over_log_en. |
| 752 | wire imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides the |
| 753 | // current value of |
| 754 | // imu_error_log_en_reg_eq_not_en_log_en. |
| 755 | wire imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides |
| 756 | // the current value of |
| 757 | // imu_error_log_en_reg_msi_mal_err_log_en. |
| 758 | wire imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides |
| 759 | // the current value of |
| 760 | // imu_error_log_en_reg_msi_par_err_log_en. |
| 761 | wire imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal |
| 762 | // provides the |
| 763 | // current value of |
| 764 | // imu_error_log_en_reg_pmeack_mes_not_en_log_en. |
| 765 | wire imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal |
| 766 | // provides the |
| 767 | // current value of |
| 768 | // imu_error_log_en_reg_pmpme_mes_not_en_log_en. |
| 769 | wire imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal |
| 770 | // provides the |
| 771 | // current value of |
| 772 | // imu_error_log_en_reg_fatal_mes_not_en_log_en. |
| 773 | wire imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal |
| 774 | // provides the |
| 775 | // current value |
| 776 | // of |
| 777 | // imu_error_log_en_reg_nonfatal_mes_not_en_log_en. |
| 778 | wire imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal |
| 779 | // provides the |
| 780 | // current value of |
| 781 | // imu_error_log_en_reg_cor_mes_not_en_log_en. |
| 782 | wire imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides |
| 783 | // the current value of |
| 784 | // imu_error_log_en_reg_msi_not_en_log_en. |
| 785 | wire imu_error_log_en_reg_select_pulse; // select |
| 786 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC] imu_int_en_reg_spare_s_int_en_hw_read; |
| 787 | // This signal provides the current value of imu_int_en_reg_spare_s_int_en. |
| 788 | wire imu_int_en_reg_eq_over_s_int_en_hw_read; // This signal provides the |
| 789 | // current value of |
| 790 | // imu_int_en_reg_eq_over_s_int_en. |
| 791 | wire imu_int_en_reg_eq_not_en_s_int_en_hw_read; // This signal provides the |
| 792 | // current value of |
| 793 | // imu_int_en_reg_eq_not_en_s_int_en. |
| 794 | wire imu_int_en_reg_msi_mal_err_s_int_en_hw_read; // This signal provides the |
| 795 | // current value of |
| 796 | // imu_int_en_reg_msi_mal_err_s_int_en. |
| 797 | wire imu_int_en_reg_msi_par_err_s_int_en_hw_read; // This signal provides the |
| 798 | // current value of |
| 799 | // imu_int_en_reg_msi_par_err_s_int_en. |
| 800 | wire imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read; // This signal provides |
| 801 | // the current value of |
| 802 | // imu_int_en_reg_pmeack_mes_not_en_s_int_en. |
| 803 | wire imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read; // This signal provides |
| 804 | // the current value of |
| 805 | // imu_int_en_reg_pmpme_mes_not_en_s_int_en. |
| 806 | wire imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read; // This signal provides |
| 807 | // the current value of |
| 808 | // imu_int_en_reg_fatal_mes_not_en_s_int_en. |
| 809 | wire imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read; // This signal |
| 810 | // provides the |
| 811 | // current value of |
| 812 | // imu_int_en_reg_nonfatal_mes_not_en_s_int_en. |
| 813 | wire imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read; // This signal provides |
| 814 | // the current value of |
| 815 | // imu_int_en_reg_cor_mes_not_en_s_int_en. |
| 816 | wire imu_int_en_reg_msi_not_en_s_int_en_hw_read; // This signal provides the |
| 817 | // current value of |
| 818 | // imu_int_en_reg_msi_not_en_s_int_en. |
| 819 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC] imu_int_en_reg_spare_p_int_en_hw_read; |
| 820 | // This signal provides the current value of imu_int_en_reg_spare_p_int_en. |
| 821 | wire imu_int_en_reg_eq_over_p_int_en_hw_read; // This signal provides the |
| 822 | // current value of |
| 823 | // imu_int_en_reg_eq_over_p_int_en. |
| 824 | wire imu_int_en_reg_eq_not_en_p_int_en_hw_read; // This signal provides the |
| 825 | // current value of |
| 826 | // imu_int_en_reg_eq_not_en_p_int_en. |
| 827 | wire imu_int_en_reg_msi_mal_err_p_int_en_hw_read; // This signal provides the |
| 828 | // current value of |
| 829 | // imu_int_en_reg_msi_mal_err_p_int_en. |
| 830 | wire imu_int_en_reg_msi_par_err_p_int_en_hw_read; // This signal provides the |
| 831 | // current value of |
| 832 | // imu_int_en_reg_msi_par_err_p_int_en. |
| 833 | wire imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read; // This signal provides |
| 834 | // the current value of |
| 835 | // imu_int_en_reg_pmeack_mes_not_en_p_int_en. |
| 836 | wire imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read; // This signal provides |
| 837 | // the current value of |
| 838 | // imu_int_en_reg_pmpme_mes_not_en_p_int_en. |
| 839 | wire imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read; // This signal provides |
| 840 | // the current value of |
| 841 | // imu_int_en_reg_fatal_mes_not_en_p_int_en. |
| 842 | wire imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read; // This signal |
| 843 | // provides the |
| 844 | // current value of |
| 845 | // imu_int_en_reg_nonfatal_mes_not_en_p_int_en. |
| 846 | wire imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read; // This signal provides |
| 847 | // the current value of |
| 848 | // imu_int_en_reg_cor_mes_not_en_p_int_en. |
| 849 | wire imu_int_en_reg_msi_not_en_p_int_en_hw_read; // This signal provides the |
| 850 | // current value of |
| 851 | // imu_int_en_reg_msi_not_en_p_int_en. |
| 852 | wire imu_int_en_reg_select_pulse; // select |
| 853 | wire imu_enabled_error_status_reg_select; // select |
| 854 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] imu_enabled_error_status_reg_ext_read_data; |
| 855 | // Read Data |
| 856 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC] |
| 857 | imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for |
| 858 | // imu_logged_error_status_reg_spare_s. |
| 859 | // When set |
| 860 | // imu_logged_error_status_reg |
| 861 | // will be set to one. |
| 862 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC] |
| 863 | imu_logged_error_status_reg_spare_s_hw_read; // This signal provides the |
| 864 | // current value of |
| 865 | // imu_logged_error_status_reg_spare_s. |
| 866 | wire imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for |
| 867 | // imu_logged_error_status_reg_eq_over_s. |
| 868 | // When set |
| 869 | // imu_logged_error_status_reg |
| 870 | // will be set to one. |
| 871 | wire imu_logged_error_status_reg_eq_over_s_hw_read; // This signal provides the |
| 872 | // current value of |
| 873 | // imu_logged_error_status_reg_eq_over_s. |
| 874 | wire imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal for |
| 875 | // imu_logged_error_status_reg_eq_not_en_s. |
| 876 | // When set |
| 877 | // imu_logged_error_status_reg |
| 878 | // will be set to one. |
| 879 | wire imu_logged_error_status_reg_eq_not_en_s_hw_read; // This signal provides |
| 880 | // the current value of |
| 881 | // imu_logged_error_status_reg_eq_not_en_s. |
| 882 | wire imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal |
| 883 | // for |
| 884 | // imu_logged_error_status_reg_msi_mal_err_s. |
| 885 | // When set |
| 886 | // imu_logged_error_status_reg |
| 887 | // will be set to one. |
| 888 | wire imu_logged_error_status_reg_msi_mal_err_s_hw_read; // This signal provides |
| 889 | // the current value of |
| 890 | // imu_logged_error_status_reg_msi_mal_err_s. |
| 891 | wire imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal |
| 892 | // for |
| 893 | // imu_logged_error_status_reg_msi_par_err_s. |
| 894 | // When set |
| 895 | // imu_logged_error_status_reg |
| 896 | // will be set to one. |
| 897 | wire imu_logged_error_status_reg_msi_par_err_s_hw_read; // This signal provides |
| 898 | // the current value of |
| 899 | // imu_logged_error_status_reg_msi_par_err_s. |
| 900 | wire imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set |
| 901 | // signal for |
| 902 | // imu_logged_error_status_reg_pmeack_mes_not_en_s. |
| 903 | // When set |
| 904 | // imu_logged_error_status_reg |
| 905 | // will be set to |
| 906 | // one. |
| 907 | wire imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read; // This signal |
| 908 | // provides the |
| 909 | // current value |
| 910 | // of |
| 911 | // imu_logged_error_status_reg_pmeack_mes_not_en_s. |
| 912 | wire imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set |
| 913 | // signal for |
| 914 | // imu_logged_error_status_reg_pmpme_mes_not_en_s. |
| 915 | // When set |
| 916 | // imu_logged_error_status_reg |
| 917 | // will be set to |
| 918 | // one. |
| 919 | wire imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read; // This signal |
| 920 | // provides the |
| 921 | // current value |
| 922 | // of |
| 923 | // imu_logged_error_status_reg_pmpme_mes_not_en_s. |
| 924 | wire imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set |
| 925 | // signal for |
| 926 | // imu_logged_error_status_reg_fatal_mes_not_en_s. |
| 927 | // When set |
| 928 | // imu_logged_error_status_reg |
| 929 | // will be set to |
| 930 | // one. |
| 931 | wire imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read; // This signal |
| 932 | // provides the |
| 933 | // current value |
| 934 | // of |
| 935 | // imu_logged_error_status_reg_fatal_mes_not_en_s. |
| 936 | wire imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware set |
| 937 | // signal for |
| 938 | // imu_logged_error_status_reg_nonfatal_mes_not_en_s. |
| 939 | // When set |
| 940 | // imu_logged_error_status_reg |
| 941 | // will be set |
| 942 | // to one. |
| 943 | wire imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read; // This signal |
| 944 | // provides the |
| 945 | // current |
| 946 | // value of |
| 947 | // imu_logged_error_status_reg_nonfatal_mes_not_en_s. |
| 948 | wire imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set |
| 949 | // signal for |
| 950 | // imu_logged_error_status_reg_cor_mes_not_en_s. |
| 951 | // When set |
| 952 | // imu_logged_error_status_reg |
| 953 | // will be set to |
| 954 | // one. |
| 955 | wire imu_logged_error_status_reg_cor_mes_not_en_s_hw_read; // This signal |
| 956 | // provides the |
| 957 | // current value of |
| 958 | // imu_logged_error_status_reg_cor_mes_not_en_s. |
| 959 | wire imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal |
| 960 | // for |
| 961 | // imu_logged_error_status_reg_msi_not_en_s. |
| 962 | // When set |
| 963 | // imu_logged_error_status_reg |
| 964 | // will be set to one. |
| 965 | wire imu_logged_error_status_reg_msi_not_en_s_hw_read; // This signal provides |
| 966 | // the current value of |
| 967 | // imu_logged_error_status_reg_msi_not_en_s. |
| 968 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC] |
| 969 | imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for |
| 970 | // imu_logged_error_status_reg_spare_p. |
| 971 | // When set |
| 972 | // imu_logged_error_status_reg |
| 973 | // will be set to one. |
| 974 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC] |
| 975 | imu_logged_error_status_reg_spare_p_hw_read; // This signal provides the |
| 976 | // current value of |
| 977 | // imu_logged_error_status_reg_spare_p. |
| 978 | wire imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for |
| 979 | // imu_logged_error_status_reg_eq_over_p. |
| 980 | // When set |
| 981 | // imu_logged_error_status_reg |
| 982 | // will be set to one. |
| 983 | wire imu_logged_error_status_reg_eq_over_p_hw_read; // This signal provides the |
| 984 | // current value of |
| 985 | // imu_logged_error_status_reg_eq_over_p. |
| 986 | wire imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal for |
| 987 | // imu_logged_error_status_reg_eq_not_en_p. |
| 988 | // When set |
| 989 | // imu_logged_error_status_reg |
| 990 | // will be set to one. |
| 991 | wire imu_logged_error_status_reg_eq_not_en_p_hw_read; // This signal provides |
| 992 | // the current value of |
| 993 | // imu_logged_error_status_reg_eq_not_en_p. |
| 994 | wire imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal |
| 995 | // for |
| 996 | // imu_logged_error_status_reg_msi_mal_err_p. |
| 997 | // When set |
| 998 | // imu_logged_error_status_reg |
| 999 | // will be set to one. |
| 1000 | wire imu_logged_error_status_reg_msi_mal_err_p_hw_read; // This signal provides |
| 1001 | // the current value of |
| 1002 | // imu_logged_error_status_reg_msi_mal_err_p. |
| 1003 | wire imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal |
| 1004 | // for |
| 1005 | // imu_logged_error_status_reg_msi_par_err_p. |
| 1006 | // When set |
| 1007 | // imu_logged_error_status_reg |
| 1008 | // will be set to one. |
| 1009 | wire imu_logged_error_status_reg_msi_par_err_p_hw_read; // This signal provides |
| 1010 | // the current value of |
| 1011 | // imu_logged_error_status_reg_msi_par_err_p. |
| 1012 | wire imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set |
| 1013 | // signal for |
| 1014 | // imu_logged_error_status_reg_pmeack_mes_not_en_p. |
| 1015 | // When set |
| 1016 | // imu_logged_error_status_reg |
| 1017 | // will be set to |
| 1018 | // one. |
| 1019 | wire imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read; // This signal |
| 1020 | // provides the |
| 1021 | // current value |
| 1022 | // of |
| 1023 | // imu_logged_error_status_reg_pmeack_mes_not_en_p. |
| 1024 | wire imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set |
| 1025 | // signal for |
| 1026 | // imu_logged_error_status_reg_pmpme_mes_not_en_p. |
| 1027 | // When set |
| 1028 | // imu_logged_error_status_reg |
| 1029 | // will be set to |
| 1030 | // one. |
| 1031 | wire imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read; // This signal |
| 1032 | // provides the |
| 1033 | // current value |
| 1034 | // of |
| 1035 | // imu_logged_error_status_reg_pmpme_mes_not_en_p. |
| 1036 | wire imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set |
| 1037 | // signal for |
| 1038 | // imu_logged_error_status_reg_fatal_mes_not_en_p. |
| 1039 | // When set |
| 1040 | // imu_logged_error_status_reg |
| 1041 | // will be set to |
| 1042 | // one. |
| 1043 | wire imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read; // This signal |
| 1044 | // provides the |
| 1045 | // current value |
| 1046 | // of |
| 1047 | // imu_logged_error_status_reg_fatal_mes_not_en_p. |
| 1048 | wire imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware set |
| 1049 | // signal for |
| 1050 | // imu_logged_error_status_reg_nonfatal_mes_not_en_p. |
| 1051 | // When set |
| 1052 | // imu_logged_error_status_reg |
| 1053 | // will be set |
| 1054 | // to one. |
| 1055 | wire imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read; // This signal |
| 1056 | // provides the |
| 1057 | // current |
| 1058 | // value of |
| 1059 | // imu_logged_error_status_reg_nonfatal_mes_not_en_p. |
| 1060 | wire imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set |
| 1061 | // signal for |
| 1062 | // imu_logged_error_status_reg_cor_mes_not_en_p. |
| 1063 | // When set |
| 1064 | // imu_logged_error_status_reg |
| 1065 | // will be set to |
| 1066 | // one. |
| 1067 | wire imu_logged_error_status_reg_cor_mes_not_en_p_hw_read; // This signal |
| 1068 | // provides the |
| 1069 | // current value of |
| 1070 | // imu_logged_error_status_reg_cor_mes_not_en_p. |
| 1071 | wire imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal |
| 1072 | // for |
| 1073 | // imu_logged_error_status_reg_msi_not_en_p. |
| 1074 | // When set |
| 1075 | // imu_logged_error_status_reg |
| 1076 | // will be set to one. |
| 1077 | wire imu_logged_error_status_reg_msi_not_en_p_hw_read; // This signal provides |
| 1078 | // the current value of |
| 1079 | // imu_logged_error_status_reg_msi_not_en_p. |
| 1080 | wire imu_logged_error_status_reg_select_pulse; // select |
| 1081 | wire imu_rds_error_log_reg_hw_ld; // Hardware load enable for |
| 1082 | // imu_rds_error_log_reg. When set, <hw write |
| 1083 | // signal> will be loaded into |
| 1084 | // imu_rds_error_log_reg. |
| 1085 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_hw_write; |
| 1086 | // data bus for hw loading of imu_rds_error_log_reg. |
| 1087 | wire imu_rds_error_log_reg_select_pulse; // select |
| 1088 | wire imu_scs_error_log_reg_hw_ld; // Hardware load enable for |
| 1089 | // imu_scs_error_log_reg. When set, <hw write |
| 1090 | // signal> will be loaded into |
| 1091 | // imu_scs_error_log_reg. |
| 1092 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_hw_write; |
| 1093 | // data bus for hw loading of imu_scs_error_log_reg. |
| 1094 | wire imu_scs_error_log_reg_select_pulse; // select |
| 1095 | wire imu_eqs_error_log_reg_hw_ld; // Hardware load enable for |
| 1096 | // imu_eqs_error_log_reg. When set, <hw write |
| 1097 | // signal> will be loaded into |
| 1098 | // imu_eqs_error_log_reg. |
| 1099 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_hw_write; |
| 1100 | // data bus for hw loading of imu_eqs_error_log_reg. |
| 1101 | wire imu_eqs_error_log_reg_select_pulse; // select |
| 1102 | wire dmc_interrupt_mask_reg_dmc_hw_read; // This signal provides the current |
| 1103 | // value of |
| 1104 | // dmc_interrupt_mask_reg_dmc. |
| 1105 | wire dmc_interrupt_mask_reg_debug_trig_en_hw_read; // This signal provides the |
| 1106 | // current value of |
| 1107 | // dmc_interrupt_mask_reg_debug_trig_en. |
| 1108 | wire dmc_interrupt_mask_reg_mmu_hw_read; // This signal provides the current |
| 1109 | // value of |
| 1110 | // dmc_interrupt_mask_reg_mmu. |
| 1111 | wire dmc_interrupt_mask_reg_imu_hw_read; // This signal provides the current |
| 1112 | // value of |
| 1113 | // dmc_interrupt_mask_reg_imu. |
| 1114 | wire dmc_interrupt_mask_reg_select_pulse; // select |
| 1115 | wire dmc_interrupt_status_reg_select; // select |
| 1116 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] dmc_interrupt_status_reg_ext_read_data; |
| 1117 | // Read Data |
| 1118 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC] imu_perf_cntrl_sel1_hw_read; |
| 1119 | // This signal provides the current value of imu_perf_cntrl_sel1. |
| 1120 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC] imu_perf_cntrl_sel0_hw_read; |
| 1121 | // This signal provides the current value of imu_perf_cntrl_sel0. |
| 1122 | wire imu_perf_cntrl_select_pulse; // select |
| 1123 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_write; |
| 1124 | // data bus for hw loading of imu_perf_cnt0_cnt. |
| 1125 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_read; |
| 1126 | // This signal provides the current value of imu_perf_cnt0_cnt. |
| 1127 | wire imu_perf_cnt0_select_pulse; // select |
| 1128 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_write; |
| 1129 | // data bus for hw loading of imu_perf_cnt1_cnt. |
| 1130 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_read; |
| 1131 | // This signal provides the current value of imu_perf_cnt1_cnt. |
| 1132 | wire imu_perf_cnt1_select_pulse; // select |
| 1133 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_INT_SLC] msi_32_addr_reg_addr_hw_read; |
| 1134 | // This signal provides the current value of msi_32_addr_reg_addr. |
| 1135 | wire msi_32_addr_reg_select_pulse; // select |
| 1136 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_INT_SLC] msi_64_addr_reg_addr_hw_read; |
| 1137 | // This signal provides the current value of msi_64_addr_reg_addr. |
| 1138 | wire msi_64_addr_reg_select_pulse; // select |
| 1139 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC] mem_64_pcie_offset_reg_addr_hw_read; |
| 1140 | // This signal provides the current value of mem_64_pcie_offset_reg_addr. |
| 1141 | wire mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load enable |
| 1142 | // for |
| 1143 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 1144 | // When set, <hw write |
| 1145 | // signal> will be |
| 1146 | // loaded into |
| 1147 | // mem_64_pcie_offset_reg. |
| 1148 | wire mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw |
| 1149 | // loading of |
| 1150 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 1151 | wire mem_64_pcie_offset_reg_spare_control_load_7_hw_read; // This signal |
| 1152 | // provides the |
| 1153 | // current value of |
| 1154 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 1155 | wire mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load enable |
| 1156 | // for |
| 1157 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 1158 | // When set, <hw write |
| 1159 | // signal> will be |
| 1160 | // loaded into |
| 1161 | // mem_64_pcie_offset_reg. |
| 1162 | wire mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw |
| 1163 | // loading of |
| 1164 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 1165 | wire mem_64_pcie_offset_reg_spare_control_load_6_hw_read; // This signal |
| 1166 | // provides the |
| 1167 | // current value of |
| 1168 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 1169 | wire mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load enable |
| 1170 | // for |
| 1171 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 1172 | // When set, <hw write |
| 1173 | // signal> will be |
| 1174 | // loaded into |
| 1175 | // mem_64_pcie_offset_reg. |
| 1176 | wire mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw |
| 1177 | // loading of |
| 1178 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 1179 | wire mem_64_pcie_offset_reg_spare_control_load_5_hw_read; // This signal |
| 1180 | // provides the |
| 1181 | // current value of |
| 1182 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 1183 | wire mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load enable |
| 1184 | // for |
| 1185 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 1186 | // When set, <hw write |
| 1187 | // signal> will be |
| 1188 | // loaded into |
| 1189 | // mem_64_pcie_offset_reg. |
| 1190 | wire mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw |
| 1191 | // loading of |
| 1192 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 1193 | wire mem_64_pcie_offset_reg_spare_control_load_4_hw_read; // This signal |
| 1194 | // provides the |
| 1195 | // current value of |
| 1196 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 1197 | wire mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load enable |
| 1198 | // for |
| 1199 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 1200 | // When set, <hw write |
| 1201 | // signal> will be |
| 1202 | // loaded into |
| 1203 | // mem_64_pcie_offset_reg. |
| 1204 | wire mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw |
| 1205 | // loading of |
| 1206 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 1207 | wire mem_64_pcie_offset_reg_spare_control_load_3_hw_read; // This signal |
| 1208 | // provides the |
| 1209 | // current value of |
| 1210 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 1211 | wire mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load enable |
| 1212 | // for |
| 1213 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 1214 | // When set, <hw write |
| 1215 | // signal> will be |
| 1216 | // loaded into |
| 1217 | // mem_64_pcie_offset_reg. |
| 1218 | wire mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw |
| 1219 | // loading of |
| 1220 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 1221 | wire mem_64_pcie_offset_reg_spare_control_load_2_hw_read; // This signal |
| 1222 | // provides the |
| 1223 | // current value of |
| 1224 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 1225 | wire mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load enable |
| 1226 | // for |
| 1227 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 1228 | // When set, <hw write |
| 1229 | // signal> will be |
| 1230 | // loaded into |
| 1231 | // mem_64_pcie_offset_reg. |
| 1232 | wire mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw |
| 1233 | // loading of |
| 1234 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 1235 | wire mem_64_pcie_offset_reg_spare_control_load_1_hw_read; // This signal |
| 1236 | // provides the |
| 1237 | // current value of |
| 1238 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 1239 | wire mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load enable |
| 1240 | // for |
| 1241 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 1242 | // When set, <hw write |
| 1243 | // signal> will be |
| 1244 | // loaded into |
| 1245 | // mem_64_pcie_offset_reg. |
| 1246 | wire mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw |
| 1247 | // loading of |
| 1248 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 1249 | wire mem_64_pcie_offset_reg_spare_control_load_0_hw_read; // This signal |
| 1250 | // provides the |
| 1251 | // current value of |
| 1252 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 1253 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_write; |
| 1254 | // data bus for hw loading of mem_64_pcie_offset_reg_spare_control. |
| 1255 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_read; |
| 1256 | // This signal provides the current value of |
| 1257 | // mem_64_pcie_offset_reg_spare_control. |
| 1258 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC] mem_64_pcie_offset_reg_spare_status_hw_read; |
| 1259 | // This signal provides the current value of |
| 1260 | // mem_64_pcie_offset_reg_spare_status. |
| 1261 | wire mem_64_pcie_offset_reg_select_pulse; // select |
| 1262 | wire imu_logged_error_status_reg_rw1c_alias; // SW load |
| 1263 | wire imu_logged_error_status_reg_rw1s_alias; // SW load |
| 1264 | wire rst_l; // HW reset |
| 1265 | wire por_l; // HW reset |
| 1266 | wire daemon_csrbus_wr_in; // csrbus_wr |
| 1267 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 1268 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 1269 | |
| 1270 | |
| 1271 | //==================================================== |
| 1272 | // Local signals |
| 1273 | //==================================================== |
| 1274 | //----- For CSR register: imu_error_log_en_reg |
| 1275 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] imu_error_log_en_reg_csrbus_read_data; |
| 1276 | // Entry Based Read Data |
| 1277 | |
| 1278 | //----- For CSR register: imu_int_en_reg |
| 1279 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH-1:0] imu_int_en_reg_csrbus_read_data; |
| 1280 | // Entry Based Read Data |
| 1281 | |
| 1282 | //----- For CSR register: imu_logged_error_status_reg |
| 1283 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH-1:0] |
| 1284 | imu_logged_error_status_reg_csrbus_read_data; // Entry Based Read Data |
| 1285 | |
| 1286 | //----- For CSR register: imu_rds_error_log_reg |
| 1287 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_csrbus_read_data; |
| 1288 | // Entry Based Read Data |
| 1289 | |
| 1290 | //----- For CSR register: imu_scs_error_log_reg |
| 1291 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_csrbus_read_data; |
| 1292 | // Entry Based Read Data |
| 1293 | |
| 1294 | //----- For CSR register: imu_eqs_error_log_reg |
| 1295 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_csrbus_read_data; |
| 1296 | // Entry Based Read Data |
| 1297 | |
| 1298 | //----- For CSR register: dmc_interrupt_mask_reg |
| 1299 | wire [`FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WIDTH-1:0] dmc_interrupt_mask_reg_csrbus_read_data; |
| 1300 | // Entry Based Read Data |
| 1301 | |
| 1302 | //----- For CSR register: imu_perf_cntrl |
| 1303 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH-1:0] imu_perf_cntrl_csrbus_read_data; |
| 1304 | // Entry Based Read Data |
| 1305 | |
| 1306 | //----- For CSR register: imu_perf_cnt0 |
| 1307 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WIDTH-1:0] imu_perf_cnt0_csrbus_read_data; |
| 1308 | // Entry Based Read Data |
| 1309 | |
| 1310 | //----- For CSR register: imu_perf_cnt1 |
| 1311 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WIDTH-1:0] imu_perf_cnt1_csrbus_read_data; |
| 1312 | // Entry Based Read Data |
| 1313 | |
| 1314 | //----- For CSR register: msi_32_addr_reg |
| 1315 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH-1:0] msi_32_addr_reg_csrbus_read_data; |
| 1316 | // Entry Based Read Data |
| 1317 | |
| 1318 | //----- For CSR register: msi_64_addr_reg |
| 1319 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH-1:0] msi_64_addr_reg_csrbus_read_data; |
| 1320 | // Entry Based Read Data |
| 1321 | |
| 1322 | //----- For CSR register: mem_64_pcie_offset_reg |
| 1323 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH-1:0] mem_64_pcie_offset_reg_csrbus_read_data; |
| 1324 | // Entry Based Read Data |
| 1325 | |
| 1326 | //==================================================== |
| 1327 | // Assignments only (first stage) |
| 1328 | //==================================================== |
| 1329 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in; |
| 1330 | wire daemon_csrbus_wr = daemon_csrbus_wr_in; |
| 1331 | |
| 1332 | //==================================================== |
| 1333 | // Automatic hw_ld / hw_write |
| 1334 | //==================================================== |
| 1335 | |
| 1336 | //==================================================== |
| 1337 | // Extern select |
| 1338 | //==================================================== |
| 1339 | |
| 1340 | //===================================================== |
| 1341 | // OUTPUT: read_data_out |
| 1342 | //===================================================== |
| 1343 | dmu_imu_ics_csrpipe_15 dmu_imu_ics_csrpipe_15_inst_1 |
| 1344 | ( |
| 1345 | .clk (clk), |
| 1346 | .rst_l (rst_l), |
| 1347 | .reg_in (1'b1), |
| 1348 | .reg_out (1'b1), |
| 1349 | .data0 (imu_error_log_en_reg_csrbus_read_data), |
| 1350 | .sel0 (imu_error_log_en_reg_select_pulse), |
| 1351 | .data1 (imu_int_en_reg_csrbus_read_data), |
| 1352 | .sel1 (imu_int_en_reg_select_pulse), |
| 1353 | .data2 (imu_enabled_error_status_reg_ext_read_data), |
| 1354 | .sel2 (imu_enabled_error_status_reg_select), |
| 1355 | .data3 (imu_logged_error_status_reg_csrbus_read_data), |
| 1356 | .sel3 (imu_logged_error_status_reg_select_pulse), |
| 1357 | .data4 (imu_rds_error_log_reg_csrbus_read_data), |
| 1358 | .sel4 (imu_rds_error_log_reg_select_pulse), |
| 1359 | .data5 (imu_scs_error_log_reg_csrbus_read_data), |
| 1360 | .sel5 (imu_scs_error_log_reg_select_pulse), |
| 1361 | .data6 (imu_eqs_error_log_reg_csrbus_read_data), |
| 1362 | .sel6 (imu_eqs_error_log_reg_select_pulse), |
| 1363 | .data7 (dmc_interrupt_mask_reg_csrbus_read_data), |
| 1364 | .sel7 (dmc_interrupt_mask_reg_select_pulse), |
| 1365 | .data8 (dmc_interrupt_status_reg_ext_read_data), |
| 1366 | .sel8 (dmc_interrupt_status_reg_select), |
| 1367 | .data9 (imu_perf_cntrl_csrbus_read_data), |
| 1368 | .sel9 (imu_perf_cntrl_select_pulse), |
| 1369 | .data10 (imu_perf_cnt0_csrbus_read_data), |
| 1370 | .sel10 (imu_perf_cnt0_select_pulse), |
| 1371 | .data11 (imu_perf_cnt1_csrbus_read_data), |
| 1372 | .sel11 (imu_perf_cnt1_select_pulse), |
| 1373 | .data12 (msi_32_addr_reg_csrbus_read_data), |
| 1374 | .sel12 (msi_32_addr_reg_select_pulse), |
| 1375 | .data13 (msi_64_addr_reg_csrbus_read_data), |
| 1376 | .sel13 (msi_64_addr_reg_select_pulse), |
| 1377 | .data14 (mem_64_pcie_offset_reg_csrbus_read_data), |
| 1378 | .sel14 (mem_64_pcie_offset_reg_select_pulse), |
| 1379 | .out (read_data_0_out) |
| 1380 | ); |
| 1381 | |
| 1382 | |
| 1383 | //==================================================== |
| 1384 | // Instantiation of registers |
| 1385 | //==================================================== |
| 1386 | |
| 1387 | wire imu_error_log_en_reg_w_ld =imu_error_log_en_reg_select_pulse & daemon_csrbus_wr; |
| 1388 | |
| 1389 | dmu_imu_ics_csr_imu_error_log_en_reg imu_error_log_en_reg |
| 1390 | ( |
| 1391 | .clk (clk), |
| 1392 | .por_l (por_l), |
| 1393 | .imu_error_log_en_reg_w_ld (imu_error_log_en_reg_w_ld), |
| 1394 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1395 | .imu_error_log_en_reg_csrbus_read_data (imu_error_log_en_reg_csrbus_read_data), |
| 1396 | .imu_error_log_en_reg_spare_log_en_hw_read (imu_error_log_en_reg_spare_log_en_hw_read), |
| 1397 | .imu_error_log_en_reg_eq_over_log_en_hw_read (imu_error_log_en_reg_eq_over_log_en_hw_read), |
| 1398 | .imu_error_log_en_reg_eq_not_en_log_en_hw_read (imu_error_log_en_reg_eq_not_en_log_en_hw_read), |
| 1399 | .imu_error_log_en_reg_msi_mal_err_log_en_hw_read (imu_error_log_en_reg_msi_mal_err_log_en_hw_read), |
| 1400 | .imu_error_log_en_reg_msi_par_err_log_en_hw_read (imu_error_log_en_reg_msi_par_err_log_en_hw_read), |
| 1401 | .imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read (imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read), |
| 1402 | .imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read (imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read), |
| 1403 | .imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read (imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read), |
| 1404 | .imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read (imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read), |
| 1405 | .imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read (imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read), |
| 1406 | .imu_error_log_en_reg_msi_not_en_log_en_hw_read (imu_error_log_en_reg_msi_not_en_log_en_hw_read) |
| 1407 | ); |
| 1408 | |
| 1409 | wire imu_int_en_reg_w_ld =imu_int_en_reg_select_pulse & daemon_csrbus_wr; |
| 1410 | |
| 1411 | dmu_imu_ics_csr_imu_int_en_reg imu_int_en_reg |
| 1412 | ( |
| 1413 | .clk (clk), |
| 1414 | .rst_l (rst_l), |
| 1415 | .imu_int_en_reg_w_ld (imu_int_en_reg_w_ld), |
| 1416 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1417 | .imu_int_en_reg_csrbus_read_data (imu_int_en_reg_csrbus_read_data), |
| 1418 | .imu_int_en_reg_spare_s_int_en_hw_read (imu_int_en_reg_spare_s_int_en_hw_read), |
| 1419 | .imu_int_en_reg_eq_over_s_int_en_hw_read (imu_int_en_reg_eq_over_s_int_en_hw_read), |
| 1420 | .imu_int_en_reg_eq_not_en_s_int_en_hw_read (imu_int_en_reg_eq_not_en_s_int_en_hw_read), |
| 1421 | .imu_int_en_reg_msi_mal_err_s_int_en_hw_read (imu_int_en_reg_msi_mal_err_s_int_en_hw_read), |
| 1422 | .imu_int_en_reg_msi_par_err_s_int_en_hw_read (imu_int_en_reg_msi_par_err_s_int_en_hw_read), |
| 1423 | .imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read (imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read), |
| 1424 | .imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read (imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read), |
| 1425 | .imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read (imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read), |
| 1426 | .imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read (imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read), |
| 1427 | .imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read (imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read), |
| 1428 | .imu_int_en_reg_msi_not_en_s_int_en_hw_read (imu_int_en_reg_msi_not_en_s_int_en_hw_read), |
| 1429 | .imu_int_en_reg_spare_p_int_en_hw_read (imu_int_en_reg_spare_p_int_en_hw_read), |
| 1430 | .imu_int_en_reg_eq_over_p_int_en_hw_read (imu_int_en_reg_eq_over_p_int_en_hw_read), |
| 1431 | .imu_int_en_reg_eq_not_en_p_int_en_hw_read (imu_int_en_reg_eq_not_en_p_int_en_hw_read), |
| 1432 | .imu_int_en_reg_msi_mal_err_p_int_en_hw_read (imu_int_en_reg_msi_mal_err_p_int_en_hw_read), |
| 1433 | .imu_int_en_reg_msi_par_err_p_int_en_hw_read (imu_int_en_reg_msi_par_err_p_int_en_hw_read), |
| 1434 | .imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read (imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read), |
| 1435 | .imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read (imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read), |
| 1436 | .imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read (imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read), |
| 1437 | .imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read (imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read), |
| 1438 | .imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read (imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read), |
| 1439 | .imu_int_en_reg_msi_not_en_p_int_en_hw_read (imu_int_en_reg_msi_not_en_p_int_en_hw_read) |
| 1440 | ); |
| 1441 | |
| 1442 | wire imu_logged_error_status_reg_w_ld =imu_logged_error_status_reg_select_pulse & daemon_csrbus_wr; |
| 1443 | |
| 1444 | dmu_imu_ics_csr_imu_logged_error_status_reg imu_logged_error_status_reg |
| 1445 | ( |
| 1446 | .clk (clk), |
| 1447 | .por_l (por_l), |
| 1448 | .imu_logged_error_status_reg_w_ld (imu_logged_error_status_reg_w_ld), |
| 1449 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1450 | .rw1c_alias (imu_logged_error_status_reg_rw1c_alias), |
| 1451 | .rw1s_alias (imu_logged_error_status_reg_rw1s_alias), |
| 1452 | .imu_logged_error_status_reg_csrbus_read_data (imu_logged_error_status_reg_csrbus_read_data), |
| 1453 | .imu_logged_error_status_reg_spare_s_hw_set (imu_logged_error_status_reg_spare_s_hw_set), |
| 1454 | .imu_logged_error_status_reg_spare_s_hw_read (imu_logged_error_status_reg_spare_s_hw_read), |
| 1455 | .imu_logged_error_status_reg_eq_over_s_hw_set (imu_logged_error_status_reg_eq_over_s_hw_set), |
| 1456 | .imu_logged_error_status_reg_eq_over_s_hw_read (imu_logged_error_status_reg_eq_over_s_hw_read), |
| 1457 | .imu_logged_error_status_reg_eq_not_en_s_hw_set (imu_logged_error_status_reg_eq_not_en_s_hw_set), |
| 1458 | .imu_logged_error_status_reg_eq_not_en_s_hw_read (imu_logged_error_status_reg_eq_not_en_s_hw_read), |
| 1459 | .imu_logged_error_status_reg_msi_mal_err_s_hw_set (imu_logged_error_status_reg_msi_mal_err_s_hw_set), |
| 1460 | .imu_logged_error_status_reg_msi_mal_err_s_hw_read (imu_logged_error_status_reg_msi_mal_err_s_hw_read), |
| 1461 | .imu_logged_error_status_reg_msi_par_err_s_hw_set (imu_logged_error_status_reg_msi_par_err_s_hw_set), |
| 1462 | .imu_logged_error_status_reg_msi_par_err_s_hw_read (imu_logged_error_status_reg_msi_par_err_s_hw_read), |
| 1463 | .imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set (imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set), |
| 1464 | .imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read (imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read), |
| 1465 | .imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set (imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set), |
| 1466 | .imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read (imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read), |
| 1467 | .imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set (imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set), |
| 1468 | .imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read (imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read), |
| 1469 | .imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set (imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set), |
| 1470 | .imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read (imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read), |
| 1471 | .imu_logged_error_status_reg_cor_mes_not_en_s_hw_set (imu_logged_error_status_reg_cor_mes_not_en_s_hw_set), |
| 1472 | .imu_logged_error_status_reg_cor_mes_not_en_s_hw_read (imu_logged_error_status_reg_cor_mes_not_en_s_hw_read), |
| 1473 | .imu_logged_error_status_reg_msi_not_en_s_hw_set (imu_logged_error_status_reg_msi_not_en_s_hw_set), |
| 1474 | .imu_logged_error_status_reg_msi_not_en_s_hw_read (imu_logged_error_status_reg_msi_not_en_s_hw_read), |
| 1475 | .imu_logged_error_status_reg_spare_p_hw_set (imu_logged_error_status_reg_spare_p_hw_set), |
| 1476 | .imu_logged_error_status_reg_spare_p_hw_read (imu_logged_error_status_reg_spare_p_hw_read), |
| 1477 | .imu_logged_error_status_reg_eq_over_p_hw_set (imu_logged_error_status_reg_eq_over_p_hw_set), |
| 1478 | .imu_logged_error_status_reg_eq_over_p_hw_read (imu_logged_error_status_reg_eq_over_p_hw_read), |
| 1479 | .imu_logged_error_status_reg_eq_not_en_p_hw_set (imu_logged_error_status_reg_eq_not_en_p_hw_set), |
| 1480 | .imu_logged_error_status_reg_eq_not_en_p_hw_read (imu_logged_error_status_reg_eq_not_en_p_hw_read), |
| 1481 | .imu_logged_error_status_reg_msi_mal_err_p_hw_set (imu_logged_error_status_reg_msi_mal_err_p_hw_set), |
| 1482 | .imu_logged_error_status_reg_msi_mal_err_p_hw_read (imu_logged_error_status_reg_msi_mal_err_p_hw_read), |
| 1483 | .imu_logged_error_status_reg_msi_par_err_p_hw_set (imu_logged_error_status_reg_msi_par_err_p_hw_set), |
| 1484 | .imu_logged_error_status_reg_msi_par_err_p_hw_read (imu_logged_error_status_reg_msi_par_err_p_hw_read), |
| 1485 | .imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set (imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set), |
| 1486 | .imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read (imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read), |
| 1487 | .imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set (imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set), |
| 1488 | .imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read (imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read), |
| 1489 | .imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set (imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set), |
| 1490 | .imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read (imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read), |
| 1491 | .imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set (imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set), |
| 1492 | .imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read (imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read), |
| 1493 | .imu_logged_error_status_reg_cor_mes_not_en_p_hw_set (imu_logged_error_status_reg_cor_mes_not_en_p_hw_set), |
| 1494 | .imu_logged_error_status_reg_cor_mes_not_en_p_hw_read (imu_logged_error_status_reg_cor_mes_not_en_p_hw_read), |
| 1495 | .imu_logged_error_status_reg_msi_not_en_p_hw_set (imu_logged_error_status_reg_msi_not_en_p_hw_set), |
| 1496 | .imu_logged_error_status_reg_msi_not_en_p_hw_read (imu_logged_error_status_reg_msi_not_en_p_hw_read) |
| 1497 | ); |
| 1498 | |
| 1499 | wire imu_rds_error_log_reg_w_ld =imu_rds_error_log_reg_select_pulse & daemon_csrbus_wr; |
| 1500 | |
| 1501 | dmu_imu_ics_csr_imu_rds_error_log_reg imu_rds_error_log_reg |
| 1502 | ( |
| 1503 | .clk (clk), |
| 1504 | .por_l (por_l), |
| 1505 | .imu_rds_error_log_reg_w_ld (imu_rds_error_log_reg_w_ld), |
| 1506 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1507 | .imu_rds_error_log_reg_csrbus_read_data (imu_rds_error_log_reg_csrbus_read_data), |
| 1508 | .imu_rds_error_log_reg_hw_ld (imu_rds_error_log_reg_hw_ld), |
| 1509 | .imu_rds_error_log_reg_hw_write (imu_rds_error_log_reg_hw_write) |
| 1510 | ); |
| 1511 | |
| 1512 | wire imu_scs_error_log_reg_w_ld =imu_scs_error_log_reg_select_pulse & daemon_csrbus_wr; |
| 1513 | |
| 1514 | dmu_imu_ics_csr_imu_scs_error_log_reg imu_scs_error_log_reg |
| 1515 | ( |
| 1516 | .clk (clk), |
| 1517 | .por_l (por_l), |
| 1518 | .imu_scs_error_log_reg_w_ld (imu_scs_error_log_reg_w_ld), |
| 1519 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1520 | .imu_scs_error_log_reg_csrbus_read_data (imu_scs_error_log_reg_csrbus_read_data), |
| 1521 | .imu_scs_error_log_reg_hw_ld (imu_scs_error_log_reg_hw_ld), |
| 1522 | .imu_scs_error_log_reg_hw_write (imu_scs_error_log_reg_hw_write) |
| 1523 | ); |
| 1524 | |
| 1525 | wire imu_eqs_error_log_reg_w_ld =imu_eqs_error_log_reg_select_pulse & daemon_csrbus_wr; |
| 1526 | |
| 1527 | dmu_imu_ics_csr_imu_eqs_error_log_reg imu_eqs_error_log_reg |
| 1528 | ( |
| 1529 | .clk (clk), |
| 1530 | .por_l (por_l), |
| 1531 | .imu_eqs_error_log_reg_w_ld (imu_eqs_error_log_reg_w_ld), |
| 1532 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1533 | .imu_eqs_error_log_reg_csrbus_read_data (imu_eqs_error_log_reg_csrbus_read_data), |
| 1534 | .imu_eqs_error_log_reg_hw_ld (imu_eqs_error_log_reg_hw_ld), |
| 1535 | .imu_eqs_error_log_reg_hw_write (imu_eqs_error_log_reg_hw_write) |
| 1536 | ); |
| 1537 | |
| 1538 | wire dmc_interrupt_mask_reg_w_ld =dmc_interrupt_mask_reg_select_pulse & daemon_csrbus_wr; |
| 1539 | |
| 1540 | dmu_imu_ics_csr_dmc_interrupt_mask_reg dmc_interrupt_mask_reg |
| 1541 | ( |
| 1542 | .clk (clk), |
| 1543 | .rst_l (rst_l), |
| 1544 | .dmc_interrupt_mask_reg_w_ld (dmc_interrupt_mask_reg_w_ld), |
| 1545 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1546 | .dmc_interrupt_mask_reg_csrbus_read_data (dmc_interrupt_mask_reg_csrbus_read_data), |
| 1547 | .dmc_interrupt_mask_reg_dmc_hw_read (dmc_interrupt_mask_reg_dmc_hw_read), |
| 1548 | .dmc_interrupt_mask_reg_debug_trig_en_hw_read (dmc_interrupt_mask_reg_debug_trig_en_hw_read), |
| 1549 | .dmc_interrupt_mask_reg_mmu_hw_read (dmc_interrupt_mask_reg_mmu_hw_read), |
| 1550 | .dmc_interrupt_mask_reg_imu_hw_read (dmc_interrupt_mask_reg_imu_hw_read) |
| 1551 | ); |
| 1552 | |
| 1553 | wire imu_perf_cntrl_w_ld =imu_perf_cntrl_select_pulse & daemon_csrbus_wr; |
| 1554 | |
| 1555 | dmu_imu_ics_csr_imu_perf_cntrl imu_perf_cntrl |
| 1556 | ( |
| 1557 | .clk (clk), |
| 1558 | .rst_l (rst_l), |
| 1559 | .imu_perf_cntrl_w_ld (imu_perf_cntrl_w_ld), |
| 1560 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1561 | .imu_perf_cntrl_csrbus_read_data (imu_perf_cntrl_csrbus_read_data), |
| 1562 | .imu_perf_cntrl_sel1_hw_read (imu_perf_cntrl_sel1_hw_read), |
| 1563 | .imu_perf_cntrl_sel0_hw_read (imu_perf_cntrl_sel0_hw_read) |
| 1564 | ); |
| 1565 | |
| 1566 | wire imu_perf_cnt0_w_ld =imu_perf_cnt0_select_pulse & daemon_csrbus_wr; |
| 1567 | |
| 1568 | dmu_imu_ics_csr_imu_perf_cnt0 imu_perf_cnt0 |
| 1569 | ( |
| 1570 | .clk (clk), |
| 1571 | .rst_l (rst_l), |
| 1572 | .imu_perf_cnt0_w_ld (imu_perf_cnt0_w_ld), |
| 1573 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1574 | .imu_perf_cnt0_csrbus_read_data (imu_perf_cnt0_csrbus_read_data), |
| 1575 | .imu_perf_cnt0_cnt_hw_write (imu_perf_cnt0_cnt_hw_write), |
| 1576 | .imu_perf_cnt0_cnt_hw_read (imu_perf_cnt0_cnt_hw_read) |
| 1577 | ); |
| 1578 | |
| 1579 | wire imu_perf_cnt1_w_ld =imu_perf_cnt1_select_pulse & daemon_csrbus_wr; |
| 1580 | |
| 1581 | dmu_imu_ics_csr_imu_perf_cnt1 imu_perf_cnt1 |
| 1582 | ( |
| 1583 | .clk (clk), |
| 1584 | .rst_l (rst_l), |
| 1585 | .imu_perf_cnt1_w_ld (imu_perf_cnt1_w_ld), |
| 1586 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1587 | .imu_perf_cnt1_csrbus_read_data (imu_perf_cnt1_csrbus_read_data), |
| 1588 | .imu_perf_cnt1_cnt_hw_write (imu_perf_cnt1_cnt_hw_write), |
| 1589 | .imu_perf_cnt1_cnt_hw_read (imu_perf_cnt1_cnt_hw_read) |
| 1590 | ); |
| 1591 | |
| 1592 | wire msi_32_addr_reg_w_ld =msi_32_addr_reg_select_pulse & daemon_csrbus_wr; |
| 1593 | |
| 1594 | dmu_imu_ics_csr_msi_32_addr_reg msi_32_addr_reg |
| 1595 | ( |
| 1596 | .clk (clk), |
| 1597 | .rst_l (rst_l), |
| 1598 | .msi_32_addr_reg_w_ld (msi_32_addr_reg_w_ld), |
| 1599 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1600 | .msi_32_addr_reg_csrbus_read_data (msi_32_addr_reg_csrbus_read_data), |
| 1601 | .msi_32_addr_reg_addr_hw_read (msi_32_addr_reg_addr_hw_read) |
| 1602 | ); |
| 1603 | |
| 1604 | wire msi_64_addr_reg_w_ld =msi_64_addr_reg_select_pulse & daemon_csrbus_wr; |
| 1605 | |
| 1606 | dmu_imu_ics_csr_msi_64_addr_reg msi_64_addr_reg |
| 1607 | ( |
| 1608 | .clk (clk), |
| 1609 | .rst_l (rst_l), |
| 1610 | .msi_64_addr_reg_w_ld (msi_64_addr_reg_w_ld), |
| 1611 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1612 | .msi_64_addr_reg_csrbus_read_data (msi_64_addr_reg_csrbus_read_data), |
| 1613 | .msi_64_addr_reg_addr_hw_read (msi_64_addr_reg_addr_hw_read) |
| 1614 | ); |
| 1615 | |
| 1616 | wire mem_64_pcie_offset_reg_w_ld =mem_64_pcie_offset_reg_select_pulse & daemon_csrbus_wr; |
| 1617 | |
| 1618 | dmu_imu_ics_csr_mem_64_pcie_offset_reg mem_64_pcie_offset_reg |
| 1619 | ( |
| 1620 | .clk (clk), |
| 1621 | .rst_l (rst_l), |
| 1622 | .mem_64_pcie_offset_reg_w_ld (mem_64_pcie_offset_reg_w_ld), |
| 1623 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 1624 | .mem_64_pcie_offset_reg_csrbus_read_data (mem_64_pcie_offset_reg_csrbus_read_data), |
| 1625 | .mem_64_pcie_offset_reg_addr_hw_read (mem_64_pcie_offset_reg_addr_hw_read), |
| 1626 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_ld (mem_64_pcie_offset_reg_spare_control_load_7_hw_ld), |
| 1627 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_write (mem_64_pcie_offset_reg_spare_control_load_7_hw_write), |
| 1628 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_read (mem_64_pcie_offset_reg_spare_control_load_7_hw_read), |
| 1629 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_ld (mem_64_pcie_offset_reg_spare_control_load_6_hw_ld), |
| 1630 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_write (mem_64_pcie_offset_reg_spare_control_load_6_hw_write), |
| 1631 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_read (mem_64_pcie_offset_reg_spare_control_load_6_hw_read), |
| 1632 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_ld (mem_64_pcie_offset_reg_spare_control_load_5_hw_ld), |
| 1633 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_write (mem_64_pcie_offset_reg_spare_control_load_5_hw_write), |
| 1634 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_read (mem_64_pcie_offset_reg_spare_control_load_5_hw_read), |
| 1635 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_ld (mem_64_pcie_offset_reg_spare_control_load_4_hw_ld), |
| 1636 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_write (mem_64_pcie_offset_reg_spare_control_load_4_hw_write), |
| 1637 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_read (mem_64_pcie_offset_reg_spare_control_load_4_hw_read), |
| 1638 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_ld (mem_64_pcie_offset_reg_spare_control_load_3_hw_ld), |
| 1639 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_write (mem_64_pcie_offset_reg_spare_control_load_3_hw_write), |
| 1640 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_read (mem_64_pcie_offset_reg_spare_control_load_3_hw_read), |
| 1641 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_ld (mem_64_pcie_offset_reg_spare_control_load_2_hw_ld), |
| 1642 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_write (mem_64_pcie_offset_reg_spare_control_load_2_hw_write), |
| 1643 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_read (mem_64_pcie_offset_reg_spare_control_load_2_hw_read), |
| 1644 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_ld (mem_64_pcie_offset_reg_spare_control_load_1_hw_ld), |
| 1645 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_write (mem_64_pcie_offset_reg_spare_control_load_1_hw_write), |
| 1646 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_read (mem_64_pcie_offset_reg_spare_control_load_1_hw_read), |
| 1647 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_ld (mem_64_pcie_offset_reg_spare_control_load_0_hw_ld), |
| 1648 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_write (mem_64_pcie_offset_reg_spare_control_load_0_hw_write), |
| 1649 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_read (mem_64_pcie_offset_reg_spare_control_load_0_hw_read), |
| 1650 | .mem_64_pcie_offset_reg_spare_control_hw_write (mem_64_pcie_offset_reg_spare_control_hw_write), |
| 1651 | .mem_64_pcie_offset_reg_spare_control_hw_read (mem_64_pcie_offset_reg_spare_control_hw_read), |
| 1652 | .mem_64_pcie_offset_reg_spare_status_hw_read (mem_64_pcie_offset_reg_spare_status_hw_read) |
| 1653 | ); |
| 1654 | |
| 1655 | endmodule // dmu_imu_ics_default_grp |