| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_stage_mux_only.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_stage_mux_only |
| 36 | ( |
| 37 | clk, |
| 38 | read_data_0, |
| 39 | imu_error_log_en_reg_select_pulse, |
| 40 | imu_error_log_en_reg_select_pulse_out, |
| 41 | imu_int_en_reg_select_pulse, |
| 42 | imu_int_en_reg_select_pulse_out, |
| 43 | imu_enabled_error_status_reg_select, |
| 44 | imu_enabled_error_status_reg_select_out, |
| 45 | imu_logged_error_status_reg_select_pulse, |
| 46 | imu_logged_error_status_reg_select_pulse_out, |
| 47 | imu_rds_error_log_reg_select_pulse, |
| 48 | imu_rds_error_log_reg_select_pulse_out, |
| 49 | imu_scs_error_log_reg_select_pulse, |
| 50 | imu_scs_error_log_reg_select_pulse_out, |
| 51 | imu_eqs_error_log_reg_select_pulse, |
| 52 | imu_eqs_error_log_reg_select_pulse_out, |
| 53 | dmc_interrupt_mask_reg_select_pulse, |
| 54 | dmc_interrupt_mask_reg_select_pulse_out, |
| 55 | dmc_interrupt_status_reg_select, |
| 56 | dmc_interrupt_status_reg_select_out, |
| 57 | imu_perf_cntrl_select_pulse, |
| 58 | imu_perf_cntrl_select_pulse_out, |
| 59 | imu_perf_cnt0_select_pulse, |
| 60 | imu_perf_cnt0_select_pulse_out, |
| 61 | imu_perf_cnt1_select_pulse, |
| 62 | imu_perf_cnt1_select_pulse_out, |
| 63 | msi_32_addr_reg_select_pulse, |
| 64 | msi_32_addr_reg_select_pulse_out, |
| 65 | msi_64_addr_reg_select_pulse, |
| 66 | msi_64_addr_reg_select_pulse_out, |
| 67 | mem_64_pcie_offset_reg_select_pulse, |
| 68 | mem_64_pcie_offset_reg_select_pulse_out, |
| 69 | imu_logged_error_status_reg_rw1c_alias, |
| 70 | imu_logged_error_status_reg_rw1c_alias_out, |
| 71 | imu_logged_error_status_reg_rw1s_alias, |
| 72 | imu_logged_error_status_reg_rw1s_alias_out, |
| 73 | daemon_csrbus_wr_in, |
| 74 | daemon_csrbus_wr_out, |
| 75 | daemon_csrbus_wr_data_in, |
| 76 | daemon_csrbus_wr_data_out, |
| 77 | read_data_0_out, |
| 78 | rst_l, |
| 79 | rst_l_out, |
| 80 | por_l, |
| 81 | por_l_out |
| 82 | ); |
| 83 | |
| 84 | //==================================================== |
| 85 | // Polarity declarations |
| 86 | //==================================================== |
| 87 | input clk; // Clock signal |
| 88 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data |
| 89 | input imu_error_log_en_reg_select_pulse; // select |
| 90 | output imu_error_log_en_reg_select_pulse_out; // select |
| 91 | input imu_int_en_reg_select_pulse; // select |
| 92 | output imu_int_en_reg_select_pulse_out; // select |
| 93 | input imu_enabled_error_status_reg_select; // select |
| 94 | output imu_enabled_error_status_reg_select_out; // select |
| 95 | input imu_logged_error_status_reg_select_pulse; // select |
| 96 | output imu_logged_error_status_reg_select_pulse_out; // select |
| 97 | input imu_rds_error_log_reg_select_pulse; // select |
| 98 | output imu_rds_error_log_reg_select_pulse_out; // select |
| 99 | input imu_scs_error_log_reg_select_pulse; // select |
| 100 | output imu_scs_error_log_reg_select_pulse_out; // select |
| 101 | input imu_eqs_error_log_reg_select_pulse; // select |
| 102 | output imu_eqs_error_log_reg_select_pulse_out; // select |
| 103 | input dmc_interrupt_mask_reg_select_pulse; // select |
| 104 | output dmc_interrupt_mask_reg_select_pulse_out; // select |
| 105 | input dmc_interrupt_status_reg_select; // select |
| 106 | output dmc_interrupt_status_reg_select_out; // select |
| 107 | input imu_perf_cntrl_select_pulse; // select |
| 108 | output imu_perf_cntrl_select_pulse_out; // select |
| 109 | input imu_perf_cnt0_select_pulse; // select |
| 110 | output imu_perf_cnt0_select_pulse_out; // select |
| 111 | input imu_perf_cnt1_select_pulse; // select |
| 112 | output imu_perf_cnt1_select_pulse_out; // select |
| 113 | input msi_32_addr_reg_select_pulse; // select |
| 114 | output msi_32_addr_reg_select_pulse_out; // select |
| 115 | input msi_64_addr_reg_select_pulse; // select |
| 116 | output msi_64_addr_reg_select_pulse_out; // select |
| 117 | input mem_64_pcie_offset_reg_select_pulse; // select |
| 118 | output mem_64_pcie_offset_reg_select_pulse_out; // select |
| 119 | input imu_logged_error_status_reg_rw1c_alias; // SW load |
| 120 | output imu_logged_error_status_reg_rw1c_alias_out; // alias |
| 121 | input imu_logged_error_status_reg_rw1s_alias; // SW load |
| 122 | output imu_logged_error_status_reg_rw1s_alias_out; // alias |
| 123 | input daemon_csrbus_wr_in; // csrbus_wr |
| 124 | output daemon_csrbus_wr_out; // csrbus_wr |
| 125 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 126 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write |
| 127 | // data |
| 128 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 129 | input rst_l; // HW reset |
| 130 | output rst_l_out; // HW reset |
| 131 | input por_l; // HW reset |
| 132 | output por_l_out; // HW reset |
| 133 | |
| 134 | //==================================================== |
| 135 | // Type declarations |
| 136 | //==================================================== |
| 137 | wire clk; // Clock signal |
| 138 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data |
| 139 | wire imu_error_log_en_reg_select_pulse; // select |
| 140 | wire imu_error_log_en_reg_select_pulse_out; // select |
| 141 | wire imu_int_en_reg_select_pulse; // select |
| 142 | wire imu_int_en_reg_select_pulse_out; // select |
| 143 | wire imu_enabled_error_status_reg_select; // select |
| 144 | wire imu_enabled_error_status_reg_select_out; // select |
| 145 | wire imu_logged_error_status_reg_select_pulse; // select |
| 146 | wire imu_logged_error_status_reg_select_pulse_out; // select |
| 147 | wire imu_rds_error_log_reg_select_pulse; // select |
| 148 | wire imu_rds_error_log_reg_select_pulse_out; // select |
| 149 | wire imu_scs_error_log_reg_select_pulse; // select |
| 150 | wire imu_scs_error_log_reg_select_pulse_out; // select |
| 151 | wire imu_eqs_error_log_reg_select_pulse; // select |
| 152 | wire imu_eqs_error_log_reg_select_pulse_out; // select |
| 153 | wire dmc_interrupt_mask_reg_select_pulse; // select |
| 154 | wire dmc_interrupt_mask_reg_select_pulse_out; // select |
| 155 | wire dmc_interrupt_status_reg_select; // select |
| 156 | wire dmc_interrupt_status_reg_select_out; // select |
| 157 | wire imu_perf_cntrl_select_pulse; // select |
| 158 | wire imu_perf_cntrl_select_pulse_out; // select |
| 159 | wire imu_perf_cnt0_select_pulse; // select |
| 160 | wire imu_perf_cnt0_select_pulse_out; // select |
| 161 | wire imu_perf_cnt1_select_pulse; // select |
| 162 | wire imu_perf_cnt1_select_pulse_out; // select |
| 163 | wire msi_32_addr_reg_select_pulse; // select |
| 164 | wire msi_32_addr_reg_select_pulse_out; // select |
| 165 | wire msi_64_addr_reg_select_pulse; // select |
| 166 | wire msi_64_addr_reg_select_pulse_out; // select |
| 167 | wire mem_64_pcie_offset_reg_select_pulse; // select |
| 168 | wire mem_64_pcie_offset_reg_select_pulse_out; // select |
| 169 | wire imu_logged_error_status_reg_rw1c_alias; // SW load |
| 170 | wire imu_logged_error_status_reg_rw1c_alias_out; // alias |
| 171 | wire imu_logged_error_status_reg_rw1s_alias; // SW load |
| 172 | wire imu_logged_error_status_reg_rw1s_alias_out; // alias |
| 173 | wire daemon_csrbus_wr_in; // csrbus_wr |
| 174 | wire daemon_csrbus_wr_out; // csrbus_wr |
| 175 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 176 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data |
| 177 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 178 | wire rst_l; // HW reset |
| 179 | wire rst_l_out; // HW reset |
| 180 | wire por_l; // HW reset |
| 181 | wire por_l_out; // HW reset |
| 182 | |
| 183 | |
| 184 | //==================================================== |
| 185 | // Assignments only |
| 186 | //==================================================== |
| 187 | assign imu_error_log_en_reg_select_pulse_out = imu_error_log_en_reg_select_pulse; |
| 188 | assign imu_int_en_reg_select_pulse_out = imu_int_en_reg_select_pulse; |
| 189 | assign imu_enabled_error_status_reg_select_out = imu_enabled_error_status_reg_select; |
| 190 | assign imu_logged_error_status_reg_select_pulse_out = imu_logged_error_status_reg_select_pulse; |
| 191 | assign imu_rds_error_log_reg_select_pulse_out = imu_rds_error_log_reg_select_pulse; |
| 192 | assign imu_scs_error_log_reg_select_pulse_out = imu_scs_error_log_reg_select_pulse; |
| 193 | assign imu_eqs_error_log_reg_select_pulse_out = imu_eqs_error_log_reg_select_pulse; |
| 194 | assign dmc_interrupt_mask_reg_select_pulse_out = dmc_interrupt_mask_reg_select_pulse; |
| 195 | assign dmc_interrupt_status_reg_select_out = dmc_interrupt_status_reg_select; |
| 196 | assign imu_perf_cntrl_select_pulse_out = imu_perf_cntrl_select_pulse; |
| 197 | assign imu_perf_cnt0_select_pulse_out = imu_perf_cnt0_select_pulse; |
| 198 | assign imu_perf_cnt1_select_pulse_out = imu_perf_cnt1_select_pulse; |
| 199 | assign msi_32_addr_reg_select_pulse_out = msi_32_addr_reg_select_pulse; |
| 200 | assign msi_64_addr_reg_select_pulse_out = msi_64_addr_reg_select_pulse; |
| 201 | assign mem_64_pcie_offset_reg_select_pulse_out = mem_64_pcie_offset_reg_select_pulse; |
| 202 | assign imu_logged_error_status_reg_rw1c_alias_out = imu_logged_error_status_reg_rw1c_alias; |
| 203 | assign imu_logged_error_status_reg_rw1s_alias_out = imu_logged_error_status_reg_rw1s_alias; |
| 204 | assign rst_l_out = rst_l; |
| 205 | assign por_l_out = por_l; |
| 206 | assign daemon_csrbus_wr_out = daemon_csrbus_wr_in; |
| 207 | assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in; |
| 208 | |
| 209 | |
| 210 | //===================================================== |
| 211 | // OUTPUT: read_data_out |
| 212 | //===================================================== |
| 213 | dmu_imu_ics_csrpipe_5 dmu_imu_ics_csrpipe_5_inst_1 |
| 214 | ( |
| 215 | .clk (clk), |
| 216 | .rst_l (rst_l), |
| 217 | .reg_in (1'b0), |
| 218 | .reg_out (1'b0), |
| 219 | .data0 (read_data_0), |
| 220 | .sel0 (1'b1), |
| 221 | .data1 (64'b0), |
| 222 | .sel1 (1'b1), |
| 223 | .data2 (64'b0), |
| 224 | .sel2 (1'b1), |
| 225 | .data3 (64'b0), |
| 226 | .sel3 (1'b1), |
| 227 | .data4 (64'b0), |
| 228 | .sel4 (1'b1), |
| 229 | .out (read_data_0_out) |
| 230 | ); |
| 231 | |
| 232 | endmodule // dmu_imu_ics_stage_mux_only |