| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_iss.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_iss ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // External Interrupt Signals |
| 43 | |
| 44 | // j2d_ext_int_l, |
| 45 | |
| 46 | // INT X Interrupt Signals |
| 47 | |
| 48 | rds2iss_intx_int_l, |
| 49 | |
| 50 | // EQ Interrupt Signals |
| 51 | |
| 52 | eqs2iss_eq_int_l, |
| 53 | |
| 54 | // I2C Interrupt Signals |
| 55 | |
| 56 | // j2d_i2c0_int_l, |
| 57 | // j2d_i2c1_int_l, |
| 58 | |
| 59 | // Internal Core Interrupt Signals |
| 60 | |
| 61 | ics2iss_mondo_62_int_l, |
| 62 | ics2iss_mondo_63_int_l, |
| 63 | // j2d_jbc_int_l, |
| 64 | |
| 65 | // Mondo Request Outputs to GCS |
| 66 | |
| 67 | iss2gcs_gc_0_mdo_needed, |
| 68 | iss2gcs_gc_1_mdo_needed, |
| 69 | iss2gcs_gc_2_mdo_needed, |
| 70 | iss2gcs_gc_3_mdo_needed, |
| 71 | |
| 72 | // CPU ID Request Inputs from GCS |
| 73 | |
| 74 | gcs2iss_tid_req, |
| 75 | gcs2iss_tid_sel, |
| 76 | gcs2iss_mdo_pending, |
| 77 | |
| 78 | // CPU ID Response Outputs to GCS |
| 79 | |
| 80 | iss2gcs_tid_ack, |
| 81 | iss2gcs_tid, |
| 82 | iss2gcs_mondo_mode, |
| 83 | |
| 84 | // Retry Timer Counter Limit to GCS |
| 85 | |
| 86 | iss2gcs_counter_limit, |
| 87 | |
| 88 | // CSR Bus Signals |
| 89 | |
| 90 | csrbus_valid, |
| 91 | csrbus_done, |
| 92 | csrbus_mapped, |
| 93 | csrbus_wr_data, |
| 94 | csrbus_wr, |
| 95 | csrbus_read_data, |
| 96 | csrbus_addr, |
| 97 | csrbus_src_bus, |
| 98 | csrbus_acc_vio, |
| 99 | |
| 100 | // Static ID Sel |
| 101 | |
| 102 | j2d_instance_id, |
| 103 | |
| 104 | |
| 105 | // Debug Ports |
| 106 | |
| 107 | dbg2iss_dbg_sel_a, |
| 108 | dbg2iss_dbg_sel_b, |
| 109 | iss2dbg_dbg_a, |
| 110 | iss2dbg_dbg_b |
| 111 | |
| 112 | ); |
| 113 | |
| 114 | |
| 115 | //############################################################################ |
| 116 | // PORT DECLARATIONS |
| 117 | //############################################################################ |
| 118 | |
| 119 | |
| 120 | //------------------------------------------------------------------------ |
| 121 | // Clock and Reset Signals |
| 122 | //------------------------------------------------------------------------ |
| 123 | input clk; |
| 124 | input rst_l; |
| 125 | |
| 126 | //------------------------------------------------------------------------ |
| 127 | // External Interrupt Signals |
| 128 | //------------------------------------------------------------------------ |
| 129 | // input [19:0] j2d_ext_int_l; |
| 130 | |
| 131 | |
| 132 | //------------------------------------------------------------------------ |
| 133 | // INT X Interrupt Signals |
| 134 | //------------------------------------------------------------------------ |
| 135 | input [3:0] rds2iss_intx_int_l; |
| 136 | |
| 137 | |
| 138 | //------------------------------------------------------------------------ |
| 139 | // EQ Interrupt Signals |
| 140 | //------------------------------------------------------------------------ |
| 141 | input [35:0] eqs2iss_eq_int_l; |
| 142 | |
| 143 | |
| 144 | //------------------------------------------------------------------------ |
| 145 | // I2C Interrupt Signals |
| 146 | //------------------------------------------------------------------------ |
| 147 | // input j2d_i2c0_int_l; |
| 148 | // input j2d_i2c1_int_l; |
| 149 | |
| 150 | //------------------------------------------------------------------------ |
| 151 | // Internal Core Interrupt Signals |
| 152 | //------------------------------------------------------------------------ |
| 153 | input ics2iss_mondo_62_int_l; |
| 154 | input ics2iss_mondo_63_int_l; |
| 155 | // input j2d_jbc_int_l; |
| 156 | |
| 157 | |
| 158 | //------------------------------------------------------------------------ |
| 159 | // Mondo Requests Going to each of the 4 group controllers |
| 160 | //------------------------------------------------------------------------ |
| 161 | |
| 162 | output [63:0] iss2gcs_gc_0_mdo_needed; //Requests to issue and interrupt from GC 0 |
| 163 | output [63:0] iss2gcs_gc_1_mdo_needed; //Requests to issue and interrupt from GC 1 |
| 164 | output [63:0] iss2gcs_gc_2_mdo_needed; //Requests to issue and interrupt from GC 2 |
| 165 | output [63:0] iss2gcs_gc_3_mdo_needed; //Requests to issue and interrupt from GC 3 |
| 166 | |
| 167 | //------------------------------------------------------------------------ |
| 168 | // Requests to INT state for TID and to move winner to PENDING |
| 169 | //------------------------------------------------------------------------ |
| 170 | |
| 171 | input gcs2iss_tid_req; // Request to ISS for TID for accepted mondo |
| 172 | input [5:0] gcs2iss_tid_sel; // Select for the TID output mux |
| 173 | input [63:0] gcs2iss_mdo_pending; // ID of mondo that was accecpted |
| 174 | |
| 175 | output iss2gcs_tid_ack; // ACK Qualifier for tid of mondo |
| 176 | output [5:0] iss2gcs_tid; // TID of mondo |
| 177 | output iss2gcs_mondo_mode; // Mondo Mode of the Mondo |
| 178 | |
| 179 | |
| 180 | //------------------------------------------------------------------------ |
| 181 | // PIO INTERFACE |
| 182 | //------------------------------------------------------------------------ |
| 183 | |
| 184 | output [24:0] iss2gcs_counter_limit; // COunter Limit for the Mondo Retry Counter |
| 185 | |
| 186 | //------------------------------------------------------------------------ |
| 187 | // PIO INTERFACE |
| 188 | //------------------------------------------------------------------------ |
| 189 | input csrbus_valid; |
| 190 | output csrbus_done; |
| 191 | output csrbus_mapped; |
| 192 | |
| 193 | input [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_wr_data; |
| 194 | input csrbus_wr; |
| 195 | |
| 196 | output [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_read_data; |
| 197 | |
| 198 | input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] csrbus_addr; |
| 199 | |
| 200 | input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] csrbus_src_bus; |
| 201 | output csrbus_acc_vio; |
| 202 | |
| 203 | |
| 204 | |
| 205 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; |
| 206 | |
| 207 | //------------------------------------------------------------------------ |
| 208 | // Debug Ports |
| 209 | //------------------------------------------------------------------------ |
| 210 | |
| 211 | input [2:0] dbg2iss_dbg_sel_a; |
| 212 | input [2:0] dbg2iss_dbg_sel_b; |
| 213 | output [`FIRE_DEBUG_WDTH-1:0] iss2dbg_dbg_a; |
| 214 | output [`FIRE_DEBUG_WDTH-1:0] iss2dbg_dbg_b; |
| 215 | |
| 216 | |
| 217 | //############################################################################ |
| 218 | // SIGNAL DECLARATIONS |
| 219 | //############################################################################ |
| 220 | |
| 221 | //************************************************** |
| 222 | // Wires |
| 223 | //************************************************** |
| 224 | |
| 225 | //------------------------------------------------------------------------ |
| 226 | // Wires for the CSR access to the state machines |
| 227 | //------------------------------------------------------------------------ |
| 228 | |
| 229 | wire [1:0] sw_state_data; // The two bits of data to control the state of each Mondo |
| 230 | wire sw_state_wr; // Write strobe saying PIO is to a state reg |
| 231 | |
| 232 | wire ext_wr; // Signals from the PIO controller that serve the same purpose as above |
| 233 | wire [1:0] int_state_ext_wr_data; |
| 234 | |
| 235 | //------------------------------------------------------------------------ |
| 236 | // Wires for setting up the maskes for each of the group controllers |
| 237 | //------------------------------------------------------------------------ |
| 238 | wire [63:0] g0_mask; |
| 239 | wire [63:0] g1_mask; |
| 240 | wire [63:0] g2_mask; |
| 241 | wire [63:0] g3_mask; |
| 242 | wire [63:0] group_valid; |
| 243 | |
| 244 | wire [23:0] sw_mondo_state_1; |
| 245 | wire [63:0] sw_mondo_state_2; |
| 246 | |
| 247 | wire [63:0] mondo_state_vector_0; |
| 248 | wire [63:0] mondo_state_vector_1; |
| 249 | |
| 250 | |
| 251 | //------------------ |
| 252 | // Mondo Mode Bits |
| 253 | //------------------ |
| 254 | wire mondo_mode_0, mondo_mode_1, mondo_mode_2, mondo_mode_3, mondo_mode_4, mondo_mode_5, mondo_mode_6, mondo_mode_7; |
| 255 | wire mondo_mode_8, mondo_mode_9, mondo_mode_10, mondo_mode_11, mondo_mode_12, mondo_mode_13, mondo_mode_14, mondo_mode_15; |
| 256 | wire mondo_mode_16, mondo_mode_17, mondo_mode_18, mondo_mode_19, mondo_mode_20, mondo_mode_21, mondo_mode_22, mondo_mode_23; |
| 257 | wire mondo_mode_24, mondo_mode_25, mondo_mode_26, mondo_mode_27, mondo_mode_28, mondo_mode_29, mondo_mode_30, mondo_mode_31; |
| 258 | wire mondo_mode_32, mondo_mode_33, mondo_mode_34, mondo_mode_35, mondo_mode_36, mondo_mode_37, mondo_mode_38, mondo_mode_39; |
| 259 | wire mondo_mode_40, mondo_mode_41, mondo_mode_42, mondo_mode_43, mondo_mode_44, mondo_mode_45, mondo_mode_46, mondo_mode_47; |
| 260 | wire mondo_mode_48, mondo_mode_49, mondo_mode_50, mondo_mode_51, mondo_mode_52, mondo_mode_53, mondo_mode_54, mondo_mode_55; |
| 261 | wire mondo_mode_56, mondo_mode_57, mondo_mode_58, mondo_mode_59, mondo_mode_60, mondo_mode_61, mondo_mode_62, mondo_mode_63; |
| 262 | |
| 263 | |
| 264 | |
| 265 | //------------------ |
| 266 | // Mondo Valid Bits |
| 267 | //------------------ |
| 268 | wire valid_0, valid_1, valid_2, valid_3, valid_4, valid_5, valid_6, valid_7; |
| 269 | wire valid_8, valid_9, valid_10, valid_11, valid_12, valid_13, valid_14, valid_15; |
| 270 | wire valid_16, valid_17, valid_18, valid_19, valid_20, valid_21, valid_22, valid_23; |
| 271 | wire valid_24, valid_25, valid_26, valid_27, valid_28, valid_29, valid_30, valid_31; |
| 272 | wire valid_32, valid_33, valid_34, valid_35, valid_36, valid_37, valid_38, valid_39; |
| 273 | wire valid_40, valid_41, valid_42, valid_43, valid_44, valid_45, valid_46, valid_47; |
| 274 | wire valid_48, valid_49, valid_50, valid_51, valid_52, valid_53, valid_54, valid_55; |
| 275 | wire valid_56, valid_57, valid_58, valid_59, valid_60, valid_61, valid_62, valid_63; |
| 276 | |
| 277 | |
| 278 | //------------------ |
| 279 | // Mondo Group Bits |
| 280 | //------------------ |
| 281 | wire [3:0] group_0, group_1, group_2, group_3, group_4, group_5, group_6, group_7; |
| 282 | wire [3:0] group_8, group_9, group_10, group_11, group_12, group_13, group_14, group_15; |
| 283 | wire [3:0] group_16, group_17, group_18, group_19, group_20, group_21, group_22, group_23; |
| 284 | wire [3:0] group_24, group_25, group_26, group_27, group_28, group_29, group_30, group_31; |
| 285 | wire [3:0] group_32, group_33, group_34, group_35, group_36, group_37, group_38, group_39; |
| 286 | wire [3:0] group_40, group_41, group_42, group_43, group_44, group_45, group_46, group_47; |
| 287 | wire [3:0] group_48, group_49, group_50, group_51, group_52, group_53, group_54, group_55; |
| 288 | wire [3:0] group_56, group_57, group_58, group_59, group_60, group_61, group_62, group_63; |
| 289 | |
| 290 | |
| 291 | //------------------ |
| 292 | // Mondo TID Bits |
| 293 | //------------------ |
| 294 | wire [5:0] tid_0, tid_1, tid_2, tid_3, tid_4, tid_5, tid_6, tid_7; |
| 295 | wire [5:0] tid_8, tid_9, tid_10, tid_11, tid_12, tid_13, tid_14, tid_15; |
| 296 | wire [5:0] tid_16, tid_17, tid_18, tid_19, tid_20, tid_21, tid_22, tid_23; |
| 297 | wire [5:0] tid_24, tid_25, tid_26, tid_27, tid_28, tid_29, tid_30, tid_31; |
| 298 | wire [5:0] tid_32, tid_33, tid_34, tid_35, tid_36, tid_37, tid_38, tid_39; |
| 299 | wire [5:0] tid_40, tid_41, tid_42, tid_43, tid_44, tid_45, tid_46, tid_47; |
| 300 | wire [5:0] tid_48, tid_49, tid_50, tid_51, tid_52, tid_53, tid_54, tid_55; |
| 301 | wire [5:0] tid_56, tid_57, tid_58, tid_59, tid_60, tid_61, tid_62, tid_63; |
| 302 | |
| 303 | |
| 304 | |
| 305 | |
| 306 | //------------------------- |
| 307 | // Mondo State Bits |
| 308 | //------------------------- |
| 309 | |
| 310 | wire [1:0] mondo_state_0, mondo_state_1, mondo_state_2, mondo_state_3, mondo_state_4, mondo_state_5, mondo_state_6, mondo_state_7; |
| 311 | wire [1:0] mondo_state_8, mondo_state_9, mondo_state_10, mondo_state_11, mondo_state_12, mondo_state_13, mondo_state_14, mondo_state_15; |
| 312 | wire [1:0] mondo_state_16, mondo_state_17, mondo_state_18, mondo_state_19, mondo_state_20, mondo_state_21, mondo_state_22, mondo_state_23; |
| 313 | wire [1:0] mondo_state_24, mondo_state_25, mondo_state_26, mondo_state_27, mondo_state_28, mondo_state_29, mondo_state_30, mondo_state_31; |
| 314 | wire [1:0] mondo_state_32, mondo_state_33, mondo_state_34, mondo_state_35, mondo_state_36, mondo_state_37, mondo_state_38, mondo_state_39; |
| 315 | wire [1:0] mondo_state_40, mondo_state_41, mondo_state_42, mondo_state_43, mondo_state_44, mondo_state_45, mondo_state_46, mondo_state_47; |
| 316 | wire [1:0] mondo_state_48, mondo_state_49, mondo_state_50, mondo_state_51, mondo_state_52, mondo_state_53, mondo_state_54, mondo_state_55; |
| 317 | wire [1:0] mondo_state_56, mondo_state_57, mondo_state_58, mondo_state_59, mondo_state_60, mondo_state_61, mondo_state_62, mondo_state_63; |
| 318 | |
| 319 | |
| 320 | //---------------------------------- |
| 321 | // SW Address selects for the state |
| 322 | //---------------------------------- |
| 323 | |
| 324 | wire sw_state_addr_sel_0, sw_state_addr_sel_1, sw_state_addr_sel_2, sw_state_addr_sel_3, sw_state_addr_sel_4, sw_state_addr_sel_5, sw_state_addr_sel_6, sw_state_addr_sel_7; |
| 325 | wire sw_state_addr_sel_8, sw_state_addr_sel_9, sw_state_addr_sel_10, sw_state_addr_sel_11, sw_state_addr_sel_12, sw_state_addr_sel_13, sw_state_addr_sel_14, sw_state_addr_sel_15; |
| 326 | wire sw_state_addr_sel_16, sw_state_addr_sel_17, sw_state_addr_sel_18, sw_state_addr_sel_19, sw_state_addr_sel_20, sw_state_addr_sel_21, sw_state_addr_sel_22, sw_state_addr_sel_23; |
| 327 | wire sw_state_addr_sel_24, sw_state_addr_sel_25, sw_state_addr_sel_26, sw_state_addr_sel_27, sw_state_addr_sel_28, sw_state_addr_sel_29, sw_state_addr_sel_30, sw_state_addr_sel_31; |
| 328 | wire sw_state_addr_sel_32, sw_state_addr_sel_33, sw_state_addr_sel_34, sw_state_addr_sel_35, sw_state_addr_sel_36, sw_state_addr_sel_37, sw_state_addr_sel_38, sw_state_addr_sel_39; |
| 329 | wire sw_state_addr_sel_40, sw_state_addr_sel_41, sw_state_addr_sel_42, sw_state_addr_sel_43, sw_state_addr_sel_44, sw_state_addr_sel_45, sw_state_addr_sel_46, sw_state_addr_sel_47; |
| 330 | wire sw_state_addr_sel_48, sw_state_addr_sel_49, sw_state_addr_sel_50, sw_state_addr_sel_51, sw_state_addr_sel_52, sw_state_addr_sel_53, sw_state_addr_sel_54, sw_state_addr_sel_55; |
| 331 | wire sw_state_addr_sel_56, sw_state_addr_sel_57, sw_state_addr_sel_58, sw_state_addr_sel_59, sw_state_addr_sel_60, sw_state_addr_sel_61, sw_state_addr_sel_62, sw_state_addr_sel_63; |
| 332 | |
| 333 | |
| 334 | //----------------------------------------------------- |
| 335 | // Wires used to take FSM's from RECEIVED to PENDING |
| 336 | //----------------------------------------------------- |
| 337 | |
| 338 | wire int_scheduled_0, int_scheduled_1, int_scheduled_2, int_scheduled_3, int_scheduled_4, int_scheduled_5, int_scheduled_6, int_scheduled_7; |
| 339 | wire int_scheduled_8, int_scheduled_9, int_scheduled_10, int_scheduled_11, int_scheduled_12, int_scheduled_13, int_scheduled_14, int_scheduled_15; |
| 340 | wire int_scheduled_16, int_scheduled_17, int_scheduled_18, int_scheduled_19, int_scheduled_20, int_scheduled_21, int_scheduled_22, int_scheduled_23; |
| 341 | wire int_scheduled_24, int_scheduled_25, int_scheduled_26, int_scheduled_27, int_scheduled_28, int_scheduled_29, int_scheduled_30, int_scheduled_31; |
| 342 | wire int_scheduled_32, int_scheduled_33, int_scheduled_34, int_scheduled_35, int_scheduled_36, int_scheduled_37, int_scheduled_38, int_scheduled_39; |
| 343 | wire int_scheduled_40, int_scheduled_41, int_scheduled_42, int_scheduled_43, int_scheduled_44, int_scheduled_45, int_scheduled_46, int_scheduled_47; |
| 344 | wire int_scheduled_48, int_scheduled_49, int_scheduled_50, int_scheduled_51, int_scheduled_52, int_scheduled_53, int_scheduled_54, int_scheduled_55; |
| 345 | wire int_scheduled_56, int_scheduled_57, int_scheduled_58, int_scheduled_59, int_scheduled_60, int_scheduled_61, int_scheduled_62, int_scheduled_63; |
| 346 | |
| 347 | |
| 348 | |
| 349 | //-------------------------------------------------------- |
| 350 | // Wires used for ext wr_data for Int_clr_reg |
| 351 | //-------------------------------------------------------- |
| 352 | |
| 353 | wire [1:0] int_state_20_ext_wr_data,int_state_21_ext_wr_data,int_state_22_ext_wr_data,int_state_23_ext_wr_data,int_state_24_ext_wr_data,int_state_25_ext_wr_data,int_state_26_ext_wr_data,int_state_27_ext_wr_data,int_state_28_ext_wr_data,int_state_29_ext_wr_data; |
| 354 | wire [1:0] int_state_30_ext_wr_data,int_state_31_ext_wr_data,int_state_32_ext_wr_data,int_state_33_ext_wr_data,int_state_34_ext_wr_data,int_state_35_ext_wr_data,int_state_36_ext_wr_data,int_state_37_ext_wr_data,int_state_38_ext_wr_data,int_state_39_ext_wr_data; |
| 355 | wire [1:0] int_state_40_ext_wr_data,int_state_41_ext_wr_data,int_state_42_ext_wr_data,int_state_43_ext_wr_data,int_state_44_ext_wr_data,int_state_45_ext_wr_data,int_state_46_ext_wr_data,int_state_47_ext_wr_data,int_state_48_ext_wr_data,int_state_49_ext_wr_data; |
| 356 | wire [1:0] int_state_50_ext_wr_data,int_state_51_ext_wr_data,int_state_52_ext_wr_data,int_state_53_ext_wr_data,int_state_54_ext_wr_data,int_state_55_ext_wr_data,int_state_56_ext_wr_data,int_state_57_ext_wr_data,int_state_58_ext_wr_data,int_state_59_ext_wr_data; |
| 357 | wire [1:0] int_state_62_ext_wr_data,int_state_63_ext_wr_data; |
| 358 | |
| 359 | //************************************************** |
| 360 | // Registers that Are Not Flops |
| 361 | //************************************************** |
| 362 | |
| 363 | //---------------------------------------------------------- |
| 364 | // Registres used for output muxing of TID value back to GCS |
| 365 | //--------------------------------------------------------- |
| 366 | reg [6:0] tid_mux_0; |
| 367 | reg [6:0] tid_mux_1; |
| 368 | reg [6:0] tid_mux_2; |
| 369 | reg [6:0] tid_mux_3; |
| 370 | reg [6:0] tid_mux_4; |
| 371 | reg [6:0] tid_mux_5; |
| 372 | reg [6:0] tid_mux_6; |
| 373 | reg [6:0] tid_mux_7; |
| 374 | reg [6:0] tid_mux; |
| 375 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_a; |
| 376 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_b; |
| 377 | |
| 378 | |
| 379 | //************************************************** |
| 380 | // Registers that Are Flops |
| 381 | //************************************************** |
| 382 | reg tid_req_reg; // Register to hold the value of the req signal |
| 383 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_a; |
| 384 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_b; |
| 385 | |
| 386 | //############################################################################ |
| 387 | // ZERO IN CHECKERS |
| 388 | //############################################################################ |
| 389 | |
| 390 | //----------------------------------------------------- |
| 391 | // Make Sure only 1 bit is ever set |
| 392 | //----------------------------------------------------- |
| 393 | |
| 394 | //0in bits_on -var gcs2iss_mdo_pending -max 1 |
| 395 | |
| 396 | |
| 397 | //############################################################################ |
| 398 | // COMBINATIONAL LOGIC |
| 399 | //############################################################################ |
| 400 | |
| 401 | //------------------------------------------------------- |
| 402 | // Assigning signals from DCM to names for FSM's |
| 403 | //------------------------------------------------------- |
| 404 | assign int_state_ext_wr_data = int_state_20_ext_wr_data; |
| 405 | assign sw_state_wr = ext_wr; |
| 406 | assign sw_state_data = int_state_ext_wr_data; |
| 407 | |
| 408 | |
| 409 | //---------------------------------------------------------- |
| 410 | // Getting the state for all of the Mondos for Software |
| 411 | //---------------------------------------------------------- |
| 412 | |
| 413 | assign sw_mondo_state_1 = |
| 414 | { mondo_state_31[1], mondo_state_31[0], mondo_state_30[1], mondo_state_30[0], mondo_state_29[1], mondo_state_29[0], |
| 415 | mondo_state_28[1], mondo_state_28[0], mondo_state_27[1], mondo_state_27[0], mondo_state_26[1], mondo_state_26[0], |
| 416 | mondo_state_25[1], mondo_state_25[0], mondo_state_24[1], mondo_state_24[0], mondo_state_23[1], mondo_state_23[0], |
| 417 | mondo_state_22[1], mondo_state_22[0], mondo_state_21[1], mondo_state_21[0], mondo_state_20[1], mondo_state_20[0] |
| 418 | }; |
| 419 | |
| 420 | |
| 421 | assign sw_mondo_state_2 = |
| 422 | { mondo_state_63[1], mondo_state_63[0], mondo_state_62[1], mondo_state_62[0], 4'b0, |
| 423 | mondo_state_59[1], mondo_state_59[0], mondo_state_58[1], mondo_state_58[0], |
| 424 | mondo_state_57[1], mondo_state_57[0], mondo_state_56[1], mondo_state_56[0], mondo_state_55[1], mondo_state_55[0], |
| 425 | mondo_state_54[1], mondo_state_54[0], mondo_state_53[1], mondo_state_53[0], mondo_state_52[1], mondo_state_52[0], |
| 426 | mondo_state_51[1], mondo_state_51[0], mondo_state_50[1], mondo_state_50[0], mondo_state_49[1], mondo_state_49[0], |
| 427 | mondo_state_48[1], mondo_state_48[0], mondo_state_47[1], mondo_state_47[0], mondo_state_46[1], mondo_state_46[0], |
| 428 | mondo_state_45[1], mondo_state_45[0], mondo_state_44[1], mondo_state_44[0], mondo_state_43[1], mondo_state_43[0], |
| 429 | mondo_state_42[1], mondo_state_42[0], mondo_state_41[1], mondo_state_41[0], mondo_state_40[1], mondo_state_40[0], |
| 430 | mondo_state_39[1], mondo_state_39[0], mondo_state_38[1], mondo_state_38[0], mondo_state_37[1], mondo_state_37[0], |
| 431 | mondo_state_36[1], mondo_state_36[0], mondo_state_35[1], mondo_state_35[0], mondo_state_34[1], mondo_state_34[0], |
| 432 | mondo_state_33[1], mondo_state_33[0], mondo_state_32[1], mondo_state_32[0] |
| 433 | |
| 434 | }; |
| 435 | |
| 436 | //---------------------------------------------------------- |
| 437 | // Getting the state for all of the Mondos at the same time |
| 438 | //---------------------------------------------------------- |
| 439 | |
| 440 | assign mondo_state_vector_0 = |
| 441 | { |
| 442 | mondo_state_63[0], mondo_state_62[0], 2'b0, mondo_state_59[0], mondo_state_58[0], mondo_state_57[0], mondo_state_56[0], |
| 443 | mondo_state_55[0], mondo_state_54[0], mondo_state_53[0], mondo_state_52[0], mondo_state_51[0], mondo_state_50[0], mondo_state_49[0], mondo_state_48[0], |
| 444 | mondo_state_47[0], mondo_state_46[0], mondo_state_45[0], mondo_state_44[0], mondo_state_43[0], mondo_state_42[0], mondo_state_41[0], mondo_state_40[0], |
| 445 | mondo_state_39[0], mondo_state_38[0], mondo_state_37[0], mondo_state_36[0], mondo_state_35[0], mondo_state_34[0], mondo_state_33[0], mondo_state_32[0], |
| 446 | mondo_state_31[0], mondo_state_30[0], mondo_state_29[0], mondo_state_28[0], mondo_state_27[0], mondo_state_26[0], mondo_state_25[0], mondo_state_24[0], |
| 447 | mondo_state_23[0], mondo_state_22[0], mondo_state_21[0], mondo_state_20[0], 20'b0 |
| 448 | }; |
| 449 | |
| 450 | |
| 451 | assign mondo_state_vector_1 = |
| 452 | { |
| 453 | mondo_state_63[1], mondo_state_62[1], 2'b0, mondo_state_59[1], mondo_state_58[1], mondo_state_57[1], mondo_state_56[1], |
| 454 | mondo_state_55[1], mondo_state_54[1], mondo_state_53[1], mondo_state_52[1], mondo_state_51[1], mondo_state_50[1], mondo_state_49[1], mondo_state_48[1], |
| 455 | mondo_state_47[1], mondo_state_46[1], mondo_state_45[1], mondo_state_44[1], mondo_state_43[1], mondo_state_42[1], mondo_state_41[1], mondo_state_40[1], |
| 456 | mondo_state_39[1], mondo_state_38[1], mondo_state_37[1], mondo_state_36[1], mondo_state_35[1], mondo_state_34[1], mondo_state_33[1], mondo_state_32[1], |
| 457 | mondo_state_31[1], mondo_state_30[1], mondo_state_29[1], mondo_state_28[1], mondo_state_27[1], mondo_state_26[1], mondo_state_25[1], mondo_state_24[1], |
| 458 | mondo_state_23[1], mondo_state_22[1], mondo_state_21[1], mondo_state_20[1], 20'b0 |
| 459 | }; |
| 460 | |
| 461 | //---------------------------------------------------------- |
| 462 | // Creating the masks for each of the 4 Group controllers |
| 463 | //---------------------------------------------------------- |
| 464 | |
| 465 | |
| 466 | assign g0_mask = |
| 467 | { |
| 468 | group_63[0], group_62[0], 2'b0, group_59[0], group_58[0], group_57[0], group_56[0], |
| 469 | group_55[0], group_54[0], group_53[0], group_52[0], group_51[0], group_50[0], group_49[0], group_48[0], |
| 470 | group_47[0], group_46[0], group_45[0], group_44[0], group_43[0], group_42[0], group_41[0], group_40[0], |
| 471 | group_39[0], group_38[0], group_37[0], group_36[0], group_35[0], group_34[0], group_33[0], group_32[0], |
| 472 | group_31[0], group_30[0], group_29[0], group_28[0], group_27[0], group_26[0], group_25[0], group_24[0], |
| 473 | group_23[0], group_22[0], group_21[0], group_20[0], 20'b0 |
| 474 | }; |
| 475 | |
| 476 | |
| 477 | assign g1_mask = |
| 478 | { |
| 479 | group_63[1], group_62[1], 2'b0, group_59[1], group_58[1], group_57[1], group_56[1], |
| 480 | group_55[1], group_54[1], group_53[1], group_52[1], group_51[1], group_50[1], group_49[1], group_48[1], |
| 481 | group_47[1], group_46[1], group_45[1], group_44[1], group_43[1], group_42[1], group_41[1], group_40[1], |
| 482 | group_39[1], group_38[1], group_37[1], group_36[1], group_35[1], group_34[1], group_33[1], group_32[1], |
| 483 | group_31[1], group_30[1], group_29[1], group_28[1], group_27[1], group_26[1], group_25[1], group_24[1], |
| 484 | group_23[1], group_22[1], group_21[1], group_20[1], 20'b0 |
| 485 | }; |
| 486 | |
| 487 | |
| 488 | assign g2_mask = |
| 489 | { |
| 490 | group_63[2], group_62[2], 2'b0, group_59[2], group_58[2], group_57[2], group_56[2], |
| 491 | group_55[2], group_54[2], group_53[2], group_52[2], group_51[2], group_50[2], group_49[2], group_48[2], |
| 492 | group_47[2], group_46[2], group_45[2], group_44[2], group_43[2], group_42[2], group_41[2], group_40[2], |
| 493 | group_39[2], group_38[2], group_37[2], group_36[2], group_35[2], group_34[2], group_33[2], group_32[2], |
| 494 | group_31[2], group_30[2], group_29[2], group_28[2], group_27[2], group_26[2], group_25[2], group_24[2], |
| 495 | group_23[2], group_22[2], group_21[2], group_20[2], 20'b0 |
| 496 | }; |
| 497 | |
| 498 | |
| 499 | assign g3_mask = |
| 500 | { |
| 501 | group_63[3], group_62[3], 2'b0, group_59[3], group_58[3], group_57[3], group_56[3], |
| 502 | group_55[3], group_54[3], group_53[3], group_52[3], group_51[3], group_50[3], group_49[3], group_48[3], |
| 503 | group_47[3], group_46[3], group_45[3], group_44[3], group_43[3], group_42[3], group_41[3], group_40[3], |
| 504 | group_39[3], group_38[3], group_37[3], group_36[3], group_35[3], group_34[3], group_33[3], group_32[3], |
| 505 | group_31[3], group_30[3], group_29[3], group_28[3], group_27[3], group_26[3], group_25[3], group_24[3], |
| 506 | group_23[3], group_22[3], group_21[3], group_20[3], 20'b0 |
| 507 | }; |
| 508 | |
| 509 | |
| 510 | //---------------------------------------------------------- |
| 511 | // Creating the valid vector for all mondo's |
| 512 | //---------------------------------------------------------- |
| 513 | |
| 514 | assign group_valid = |
| 515 | { |
| 516 | valid_63, valid_62, 2'b0, valid_59, valid_58, valid_57, valid_56, |
| 517 | valid_55, valid_54, valid_53, valid_52, valid_51, valid_50, valid_49, valid_48, |
| 518 | valid_47, valid_46, valid_45, valid_44, valid_43, valid_42, valid_41, valid_40, |
| 519 | valid_39, valid_38, valid_37, valid_36, valid_35, valid_34, valid_33, valid_32, |
| 520 | valid_31, valid_30, valid_29, valid_28, valid_27, valid_26, valid_25, valid_24, |
| 521 | valid_23, valid_22, valid_21, valid_20, 20'b0 |
| 522 | }; |
| 523 | |
| 524 | //---------------------------------------------------------- |
| 525 | // Logic for the Interrupt vectors waiting to be arbitrated for |
| 526 | // by each of the group controllers |
| 527 | // |
| 528 | // - Each bit can only be asserted in that possition across |
| 529 | // all four of the vectors |
| 530 | // - It will only be assrted if |
| 531 | // - the mondo is in the received state |
| 532 | // - mask allows for it |
| 533 | // - and mondo valid bit is set |
| 534 | // |
| 535 | // |
| 536 | // - There are race conditions here between a mondo |
| 537 | // being selected for arbitration and software |
| 538 | // disableing the valid bit. |
| 539 | // |
| 540 | // - It is possible for the group controller arb to |
| 541 | // select a winner (1 of 64) and not have that Mondo |
| 542 | // yet be in pending as it still needs to be arbed |
| 543 | // for by the GCS arb (1 of 4) So during that window |
| 544 | // it is possible for SW to disable the valid bit. |
| 545 | // Howevere this mondo will still go to pending and |
| 546 | // the interrupt sent. That max time for this race |
| 547 | // condition is 13 clock cycles. As long as software |
| 548 | // doesn't disable the valid bit and read the mondo |
| 549 | // status in less than 13 clock cycles. The results of |
| 550 | // the read will be true. |
| 551 | // |
| 552 | // |
| 553 | //---------------------------------------------------------- |
| 554 | |
| 555 | |
| 556 | assign iss2gcs_gc_0_mdo_needed = ((~mondo_state_vector_1) & mondo_state_vector_0) & g0_mask & group_valid; |
| 557 | assign iss2gcs_gc_1_mdo_needed = ((~mondo_state_vector_1) & mondo_state_vector_0) & g1_mask & group_valid; |
| 558 | assign iss2gcs_gc_2_mdo_needed = ((~mondo_state_vector_1) & mondo_state_vector_0) & g2_mask & group_valid; |
| 559 | assign iss2gcs_gc_3_mdo_needed = ((~mondo_state_vector_1) & mondo_state_vector_0) & g3_mask & group_valid; |
| 560 | |
| 561 | |
| 562 | |
| 563 | //----------------------------------------------------------------- |
| 564 | // This logic is used to select which one of the 64 TID's should |
| 565 | // be sent back to the GCS sub-block. |
| 566 | // |
| 567 | //It is basically a 64 to one mux |
| 568 | // |
| 569 | // It consists of 8, 8 to 1 muxs and then an assignment at the end |
| 570 | //----------------------------------------------------------------- |
| 571 | |
| 572 | // always @ (gcs2iss_tid_sel[2:0] or tid_0 or tid_1 or tid_2 or |
| 573 | // tid_3 or tid_4 or tid_5 or tid_6 or tid_7 or |
| 574 | // mondo_mode_0 or mondo_mode_1 or mondo_mode_2 or mondo_mode_3 or |
| 575 | // mondo_mode_4 or mondo_mode_5 or mondo_mode_6 or mondo_mode_7) |
| 576 | // |
| 577 | // case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 578 | // 3'b000 : tid_mux_0 = {mondo_mode_0,tid_0}; |
| 579 | // 3'b001 : tid_mux_0 = {mondo_mode_1,tid_1}; |
| 580 | // 3'b010 : tid_mux_0 = {mondo_mode_2,tid_2}; |
| 581 | // 3'b011 : tid_mux_0 = {mondo_mode_3,tid_3}; |
| 582 | // 3'b100 : tid_mux_0 = {mondo_mode_4,tid_4}; |
| 583 | // 3'b101 : tid_mux_0 = {mondo_mode_5,tid_5}; |
| 584 | // 3'b110 : tid_mux_0 = {mondo_mode_6,tid_6}; |
| 585 | // 3'b111 : tid_mux_0 = {mondo_mode_7,tid_7}; |
| 586 | // endcase |
| 587 | |
| 588 | //always @ (gcs2iss_tid_sel[2:0] or tid_8 or tid_9 or tid_10 or |
| 589 | // tid_11 or tid_12 or tid_13 or tid_14 or tid_15 or |
| 590 | // mondo_mode_8 or mondo_mode_9 or mondo_mode_10 or mondo_mode_11 or |
| 591 | // mondo_mode_12 or mondo_mode_13 or mondo_mode_14 or mondo_mode_15) |
| 592 | // |
| 593 | // case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 594 | // 3'b000 : tid_mux_1 = {mondo_mode_8,tid_8}; |
| 595 | // 3'b001 : tid_mux_1 = {mondo_mode_9,tid_9}; |
| 596 | // 3'b010 : tid_mux_1 = {mondo_mode_10,tid_10}; |
| 597 | // 3'b011 : tid_mux_1 = {mondo_mode_11,tid_11}; |
| 598 | // 3'b100 : tid_mux_1 = {mondo_mode_12,tid_12}; |
| 599 | // 3'b101 : tid_mux_1 = {mondo_mode_13,tid_13}; |
| 600 | // 3'b110 : tid_mux_1 = {mondo_mode_14,tid_14}; |
| 601 | // 3'b111 : tid_mux_1 = {mondo_mode_15,tid_15}; |
| 602 | // endcase |
| 603 | |
| 604 | |
| 605 | always @ (gcs2iss_tid_sel[2:0] or |
| 606 | tid_20 or tid_21 or tid_22 or tid_23 or |
| 607 | mondo_mode_20 or mondo_mode_21 or mondo_mode_22 or mondo_mode_23) |
| 608 | |
| 609 | case (gcs2iss_tid_sel[2:0]) // synopsys full_case parallel_case infer_mux |
| 610 | 3'b000 : tid_mux_2 = 7'b0; |
| 611 | 3'b001 : tid_mux_2 = 7'b0; |
| 612 | 3'b010 : tid_mux_2 = 7'b0; |
| 613 | 3'b011 : tid_mux_2 = 7'b0; |
| 614 | 3'b100 : tid_mux_2 = {mondo_mode_20,tid_20}; |
| 615 | 3'b101 : tid_mux_2 = {mondo_mode_21,tid_21}; |
| 616 | 3'b110 : tid_mux_2 = {mondo_mode_22,tid_22}; |
| 617 | 3'b111 : tid_mux_2 = {mondo_mode_23,tid_23}; |
| 618 | endcase |
| 619 | |
| 620 | always @ (gcs2iss_tid_sel[2:0] or tid_24 or tid_25 or tid_26 or |
| 621 | tid_27 or tid_28 or tid_29 or tid_30 or tid_31 or |
| 622 | mondo_mode_24 or mondo_mode_25 or mondo_mode_26 or mondo_mode_27 or |
| 623 | mondo_mode_28 or mondo_mode_29 or mondo_mode_30 or mondo_mode_31) |
| 624 | |
| 625 | case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 626 | 3'b000 : tid_mux_3 = {mondo_mode_24,tid_24}; |
| 627 | 3'b001 : tid_mux_3 = {mondo_mode_25,tid_25}; |
| 628 | 3'b010 : tid_mux_3 = {mondo_mode_26,tid_26}; |
| 629 | 3'b011 : tid_mux_3 = {mondo_mode_27,tid_27}; |
| 630 | 3'b100 : tid_mux_3 = {mondo_mode_28,tid_28}; |
| 631 | 3'b101 : tid_mux_3 = {mondo_mode_29,tid_29}; |
| 632 | 3'b110 : tid_mux_3 = {mondo_mode_30,tid_30}; |
| 633 | 3'b111 : tid_mux_3 = {mondo_mode_31,tid_31}; |
| 634 | endcase |
| 635 | |
| 636 | always @ (gcs2iss_tid_sel[2:0] or tid_32 or tid_33 or tid_34 or |
| 637 | tid_35 or tid_36 or tid_37 or tid_38 or tid_39 or |
| 638 | mondo_mode_32 or mondo_mode_33 or mondo_mode_34 or mondo_mode_35 or |
| 639 | mondo_mode_36 or mondo_mode_37 or mondo_mode_38 or mondo_mode_39) |
| 640 | |
| 641 | case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 642 | 3'b000 : tid_mux_4 = {mondo_mode_32,tid_32}; |
| 643 | 3'b001 : tid_mux_4 = {mondo_mode_33,tid_33}; |
| 644 | 3'b010 : tid_mux_4 = {mondo_mode_34,tid_34}; |
| 645 | 3'b011 : tid_mux_4 = {mondo_mode_35,tid_35}; |
| 646 | 3'b100 : tid_mux_4 = {mondo_mode_36,tid_36}; |
| 647 | 3'b101 : tid_mux_4 = {mondo_mode_37,tid_37}; |
| 648 | 3'b110 : tid_mux_4 = {mondo_mode_38,tid_38}; |
| 649 | 3'b111 : tid_mux_4 = {mondo_mode_39,tid_39}; |
| 650 | endcase |
| 651 | |
| 652 | always @ (gcs2iss_tid_sel[2:0] or tid_40 or tid_41 or tid_42 or |
| 653 | tid_43 or tid_44 or tid_45 or tid_46 or tid_47 or |
| 654 | mondo_mode_40 or mondo_mode_41 or mondo_mode_42 or mondo_mode_43 or |
| 655 | mondo_mode_44 or mondo_mode_45 or mondo_mode_46 or mondo_mode_47) |
| 656 | |
| 657 | case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 658 | 3'b000 : tid_mux_5 = {mondo_mode_40,tid_40}; |
| 659 | 3'b001 : tid_mux_5 = {mondo_mode_41,tid_41}; |
| 660 | 3'b010 : tid_mux_5 = {mondo_mode_42,tid_42}; |
| 661 | 3'b011 : tid_mux_5 = {mondo_mode_43,tid_43}; |
| 662 | 3'b100 : tid_mux_5 = {mondo_mode_44,tid_44}; |
| 663 | 3'b101 : tid_mux_5 = {mondo_mode_45,tid_45}; |
| 664 | 3'b110 : tid_mux_5 = {mondo_mode_46,tid_46}; |
| 665 | 3'b111 : tid_mux_5 = {mondo_mode_47,tid_47}; |
| 666 | endcase |
| 667 | |
| 668 | always @ (gcs2iss_tid_sel[2:0] or tid_48 or tid_49 or tid_50 or |
| 669 | tid_51 or tid_52 or tid_53 or tid_54 or tid_55 or |
| 670 | mondo_mode_48 or mondo_mode_49 or mondo_mode_50 or mondo_mode_51 or |
| 671 | mondo_mode_52 or mondo_mode_53 or mondo_mode_54 or mondo_mode_55) |
| 672 | |
| 673 | case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 674 | 3'b000 : tid_mux_6 = {mondo_mode_48,tid_48}; |
| 675 | 3'b001 : tid_mux_6 = {mondo_mode_49,tid_49}; |
| 676 | 3'b010 : tid_mux_6 = {mondo_mode_50,tid_50}; |
| 677 | 3'b011 : tid_mux_6 = {mondo_mode_51,tid_51}; |
| 678 | 3'b100 : tid_mux_6 = {mondo_mode_52,tid_52}; |
| 679 | 3'b101 : tid_mux_6 = {mondo_mode_53,tid_53}; |
| 680 | 3'b110 : tid_mux_6 = {mondo_mode_54,tid_54}; |
| 681 | 3'b111 : tid_mux_6 = {mondo_mode_55,tid_55}; |
| 682 | endcase |
| 683 | |
| 684 | always @ (gcs2iss_tid_sel[2:0] or tid_56 or tid_57 or tid_58 or |
| 685 | tid_59 or tid_62 or tid_63 or |
| 686 | mondo_mode_56 or mondo_mode_57 or mondo_mode_58 or mondo_mode_59 or |
| 687 | mondo_mode_62 or mondo_mode_63) |
| 688 | |
| 689 | case (gcs2iss_tid_sel[2:0]) // synopsys parallel_case full_case infer_mux |
| 690 | 3'b000 : tid_mux_7 = {mondo_mode_56,tid_56}; |
| 691 | 3'b001 : tid_mux_7 = {mondo_mode_57,tid_57}; |
| 692 | 3'b010 : tid_mux_7 = {mondo_mode_58,tid_58}; |
| 693 | 3'b011 : tid_mux_7 = {mondo_mode_59,tid_59}; |
| 694 | 3'b100 : tid_mux_7 = 7'b0; |
| 695 | 3'b101 : tid_mux_7 = 7'b0; |
| 696 | 3'b110 : tid_mux_7 = {mondo_mode_62,tid_62}; |
| 697 | 3'b111 : tid_mux_7 = {mondo_mode_63,tid_63}; |
| 698 | endcase |
| 699 | |
| 700 | always @ (gcs2iss_tid_sel[5:3] or tid_mux_2 or |
| 701 | tid_mux_3 or tid_mux_4 or tid_mux_5 or tid_mux_6 or tid_mux_7) |
| 702 | |
| 703 | case (gcs2iss_tid_sel[5:3]) // synopsys parallel_case full_case infer_mux |
| 704 | 3'b000 : tid_mux = 7'b0; |
| 705 | 3'b001 : tid_mux = 7'b0; |
| 706 | 3'b010 : tid_mux = tid_mux_2; |
| 707 | 3'b011 : tid_mux = tid_mux_3; |
| 708 | 3'b100 : tid_mux = tid_mux_4; |
| 709 | 3'b101 : tid_mux = tid_mux_5; |
| 710 | 3'b110 : tid_mux = tid_mux_6; |
| 711 | 3'b111 : tid_mux = tid_mux_7; |
| 712 | endcase |
| 713 | |
| 714 | |
| 715 | assign iss2gcs_tid = tid_mux[5:0]; |
| 716 | assign iss2gcs_mondo_mode = tid_mux[6]; |
| 717 | |
| 718 | //----------------------------------------------------------------- |
| 719 | // Logic to take state machines to from RECEIVED TO PEDNING |
| 720 | // |
| 721 | // When the tid_req comes in it looks at which one of the bit sis set |
| 722 | //----------------------------------------------------------------- |
| 723 | |
| 724 | // assign int_scheduled_0 = gcs2iss_tid_req & gcs2iss_mdo_pending[0]; |
| 725 | // assign int_scheduled_1 = gcs2iss_tid_req & gcs2iss_mdo_pending[1]; |
| 726 | // assign int_scheduled_2 = gcs2iss_tid_req & gcs2iss_mdo_pending[2]; |
| 727 | // assign int_scheduled_3 = gcs2iss_tid_req & gcs2iss_mdo_pending[3]; |
| 728 | // assign int_scheduled_4 = gcs2iss_tid_req & gcs2iss_mdo_pending[4]; |
| 729 | // assign int_scheduled_5 = gcs2iss_tid_req & gcs2iss_mdo_pending[5]; |
| 730 | // assign int_scheduled_6 = gcs2iss_tid_req & gcs2iss_mdo_pending[6]; |
| 731 | // assign int_scheduled_7 = gcs2iss_tid_req & gcs2iss_mdo_pending[7]; |
| 732 | // assign int_scheduled_8 = gcs2iss_tid_req & gcs2iss_mdo_pending[8]; |
| 733 | // assign int_scheduled_9 = gcs2iss_tid_req & gcs2iss_mdo_pending[9]; |
| 734 | |
| 735 | // assign int_scheduled_10 = gcs2iss_tid_req & gcs2iss_mdo_pending[10]; |
| 736 | // assign int_scheduled_11 = gcs2iss_tid_req & gcs2iss_mdo_pending[11]; |
| 737 | // assign int_scheduled_12 = gcs2iss_tid_req & gcs2iss_mdo_pending[12]; |
| 738 | // assign int_scheduled_13 = gcs2iss_tid_req & gcs2iss_mdo_pending[13]; |
| 739 | // assign int_scheduled_14 = gcs2iss_tid_req & gcs2iss_mdo_pending[14]; |
| 740 | // assign int_scheduled_15 = gcs2iss_tid_req & gcs2iss_mdo_pending[15]; |
| 741 | // assign int_scheduled_16 = gcs2iss_tid_req & gcs2iss_mdo_pending[16]; |
| 742 | // assign int_scheduled_17 = gcs2iss_tid_req & gcs2iss_mdo_pending[17]; |
| 743 | // assign int_scheduled_18 = gcs2iss_tid_req & gcs2iss_mdo_pending[18]; |
| 744 | // assign int_scheduled_19 = gcs2iss_tid_req & gcs2iss_mdo_pending[19]; |
| 745 | |
| 746 | assign int_scheduled_20 = gcs2iss_tid_req & gcs2iss_mdo_pending[20]; |
| 747 | assign int_scheduled_21 = gcs2iss_tid_req & gcs2iss_mdo_pending[21]; |
| 748 | assign int_scheduled_22 = gcs2iss_tid_req & gcs2iss_mdo_pending[22]; |
| 749 | assign int_scheduled_23 = gcs2iss_tid_req & gcs2iss_mdo_pending[23]; |
| 750 | assign int_scheduled_24 = gcs2iss_tid_req & gcs2iss_mdo_pending[24]; |
| 751 | assign int_scheduled_25 = gcs2iss_tid_req & gcs2iss_mdo_pending[25]; |
| 752 | assign int_scheduled_26 = gcs2iss_tid_req & gcs2iss_mdo_pending[26]; |
| 753 | assign int_scheduled_27 = gcs2iss_tid_req & gcs2iss_mdo_pending[27]; |
| 754 | assign int_scheduled_28 = gcs2iss_tid_req & gcs2iss_mdo_pending[28]; |
| 755 | assign int_scheduled_29 = gcs2iss_tid_req & gcs2iss_mdo_pending[29]; |
| 756 | |
| 757 | assign int_scheduled_30 = gcs2iss_tid_req & gcs2iss_mdo_pending[30]; |
| 758 | assign int_scheduled_31 = gcs2iss_tid_req & gcs2iss_mdo_pending[31]; |
| 759 | assign int_scheduled_32 = gcs2iss_tid_req & gcs2iss_mdo_pending[32]; |
| 760 | assign int_scheduled_33 = gcs2iss_tid_req & gcs2iss_mdo_pending[33]; |
| 761 | assign int_scheduled_34 = gcs2iss_tid_req & gcs2iss_mdo_pending[34]; |
| 762 | assign int_scheduled_35 = gcs2iss_tid_req & gcs2iss_mdo_pending[35]; |
| 763 | assign int_scheduled_36 = gcs2iss_tid_req & gcs2iss_mdo_pending[36]; |
| 764 | assign int_scheduled_37 = gcs2iss_tid_req & gcs2iss_mdo_pending[37]; |
| 765 | assign int_scheduled_38 = gcs2iss_tid_req & gcs2iss_mdo_pending[38]; |
| 766 | assign int_scheduled_39 = gcs2iss_tid_req & gcs2iss_mdo_pending[39]; |
| 767 | |
| 768 | assign int_scheduled_40 = gcs2iss_tid_req & gcs2iss_mdo_pending[40]; |
| 769 | assign int_scheduled_41 = gcs2iss_tid_req & gcs2iss_mdo_pending[41]; |
| 770 | assign int_scheduled_42 = gcs2iss_tid_req & gcs2iss_mdo_pending[42]; |
| 771 | assign int_scheduled_43 = gcs2iss_tid_req & gcs2iss_mdo_pending[43]; |
| 772 | assign int_scheduled_44 = gcs2iss_tid_req & gcs2iss_mdo_pending[44]; |
| 773 | assign int_scheduled_45 = gcs2iss_tid_req & gcs2iss_mdo_pending[45]; |
| 774 | assign int_scheduled_46 = gcs2iss_tid_req & gcs2iss_mdo_pending[46]; |
| 775 | assign int_scheduled_47 = gcs2iss_tid_req & gcs2iss_mdo_pending[47]; |
| 776 | assign int_scheduled_48 = gcs2iss_tid_req & gcs2iss_mdo_pending[48]; |
| 777 | assign int_scheduled_49 = gcs2iss_tid_req & gcs2iss_mdo_pending[49]; |
| 778 | |
| 779 | assign int_scheduled_50 = gcs2iss_tid_req & gcs2iss_mdo_pending[50]; |
| 780 | assign int_scheduled_51 = gcs2iss_tid_req & gcs2iss_mdo_pending[51]; |
| 781 | assign int_scheduled_52 = gcs2iss_tid_req & gcs2iss_mdo_pending[52]; |
| 782 | assign int_scheduled_53 = gcs2iss_tid_req & gcs2iss_mdo_pending[53]; |
| 783 | assign int_scheduled_54 = gcs2iss_tid_req & gcs2iss_mdo_pending[54]; |
| 784 | assign int_scheduled_55 = gcs2iss_tid_req & gcs2iss_mdo_pending[55]; |
| 785 | assign int_scheduled_56 = gcs2iss_tid_req & gcs2iss_mdo_pending[56]; |
| 786 | assign int_scheduled_57 = gcs2iss_tid_req & gcs2iss_mdo_pending[57]; |
| 787 | assign int_scheduled_58 = gcs2iss_tid_req & gcs2iss_mdo_pending[58]; |
| 788 | assign int_scheduled_59 = gcs2iss_tid_req & gcs2iss_mdo_pending[59]; |
| 789 | |
| 790 | // assign int_scheduled_60 = gcs2iss_tid_req & gcs2iss_mdo_pending[60]; |
| 791 | // assign int_scheduled_61 = gcs2iss_tid_req & gcs2iss_mdo_pending[61]; |
| 792 | assign int_scheduled_62 = gcs2iss_tid_req & gcs2iss_mdo_pending[62]; |
| 793 | assign int_scheduled_63 = gcs2iss_tid_req & gcs2iss_mdo_pending[63]; |
| 794 | |
| 795 | |
| 796 | |
| 797 | //############################################################################ |
| 798 | // SEQUENTIAL LOGIC |
| 799 | //############################################################################ |
| 800 | |
| 801 | |
| 802 | //------------------------------------------------ |
| 803 | // Logic to Register the TID request to know when |
| 804 | // to send back the ACK |
| 805 | //------------------------------------------------ |
| 806 | |
| 807 | always @ (posedge clk) |
| 808 | begin |
| 809 | if (~rst_l) |
| 810 | begin |
| 811 | tid_req_reg <= 1'b0; |
| 812 | end |
| 813 | else |
| 814 | begin |
| 815 | tid_req_reg <= gcs2iss_tid_req; |
| 816 | end |
| 817 | end |
| 818 | |
| 819 | //---------------------------------------------------- |
| 820 | // Produce the ACK signal back to the GCS |
| 821 | //---------------------------------------------------- |
| 822 | |
| 823 | assign iss2gcs_tid_ack = gcs2iss_tid_req & tid_req_reg; |
| 824 | |
| 825 | |
| 826 | //----------------------------------------------------- |
| 827 | // Debug Ports |
| 828 | //----------------------------------------------------- |
| 829 | |
| 830 | always @ (dbg2iss_dbg_sel_a or iss2gcs_mondo_mode or iss2gcs_tid[4:0] or gcs2iss_tid_req or iss2gcs_tid_ack or |
| 831 | gcs2iss_tid_sel or ics2iss_mondo_62_int_l or ics2iss_mondo_63_int_l or |
| 832 | rds2iss_intx_int_l or sw_state_wr or int_state_ext_wr_data) |
| 833 | begin |
| 834 | case (dbg2iss_dbg_sel_a) // synopsys infer_mux |
| 835 | 3'b000: n_dbg_a = {iss2gcs_mondo_mode, iss2gcs_tid[4:0], gcs2iss_tid_req, iss2gcs_tid_ack}; |
| 836 | 3'b001: n_dbg_a = {gcs2iss_tid_sel[5:0], 2'h0}; |
| 837 | 3'b010: n_dbg_a = {2'h0, ics2iss_mondo_62_int_l, ics2iss_mondo_63_int_l, rds2iss_intx_int_l[3:0]}; |
| 838 | 3'b011: n_dbg_a = 8'h00; |
| 839 | 3'b100: n_dbg_a = 8'h00; |
| 840 | 3'b101: n_dbg_a = {1'h0, sw_state_wr, int_state_ext_wr_data[1:0], 4'b0}; |
| 841 | 3'b110: n_dbg_a = 8'h00; |
| 842 | 3'b111: n_dbg_a = 8'h00; |
| 843 | endcase |
| 844 | end |
| 845 | |
| 846 | always @ (dbg2iss_dbg_sel_b or iss2gcs_mondo_mode or iss2gcs_tid[4:0] or gcs2iss_tid_req or iss2gcs_tid_ack or |
| 847 | gcs2iss_tid_sel or ics2iss_mondo_62_int_l or ics2iss_mondo_63_int_l or |
| 848 | rds2iss_intx_int_l or sw_state_wr or int_state_ext_wr_data) |
| 849 | begin |
| 850 | case (dbg2iss_dbg_sel_b) // synopsys infer_mux |
| 851 | 3'b000: n_dbg_b = {iss2gcs_mondo_mode, iss2gcs_tid[4:0], gcs2iss_tid_req, iss2gcs_tid_ack}; |
| 852 | 3'b001: n_dbg_b = {gcs2iss_tid_sel[5:0], 2'h0}; |
| 853 | 3'b010: n_dbg_b = {2'h0, ics2iss_mondo_62_int_l, ics2iss_mondo_63_int_l, rds2iss_intx_int_l[3:0]}; |
| 854 | 3'b011: n_dbg_b = 8'h00; |
| 855 | 3'b100: n_dbg_b = 8'h00; |
| 856 | 3'b101: n_dbg_b = {1'h0, sw_state_wr, int_state_ext_wr_data[1:0], 4'b0 }; |
| 857 | 3'b110: n_dbg_b = 8'h00; |
| 858 | 3'b111: n_dbg_b = 8'h00; |
| 859 | endcase |
| 860 | end |
| 861 | |
| 862 | |
| 863 | always @ (posedge clk) |
| 864 | begin |
| 865 | if (!rst_l) begin |
| 866 | dbg_a <= 8'b0; |
| 867 | dbg_b <= 8'b0; |
| 868 | end |
| 869 | else begin |
| 870 | dbg_a <= n_dbg_a; |
| 871 | dbg_b <= n_dbg_b; |
| 872 | end |
| 873 | end |
| 874 | |
| 875 | |
| 876 | assign iss2dbg_dbg_a = dbg_a; |
| 877 | assign iss2dbg_dbg_b = dbg_b; |
| 878 | |
| 879 | |
| 880 | //############################################################################ |
| 881 | // MODULE INSTANTIATIONS |
| 882 | //############################################################################ |
| 883 | |
| 884 | //--------------------------------- |
| 885 | // DCM Instanciation |
| 886 | //---------------------------------- |
| 887 | |
| 888 | dmu_imu_iss_csr csr ( |
| 889 | .clk (clk), |
| 890 | .csrbus_addr (csrbus_addr), |
| 891 | .csrbus_wr_data (csrbus_wr_data), |
| 892 | .csrbus_wr (csrbus_wr), |
| 893 | .csrbus_valid (csrbus_valid), |
| 894 | .csrbus_mapped (csrbus_mapped), |
| 895 | .csrbus_done (csrbus_done), |
| 896 | .csrbus_read_data (csrbus_read_data), |
| 897 | .rst_l (rst_l), |
| 898 | .csrbus_src_bus (csrbus_src_bus), |
| 899 | .csrbus_acc_vio (csrbus_acc_vio), |
| 900 | .instance_id (j2d_instance_id), |
| 901 | .ext_wr (ext_wr), |
| 902 | .interrupt_mapping_20_mdo_mode_hw_read (mondo_mode_20), |
| 903 | .interrupt_mapping_20_v_hw_read (valid_20), |
| 904 | .interrupt_mapping_20_t_id_hw_read (tid_20), |
| 905 | .interrupt_mapping_20_int_cntrl_num_hw_read (group_20), |
| 906 | .interrupt_mapping_21_mdo_mode_hw_read (mondo_mode_21), |
| 907 | .interrupt_mapping_21_v_hw_read (valid_21), |
| 908 | .interrupt_mapping_21_t_id_hw_read (tid_21), |
| 909 | .interrupt_mapping_21_int_cntrl_num_hw_read (group_21), |
| 910 | .interrupt_mapping_22_mdo_mode_hw_read (mondo_mode_22), |
| 911 | .interrupt_mapping_22_v_hw_read (valid_22), |
| 912 | .interrupt_mapping_22_t_id_hw_read (tid_22), |
| 913 | .interrupt_mapping_22_int_cntrl_num_hw_read (group_22), |
| 914 | .interrupt_mapping_23_mdo_mode_hw_read (mondo_mode_23), |
| 915 | .interrupt_mapping_23_v_hw_read (valid_23), |
| 916 | .interrupt_mapping_23_t_id_hw_read (tid_23), |
| 917 | .interrupt_mapping_23_int_cntrl_num_hw_read (group_23), |
| 918 | .interrupt_mapping_24_mdo_mode_hw_read (mondo_mode_24), |
| 919 | .interrupt_mapping_24_v_hw_read (valid_24), |
| 920 | .interrupt_mapping_24_t_id_hw_read (tid_24), |
| 921 | .interrupt_mapping_24_int_cntrl_num_hw_read (group_24), |
| 922 | .interrupt_mapping_25_mdo_mode_hw_read (mondo_mode_25), |
| 923 | .interrupt_mapping_25_v_hw_read (valid_25), |
| 924 | .interrupt_mapping_25_t_id_hw_read (tid_25), |
| 925 | .interrupt_mapping_25_int_cntrl_num_hw_read (group_25), |
| 926 | .interrupt_mapping_26_mdo_mode_hw_read (mondo_mode_26), |
| 927 | .interrupt_mapping_26_v_hw_read (valid_26), |
| 928 | .interrupt_mapping_26_t_id_hw_read (tid_26), |
| 929 | .interrupt_mapping_26_int_cntrl_num_hw_read (group_26), |
| 930 | .interrupt_mapping_27_mdo_mode_hw_read (mondo_mode_27), |
| 931 | .interrupt_mapping_27_v_hw_read (valid_27), |
| 932 | .interrupt_mapping_27_t_id_hw_read (tid_27), |
| 933 | .interrupt_mapping_27_int_cntrl_num_hw_read (group_27), |
| 934 | .interrupt_mapping_28_mdo_mode_hw_read (mondo_mode_28), |
| 935 | .interrupt_mapping_28_v_hw_read (valid_28), |
| 936 | .interrupt_mapping_28_t_id_hw_read (tid_28), |
| 937 | .interrupt_mapping_28_int_cntrl_num_hw_read (group_28), |
| 938 | .interrupt_mapping_29_mdo_mode_hw_read (mondo_mode_29), |
| 939 | .interrupt_mapping_29_v_hw_read (valid_29), |
| 940 | .interrupt_mapping_29_t_id_hw_read (tid_29), |
| 941 | .interrupt_mapping_29_int_cntrl_num_hw_read (group_29), |
| 942 | .interrupt_mapping_30_mdo_mode_hw_read (mondo_mode_30), |
| 943 | .interrupt_mapping_30_v_hw_read (valid_30), |
| 944 | .interrupt_mapping_30_t_id_hw_read (tid_30), |
| 945 | .interrupt_mapping_30_int_cntrl_num_hw_read (group_30), |
| 946 | .interrupt_mapping_31_mdo_mode_hw_read (mondo_mode_31), |
| 947 | .interrupt_mapping_31_v_hw_read (valid_31), |
| 948 | .interrupt_mapping_31_t_id_hw_read (tid_31), |
| 949 | .interrupt_mapping_31_int_cntrl_num_hw_read (group_31), |
| 950 | .interrupt_mapping_32_mdo_mode_hw_read (mondo_mode_32), |
| 951 | .interrupt_mapping_32_v_hw_read (valid_32), |
| 952 | .interrupt_mapping_32_t_id_hw_read (tid_32), |
| 953 | .interrupt_mapping_32_int_cntrl_num_hw_read (group_32), |
| 954 | .interrupt_mapping_33_mdo_mode_hw_read (mondo_mode_33), |
| 955 | .interrupt_mapping_33_v_hw_read (valid_33), |
| 956 | .interrupt_mapping_33_t_id_hw_read (tid_33), |
| 957 | .interrupt_mapping_33_int_cntrl_num_hw_read (group_33), |
| 958 | .interrupt_mapping_34_mdo_mode_hw_read (mondo_mode_34), |
| 959 | .interrupt_mapping_34_v_hw_read (valid_34), |
| 960 | .interrupt_mapping_34_t_id_hw_read (tid_34), |
| 961 | .interrupt_mapping_34_int_cntrl_num_hw_read (group_34), |
| 962 | .interrupt_mapping_35_mdo_mode_hw_read (mondo_mode_35), |
| 963 | .interrupt_mapping_35_v_hw_read (valid_35), |
| 964 | .interrupt_mapping_35_t_id_hw_read (tid_35), |
| 965 | .interrupt_mapping_35_int_cntrl_num_hw_read (group_35), |
| 966 | .interrupt_mapping_36_mdo_mode_hw_read (mondo_mode_36), |
| 967 | .interrupt_mapping_36_v_hw_read (valid_36), |
| 968 | .interrupt_mapping_36_t_id_hw_read (tid_36), |
| 969 | .interrupt_mapping_36_int_cntrl_num_hw_read (group_36), |
| 970 | .interrupt_mapping_37_mdo_mode_hw_read (mondo_mode_37), |
| 971 | .interrupt_mapping_37_v_hw_read (valid_37), |
| 972 | .interrupt_mapping_37_t_id_hw_read (tid_37), |
| 973 | .interrupt_mapping_37_int_cntrl_num_hw_read (group_37), |
| 974 | .interrupt_mapping_38_mdo_mode_hw_read (mondo_mode_38), |
| 975 | .interrupt_mapping_38_v_hw_read (valid_38), |
| 976 | .interrupt_mapping_38_t_id_hw_read (tid_38), |
| 977 | .interrupt_mapping_38_int_cntrl_num_hw_read (group_38), |
| 978 | .interrupt_mapping_39_mdo_mode_hw_read (mondo_mode_39), |
| 979 | .interrupt_mapping_39_v_hw_read (valid_39), |
| 980 | .interrupt_mapping_39_t_id_hw_read (tid_39), |
| 981 | .interrupt_mapping_39_int_cntrl_num_hw_read (group_39), |
| 982 | .interrupt_mapping_40_mdo_mode_hw_read (mondo_mode_40), |
| 983 | .interrupt_mapping_40_v_hw_read (valid_40), |
| 984 | .interrupt_mapping_40_t_id_hw_read (tid_40), |
| 985 | .interrupt_mapping_40_int_cntrl_num_hw_read (group_40), |
| 986 | .interrupt_mapping_41_mdo_mode_hw_read (mondo_mode_41), |
| 987 | .interrupt_mapping_41_v_hw_read (valid_41), |
| 988 | .interrupt_mapping_41_t_id_hw_read (tid_41), |
| 989 | .interrupt_mapping_41_int_cntrl_num_hw_read (group_41), |
| 990 | .interrupt_mapping_42_mdo_mode_hw_read (mondo_mode_42), |
| 991 | .interrupt_mapping_42_v_hw_read (valid_42), |
| 992 | .interrupt_mapping_42_t_id_hw_read (tid_42), |
| 993 | .interrupt_mapping_42_int_cntrl_num_hw_read (group_42), |
| 994 | .interrupt_mapping_43_mdo_mode_hw_read (mondo_mode_43), |
| 995 | .interrupt_mapping_43_v_hw_read (valid_43), |
| 996 | .interrupt_mapping_43_t_id_hw_read (tid_43), |
| 997 | .interrupt_mapping_43_int_cntrl_num_hw_read (group_43), |
| 998 | .interrupt_mapping_44_mdo_mode_hw_read (mondo_mode_44), |
| 999 | .interrupt_mapping_44_v_hw_read (valid_44), |
| 1000 | .interrupt_mapping_44_t_id_hw_read (tid_44), |
| 1001 | .interrupt_mapping_44_int_cntrl_num_hw_read (group_44), |
| 1002 | .interrupt_mapping_45_mdo_mode_hw_read (mondo_mode_45), |
| 1003 | .interrupt_mapping_45_v_hw_read (valid_45), |
| 1004 | .interrupt_mapping_45_t_id_hw_read (tid_45), |
| 1005 | .interrupt_mapping_45_int_cntrl_num_hw_read (group_45), |
| 1006 | .interrupt_mapping_46_mdo_mode_hw_read (mondo_mode_46), |
| 1007 | .interrupt_mapping_46_v_hw_read (valid_46), |
| 1008 | .interrupt_mapping_46_t_id_hw_read (tid_46), |
| 1009 | .interrupt_mapping_46_int_cntrl_num_hw_read (group_46), |
| 1010 | .interrupt_mapping_47_mdo_mode_hw_read (mondo_mode_47), |
| 1011 | .interrupt_mapping_47_v_hw_read (valid_47), |
| 1012 | .interrupt_mapping_47_t_id_hw_read (tid_47), |
| 1013 | .interrupt_mapping_47_int_cntrl_num_hw_read (group_47), |
| 1014 | .interrupt_mapping_48_mdo_mode_hw_read (mondo_mode_48), |
| 1015 | .interrupt_mapping_48_v_hw_read (valid_48), |
| 1016 | .interrupt_mapping_48_t_id_hw_read (tid_48), |
| 1017 | .interrupt_mapping_48_int_cntrl_num_hw_read (group_48), |
| 1018 | .interrupt_mapping_49_mdo_mode_hw_read (mondo_mode_49), |
| 1019 | .interrupt_mapping_49_v_hw_read (valid_49), |
| 1020 | .interrupt_mapping_49_t_id_hw_read (tid_49), |
| 1021 | .interrupt_mapping_49_int_cntrl_num_hw_read (group_49), |
| 1022 | .interrupt_mapping_50_mdo_mode_hw_read (mondo_mode_50), |
| 1023 | .interrupt_mapping_50_v_hw_read (valid_50), |
| 1024 | .interrupt_mapping_50_t_id_hw_read (tid_50), |
| 1025 | .interrupt_mapping_50_int_cntrl_num_hw_read (group_50), |
| 1026 | .interrupt_mapping_51_mdo_mode_hw_read (mondo_mode_51), |
| 1027 | .interrupt_mapping_51_v_hw_read (valid_51), |
| 1028 | .interrupt_mapping_51_t_id_hw_read (tid_51), |
| 1029 | .interrupt_mapping_51_int_cntrl_num_hw_read (group_51), |
| 1030 | .interrupt_mapping_52_mdo_mode_hw_read (mondo_mode_52), |
| 1031 | .interrupt_mapping_52_v_hw_read (valid_52), |
| 1032 | .interrupt_mapping_52_t_id_hw_read (tid_52), |
| 1033 | .interrupt_mapping_52_int_cntrl_num_hw_read (group_52), |
| 1034 | .interrupt_mapping_53_mdo_mode_hw_read (mondo_mode_53), |
| 1035 | .interrupt_mapping_53_v_hw_read (valid_53), |
| 1036 | .interrupt_mapping_53_t_id_hw_read (tid_53), |
| 1037 | .interrupt_mapping_53_int_cntrl_num_hw_read (group_53), |
| 1038 | .interrupt_mapping_54_mdo_mode_hw_read (mondo_mode_54), |
| 1039 | .interrupt_mapping_54_v_hw_read (valid_54), |
| 1040 | .interrupt_mapping_54_t_id_hw_read (tid_54), |
| 1041 | .interrupt_mapping_54_int_cntrl_num_hw_read (group_54), |
| 1042 | .interrupt_mapping_55_mdo_mode_hw_read (mondo_mode_55), |
| 1043 | .interrupt_mapping_55_v_hw_read (valid_55), |
| 1044 | .interrupt_mapping_55_t_id_hw_read (tid_55), |
| 1045 | .interrupt_mapping_55_int_cntrl_num_hw_read (group_55), |
| 1046 | .interrupt_mapping_56_mdo_mode_hw_read (mondo_mode_56), |
| 1047 | .interrupt_mapping_56_v_hw_read (valid_56), |
| 1048 | .interrupt_mapping_56_t_id_hw_read (tid_56), |
| 1049 | .interrupt_mapping_56_int_cntrl_num_hw_read (group_56), |
| 1050 | .interrupt_mapping_57_mdo_mode_hw_read (mondo_mode_57), |
| 1051 | .interrupt_mapping_57_v_hw_read (valid_57), |
| 1052 | .interrupt_mapping_57_t_id_hw_read (tid_57), |
| 1053 | .interrupt_mapping_57_int_cntrl_num_hw_read (group_57), |
| 1054 | .interrupt_mapping_58_mdo_mode_hw_read (mondo_mode_58), |
| 1055 | .interrupt_mapping_58_v_hw_read (valid_58), |
| 1056 | .interrupt_mapping_58_t_id_hw_read (tid_58), |
| 1057 | .interrupt_mapping_58_int_cntrl_num_hw_read (group_58), |
| 1058 | .interrupt_mapping_59_mdo_mode_hw_read (mondo_mode_59), |
| 1059 | .interrupt_mapping_59_v_hw_read (valid_59), |
| 1060 | .interrupt_mapping_59_t_id_hw_read (tid_59), |
| 1061 | .interrupt_mapping_59_int_cntrl_num_hw_read (group_59), |
| 1062 | .interrupt_mapping_62_mdo_mode_hw_read (mondo_mode_62), |
| 1063 | .interrupt_mapping_62_v_hw_read (valid_62), |
| 1064 | .interrupt_mapping_62_t_id_hw_read (tid_62), |
| 1065 | .interrupt_mapping_62_int_cntrl_num_hw_read (group_62), |
| 1066 | .interrupt_mapping_63_mdo_mode_hw_read (mondo_mode_63), |
| 1067 | .interrupt_mapping_63_v_hw_read (valid_63), |
| 1068 | .interrupt_mapping_63_t_id_hw_read (tid_63), |
| 1069 | .interrupt_mapping_63_int_cntrl_num_hw_read (group_63), |
| 1070 | .clr_int_reg_20_int_state_ext_wr_data (int_state_20_ext_wr_data), |
| 1071 | .clr_int_reg_20_ext_select (sw_state_addr_sel_20), |
| 1072 | .clr_int_reg_20_int_state_ext_read_data (mondo_state_20), |
| 1073 | .clr_int_reg_21_int_state_ext_wr_data (int_state_21_ext_wr_data), |
| 1074 | .clr_int_reg_21_ext_select (sw_state_addr_sel_21), |
| 1075 | .clr_int_reg_21_int_state_ext_read_data (mondo_state_21), |
| 1076 | .clr_int_reg_22_int_state_ext_wr_data (int_state_22_ext_wr_data), |
| 1077 | .clr_int_reg_22_ext_select (sw_state_addr_sel_22), |
| 1078 | .clr_int_reg_22_int_state_ext_read_data (mondo_state_22), |
| 1079 | .clr_int_reg_23_int_state_ext_wr_data (int_state_23_ext_wr_data), |
| 1080 | .clr_int_reg_23_ext_select (sw_state_addr_sel_23), |
| 1081 | .clr_int_reg_23_int_state_ext_read_data (mondo_state_23), |
| 1082 | .clr_int_reg_24_int_state_ext_wr_data (int_state_24_ext_wr_data), |
| 1083 | .clr_int_reg_24_ext_select (sw_state_addr_sel_24), |
| 1084 | .clr_int_reg_24_int_state_ext_read_data (mondo_state_24), |
| 1085 | .clr_int_reg_25_int_state_ext_wr_data (int_state_25_ext_wr_data), |
| 1086 | .clr_int_reg_25_ext_select (sw_state_addr_sel_25), |
| 1087 | .clr_int_reg_25_int_state_ext_read_data (mondo_state_25), |
| 1088 | .clr_int_reg_26_int_state_ext_wr_data (int_state_26_ext_wr_data), |
| 1089 | .clr_int_reg_26_ext_select (sw_state_addr_sel_26), |
| 1090 | .clr_int_reg_26_int_state_ext_read_data (mondo_state_26), |
| 1091 | .clr_int_reg_27_int_state_ext_wr_data (int_state_27_ext_wr_data), |
| 1092 | .clr_int_reg_27_ext_select (sw_state_addr_sel_27), |
| 1093 | .clr_int_reg_27_int_state_ext_read_data (mondo_state_27), |
| 1094 | .clr_int_reg_28_int_state_ext_wr_data (int_state_28_ext_wr_data), |
| 1095 | .clr_int_reg_28_ext_select (sw_state_addr_sel_28), |
| 1096 | .clr_int_reg_28_int_state_ext_read_data (mondo_state_28), |
| 1097 | .clr_int_reg_29_int_state_ext_wr_data (int_state_29_ext_wr_data), |
| 1098 | .clr_int_reg_29_ext_select (sw_state_addr_sel_29), |
| 1099 | .clr_int_reg_29_int_state_ext_read_data (mondo_state_29), |
| 1100 | .clr_int_reg_30_int_state_ext_wr_data (int_state_30_ext_wr_data), |
| 1101 | .clr_int_reg_30_ext_select (sw_state_addr_sel_30), |
| 1102 | .clr_int_reg_30_int_state_ext_read_data (mondo_state_30), |
| 1103 | .clr_int_reg_31_int_state_ext_wr_data (int_state_31_ext_wr_data), |
| 1104 | .clr_int_reg_31_ext_select (sw_state_addr_sel_31), |
| 1105 | .clr_int_reg_31_int_state_ext_read_data (mondo_state_31), |
| 1106 | .clr_int_reg_32_int_state_ext_wr_data (int_state_32_ext_wr_data), |
| 1107 | .clr_int_reg_32_ext_select (sw_state_addr_sel_32), |
| 1108 | .clr_int_reg_32_int_state_ext_read_data (mondo_state_32), |
| 1109 | .clr_int_reg_33_int_state_ext_wr_data (int_state_33_ext_wr_data), |
| 1110 | .clr_int_reg_33_ext_select (sw_state_addr_sel_33), |
| 1111 | .clr_int_reg_33_int_state_ext_read_data (mondo_state_33), |
| 1112 | .clr_int_reg_34_int_state_ext_wr_data (int_state_34_ext_wr_data), |
| 1113 | .clr_int_reg_34_ext_select (sw_state_addr_sel_34), |
| 1114 | .clr_int_reg_34_int_state_ext_read_data (mondo_state_34), |
| 1115 | .clr_int_reg_35_int_state_ext_wr_data (int_state_35_ext_wr_data), |
| 1116 | .clr_int_reg_35_ext_select (sw_state_addr_sel_35), |
| 1117 | .clr_int_reg_35_int_state_ext_read_data (mondo_state_35), |
| 1118 | .clr_int_reg_36_int_state_ext_wr_data (int_state_36_ext_wr_data), |
| 1119 | .clr_int_reg_36_ext_select (sw_state_addr_sel_36), |
| 1120 | .clr_int_reg_36_int_state_ext_read_data (mondo_state_36), |
| 1121 | .clr_int_reg_37_int_state_ext_wr_data (int_state_37_ext_wr_data), |
| 1122 | .clr_int_reg_37_ext_select (sw_state_addr_sel_37), |
| 1123 | .clr_int_reg_37_int_state_ext_read_data (mondo_state_37), |
| 1124 | .clr_int_reg_38_int_state_ext_wr_data (int_state_38_ext_wr_data), |
| 1125 | .clr_int_reg_38_ext_select (sw_state_addr_sel_38), |
| 1126 | .clr_int_reg_38_int_state_ext_read_data (mondo_state_38), |
| 1127 | .clr_int_reg_39_int_state_ext_wr_data (int_state_39_ext_wr_data), |
| 1128 | .clr_int_reg_39_ext_select (sw_state_addr_sel_39), |
| 1129 | .clr_int_reg_39_int_state_ext_read_data (mondo_state_39), |
| 1130 | .clr_int_reg_40_int_state_ext_wr_data (int_state_40_ext_wr_data), |
| 1131 | .clr_int_reg_40_ext_select (sw_state_addr_sel_40), |
| 1132 | .clr_int_reg_40_int_state_ext_read_data (mondo_state_40), |
| 1133 | .clr_int_reg_41_int_state_ext_wr_data (int_state_41_ext_wr_data), |
| 1134 | .clr_int_reg_41_ext_select (sw_state_addr_sel_41), |
| 1135 | .clr_int_reg_41_int_state_ext_read_data (mondo_state_41), |
| 1136 | .clr_int_reg_42_int_state_ext_wr_data (int_state_42_ext_wr_data), |
| 1137 | .clr_int_reg_42_ext_select (sw_state_addr_sel_42), |
| 1138 | .clr_int_reg_42_int_state_ext_read_data (mondo_state_42), |
| 1139 | .clr_int_reg_43_int_state_ext_wr_data (int_state_43_ext_wr_data), |
| 1140 | .clr_int_reg_43_ext_select (sw_state_addr_sel_43), |
| 1141 | .clr_int_reg_43_int_state_ext_read_data (mondo_state_43), |
| 1142 | .clr_int_reg_44_int_state_ext_wr_data (int_state_44_ext_wr_data), |
| 1143 | .clr_int_reg_44_ext_select (sw_state_addr_sel_44), |
| 1144 | .clr_int_reg_44_int_state_ext_read_data (mondo_state_44), |
| 1145 | .clr_int_reg_45_int_state_ext_wr_data (int_state_45_ext_wr_data), |
| 1146 | .clr_int_reg_45_ext_select (sw_state_addr_sel_45), |
| 1147 | .clr_int_reg_45_int_state_ext_read_data (mondo_state_45), |
| 1148 | .clr_int_reg_46_int_state_ext_wr_data (int_state_46_ext_wr_data), |
| 1149 | .clr_int_reg_46_ext_select (sw_state_addr_sel_46), |
| 1150 | .clr_int_reg_46_int_state_ext_read_data (mondo_state_46), |
| 1151 | .clr_int_reg_47_int_state_ext_wr_data (int_state_47_ext_wr_data), |
| 1152 | .clr_int_reg_47_ext_select (sw_state_addr_sel_47), |
| 1153 | .clr_int_reg_47_int_state_ext_read_data (mondo_state_47), |
| 1154 | .clr_int_reg_48_int_state_ext_wr_data (int_state_48_ext_wr_data), |
| 1155 | .clr_int_reg_48_ext_select (sw_state_addr_sel_48), |
| 1156 | .clr_int_reg_48_int_state_ext_read_data (mondo_state_48), |
| 1157 | .clr_int_reg_49_int_state_ext_wr_data (int_state_49_ext_wr_data), |
| 1158 | .clr_int_reg_49_ext_select (sw_state_addr_sel_49), |
| 1159 | .clr_int_reg_49_int_state_ext_read_data (mondo_state_49), |
| 1160 | .clr_int_reg_50_int_state_ext_wr_data (int_state_50_ext_wr_data), |
| 1161 | .clr_int_reg_50_ext_select (sw_state_addr_sel_50), |
| 1162 | .clr_int_reg_50_int_state_ext_read_data (mondo_state_50), |
| 1163 | .clr_int_reg_51_int_state_ext_wr_data (int_state_51_ext_wr_data), |
| 1164 | .clr_int_reg_51_ext_select (sw_state_addr_sel_51), |
| 1165 | .clr_int_reg_51_int_state_ext_read_data (mondo_state_51), |
| 1166 | .clr_int_reg_52_int_state_ext_wr_data (int_state_52_ext_wr_data), |
| 1167 | .clr_int_reg_52_ext_select (sw_state_addr_sel_52), |
| 1168 | .clr_int_reg_52_int_state_ext_read_data (mondo_state_52), |
| 1169 | .clr_int_reg_53_int_state_ext_wr_data (int_state_53_ext_wr_data), |
| 1170 | .clr_int_reg_53_ext_select (sw_state_addr_sel_53), |
| 1171 | .clr_int_reg_53_int_state_ext_read_data (mondo_state_53), |
| 1172 | .clr_int_reg_54_int_state_ext_wr_data (int_state_54_ext_wr_data), |
| 1173 | .clr_int_reg_54_ext_select (sw_state_addr_sel_54), |
| 1174 | .clr_int_reg_54_int_state_ext_read_data (mondo_state_54), |
| 1175 | .clr_int_reg_55_int_state_ext_wr_data (int_state_55_ext_wr_data), |
| 1176 | .clr_int_reg_55_ext_select (sw_state_addr_sel_55), |
| 1177 | .clr_int_reg_55_int_state_ext_read_data (mondo_state_55), |
| 1178 | .clr_int_reg_56_int_state_ext_wr_data (int_state_56_ext_wr_data), |
| 1179 | .clr_int_reg_56_ext_select (sw_state_addr_sel_56), |
| 1180 | .clr_int_reg_56_int_state_ext_read_data (mondo_state_56), |
| 1181 | .clr_int_reg_57_int_state_ext_wr_data (int_state_57_ext_wr_data), |
| 1182 | .clr_int_reg_57_ext_select (sw_state_addr_sel_57), |
| 1183 | .clr_int_reg_57_int_state_ext_read_data (mondo_state_57), |
| 1184 | .clr_int_reg_58_int_state_ext_wr_data (int_state_58_ext_wr_data), |
| 1185 | .clr_int_reg_58_ext_select (sw_state_addr_sel_58), |
| 1186 | .clr_int_reg_58_int_state_ext_read_data (mondo_state_58), |
| 1187 | .clr_int_reg_59_int_state_ext_wr_data (int_state_59_ext_wr_data), |
| 1188 | .clr_int_reg_59_ext_select (sw_state_addr_sel_59), |
| 1189 | .clr_int_reg_59_int_state_ext_read_data (mondo_state_59), |
| 1190 | .clr_int_reg_62_int_state_ext_wr_data (int_state_62_ext_wr_data), |
| 1191 | .clr_int_reg_62_ext_select (sw_state_addr_sel_62), |
| 1192 | .clr_int_reg_62_int_state_ext_read_data (mondo_state_62), |
| 1193 | .clr_int_reg_63_int_state_ext_wr_data (int_state_63_ext_wr_data), |
| 1194 | .clr_int_reg_63_ext_select (sw_state_addr_sel_63), |
| 1195 | .clr_int_reg_63_int_state_ext_read_data (mondo_state_63), |
| 1196 | .interrupt_retry_timer_limit_hw_read (iss2gcs_counter_limit), |
| 1197 | .interrupt_state_status_1_state_ext_read_data (sw_mondo_state_1), |
| 1198 | .interrupt_state_status_2_state_ext_read_data (sw_mondo_state_2) |
| 1199 | |
| 1200 | ); |
| 1201 | |
| 1202 | |
| 1203 | //--------------------------------------------- |
| 1204 | // External Interupt FSM's Mondo's 0-19 |
| 1205 | //--------------------------------------------- |
| 1206 | |
| 1207 | //dmu_imu_iss_fsm fsm_0( |
| 1208 | // |
| 1209 | // .clk (clk), |
| 1210 | // .rst_l (rst_l), |
| 1211 | // |
| 1212 | // .int_detected (j2d_ext_int_l[0]), |
| 1213 | // .int_scheduled (int_scheduled_0), |
| 1214 | // |
| 1215 | // .sw_wr (sw_state_wr), |
| 1216 | // .sw_addr_sel (sw_state_addr_sel_0), |
| 1217 | // .sw_wr_data (sw_state_data), |
| 1218 | // |
| 1219 | // .mondo_state (mondo_state_0) |
| 1220 | // |
| 1221 | // ); |
| 1222 | // |
| 1223 | //dmu_imu_iss_fsm fsm_1( |
| 1224 | // |
| 1225 | // .clk (clk), |
| 1226 | // .rst_l (rst_l), |
| 1227 | // |
| 1228 | // .int_detected (j2d_ext_int_l[1]), |
| 1229 | // .int_scheduled (int_scheduled_1), |
| 1230 | // |
| 1231 | // .sw_wr (sw_state_wr), |
| 1232 | // .sw_addr_sel (sw_state_addr_sel_1), |
| 1233 | // .sw_wr_data (sw_state_data), |
| 1234 | // |
| 1235 | // .mondo_state (mondo_state_1) |
| 1236 | // |
| 1237 | // ); |
| 1238 | // |
| 1239 | // |
| 1240 | //dmu_imu_iss_fsm fsm_2( |
| 1241 | // |
| 1242 | // .clk (clk), |
| 1243 | // .rst_l (rst_l), |
| 1244 | // |
| 1245 | // .int_detected (j2d_ext_int_l[2]), |
| 1246 | // .int_scheduled (int_scheduled_2), |
| 1247 | // |
| 1248 | // .sw_wr (sw_state_wr), |
| 1249 | // .sw_addr_sel (sw_state_addr_sel_2), |
| 1250 | // .sw_wr_data (sw_state_data), |
| 1251 | // |
| 1252 | // .mondo_state (mondo_state_2) |
| 1253 | // |
| 1254 | // ); |
| 1255 | // |
| 1256 | // |
| 1257 | //dmu_imu_iss_fsm fsm_3( |
| 1258 | // |
| 1259 | // .clk (clk), |
| 1260 | // .rst_l (rst_l), |
| 1261 | // |
| 1262 | // .int_detected (j2d_ext_int_l[3]), |
| 1263 | // .int_scheduled (int_scheduled_3), |
| 1264 | // |
| 1265 | // .sw_wr (sw_state_wr), |
| 1266 | // .sw_addr_sel (sw_state_addr_sel_3), |
| 1267 | // .sw_wr_data (sw_state_data), |
| 1268 | // |
| 1269 | // .mondo_state (mondo_state_3) |
| 1270 | // |
| 1271 | // ); |
| 1272 | // |
| 1273 | // |
| 1274 | // |
| 1275 | //dmu_imu_iss_fsm fsm_4( |
| 1276 | // |
| 1277 | // .clk (clk), |
| 1278 | // .rst_l (rst_l), |
| 1279 | // |
| 1280 | // .int_detected (j2d_ext_int_l[4]), |
| 1281 | // .int_scheduled (int_scheduled_4), |
| 1282 | // |
| 1283 | // .sw_wr (sw_state_wr), |
| 1284 | // .sw_addr_sel (sw_state_addr_sel_4), |
| 1285 | // .sw_wr_data (sw_state_data), |
| 1286 | // |
| 1287 | // .mondo_state (mondo_state_4) |
| 1288 | // |
| 1289 | // ); |
| 1290 | // |
| 1291 | // |
| 1292 | //dmu_imu_iss_fsm fsm_5( |
| 1293 | // |
| 1294 | // .clk (clk), |
| 1295 | // .rst_l (rst_l), |
| 1296 | // |
| 1297 | // .int_detected (j2d_ext_int_l[5]), |
| 1298 | // .int_scheduled (int_scheduled_5), |
| 1299 | // |
| 1300 | // .sw_wr (sw_state_wr), |
| 1301 | // .sw_addr_sel (sw_state_addr_sel_5), |
| 1302 | // .sw_wr_data (sw_state_data), |
| 1303 | // |
| 1304 | // .mondo_state (mondo_state_5) |
| 1305 | // |
| 1306 | // ); |
| 1307 | // |
| 1308 | //dmu_imu_iss_fsm fsm_6( |
| 1309 | // |
| 1310 | // .clk (clk), |
| 1311 | // .rst_l (rst_l), |
| 1312 | // |
| 1313 | // .int_detected (j2d_ext_int_l[6]), |
| 1314 | // .int_scheduled (int_scheduled_6), |
| 1315 | // |
| 1316 | // .sw_wr (sw_state_wr), |
| 1317 | // .sw_addr_sel (sw_state_addr_sel_6), |
| 1318 | // .sw_wr_data (sw_state_data), |
| 1319 | // |
| 1320 | // .mondo_state (mondo_state_6) |
| 1321 | // |
| 1322 | // ); |
| 1323 | // |
| 1324 | //dmu_imu_iss_fsm fsm_7( |
| 1325 | // |
| 1326 | // .clk (clk), |
| 1327 | // .rst_l (rst_l), |
| 1328 | // |
| 1329 | // .int_detected (j2d_ext_int_l[7]), |
| 1330 | // .int_scheduled (int_scheduled_7), |
| 1331 | // |
| 1332 | // .sw_wr (sw_state_wr), |
| 1333 | // .sw_addr_sel (sw_state_addr_sel_7), |
| 1334 | // .sw_wr_data (sw_state_data), |
| 1335 | // |
| 1336 | // .mondo_state (mondo_state_7) |
| 1337 | // |
| 1338 | // ); |
| 1339 | // |
| 1340 | //dmu_imu_iss_fsm fsm_8( |
| 1341 | // |
| 1342 | // .clk (clk), |
| 1343 | // .rst_l (rst_l), |
| 1344 | // |
| 1345 | // .int_detected (j2d_ext_int_l[8]), |
| 1346 | // .int_scheduled (int_scheduled_8), |
| 1347 | // |
| 1348 | // .sw_wr (sw_state_wr), |
| 1349 | // .sw_addr_sel (sw_state_addr_sel_8), |
| 1350 | // .sw_wr_data (sw_state_data), |
| 1351 | // |
| 1352 | // |
| 1353 | // .mondo_state (mondo_state_8) |
| 1354 | // |
| 1355 | // ); |
| 1356 | // |
| 1357 | // |
| 1358 | //dmu_imu_iss_fsm fsm_9( |
| 1359 | // |
| 1360 | // .clk (clk), |
| 1361 | // .rst_l (rst_l), |
| 1362 | // |
| 1363 | // .int_detected (j2d_ext_int_l[9]), |
| 1364 | // .int_scheduled (int_scheduled_9), |
| 1365 | // |
| 1366 | // .sw_wr (sw_state_wr), |
| 1367 | // .sw_addr_sel (sw_state_addr_sel_9), |
| 1368 | // .sw_wr_data (sw_state_data), |
| 1369 | // |
| 1370 | // .mondo_state (mondo_state_9) |
| 1371 | // |
| 1372 | // ); |
| 1373 | // |
| 1374 | // |
| 1375 | // |
| 1376 | //dmu_imu_iss_fsm fsm_10( |
| 1377 | // |
| 1378 | // .clk (clk), |
| 1379 | // .rst_l (rst_l), |
| 1380 | // |
| 1381 | // .int_detected (j2d_ext_int_l[10]), |
| 1382 | // .int_scheduled (int_scheduled_10), |
| 1383 | // |
| 1384 | // .sw_wr (sw_state_wr), |
| 1385 | // .sw_addr_sel (sw_state_addr_sel_10), |
| 1386 | // .sw_wr_data (sw_state_data), |
| 1387 | // |
| 1388 | // .mondo_state (mondo_state_10) |
| 1389 | // |
| 1390 | // ); |
| 1391 | // |
| 1392 | //dmu_imu_iss_fsm fsm_11( |
| 1393 | // |
| 1394 | // .clk (clk), |
| 1395 | // .rst_l (rst_l), |
| 1396 | // |
| 1397 | // .int_detected (j2d_ext_int_l[11]), |
| 1398 | // .int_scheduled (int_scheduled_11), |
| 1399 | // |
| 1400 | // .sw_wr (sw_state_wr), |
| 1401 | // .sw_addr_sel (sw_state_addr_sel_11), |
| 1402 | // .sw_wr_data (sw_state_data), |
| 1403 | // |
| 1404 | // .mondo_state (mondo_state_11) |
| 1405 | // |
| 1406 | // ); |
| 1407 | // |
| 1408 | // |
| 1409 | //dmu_imu_iss_fsm fsm_12( |
| 1410 | // |
| 1411 | // .clk (clk), |
| 1412 | // .rst_l (rst_l), |
| 1413 | // |
| 1414 | // .int_detected (j2d_ext_int_l[12]), |
| 1415 | // .int_scheduled (int_scheduled_12), |
| 1416 | // |
| 1417 | // .sw_wr (sw_state_wr), |
| 1418 | // .sw_addr_sel (sw_state_addr_sel_12), |
| 1419 | // .sw_wr_data (sw_state_data), |
| 1420 | // |
| 1421 | // .mondo_state (mondo_state_12) |
| 1422 | // |
| 1423 | // ); |
| 1424 | // |
| 1425 | // |
| 1426 | //dmu_imu_iss_fsm fsm_13( |
| 1427 | // |
| 1428 | // .clk (clk), |
| 1429 | // .rst_l (rst_l), |
| 1430 | // |
| 1431 | // .int_detected (j2d_ext_int_l[13]), |
| 1432 | // .int_scheduled (int_scheduled_13), |
| 1433 | // |
| 1434 | // .sw_wr (sw_state_wr), |
| 1435 | // .sw_addr_sel (sw_state_addr_sel_13), |
| 1436 | // .sw_wr_data (sw_state_data), |
| 1437 | // |
| 1438 | // .mondo_state (mondo_state_13) |
| 1439 | // |
| 1440 | // ); |
| 1441 | // |
| 1442 | // |
| 1443 | // |
| 1444 | //dmu_imu_iss_fsm fsm_14( |
| 1445 | // |
| 1446 | // .clk (clk), |
| 1447 | // .rst_l (rst_l), |
| 1448 | // |
| 1449 | // .int_detected (j2d_ext_int_l[14]), |
| 1450 | // .int_scheduled (int_scheduled_14), |
| 1451 | // |
| 1452 | // .sw_wr (sw_state_wr), |
| 1453 | // .sw_addr_sel (sw_state_addr_sel_14), |
| 1454 | // .sw_wr_data (sw_state_data), |
| 1455 | // |
| 1456 | // .mondo_state (mondo_state_14) |
| 1457 | // |
| 1458 | // ); |
| 1459 | // |
| 1460 | // |
| 1461 | //dmu_imu_iss_fsm fsm_15( |
| 1462 | // |
| 1463 | // .clk (clk), |
| 1464 | // .rst_l (rst_l), |
| 1465 | // |
| 1466 | // .int_detected (j2d_ext_int_l[15]), |
| 1467 | // .int_scheduled (int_scheduled_15), |
| 1468 | // |
| 1469 | // .sw_wr (sw_state_wr), |
| 1470 | // .sw_addr_sel (sw_state_addr_sel_15), |
| 1471 | // .sw_wr_data (sw_state_data), |
| 1472 | // |
| 1473 | // .mondo_state (mondo_state_15) |
| 1474 | // |
| 1475 | // ); |
| 1476 | // |
| 1477 | //dmu_imu_iss_fsm fsm_16( |
| 1478 | // |
| 1479 | // .clk (clk), |
| 1480 | // .rst_l (rst_l), |
| 1481 | // |
| 1482 | // .int_detected (j2d_ext_int_l[16]), |
| 1483 | // .int_scheduled (int_scheduled_16), |
| 1484 | // |
| 1485 | // .sw_wr (sw_state_wr), |
| 1486 | // .sw_addr_sel (sw_state_addr_sel_16), |
| 1487 | // .sw_wr_data (sw_state_data), |
| 1488 | // |
| 1489 | // .mondo_state (mondo_state_16) |
| 1490 | // |
| 1491 | // ); |
| 1492 | // |
| 1493 | //dmu_imu_iss_fsm fsm_17( |
| 1494 | // |
| 1495 | // .clk (clk), |
| 1496 | // .rst_l (rst_l), |
| 1497 | // |
| 1498 | // .int_detected (j2d_ext_int_l[17]), |
| 1499 | // .int_scheduled (int_scheduled_17), |
| 1500 | // |
| 1501 | // .sw_wr (sw_state_wr), |
| 1502 | // .sw_addr_sel (sw_state_addr_sel_17), |
| 1503 | // .sw_wr_data (sw_state_data), |
| 1504 | // |
| 1505 | // .mondo_state (mondo_state_17) |
| 1506 | // |
| 1507 | // ); |
| 1508 | // |
| 1509 | //dmu_imu_iss_fsm fsm_18( |
| 1510 | // |
| 1511 | // .clk (clk), |
| 1512 | // .rst_l (rst_l), |
| 1513 | // |
| 1514 | // .int_detected (j2d_ext_int_l[18]), |
| 1515 | // .int_scheduled (int_scheduled_18), |
| 1516 | // |
| 1517 | // .sw_wr (sw_state_wr), |
| 1518 | // .sw_addr_sel (sw_state_addr_sel_18), |
| 1519 | // .sw_wr_data (sw_state_data), |
| 1520 | // |
| 1521 | // .mondo_state (mondo_state_18) |
| 1522 | // |
| 1523 | // ); |
| 1524 | // |
| 1525 | // |
| 1526 | // |
| 1527 | //dmu_imu_iss_fsm fsm_19( |
| 1528 | // |
| 1529 | // .clk (clk), |
| 1530 | // .rst_l (rst_l), |
| 1531 | // |
| 1532 | // .int_detected (j2d_ext_int_l[19]), |
| 1533 | // .int_scheduled (int_scheduled_19), |
| 1534 | // |
| 1535 | // .sw_wr (sw_state_wr), |
| 1536 | // .sw_addr_sel (sw_state_addr_sel_19), |
| 1537 | // .sw_wr_data (sw_state_data), |
| 1538 | // |
| 1539 | // .mondo_state (mondo_state_19) |
| 1540 | // |
| 1541 | // ); |
| 1542 | |
| 1543 | |
| 1544 | //--------------------------------------------- |
| 1545 | // INTX Interupt fsm_'s Mondo's 20 -23 |
| 1546 | //--------------------------------------------- |
| 1547 | |
| 1548 | |
| 1549 | |
| 1550 | dmu_imu_iss_fsm fsm_20( |
| 1551 | |
| 1552 | .clk (clk), |
| 1553 | .rst_l (rst_l), |
| 1554 | |
| 1555 | .int_detected (rds2iss_intx_int_l[0]), |
| 1556 | .int_scheduled (int_scheduled_20), |
| 1557 | |
| 1558 | .sw_wr (sw_state_wr), |
| 1559 | .sw_addr_sel (sw_state_addr_sel_20), |
| 1560 | .sw_wr_data (sw_state_data), |
| 1561 | |
| 1562 | .mondo_state (mondo_state_20) |
| 1563 | |
| 1564 | ); |
| 1565 | |
| 1566 | dmu_imu_iss_fsm fsm_21( |
| 1567 | |
| 1568 | .clk (clk), |
| 1569 | .rst_l (rst_l), |
| 1570 | |
| 1571 | .int_detected (rds2iss_intx_int_l[1]), |
| 1572 | .int_scheduled (int_scheduled_21), |
| 1573 | |
| 1574 | .sw_wr (sw_state_wr), |
| 1575 | .sw_addr_sel (sw_state_addr_sel_21), |
| 1576 | .sw_wr_data (sw_state_data), |
| 1577 | |
| 1578 | .mondo_state (mondo_state_21) |
| 1579 | |
| 1580 | ); |
| 1581 | |
| 1582 | |
| 1583 | dmu_imu_iss_fsm fsm_22( |
| 1584 | |
| 1585 | .clk (clk), |
| 1586 | .rst_l (rst_l), |
| 1587 | |
| 1588 | .int_detected (rds2iss_intx_int_l[2]), |
| 1589 | .int_scheduled (int_scheduled_22), |
| 1590 | |
| 1591 | .sw_wr (sw_state_wr), |
| 1592 | .sw_addr_sel (sw_state_addr_sel_22), |
| 1593 | .sw_wr_data (sw_state_data), |
| 1594 | |
| 1595 | .mondo_state (mondo_state_22) |
| 1596 | |
| 1597 | ); |
| 1598 | |
| 1599 | |
| 1600 | dmu_imu_iss_fsm fsm_23( |
| 1601 | |
| 1602 | .clk (clk), |
| 1603 | .rst_l (rst_l), |
| 1604 | |
| 1605 | .int_detected (rds2iss_intx_int_l[3]), |
| 1606 | .int_scheduled (int_scheduled_23), |
| 1607 | |
| 1608 | .sw_wr (sw_state_wr), |
| 1609 | .sw_addr_sel (sw_state_addr_sel_23), |
| 1610 | .sw_wr_data (sw_state_data), |
| 1611 | |
| 1612 | .mondo_state (mondo_state_23) |
| 1613 | |
| 1614 | ); |
| 1615 | |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | //--------------------------------------------- |
| 1620 | // EQ Interupt fsm_'s (Mondo's 24-59) |
| 1621 | //--------------------------------------------- |
| 1622 | |
| 1623 | dmu_imu_iss_fsm fsm_24( |
| 1624 | |
| 1625 | .clk (clk), |
| 1626 | .rst_l (rst_l), |
| 1627 | |
| 1628 | .int_detected (eqs2iss_eq_int_l[0]), |
| 1629 | .int_scheduled (int_scheduled_24), |
| 1630 | |
| 1631 | .sw_wr (sw_state_wr), |
| 1632 | .sw_addr_sel (sw_state_addr_sel_24), |
| 1633 | .sw_wr_data (sw_state_data), |
| 1634 | |
| 1635 | .mondo_state (mondo_state_24) |
| 1636 | |
| 1637 | ); |
| 1638 | |
| 1639 | |
| 1640 | dmu_imu_iss_fsm fsm_25( |
| 1641 | |
| 1642 | .clk (clk), |
| 1643 | .rst_l (rst_l), |
| 1644 | |
| 1645 | .int_detected (eqs2iss_eq_int_l[1]), |
| 1646 | .int_scheduled (int_scheduled_25), |
| 1647 | |
| 1648 | .sw_wr (sw_state_wr), |
| 1649 | .sw_addr_sel (sw_state_addr_sel_25), |
| 1650 | .sw_wr_data (sw_state_data), |
| 1651 | |
| 1652 | .mondo_state (mondo_state_25) |
| 1653 | |
| 1654 | ); |
| 1655 | |
| 1656 | dmu_imu_iss_fsm fsm_26( |
| 1657 | |
| 1658 | .clk (clk), |
| 1659 | .rst_l (rst_l), |
| 1660 | |
| 1661 | .int_detected (eqs2iss_eq_int_l[2]), |
| 1662 | .int_scheduled (int_scheduled_26), |
| 1663 | |
| 1664 | .sw_wr (sw_state_wr), |
| 1665 | .sw_addr_sel (sw_state_addr_sel_26), |
| 1666 | .sw_wr_data (sw_state_data), |
| 1667 | |
| 1668 | .mondo_state (mondo_state_26) |
| 1669 | |
| 1670 | ); |
| 1671 | |
| 1672 | dmu_imu_iss_fsm fsm_27( |
| 1673 | |
| 1674 | .clk (clk), |
| 1675 | .rst_l (rst_l), |
| 1676 | |
| 1677 | .int_detected (eqs2iss_eq_int_l[3]), |
| 1678 | .int_scheduled (int_scheduled_27), |
| 1679 | |
| 1680 | .sw_wr (sw_state_wr), |
| 1681 | .sw_addr_sel (sw_state_addr_sel_27), |
| 1682 | .sw_wr_data (sw_state_data), |
| 1683 | |
| 1684 | .mondo_state (mondo_state_27) |
| 1685 | |
| 1686 | ); |
| 1687 | |
| 1688 | dmu_imu_iss_fsm fsm_28( |
| 1689 | |
| 1690 | .clk (clk), |
| 1691 | .rst_l (rst_l), |
| 1692 | |
| 1693 | .int_detected (eqs2iss_eq_int_l[4]), |
| 1694 | .int_scheduled (int_scheduled_28), |
| 1695 | |
| 1696 | .sw_wr (sw_state_wr), |
| 1697 | .sw_addr_sel (sw_state_addr_sel_28), |
| 1698 | .sw_wr_data (sw_state_data), |
| 1699 | |
| 1700 | .mondo_state (mondo_state_28) |
| 1701 | |
| 1702 | ); |
| 1703 | |
| 1704 | |
| 1705 | dmu_imu_iss_fsm fsm_29( |
| 1706 | |
| 1707 | .clk (clk), |
| 1708 | .rst_l (rst_l), |
| 1709 | |
| 1710 | .int_detected (eqs2iss_eq_int_l[5]), |
| 1711 | .int_scheduled (int_scheduled_29), |
| 1712 | |
| 1713 | .sw_wr (sw_state_wr), |
| 1714 | .sw_addr_sel (sw_state_addr_sel_29), |
| 1715 | .sw_wr_data (sw_state_data), |
| 1716 | |
| 1717 | .mondo_state (mondo_state_29) |
| 1718 | |
| 1719 | ); |
| 1720 | |
| 1721 | |
| 1722 | dmu_imu_iss_fsm fsm_30( |
| 1723 | |
| 1724 | .clk (clk), |
| 1725 | .rst_l (rst_l), |
| 1726 | |
| 1727 | .int_detected (eqs2iss_eq_int_l[6]), |
| 1728 | .int_scheduled (int_scheduled_30), |
| 1729 | |
| 1730 | .sw_wr (sw_state_wr), |
| 1731 | .sw_addr_sel (sw_state_addr_sel_30), |
| 1732 | .sw_wr_data (sw_state_data), |
| 1733 | |
| 1734 | .mondo_state (mondo_state_30) |
| 1735 | |
| 1736 | ); |
| 1737 | |
| 1738 | dmu_imu_iss_fsm fsm_31( |
| 1739 | |
| 1740 | .clk (clk), |
| 1741 | .rst_l (rst_l), |
| 1742 | |
| 1743 | .int_detected (eqs2iss_eq_int_l[7]), |
| 1744 | .int_scheduled (int_scheduled_31), |
| 1745 | |
| 1746 | .sw_wr (sw_state_wr), |
| 1747 | .sw_addr_sel (sw_state_addr_sel_31), |
| 1748 | .sw_wr_data (sw_state_data), |
| 1749 | |
| 1750 | .mondo_state (mondo_state_31) |
| 1751 | |
| 1752 | ); |
| 1753 | |
| 1754 | |
| 1755 | dmu_imu_iss_fsm fsm_32( |
| 1756 | |
| 1757 | .clk (clk), |
| 1758 | .rst_l (rst_l), |
| 1759 | |
| 1760 | .int_detected (eqs2iss_eq_int_l[8]), |
| 1761 | .int_scheduled (int_scheduled_32), |
| 1762 | |
| 1763 | .sw_wr (sw_state_wr), |
| 1764 | .sw_addr_sel (sw_state_addr_sel_32), |
| 1765 | .sw_wr_data (sw_state_data), |
| 1766 | |
| 1767 | .mondo_state (mondo_state_32) |
| 1768 | |
| 1769 | ); |
| 1770 | |
| 1771 | |
| 1772 | dmu_imu_iss_fsm fsm_33( |
| 1773 | |
| 1774 | .clk (clk), |
| 1775 | .rst_l (rst_l), |
| 1776 | |
| 1777 | .int_detected (eqs2iss_eq_int_l[9]), |
| 1778 | .int_scheduled (int_scheduled_33), |
| 1779 | |
| 1780 | .sw_wr (sw_state_wr), |
| 1781 | .sw_addr_sel (sw_state_addr_sel_33), |
| 1782 | .sw_wr_data (sw_state_data), |
| 1783 | |
| 1784 | .mondo_state (mondo_state_33) |
| 1785 | |
| 1786 | ); |
| 1787 | |
| 1788 | |
| 1789 | |
| 1790 | dmu_imu_iss_fsm fsm_34( |
| 1791 | |
| 1792 | .clk (clk), |
| 1793 | .rst_l (rst_l), |
| 1794 | |
| 1795 | .int_detected (eqs2iss_eq_int_l[10]), |
| 1796 | .int_scheduled (int_scheduled_34), |
| 1797 | |
| 1798 | .sw_wr (sw_state_wr), |
| 1799 | .sw_addr_sel (sw_state_addr_sel_34), |
| 1800 | .sw_wr_data (sw_state_data), |
| 1801 | |
| 1802 | .mondo_state (mondo_state_34) |
| 1803 | |
| 1804 | ); |
| 1805 | |
| 1806 | |
| 1807 | dmu_imu_iss_fsm fsm_35( |
| 1808 | |
| 1809 | .clk (clk), |
| 1810 | .rst_l (rst_l), |
| 1811 | |
| 1812 | .int_detected (eqs2iss_eq_int_l[11]), |
| 1813 | .int_scheduled (int_scheduled_35), |
| 1814 | |
| 1815 | .sw_wr (sw_state_wr), |
| 1816 | .sw_addr_sel (sw_state_addr_sel_35), |
| 1817 | .sw_wr_data (sw_state_data), |
| 1818 | |
| 1819 | .mondo_state (mondo_state_35) |
| 1820 | |
| 1821 | ); |
| 1822 | |
| 1823 | dmu_imu_iss_fsm fsm_36( |
| 1824 | |
| 1825 | .clk (clk), |
| 1826 | .rst_l (rst_l), |
| 1827 | |
| 1828 | .int_detected (eqs2iss_eq_int_l[12]), |
| 1829 | .int_scheduled (int_scheduled_36), |
| 1830 | |
| 1831 | .sw_wr (sw_state_wr), |
| 1832 | .sw_addr_sel (sw_state_addr_sel_36), |
| 1833 | .sw_wr_data (sw_state_data), |
| 1834 | |
| 1835 | .mondo_state (mondo_state_36) |
| 1836 | |
| 1837 | ); |
| 1838 | |
| 1839 | dmu_imu_iss_fsm fsm_37( |
| 1840 | |
| 1841 | .clk (clk), |
| 1842 | .rst_l (rst_l), |
| 1843 | |
| 1844 | .int_detected (eqs2iss_eq_int_l[13]), |
| 1845 | .int_scheduled (int_scheduled_37), |
| 1846 | |
| 1847 | .sw_wr (sw_state_wr), |
| 1848 | .sw_addr_sel (sw_state_addr_sel_37), |
| 1849 | .sw_wr_data (sw_state_data), |
| 1850 | |
| 1851 | .mondo_state (mondo_state_37) |
| 1852 | |
| 1853 | ); |
| 1854 | |
| 1855 | dmu_imu_iss_fsm fsm_38( |
| 1856 | |
| 1857 | .clk (clk), |
| 1858 | .rst_l (rst_l), |
| 1859 | |
| 1860 | .int_detected (eqs2iss_eq_int_l[14]), |
| 1861 | .int_scheduled (int_scheduled_38), |
| 1862 | |
| 1863 | .sw_wr (sw_state_wr), |
| 1864 | .sw_addr_sel (sw_state_addr_sel_38), |
| 1865 | .sw_wr_data (sw_state_data), |
| 1866 | |
| 1867 | .mondo_state (mondo_state_38) |
| 1868 | |
| 1869 | ); |
| 1870 | |
| 1871 | |
| 1872 | dmu_imu_iss_fsm fsm_39( |
| 1873 | |
| 1874 | .clk (clk), |
| 1875 | .rst_l (rst_l), |
| 1876 | |
| 1877 | .int_detected (eqs2iss_eq_int_l[15]), |
| 1878 | .int_scheduled (int_scheduled_39), |
| 1879 | |
| 1880 | .sw_wr (sw_state_wr), |
| 1881 | .sw_addr_sel (sw_state_addr_sel_39), |
| 1882 | .sw_wr_data (sw_state_data), |
| 1883 | |
| 1884 | .mondo_state (mondo_state_39) |
| 1885 | |
| 1886 | ); |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | dmu_imu_iss_fsm fsm_40( |
| 1891 | |
| 1892 | .clk (clk), |
| 1893 | .rst_l (rst_l), |
| 1894 | |
| 1895 | .int_detected (eqs2iss_eq_int_l[16]), |
| 1896 | .int_scheduled (int_scheduled_40), |
| 1897 | |
| 1898 | .sw_wr (sw_state_wr), |
| 1899 | .sw_addr_sel (sw_state_addr_sel_40), |
| 1900 | .sw_wr_data (sw_state_data), |
| 1901 | |
| 1902 | .mondo_state (mondo_state_40) |
| 1903 | |
| 1904 | ); |
| 1905 | |
| 1906 | dmu_imu_iss_fsm fsm_41( |
| 1907 | |
| 1908 | .clk (clk), |
| 1909 | .rst_l (rst_l), |
| 1910 | |
| 1911 | .int_detected (eqs2iss_eq_int_l[17]), |
| 1912 | .int_scheduled (int_scheduled_41), |
| 1913 | |
| 1914 | .sw_wr (sw_state_wr), |
| 1915 | .sw_addr_sel (sw_state_addr_sel_41), |
| 1916 | .sw_wr_data (sw_state_data), |
| 1917 | |
| 1918 | .mondo_state (mondo_state_41) |
| 1919 | |
| 1920 | ); |
| 1921 | |
| 1922 | |
| 1923 | dmu_imu_iss_fsm fsm_42( |
| 1924 | |
| 1925 | .clk (clk), |
| 1926 | .rst_l (rst_l), |
| 1927 | |
| 1928 | .int_detected (eqs2iss_eq_int_l[18]), |
| 1929 | .int_scheduled (int_scheduled_42), |
| 1930 | |
| 1931 | .sw_wr (sw_state_wr), |
| 1932 | .sw_addr_sel (sw_state_addr_sel_42), |
| 1933 | .sw_wr_data (sw_state_data), |
| 1934 | |
| 1935 | .mondo_state (mondo_state_42) |
| 1936 | |
| 1937 | ); |
| 1938 | |
| 1939 | |
| 1940 | dmu_imu_iss_fsm fsm_43( |
| 1941 | |
| 1942 | .clk (clk), |
| 1943 | .rst_l (rst_l), |
| 1944 | |
| 1945 | .int_detected (eqs2iss_eq_int_l[19]), |
| 1946 | .int_scheduled (int_scheduled_43), |
| 1947 | |
| 1948 | .sw_wr (sw_state_wr), |
| 1949 | .sw_addr_sel (sw_state_addr_sel_43), |
| 1950 | .sw_wr_data (sw_state_data), |
| 1951 | |
| 1952 | .mondo_state (mondo_state_43) |
| 1953 | |
| 1954 | ); |
| 1955 | |
| 1956 | |
| 1957 | dmu_imu_iss_fsm fsm_44 ( |
| 1958 | |
| 1959 | .clk (clk), |
| 1960 | .rst_l (rst_l), |
| 1961 | |
| 1962 | .int_detected (eqs2iss_eq_int_l[20]), |
| 1963 | .int_scheduled (int_scheduled_44), |
| 1964 | |
| 1965 | .sw_wr (sw_state_wr), |
| 1966 | .sw_addr_sel (sw_state_addr_sel_44), |
| 1967 | .sw_wr_data (sw_state_data), |
| 1968 | |
| 1969 | .mondo_state (mondo_state_44) |
| 1970 | |
| 1971 | ); |
| 1972 | |
| 1973 | |
| 1974 | dmu_imu_iss_fsm fsm_45( |
| 1975 | |
| 1976 | .clk (clk), |
| 1977 | .rst_l (rst_l), |
| 1978 | |
| 1979 | .int_detected (eqs2iss_eq_int_l[21]), |
| 1980 | .int_scheduled (int_scheduled_45), |
| 1981 | |
| 1982 | .sw_wr (sw_state_wr), |
| 1983 | .sw_addr_sel (sw_state_addr_sel_45), |
| 1984 | .sw_wr_data (sw_state_data), |
| 1985 | |
| 1986 | .mondo_state (mondo_state_45) |
| 1987 | |
| 1988 | ); |
| 1989 | |
| 1990 | dmu_imu_iss_fsm fsm_46( |
| 1991 | |
| 1992 | .clk (clk), |
| 1993 | .rst_l (rst_l), |
| 1994 | |
| 1995 | .int_detected (eqs2iss_eq_int_l[22]), |
| 1996 | .int_scheduled (int_scheduled_46), |
| 1997 | |
| 1998 | .sw_wr (sw_state_wr), |
| 1999 | .sw_addr_sel (sw_state_addr_sel_46), |
| 2000 | .sw_wr_data (sw_state_data), |
| 2001 | |
| 2002 | .mondo_state (mondo_state_46) |
| 2003 | |
| 2004 | ); |
| 2005 | |
| 2006 | dmu_imu_iss_fsm fsm_47( |
| 2007 | |
| 2008 | .clk (clk), |
| 2009 | .rst_l (rst_l), |
| 2010 | |
| 2011 | .int_detected (eqs2iss_eq_int_l[23]), |
| 2012 | .int_scheduled (int_scheduled_47), |
| 2013 | |
| 2014 | .sw_wr (sw_state_wr), |
| 2015 | .sw_addr_sel (sw_state_addr_sel_47), |
| 2016 | .sw_wr_data (sw_state_data), |
| 2017 | |
| 2018 | .mondo_state (mondo_state_47) |
| 2019 | |
| 2020 | ); |
| 2021 | |
| 2022 | dmu_imu_iss_fsm fsm_48( |
| 2023 | |
| 2024 | .clk (clk), |
| 2025 | .rst_l (rst_l), |
| 2026 | |
| 2027 | .int_detected (eqs2iss_eq_int_l[24]), |
| 2028 | .int_scheduled (int_scheduled_48), |
| 2029 | |
| 2030 | .sw_wr (sw_state_wr), |
| 2031 | .sw_addr_sel (sw_state_addr_sel_48), |
| 2032 | .sw_wr_data (sw_state_data), |
| 2033 | |
| 2034 | .mondo_state (mondo_state_48) |
| 2035 | |
| 2036 | ); |
| 2037 | |
| 2038 | |
| 2039 | dmu_imu_iss_fsm fsm_49( |
| 2040 | |
| 2041 | .clk (clk), |
| 2042 | .rst_l (rst_l), |
| 2043 | |
| 2044 | .int_detected (eqs2iss_eq_int_l[25]), |
| 2045 | .int_scheduled (int_scheduled_49), |
| 2046 | |
| 2047 | .sw_wr (sw_state_wr), |
| 2048 | .sw_addr_sel (sw_state_addr_sel_49), |
| 2049 | .sw_wr_data (sw_state_data), |
| 2050 | |
| 2051 | .mondo_state (mondo_state_49) |
| 2052 | |
| 2053 | ); |
| 2054 | |
| 2055 | |
| 2056 | dmu_imu_iss_fsm fsm_50( |
| 2057 | |
| 2058 | .clk (clk), |
| 2059 | .rst_l (rst_l), |
| 2060 | |
| 2061 | .int_detected (eqs2iss_eq_int_l[26]), |
| 2062 | .int_scheduled (int_scheduled_50), |
| 2063 | |
| 2064 | .sw_wr (sw_state_wr), |
| 2065 | .sw_addr_sel (sw_state_addr_sel_50), |
| 2066 | .sw_wr_data (sw_state_data), |
| 2067 | |
| 2068 | .mondo_state (mondo_state_50) |
| 2069 | |
| 2070 | ); |
| 2071 | |
| 2072 | dmu_imu_iss_fsm fsm_51( |
| 2073 | |
| 2074 | .clk (clk), |
| 2075 | .rst_l (rst_l), |
| 2076 | |
| 2077 | .int_detected (eqs2iss_eq_int_l[27]), |
| 2078 | .int_scheduled (int_scheduled_51), |
| 2079 | |
| 2080 | .sw_wr (sw_state_wr), |
| 2081 | .sw_addr_sel (sw_state_addr_sel_51), |
| 2082 | .sw_wr_data (sw_state_data), |
| 2083 | |
| 2084 | .mondo_state (mondo_state_51) |
| 2085 | |
| 2086 | ); |
| 2087 | |
| 2088 | |
| 2089 | dmu_imu_iss_fsm fsm_52( |
| 2090 | |
| 2091 | .clk (clk), |
| 2092 | .rst_l (rst_l), |
| 2093 | |
| 2094 | .int_detected (eqs2iss_eq_int_l[28]), |
| 2095 | .int_scheduled (int_scheduled_52), |
| 2096 | |
| 2097 | .sw_wr (sw_state_wr), |
| 2098 | .sw_addr_sel (sw_state_addr_sel_52), |
| 2099 | .sw_wr_data (sw_state_data), |
| 2100 | |
| 2101 | .mondo_state (mondo_state_52) |
| 2102 | |
| 2103 | ); |
| 2104 | |
| 2105 | |
| 2106 | dmu_imu_iss_fsm fsm_53( |
| 2107 | |
| 2108 | .clk (clk), |
| 2109 | .rst_l (rst_l), |
| 2110 | |
| 2111 | .int_detected (eqs2iss_eq_int_l[29]), |
| 2112 | .int_scheduled (int_scheduled_53), |
| 2113 | |
| 2114 | .sw_wr (sw_state_wr), |
| 2115 | .sw_addr_sel (sw_state_addr_sel_53), |
| 2116 | .sw_wr_data (sw_state_data), |
| 2117 | |
| 2118 | .mondo_state (mondo_state_53) |
| 2119 | |
| 2120 | ); |
| 2121 | |
| 2122 | |
| 2123 | |
| 2124 | dmu_imu_iss_fsm fsm_54( |
| 2125 | |
| 2126 | .clk (clk), |
| 2127 | .rst_l (rst_l), |
| 2128 | |
| 2129 | .int_detected (eqs2iss_eq_int_l[30]), |
| 2130 | .int_scheduled (int_scheduled_54), |
| 2131 | |
| 2132 | .sw_wr (sw_state_wr), |
| 2133 | .sw_addr_sel (sw_state_addr_sel_54), |
| 2134 | .sw_wr_data (sw_state_data), |
| 2135 | |
| 2136 | .mondo_state (mondo_state_54) |
| 2137 | |
| 2138 | ); |
| 2139 | |
| 2140 | |
| 2141 | dmu_imu_iss_fsm fsm_55( |
| 2142 | |
| 2143 | .clk (clk), |
| 2144 | .rst_l (rst_l), |
| 2145 | |
| 2146 | .int_detected (eqs2iss_eq_int_l[31]), |
| 2147 | .int_scheduled (int_scheduled_55), |
| 2148 | |
| 2149 | .sw_wr (sw_state_wr), |
| 2150 | .sw_addr_sel (sw_state_addr_sel_55), |
| 2151 | .sw_wr_data (sw_state_data), |
| 2152 | |
| 2153 | .mondo_state (mondo_state_55) |
| 2154 | |
| 2155 | ); |
| 2156 | |
| 2157 | dmu_imu_iss_fsm fsm_56( |
| 2158 | |
| 2159 | .clk (clk), |
| 2160 | .rst_l (rst_l), |
| 2161 | |
| 2162 | .int_detected (eqs2iss_eq_int_l[32]), |
| 2163 | .int_scheduled (int_scheduled_56), |
| 2164 | |
| 2165 | .sw_wr (sw_state_wr), |
| 2166 | .sw_addr_sel (sw_state_addr_sel_56), |
| 2167 | .sw_wr_data (sw_state_data), |
| 2168 | |
| 2169 | .mondo_state (mondo_state_56) |
| 2170 | |
| 2171 | ); |
| 2172 | |
| 2173 | dmu_imu_iss_fsm fsm_57( |
| 2174 | |
| 2175 | .clk (clk), |
| 2176 | .rst_l (rst_l), |
| 2177 | |
| 2178 | .int_detected (eqs2iss_eq_int_l[33]), |
| 2179 | .int_scheduled (int_scheduled_57), |
| 2180 | |
| 2181 | .sw_wr (sw_state_wr), |
| 2182 | .sw_addr_sel (sw_state_addr_sel_57), |
| 2183 | .sw_wr_data (sw_state_data), |
| 2184 | |
| 2185 | .mondo_state (mondo_state_57) |
| 2186 | |
| 2187 | ); |
| 2188 | |
| 2189 | dmu_imu_iss_fsm fsm_58( |
| 2190 | |
| 2191 | .clk (clk), |
| 2192 | .rst_l (rst_l), |
| 2193 | |
| 2194 | .int_detected (eqs2iss_eq_int_l[34]), |
| 2195 | .int_scheduled (int_scheduled_58), |
| 2196 | |
| 2197 | .sw_wr (sw_state_wr), |
| 2198 | .sw_addr_sel (sw_state_addr_sel_58), |
| 2199 | .sw_wr_data (sw_state_data), |
| 2200 | |
| 2201 | .mondo_state (mondo_state_58) |
| 2202 | |
| 2203 | ); |
| 2204 | |
| 2205 | |
| 2206 | dmu_imu_iss_fsm fsm_59( |
| 2207 | |
| 2208 | .clk (clk), |
| 2209 | .rst_l (rst_l), |
| 2210 | |
| 2211 | .int_detected (eqs2iss_eq_int_l[35]), |
| 2212 | .int_scheduled (int_scheduled_59), |
| 2213 | |
| 2214 | .sw_wr (sw_state_wr), |
| 2215 | .sw_addr_sel (sw_state_addr_sel_59), |
| 2216 | .sw_wr_data (sw_state_data), |
| 2217 | |
| 2218 | .mondo_state (mondo_state_59) |
| 2219 | |
| 2220 | ); |
| 2221 | |
| 2222 | |
| 2223 | //--------------------------------------------- |
| 2224 | // IS2 Interupt FSM's (Mondo's 60 & 61) |
| 2225 | //--------------------------------------------- |
| 2226 | |
| 2227 | // dmu_imu_iss_fsm fsm_60( |
| 2228 | // |
| 2229 | // .clk (clk), |
| 2230 | // .rst_l (rst_l), |
| 2231 | // |
| 2232 | // .int_detected (j2d_i2c0_int_l), |
| 2233 | // .int_scheduled (int_scheduled_60), |
| 2234 | // |
| 2235 | // .sw_wr (sw_state_wr), |
| 2236 | // .sw_addr_sel (sw_state_addr_sel_60), |
| 2237 | // .sw_wr_data (sw_state_data), |
| 2238 | // |
| 2239 | // .mondo_state (mondo_state_60) |
| 2240 | // |
| 2241 | // ); |
| 2242 | |
| 2243 | // dmu_imu_iss_fsm fsm_61( |
| 2244 | // |
| 2245 | // .clk (clk), |
| 2246 | // .rst_l (rst_l), |
| 2247 | // |
| 2248 | // .int_detected (j2d_i2c1_int_l), |
| 2249 | // .int_scheduled (int_scheduled_61), |
| 2250 | // |
| 2251 | // .sw_wr (sw_state_wr), |
| 2252 | // .sw_addr_sel (sw_state_addr_sel_61), |
| 2253 | // .sw_wr_data (sw_state_data), |
| 2254 | // |
| 2255 | // .mondo_state (mondo_state_61) |
| 2256 | // |
| 2257 | // ); |
| 2258 | |
| 2259 | |
| 2260 | //--------------------------------------------- |
| 2261 | // Internal Interupt FSM's (Mondo's 62 & 63) |
| 2262 | //--------------------------------------------- |
| 2263 | |
| 2264 | |
| 2265 | dmu_imu_iss_fsm fsm_62( |
| 2266 | |
| 2267 | .clk (clk), |
| 2268 | .rst_l (rst_l), |
| 2269 | |
| 2270 | .int_detected (ics2iss_mondo_62_int_l), |
| 2271 | .int_scheduled (int_scheduled_62), |
| 2272 | |
| 2273 | .sw_wr (sw_state_wr), |
| 2274 | .sw_addr_sel (sw_state_addr_sel_62), |
| 2275 | .sw_wr_data (sw_state_data), |
| 2276 | |
| 2277 | .mondo_state (mondo_state_62) |
| 2278 | |
| 2279 | ); |
| 2280 | |
| 2281 | |
| 2282 | dmu_imu_iss_fsm fsm_63( |
| 2283 | |
| 2284 | .clk (clk), |
| 2285 | .rst_l (rst_l), |
| 2286 | |
| 2287 | .int_detected (ics2iss_mondo_63_int_l), |
| 2288 | .int_scheduled (int_scheduled_63), |
| 2289 | |
| 2290 | .sw_wr (sw_state_wr), |
| 2291 | .sw_addr_sel (sw_state_addr_sel_63), |
| 2292 | .sw_wr_data (sw_state_data), |
| 2293 | |
| 2294 | .mondo_state (mondo_state_63) |
| 2295 | |
| 2296 | ); |
| 2297 | |
| 2298 | |
| 2299 | |
| 2300 | |
| 2301 | |
| 2302 | endmodule |
| 2303 | |
| 2304 | |
| 2305 | |
| 2306 | |
| 2307 | |
| 2308 | |
| 2309 | |
| 2310 | |
| 2311 | |
| 2312 | |
| 2313 | |
| 2314 | |
| 2315 | |