| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_iss_addr_decode.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_iss_addr_decode |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | daemon_csrbus_valid, |
| 40 | daemon_csrbus_addr, |
| 41 | csrbus_src_bus, |
| 42 | daemon_csrbus_wr, |
| 43 | daemon_csrbus_wr_out, |
| 44 | daemon_csrbus_wr_data, |
| 45 | daemon_csrbus_wr_data_out, |
| 46 | daemon_csrbus_mapped, |
| 47 | csrbus_acc_vio, |
| 48 | daemon_transaction_in_progress, |
| 49 | instance_id, |
| 50 | daemon_csrbus_done, |
| 51 | interrupt_mapping_20_select_pulse, |
| 52 | interrupt_mapping_21_select_pulse, |
| 53 | interrupt_mapping_22_select_pulse, |
| 54 | interrupt_mapping_23_select_pulse, |
| 55 | interrupt_mapping_24_select_pulse, |
| 56 | interrupt_mapping_25_select_pulse, |
| 57 | interrupt_mapping_26_select_pulse, |
| 58 | interrupt_mapping_27_select_pulse, |
| 59 | interrupt_mapping_28_select_pulse, |
| 60 | interrupt_mapping_29_select_pulse, |
| 61 | interrupt_mapping_30_select_pulse, |
| 62 | interrupt_mapping_31_select_pulse, |
| 63 | interrupt_mapping_32_select_pulse, |
| 64 | interrupt_mapping_33_select_pulse, |
| 65 | interrupt_mapping_34_select_pulse, |
| 66 | interrupt_mapping_35_select_pulse, |
| 67 | interrupt_mapping_36_select_pulse, |
| 68 | interrupt_mapping_37_select_pulse, |
| 69 | interrupt_mapping_38_select_pulse, |
| 70 | interrupt_mapping_39_select_pulse, |
| 71 | interrupt_mapping_40_select_pulse, |
| 72 | interrupt_mapping_41_select_pulse, |
| 73 | interrupt_mapping_42_select_pulse, |
| 74 | interrupt_mapping_43_select_pulse, |
| 75 | interrupt_mapping_44_select_pulse, |
| 76 | interrupt_mapping_45_select_pulse, |
| 77 | interrupt_mapping_46_select_pulse, |
| 78 | interrupt_mapping_47_select_pulse, |
| 79 | interrupt_mapping_48_select_pulse, |
| 80 | interrupt_mapping_49_select_pulse, |
| 81 | interrupt_mapping_50_select_pulse, |
| 82 | interrupt_mapping_51_select_pulse, |
| 83 | interrupt_mapping_52_select_pulse, |
| 84 | interrupt_mapping_53_select_pulse, |
| 85 | interrupt_mapping_54_select_pulse, |
| 86 | interrupt_mapping_55_select_pulse, |
| 87 | interrupt_mapping_56_select_pulse, |
| 88 | interrupt_mapping_57_select_pulse, |
| 89 | interrupt_mapping_58_select_pulse, |
| 90 | interrupt_mapping_59_select_pulse, |
| 91 | interrupt_mapping_62_select_pulse, |
| 92 | interrupt_mapping_63_select_pulse, |
| 93 | clr_int_reg_20_select, |
| 94 | clr_int_reg_21_select, |
| 95 | clr_int_reg_22_select, |
| 96 | clr_int_reg_23_select, |
| 97 | clr_int_reg_24_select, |
| 98 | clr_int_reg_25_select, |
| 99 | clr_int_reg_26_select, |
| 100 | clr_int_reg_27_select, |
| 101 | clr_int_reg_28_select, |
| 102 | clr_int_reg_29_select, |
| 103 | clr_int_reg_30_select, |
| 104 | clr_int_reg_31_select, |
| 105 | clr_int_reg_32_select, |
| 106 | clr_int_reg_33_select, |
| 107 | clr_int_reg_34_select, |
| 108 | clr_int_reg_35_select, |
| 109 | clr_int_reg_36_select, |
| 110 | clr_int_reg_37_select, |
| 111 | clr_int_reg_38_select, |
| 112 | clr_int_reg_39_select, |
| 113 | clr_int_reg_40_select, |
| 114 | clr_int_reg_41_select, |
| 115 | clr_int_reg_42_select, |
| 116 | clr_int_reg_43_select, |
| 117 | clr_int_reg_44_select, |
| 118 | clr_int_reg_45_select, |
| 119 | clr_int_reg_46_select, |
| 120 | clr_int_reg_47_select, |
| 121 | clr_int_reg_48_select, |
| 122 | clr_int_reg_49_select, |
| 123 | clr_int_reg_50_select, |
| 124 | clr_int_reg_51_select, |
| 125 | clr_int_reg_52_select, |
| 126 | clr_int_reg_53_select, |
| 127 | clr_int_reg_54_select, |
| 128 | clr_int_reg_55_select, |
| 129 | clr_int_reg_56_select, |
| 130 | clr_int_reg_57_select, |
| 131 | clr_int_reg_58_select, |
| 132 | clr_int_reg_59_select, |
| 133 | clr_int_reg_62_select, |
| 134 | clr_int_reg_63_select, |
| 135 | interrupt_retry_timer_select_pulse, |
| 136 | interrupt_state_status_1_select, |
| 137 | interrupt_state_status_2_select |
| 138 | ); |
| 139 | |
| 140 | //==================================================================== |
| 141 | // Polarity declarations |
| 142 | //==================================================================== |
| 143 | input clk; // Clock signal |
| 144 | input rst_l; // Reset |
| 145 | input daemon_csrbus_valid; // Daemon_Valid |
| 146 | input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr |
| 147 | input [1:0] csrbus_src_bus; // Source bus |
| 148 | input daemon_csrbus_wr; // Read/Write signal |
| 149 | output daemon_csrbus_wr_out; // Read/Write signal |
| 150 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data |
| 151 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data |
| 152 | output daemon_csrbus_mapped; // mapped |
| 153 | output csrbus_acc_vio; // acc_vio |
| 154 | input daemon_transaction_in_progress; // daemon_transaction_in_progress |
| 155 | input instance_id; // Instance ID |
| 156 | output daemon_csrbus_done; // Operation is done |
| 157 | output interrupt_mapping_20_select_pulse; // select signal |
| 158 | output interrupt_mapping_21_select_pulse; // select signal |
| 159 | output interrupt_mapping_22_select_pulse; // select signal |
| 160 | output interrupt_mapping_23_select_pulse; // select signal |
| 161 | output interrupt_mapping_24_select_pulse; // select signal |
| 162 | output interrupt_mapping_25_select_pulse; // select signal |
| 163 | output interrupt_mapping_26_select_pulse; // select signal |
| 164 | output interrupt_mapping_27_select_pulse; // select signal |
| 165 | output interrupt_mapping_28_select_pulse; // select signal |
| 166 | output interrupt_mapping_29_select_pulse; // select signal |
| 167 | output interrupt_mapping_30_select_pulse; // select signal |
| 168 | output interrupt_mapping_31_select_pulse; // select signal |
| 169 | output interrupt_mapping_32_select_pulse; // select signal |
| 170 | output interrupt_mapping_33_select_pulse; // select signal |
| 171 | output interrupt_mapping_34_select_pulse; // select signal |
| 172 | output interrupt_mapping_35_select_pulse; // select signal |
| 173 | output interrupt_mapping_36_select_pulse; // select signal |
| 174 | output interrupt_mapping_37_select_pulse; // select signal |
| 175 | output interrupt_mapping_38_select_pulse; // select signal |
| 176 | output interrupt_mapping_39_select_pulse; // select signal |
| 177 | output interrupt_mapping_40_select_pulse; // select signal |
| 178 | output interrupt_mapping_41_select_pulse; // select signal |
| 179 | output interrupt_mapping_42_select_pulse; // select signal |
| 180 | output interrupt_mapping_43_select_pulse; // select signal |
| 181 | output interrupt_mapping_44_select_pulse; // select signal |
| 182 | output interrupt_mapping_45_select_pulse; // select signal |
| 183 | output interrupt_mapping_46_select_pulse; // select signal |
| 184 | output interrupt_mapping_47_select_pulse; // select signal |
| 185 | output interrupt_mapping_48_select_pulse; // select signal |
| 186 | output interrupt_mapping_49_select_pulse; // select signal |
| 187 | output interrupt_mapping_50_select_pulse; // select signal |
| 188 | output interrupt_mapping_51_select_pulse; // select signal |
| 189 | output interrupt_mapping_52_select_pulse; // select signal |
| 190 | output interrupt_mapping_53_select_pulse; // select signal |
| 191 | output interrupt_mapping_54_select_pulse; // select signal |
| 192 | output interrupt_mapping_55_select_pulse; // select signal |
| 193 | output interrupt_mapping_56_select_pulse; // select signal |
| 194 | output interrupt_mapping_57_select_pulse; // select signal |
| 195 | output interrupt_mapping_58_select_pulse; // select signal |
| 196 | output interrupt_mapping_59_select_pulse; // select signal |
| 197 | output interrupt_mapping_62_select_pulse; // select signal |
| 198 | output interrupt_mapping_63_select_pulse; // select signal |
| 199 | output clr_int_reg_20_select; // select signal |
| 200 | output clr_int_reg_21_select; // select signal |
| 201 | output clr_int_reg_22_select; // select signal |
| 202 | output clr_int_reg_23_select; // select signal |
| 203 | output clr_int_reg_24_select; // select signal |
| 204 | output clr_int_reg_25_select; // select signal |
| 205 | output clr_int_reg_26_select; // select signal |
| 206 | output clr_int_reg_27_select; // select signal |
| 207 | output clr_int_reg_28_select; // select signal |
| 208 | output clr_int_reg_29_select; // select signal |
| 209 | output clr_int_reg_30_select; // select signal |
| 210 | output clr_int_reg_31_select; // select signal |
| 211 | output clr_int_reg_32_select; // select signal |
| 212 | output clr_int_reg_33_select; // select signal |
| 213 | output clr_int_reg_34_select; // select signal |
| 214 | output clr_int_reg_35_select; // select signal |
| 215 | output clr_int_reg_36_select; // select signal |
| 216 | output clr_int_reg_37_select; // select signal |
| 217 | output clr_int_reg_38_select; // select signal |
| 218 | output clr_int_reg_39_select; // select signal |
| 219 | output clr_int_reg_40_select; // select signal |
| 220 | output clr_int_reg_41_select; // select signal |
| 221 | output clr_int_reg_42_select; // select signal |
| 222 | output clr_int_reg_43_select; // select signal |
| 223 | output clr_int_reg_44_select; // select signal |
| 224 | output clr_int_reg_45_select; // select signal |
| 225 | output clr_int_reg_46_select; // select signal |
| 226 | output clr_int_reg_47_select; // select signal |
| 227 | output clr_int_reg_48_select; // select signal |
| 228 | output clr_int_reg_49_select; // select signal |
| 229 | output clr_int_reg_50_select; // select signal |
| 230 | output clr_int_reg_51_select; // select signal |
| 231 | output clr_int_reg_52_select; // select signal |
| 232 | output clr_int_reg_53_select; // select signal |
| 233 | output clr_int_reg_54_select; // select signal |
| 234 | output clr_int_reg_55_select; // select signal |
| 235 | output clr_int_reg_56_select; // select signal |
| 236 | output clr_int_reg_57_select; // select signal |
| 237 | output clr_int_reg_58_select; // select signal |
| 238 | output clr_int_reg_59_select; // select signal |
| 239 | output clr_int_reg_62_select; // select signal |
| 240 | output clr_int_reg_63_select; // select signal |
| 241 | output interrupt_retry_timer_select_pulse; // select signal |
| 242 | output interrupt_state_status_1_select; // select signal |
| 243 | output interrupt_state_status_2_select; // select signal |
| 244 | |
| 245 | //==================================================================== |
| 246 | // Type declarations |
| 247 | //==================================================================== |
| 248 | wire clk; // Clock signal |
| 249 | wire rst_l; // Reset |
| 250 | wire daemon_csrbus_valid; // Daemon_Valid |
| 251 | wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr |
| 252 | wire [1:0] csrbus_src_bus; // Source bus |
| 253 | wire daemon_csrbus_wr; // Read/Write signal |
| 254 | reg daemon_csrbus_wr_out; // Read/Write signal |
| 255 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data |
| 256 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data |
| 257 | wire daemon_csrbus_mapped; // mapped |
| 258 | wire csrbus_acc_vio; // acc_vio |
| 259 | wire daemon_transaction_in_progress; // daemon_transaction_in_progress |
| 260 | wire instance_id; // Instance ID |
| 261 | wire daemon_csrbus_done; // Operation is done |
| 262 | reg interrupt_mapping_20_select_pulse; // select signal |
| 263 | reg interrupt_mapping_21_select_pulse; // select signal |
| 264 | reg interrupt_mapping_22_select_pulse; // select signal |
| 265 | reg interrupt_mapping_23_select_pulse; // select signal |
| 266 | reg interrupt_mapping_24_select_pulse; // select signal |
| 267 | reg interrupt_mapping_25_select_pulse; // select signal |
| 268 | reg interrupt_mapping_26_select_pulse; // select signal |
| 269 | reg interrupt_mapping_27_select_pulse; // select signal |
| 270 | reg interrupt_mapping_28_select_pulse; // select signal |
| 271 | reg interrupt_mapping_29_select_pulse; // select signal |
| 272 | reg interrupt_mapping_30_select_pulse; // select signal |
| 273 | reg interrupt_mapping_31_select_pulse; // select signal |
| 274 | reg interrupt_mapping_32_select_pulse; // select signal |
| 275 | reg interrupt_mapping_33_select_pulse; // select signal |
| 276 | reg interrupt_mapping_34_select_pulse; // select signal |
| 277 | reg interrupt_mapping_35_select_pulse; // select signal |
| 278 | reg interrupt_mapping_36_select_pulse; // select signal |
| 279 | reg interrupt_mapping_37_select_pulse; // select signal |
| 280 | reg interrupt_mapping_38_select_pulse; // select signal |
| 281 | reg interrupt_mapping_39_select_pulse; // select signal |
| 282 | reg interrupt_mapping_40_select_pulse; // select signal |
| 283 | reg interrupt_mapping_41_select_pulse; // select signal |
| 284 | reg interrupt_mapping_42_select_pulse; // select signal |
| 285 | reg interrupt_mapping_43_select_pulse; // select signal |
| 286 | reg interrupt_mapping_44_select_pulse; // select signal |
| 287 | reg interrupt_mapping_45_select_pulse; // select signal |
| 288 | reg interrupt_mapping_46_select_pulse; // select signal |
| 289 | reg interrupt_mapping_47_select_pulse; // select signal |
| 290 | reg interrupt_mapping_48_select_pulse; // select signal |
| 291 | reg interrupt_mapping_49_select_pulse; // select signal |
| 292 | reg interrupt_mapping_50_select_pulse; // select signal |
| 293 | reg interrupt_mapping_51_select_pulse; // select signal |
| 294 | reg interrupt_mapping_52_select_pulse; // select signal |
| 295 | reg interrupt_mapping_53_select_pulse; // select signal |
| 296 | reg interrupt_mapping_54_select_pulse; // select signal |
| 297 | reg interrupt_mapping_55_select_pulse; // select signal |
| 298 | reg interrupt_mapping_56_select_pulse; // select signal |
| 299 | reg interrupt_mapping_57_select_pulse; // select signal |
| 300 | reg interrupt_mapping_58_select_pulse; // select signal |
| 301 | reg interrupt_mapping_59_select_pulse; // select signal |
| 302 | reg interrupt_mapping_62_select_pulse; // select signal |
| 303 | reg interrupt_mapping_63_select_pulse; // select signal |
| 304 | reg clr_int_reg_20_select; // select signal |
| 305 | reg clr_int_reg_21_select; // select signal |
| 306 | reg clr_int_reg_22_select; // select signal |
| 307 | reg clr_int_reg_23_select; // select signal |
| 308 | reg clr_int_reg_24_select; // select signal |
| 309 | reg clr_int_reg_25_select; // select signal |
| 310 | reg clr_int_reg_26_select; // select signal |
| 311 | reg clr_int_reg_27_select; // select signal |
| 312 | reg clr_int_reg_28_select; // select signal |
| 313 | reg clr_int_reg_29_select; // select signal |
| 314 | reg clr_int_reg_30_select; // select signal |
| 315 | reg clr_int_reg_31_select; // select signal |
| 316 | reg clr_int_reg_32_select; // select signal |
| 317 | reg clr_int_reg_33_select; // select signal |
| 318 | reg clr_int_reg_34_select; // select signal |
| 319 | reg clr_int_reg_35_select; // select signal |
| 320 | reg clr_int_reg_36_select; // select signal |
| 321 | reg clr_int_reg_37_select; // select signal |
| 322 | reg clr_int_reg_38_select; // select signal |
| 323 | reg clr_int_reg_39_select; // select signal |
| 324 | reg clr_int_reg_40_select; // select signal |
| 325 | reg clr_int_reg_41_select; // select signal |
| 326 | reg clr_int_reg_42_select; // select signal |
| 327 | reg clr_int_reg_43_select; // select signal |
| 328 | reg clr_int_reg_44_select; // select signal |
| 329 | reg clr_int_reg_45_select; // select signal |
| 330 | reg clr_int_reg_46_select; // select signal |
| 331 | reg clr_int_reg_47_select; // select signal |
| 332 | reg clr_int_reg_48_select; // select signal |
| 333 | reg clr_int_reg_49_select; // select signal |
| 334 | reg clr_int_reg_50_select; // select signal |
| 335 | reg clr_int_reg_51_select; // select signal |
| 336 | reg clr_int_reg_52_select; // select signal |
| 337 | reg clr_int_reg_53_select; // select signal |
| 338 | reg clr_int_reg_54_select; // select signal |
| 339 | reg clr_int_reg_55_select; // select signal |
| 340 | reg clr_int_reg_56_select; // select signal |
| 341 | reg clr_int_reg_57_select; // select signal |
| 342 | reg clr_int_reg_58_select; // select signal |
| 343 | reg clr_int_reg_59_select; // select signal |
| 344 | reg clr_int_reg_62_select; // select signal |
| 345 | reg clr_int_reg_63_select; // select signal |
| 346 | reg interrupt_retry_timer_select_pulse; // select signal |
| 347 | reg interrupt_state_status_1_select; // select signal |
| 348 | reg interrupt_state_status_2_select; // select signal |
| 349 | |
| 350 | |
| 351 | //==================================================================== |
| 352 | // Clocked valid |
| 353 | //==================================================================== |
| 354 | reg clocked_valid; |
| 355 | reg clocked_valid_pulse; |
| 356 | always @(posedge clk) |
| 357 | begin |
| 358 | if(~rst_l) |
| 359 | begin |
| 360 | clocked_valid <= 1'b0; |
| 361 | clocked_valid_pulse <= 1'b0; |
| 362 | end |
| 363 | else |
| 364 | begin |
| 365 | clocked_valid <= daemon_csrbus_valid; |
| 366 | clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid; |
| 367 | end |
| 368 | end |
| 369 | |
| 370 | //==================================================================== |
| 371 | // Address Decode |
| 372 | //==================================================================== |
| 373 | reg interrupt_mapping_20_addr_decoded; |
| 374 | reg interrupt_mapping_21_addr_decoded; |
| 375 | reg interrupt_mapping_22_addr_decoded; |
| 376 | reg interrupt_mapping_23_addr_decoded; |
| 377 | reg interrupt_mapping_24_addr_decoded; |
| 378 | reg interrupt_mapping_25_addr_decoded; |
| 379 | reg interrupt_mapping_26_addr_decoded; |
| 380 | reg interrupt_mapping_27_addr_decoded; |
| 381 | reg interrupt_mapping_28_addr_decoded; |
| 382 | reg interrupt_mapping_29_addr_decoded; |
| 383 | reg interrupt_mapping_30_addr_decoded; |
| 384 | reg interrupt_mapping_31_addr_decoded; |
| 385 | reg interrupt_mapping_32_addr_decoded; |
| 386 | reg interrupt_mapping_33_addr_decoded; |
| 387 | reg interrupt_mapping_34_addr_decoded; |
| 388 | reg interrupt_mapping_35_addr_decoded; |
| 389 | reg interrupt_mapping_36_addr_decoded; |
| 390 | reg interrupt_mapping_37_addr_decoded; |
| 391 | reg interrupt_mapping_38_addr_decoded; |
| 392 | reg interrupt_mapping_39_addr_decoded; |
| 393 | reg interrupt_mapping_40_addr_decoded; |
| 394 | reg interrupt_mapping_41_addr_decoded; |
| 395 | reg interrupt_mapping_42_addr_decoded; |
| 396 | reg interrupt_mapping_43_addr_decoded; |
| 397 | reg interrupt_mapping_44_addr_decoded; |
| 398 | reg interrupt_mapping_45_addr_decoded; |
| 399 | reg interrupt_mapping_46_addr_decoded; |
| 400 | reg interrupt_mapping_47_addr_decoded; |
| 401 | reg interrupt_mapping_48_addr_decoded; |
| 402 | reg interrupt_mapping_49_addr_decoded; |
| 403 | reg interrupt_mapping_50_addr_decoded; |
| 404 | reg interrupt_mapping_51_addr_decoded; |
| 405 | reg interrupt_mapping_52_addr_decoded; |
| 406 | reg interrupt_mapping_53_addr_decoded; |
| 407 | reg interrupt_mapping_54_addr_decoded; |
| 408 | reg interrupt_mapping_55_addr_decoded; |
| 409 | reg interrupt_mapping_56_addr_decoded; |
| 410 | reg interrupt_mapping_57_addr_decoded; |
| 411 | reg interrupt_mapping_58_addr_decoded; |
| 412 | reg interrupt_mapping_59_addr_decoded; |
| 413 | reg interrupt_mapping_62_addr_decoded; |
| 414 | reg interrupt_mapping_63_addr_decoded; |
| 415 | reg clr_int_reg_20_addr_decoded; |
| 416 | reg clr_int_reg_21_addr_decoded; |
| 417 | reg clr_int_reg_22_addr_decoded; |
| 418 | reg clr_int_reg_23_addr_decoded; |
| 419 | reg clr_int_reg_24_addr_decoded; |
| 420 | reg clr_int_reg_25_addr_decoded; |
| 421 | reg clr_int_reg_26_addr_decoded; |
| 422 | reg clr_int_reg_27_addr_decoded; |
| 423 | reg clr_int_reg_28_addr_decoded; |
| 424 | reg clr_int_reg_29_addr_decoded; |
| 425 | reg clr_int_reg_30_addr_decoded; |
| 426 | reg clr_int_reg_31_addr_decoded; |
| 427 | reg clr_int_reg_32_addr_decoded; |
| 428 | reg clr_int_reg_33_addr_decoded; |
| 429 | reg clr_int_reg_34_addr_decoded; |
| 430 | reg clr_int_reg_35_addr_decoded; |
| 431 | reg clr_int_reg_36_addr_decoded; |
| 432 | reg clr_int_reg_37_addr_decoded; |
| 433 | reg clr_int_reg_38_addr_decoded; |
| 434 | reg clr_int_reg_39_addr_decoded; |
| 435 | reg clr_int_reg_40_addr_decoded; |
| 436 | reg clr_int_reg_41_addr_decoded; |
| 437 | reg clr_int_reg_42_addr_decoded; |
| 438 | reg clr_int_reg_43_addr_decoded; |
| 439 | reg clr_int_reg_44_addr_decoded; |
| 440 | reg clr_int_reg_45_addr_decoded; |
| 441 | reg clr_int_reg_46_addr_decoded; |
| 442 | reg clr_int_reg_47_addr_decoded; |
| 443 | reg clr_int_reg_48_addr_decoded; |
| 444 | reg clr_int_reg_49_addr_decoded; |
| 445 | reg clr_int_reg_50_addr_decoded; |
| 446 | reg clr_int_reg_51_addr_decoded; |
| 447 | reg clr_int_reg_52_addr_decoded; |
| 448 | reg clr_int_reg_53_addr_decoded; |
| 449 | reg clr_int_reg_54_addr_decoded; |
| 450 | reg clr_int_reg_55_addr_decoded; |
| 451 | reg clr_int_reg_56_addr_decoded; |
| 452 | reg clr_int_reg_57_addr_decoded; |
| 453 | reg clr_int_reg_58_addr_decoded; |
| 454 | reg clr_int_reg_59_addr_decoded; |
| 455 | reg clr_int_reg_62_addr_decoded; |
| 456 | reg clr_int_reg_63_addr_decoded; |
| 457 | reg interrupt_retry_timer_addr_decoded; |
| 458 | reg interrupt_state_status_1_addr_decoded; |
| 459 | reg interrupt_state_status_2_addr_decoded; |
| 460 | |
| 461 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) |
| 462 | begin |
| 463 | if (~daemon_csrbus_valid) |
| 464 | begin |
| 465 | interrupt_mapping_20_addr_decoded = 1'b0; |
| 466 | interrupt_mapping_21_addr_decoded = 1'b0; |
| 467 | interrupt_mapping_22_addr_decoded = 1'b0; |
| 468 | interrupt_mapping_23_addr_decoded = 1'b0; |
| 469 | interrupt_mapping_24_addr_decoded = 1'b0; |
| 470 | interrupt_mapping_25_addr_decoded = 1'b0; |
| 471 | interrupt_mapping_26_addr_decoded = 1'b0; |
| 472 | interrupt_mapping_27_addr_decoded = 1'b0; |
| 473 | interrupt_mapping_28_addr_decoded = 1'b0; |
| 474 | interrupt_mapping_29_addr_decoded = 1'b0; |
| 475 | interrupt_mapping_30_addr_decoded = 1'b0; |
| 476 | interrupt_mapping_31_addr_decoded = 1'b0; |
| 477 | interrupt_mapping_32_addr_decoded = 1'b0; |
| 478 | interrupt_mapping_33_addr_decoded = 1'b0; |
| 479 | interrupt_mapping_34_addr_decoded = 1'b0; |
| 480 | interrupt_mapping_35_addr_decoded = 1'b0; |
| 481 | interrupt_mapping_36_addr_decoded = 1'b0; |
| 482 | interrupt_mapping_37_addr_decoded = 1'b0; |
| 483 | interrupt_mapping_38_addr_decoded = 1'b0; |
| 484 | interrupt_mapping_39_addr_decoded = 1'b0; |
| 485 | interrupt_mapping_40_addr_decoded = 1'b0; |
| 486 | interrupt_mapping_41_addr_decoded = 1'b0; |
| 487 | interrupt_mapping_42_addr_decoded = 1'b0; |
| 488 | interrupt_mapping_43_addr_decoded = 1'b0; |
| 489 | interrupt_mapping_44_addr_decoded = 1'b0; |
| 490 | interrupt_mapping_45_addr_decoded = 1'b0; |
| 491 | interrupt_mapping_46_addr_decoded = 1'b0; |
| 492 | interrupt_mapping_47_addr_decoded = 1'b0; |
| 493 | interrupt_mapping_48_addr_decoded = 1'b0; |
| 494 | interrupt_mapping_49_addr_decoded = 1'b0; |
| 495 | interrupt_mapping_50_addr_decoded = 1'b0; |
| 496 | interrupt_mapping_51_addr_decoded = 1'b0; |
| 497 | interrupt_mapping_52_addr_decoded = 1'b0; |
| 498 | interrupt_mapping_53_addr_decoded = 1'b0; |
| 499 | interrupt_mapping_54_addr_decoded = 1'b0; |
| 500 | interrupt_mapping_55_addr_decoded = 1'b0; |
| 501 | interrupt_mapping_56_addr_decoded = 1'b0; |
| 502 | interrupt_mapping_57_addr_decoded = 1'b0; |
| 503 | interrupt_mapping_58_addr_decoded = 1'b0; |
| 504 | interrupt_mapping_59_addr_decoded = 1'b0; |
| 505 | interrupt_mapping_62_addr_decoded = 1'b0; |
| 506 | interrupt_mapping_63_addr_decoded = 1'b0; |
| 507 | clr_int_reg_20_addr_decoded = 1'b0; |
| 508 | clr_int_reg_21_addr_decoded = 1'b0; |
| 509 | clr_int_reg_22_addr_decoded = 1'b0; |
| 510 | clr_int_reg_23_addr_decoded = 1'b0; |
| 511 | clr_int_reg_24_addr_decoded = 1'b0; |
| 512 | clr_int_reg_25_addr_decoded = 1'b0; |
| 513 | clr_int_reg_26_addr_decoded = 1'b0; |
| 514 | clr_int_reg_27_addr_decoded = 1'b0; |
| 515 | clr_int_reg_28_addr_decoded = 1'b0; |
| 516 | clr_int_reg_29_addr_decoded = 1'b0; |
| 517 | clr_int_reg_30_addr_decoded = 1'b0; |
| 518 | clr_int_reg_31_addr_decoded = 1'b0; |
| 519 | clr_int_reg_32_addr_decoded = 1'b0; |
| 520 | clr_int_reg_33_addr_decoded = 1'b0; |
| 521 | clr_int_reg_34_addr_decoded = 1'b0; |
| 522 | clr_int_reg_35_addr_decoded = 1'b0; |
| 523 | clr_int_reg_36_addr_decoded = 1'b0; |
| 524 | clr_int_reg_37_addr_decoded = 1'b0; |
| 525 | clr_int_reg_38_addr_decoded = 1'b0; |
| 526 | clr_int_reg_39_addr_decoded = 1'b0; |
| 527 | clr_int_reg_40_addr_decoded = 1'b0; |
| 528 | clr_int_reg_41_addr_decoded = 1'b0; |
| 529 | clr_int_reg_42_addr_decoded = 1'b0; |
| 530 | clr_int_reg_43_addr_decoded = 1'b0; |
| 531 | clr_int_reg_44_addr_decoded = 1'b0; |
| 532 | clr_int_reg_45_addr_decoded = 1'b0; |
| 533 | clr_int_reg_46_addr_decoded = 1'b0; |
| 534 | clr_int_reg_47_addr_decoded = 1'b0; |
| 535 | clr_int_reg_48_addr_decoded = 1'b0; |
| 536 | clr_int_reg_49_addr_decoded = 1'b0; |
| 537 | clr_int_reg_50_addr_decoded = 1'b0; |
| 538 | clr_int_reg_51_addr_decoded = 1'b0; |
| 539 | clr_int_reg_52_addr_decoded = 1'b0; |
| 540 | clr_int_reg_53_addr_decoded = 1'b0; |
| 541 | clr_int_reg_54_addr_decoded = 1'b0; |
| 542 | clr_int_reg_55_addr_decoded = 1'b0; |
| 543 | clr_int_reg_56_addr_decoded = 1'b0; |
| 544 | clr_int_reg_57_addr_decoded = 1'b0; |
| 545 | clr_int_reg_58_addr_decoded = 1'b0; |
| 546 | clr_int_reg_59_addr_decoded = 1'b0; |
| 547 | clr_int_reg_62_addr_decoded = 1'b0; |
| 548 | clr_int_reg_63_addr_decoded = 1'b0; |
| 549 | interrupt_retry_timer_addr_decoded = 1'b0; |
| 550 | interrupt_state_status_1_addr_decoded = 1'b0; |
| 551 | interrupt_state_status_2_addr_decoded = 1'b0; |
| 552 | end |
| 553 | else |
| 554 | case (instance_id) |
| 555 | |
| 556 | `FIRE_DLC_IMU_ISS_INSTANCE_ID_VALUE_A: |
| 557 | begin |
| 558 | interrupt_mapping_20_addr_decoded = |
| 559 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_HW_ADDR; |
| 560 | interrupt_mapping_21_addr_decoded = |
| 561 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_HW_ADDR; |
| 562 | interrupt_mapping_22_addr_decoded = |
| 563 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_HW_ADDR; |
| 564 | interrupt_mapping_23_addr_decoded = |
| 565 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_HW_ADDR; |
| 566 | interrupt_mapping_24_addr_decoded = |
| 567 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_HW_ADDR; |
| 568 | interrupt_mapping_25_addr_decoded = |
| 569 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_HW_ADDR; |
| 570 | interrupt_mapping_26_addr_decoded = |
| 571 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_HW_ADDR; |
| 572 | interrupt_mapping_27_addr_decoded = |
| 573 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_HW_ADDR; |
| 574 | interrupt_mapping_28_addr_decoded = |
| 575 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_HW_ADDR; |
| 576 | interrupt_mapping_29_addr_decoded = |
| 577 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_HW_ADDR; |
| 578 | interrupt_mapping_30_addr_decoded = |
| 579 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_HW_ADDR; |
| 580 | interrupt_mapping_31_addr_decoded = |
| 581 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_HW_ADDR; |
| 582 | interrupt_mapping_32_addr_decoded = |
| 583 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_HW_ADDR; |
| 584 | interrupt_mapping_33_addr_decoded = |
| 585 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_HW_ADDR; |
| 586 | interrupt_mapping_34_addr_decoded = |
| 587 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_HW_ADDR; |
| 588 | interrupt_mapping_35_addr_decoded = |
| 589 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_HW_ADDR; |
| 590 | interrupt_mapping_36_addr_decoded = |
| 591 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_HW_ADDR; |
| 592 | interrupt_mapping_37_addr_decoded = |
| 593 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_HW_ADDR; |
| 594 | interrupt_mapping_38_addr_decoded = |
| 595 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_HW_ADDR; |
| 596 | interrupt_mapping_39_addr_decoded = |
| 597 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_HW_ADDR; |
| 598 | interrupt_mapping_40_addr_decoded = |
| 599 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_HW_ADDR; |
| 600 | interrupt_mapping_41_addr_decoded = |
| 601 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_HW_ADDR; |
| 602 | interrupt_mapping_42_addr_decoded = |
| 603 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_HW_ADDR; |
| 604 | interrupt_mapping_43_addr_decoded = |
| 605 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_HW_ADDR; |
| 606 | interrupt_mapping_44_addr_decoded = |
| 607 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_HW_ADDR; |
| 608 | interrupt_mapping_45_addr_decoded = |
| 609 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_HW_ADDR; |
| 610 | interrupt_mapping_46_addr_decoded = |
| 611 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_HW_ADDR; |
| 612 | interrupt_mapping_47_addr_decoded = |
| 613 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_HW_ADDR; |
| 614 | interrupt_mapping_48_addr_decoded = |
| 615 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_HW_ADDR; |
| 616 | interrupt_mapping_49_addr_decoded = |
| 617 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_HW_ADDR; |
| 618 | interrupt_mapping_50_addr_decoded = |
| 619 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_HW_ADDR; |
| 620 | interrupt_mapping_51_addr_decoded = |
| 621 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_HW_ADDR; |
| 622 | interrupt_mapping_52_addr_decoded = |
| 623 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_HW_ADDR; |
| 624 | interrupt_mapping_53_addr_decoded = |
| 625 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_HW_ADDR; |
| 626 | interrupt_mapping_54_addr_decoded = |
| 627 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_HW_ADDR; |
| 628 | interrupt_mapping_55_addr_decoded = |
| 629 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_HW_ADDR; |
| 630 | interrupt_mapping_56_addr_decoded = |
| 631 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_HW_ADDR; |
| 632 | interrupt_mapping_57_addr_decoded = |
| 633 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_HW_ADDR; |
| 634 | interrupt_mapping_58_addr_decoded = |
| 635 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_HW_ADDR; |
| 636 | interrupt_mapping_59_addr_decoded = |
| 637 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_HW_ADDR; |
| 638 | interrupt_mapping_62_addr_decoded = |
| 639 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_HW_ADDR; |
| 640 | interrupt_mapping_63_addr_decoded = |
| 641 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_HW_ADDR; |
| 642 | clr_int_reg_20_addr_decoded = |
| 643 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_HW_ADDR; |
| 644 | clr_int_reg_21_addr_decoded = |
| 645 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_HW_ADDR; |
| 646 | clr_int_reg_22_addr_decoded = |
| 647 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_HW_ADDR; |
| 648 | clr_int_reg_23_addr_decoded = |
| 649 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_HW_ADDR; |
| 650 | clr_int_reg_24_addr_decoded = |
| 651 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_HW_ADDR; |
| 652 | clr_int_reg_25_addr_decoded = |
| 653 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_HW_ADDR; |
| 654 | clr_int_reg_26_addr_decoded = |
| 655 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_HW_ADDR; |
| 656 | clr_int_reg_27_addr_decoded = |
| 657 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_HW_ADDR; |
| 658 | clr_int_reg_28_addr_decoded = |
| 659 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_HW_ADDR; |
| 660 | clr_int_reg_29_addr_decoded = |
| 661 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_HW_ADDR; |
| 662 | clr_int_reg_30_addr_decoded = |
| 663 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_HW_ADDR; |
| 664 | clr_int_reg_31_addr_decoded = |
| 665 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_HW_ADDR; |
| 666 | clr_int_reg_32_addr_decoded = |
| 667 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_HW_ADDR; |
| 668 | clr_int_reg_33_addr_decoded = |
| 669 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_HW_ADDR; |
| 670 | clr_int_reg_34_addr_decoded = |
| 671 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_HW_ADDR; |
| 672 | clr_int_reg_35_addr_decoded = |
| 673 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_HW_ADDR; |
| 674 | clr_int_reg_36_addr_decoded = |
| 675 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_HW_ADDR; |
| 676 | clr_int_reg_37_addr_decoded = |
| 677 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_HW_ADDR; |
| 678 | clr_int_reg_38_addr_decoded = |
| 679 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_HW_ADDR; |
| 680 | clr_int_reg_39_addr_decoded = |
| 681 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_HW_ADDR; |
| 682 | clr_int_reg_40_addr_decoded = |
| 683 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_HW_ADDR; |
| 684 | clr_int_reg_41_addr_decoded = |
| 685 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_HW_ADDR; |
| 686 | clr_int_reg_42_addr_decoded = |
| 687 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_HW_ADDR; |
| 688 | clr_int_reg_43_addr_decoded = |
| 689 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_HW_ADDR; |
| 690 | clr_int_reg_44_addr_decoded = |
| 691 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_HW_ADDR; |
| 692 | clr_int_reg_45_addr_decoded = |
| 693 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_HW_ADDR; |
| 694 | clr_int_reg_46_addr_decoded = |
| 695 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_HW_ADDR; |
| 696 | clr_int_reg_47_addr_decoded = |
| 697 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_HW_ADDR; |
| 698 | clr_int_reg_48_addr_decoded = |
| 699 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_HW_ADDR; |
| 700 | clr_int_reg_49_addr_decoded = |
| 701 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_HW_ADDR; |
| 702 | clr_int_reg_50_addr_decoded = |
| 703 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_HW_ADDR; |
| 704 | clr_int_reg_51_addr_decoded = |
| 705 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_HW_ADDR; |
| 706 | clr_int_reg_52_addr_decoded = |
| 707 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_HW_ADDR; |
| 708 | clr_int_reg_53_addr_decoded = |
| 709 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_HW_ADDR; |
| 710 | clr_int_reg_54_addr_decoded = |
| 711 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_HW_ADDR; |
| 712 | clr_int_reg_55_addr_decoded = |
| 713 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_HW_ADDR; |
| 714 | clr_int_reg_56_addr_decoded = |
| 715 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_HW_ADDR; |
| 716 | clr_int_reg_57_addr_decoded = |
| 717 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_HW_ADDR; |
| 718 | clr_int_reg_58_addr_decoded = |
| 719 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_HW_ADDR; |
| 720 | clr_int_reg_59_addr_decoded = |
| 721 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_HW_ADDR; |
| 722 | clr_int_reg_62_addr_decoded = |
| 723 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_HW_ADDR; |
| 724 | clr_int_reg_63_addr_decoded = |
| 725 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_HW_ADDR; |
| 726 | interrupt_retry_timer_addr_decoded = |
| 727 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_HW_ADDR; |
| 728 | interrupt_state_status_1_addr_decoded = |
| 729 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_HW_ADDR; |
| 730 | interrupt_state_status_2_addr_decoded = |
| 731 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_HW_ADDR; |
| 732 | end |
| 733 | |
| 734 | `FIRE_DLC_IMU_ISS_INSTANCE_ID_VALUE_B: |
| 735 | begin |
| 736 | interrupt_mapping_20_addr_decoded = |
| 737 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_20_HW_ADDR; |
| 738 | interrupt_mapping_21_addr_decoded = |
| 739 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_21_HW_ADDR; |
| 740 | interrupt_mapping_22_addr_decoded = |
| 741 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_22_HW_ADDR; |
| 742 | interrupt_mapping_23_addr_decoded = |
| 743 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_23_HW_ADDR; |
| 744 | interrupt_mapping_24_addr_decoded = |
| 745 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_24_HW_ADDR; |
| 746 | interrupt_mapping_25_addr_decoded = |
| 747 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_25_HW_ADDR; |
| 748 | interrupt_mapping_26_addr_decoded = |
| 749 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_26_HW_ADDR; |
| 750 | interrupt_mapping_27_addr_decoded = |
| 751 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_27_HW_ADDR; |
| 752 | interrupt_mapping_28_addr_decoded = |
| 753 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_28_HW_ADDR; |
| 754 | interrupt_mapping_29_addr_decoded = |
| 755 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_29_HW_ADDR; |
| 756 | interrupt_mapping_30_addr_decoded = |
| 757 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_30_HW_ADDR; |
| 758 | interrupt_mapping_31_addr_decoded = |
| 759 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_31_HW_ADDR; |
| 760 | interrupt_mapping_32_addr_decoded = |
| 761 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_32_HW_ADDR; |
| 762 | interrupt_mapping_33_addr_decoded = |
| 763 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_33_HW_ADDR; |
| 764 | interrupt_mapping_34_addr_decoded = |
| 765 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_34_HW_ADDR; |
| 766 | interrupt_mapping_35_addr_decoded = |
| 767 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_35_HW_ADDR; |
| 768 | interrupt_mapping_36_addr_decoded = |
| 769 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_36_HW_ADDR; |
| 770 | interrupt_mapping_37_addr_decoded = |
| 771 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_37_HW_ADDR; |
| 772 | interrupt_mapping_38_addr_decoded = |
| 773 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_38_HW_ADDR; |
| 774 | interrupt_mapping_39_addr_decoded = |
| 775 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_39_HW_ADDR; |
| 776 | interrupt_mapping_40_addr_decoded = |
| 777 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_40_HW_ADDR; |
| 778 | interrupt_mapping_41_addr_decoded = |
| 779 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_41_HW_ADDR; |
| 780 | interrupt_mapping_42_addr_decoded = |
| 781 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_42_HW_ADDR; |
| 782 | interrupt_mapping_43_addr_decoded = |
| 783 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_43_HW_ADDR; |
| 784 | interrupt_mapping_44_addr_decoded = |
| 785 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_44_HW_ADDR; |
| 786 | interrupt_mapping_45_addr_decoded = |
| 787 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_45_HW_ADDR; |
| 788 | interrupt_mapping_46_addr_decoded = |
| 789 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_46_HW_ADDR; |
| 790 | interrupt_mapping_47_addr_decoded = |
| 791 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_47_HW_ADDR; |
| 792 | interrupt_mapping_48_addr_decoded = |
| 793 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_48_HW_ADDR; |
| 794 | interrupt_mapping_49_addr_decoded = |
| 795 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_49_HW_ADDR; |
| 796 | interrupt_mapping_50_addr_decoded = |
| 797 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_50_HW_ADDR; |
| 798 | interrupt_mapping_51_addr_decoded = |
| 799 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_51_HW_ADDR; |
| 800 | interrupt_mapping_52_addr_decoded = |
| 801 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_52_HW_ADDR; |
| 802 | interrupt_mapping_53_addr_decoded = |
| 803 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_53_HW_ADDR; |
| 804 | interrupt_mapping_54_addr_decoded = |
| 805 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_54_HW_ADDR; |
| 806 | interrupt_mapping_55_addr_decoded = |
| 807 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_55_HW_ADDR; |
| 808 | interrupt_mapping_56_addr_decoded = |
| 809 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_56_HW_ADDR; |
| 810 | interrupt_mapping_57_addr_decoded = |
| 811 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_57_HW_ADDR; |
| 812 | interrupt_mapping_58_addr_decoded = |
| 813 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_58_HW_ADDR; |
| 814 | interrupt_mapping_59_addr_decoded = |
| 815 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_59_HW_ADDR; |
| 816 | interrupt_mapping_62_addr_decoded = |
| 817 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_62_HW_ADDR; |
| 818 | interrupt_mapping_63_addr_decoded = |
| 819 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_63_HW_ADDR; |
| 820 | clr_int_reg_20_addr_decoded = |
| 821 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_20_HW_ADDR; |
| 822 | clr_int_reg_21_addr_decoded = |
| 823 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_21_HW_ADDR; |
| 824 | clr_int_reg_22_addr_decoded = |
| 825 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_22_HW_ADDR; |
| 826 | clr_int_reg_23_addr_decoded = |
| 827 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_23_HW_ADDR; |
| 828 | clr_int_reg_24_addr_decoded = |
| 829 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_24_HW_ADDR; |
| 830 | clr_int_reg_25_addr_decoded = |
| 831 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_25_HW_ADDR; |
| 832 | clr_int_reg_26_addr_decoded = |
| 833 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_26_HW_ADDR; |
| 834 | clr_int_reg_27_addr_decoded = |
| 835 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_27_HW_ADDR; |
| 836 | clr_int_reg_28_addr_decoded = |
| 837 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_28_HW_ADDR; |
| 838 | clr_int_reg_29_addr_decoded = |
| 839 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_29_HW_ADDR; |
| 840 | clr_int_reg_30_addr_decoded = |
| 841 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_30_HW_ADDR; |
| 842 | clr_int_reg_31_addr_decoded = |
| 843 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_31_HW_ADDR; |
| 844 | clr_int_reg_32_addr_decoded = |
| 845 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_32_HW_ADDR; |
| 846 | clr_int_reg_33_addr_decoded = |
| 847 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_33_HW_ADDR; |
| 848 | clr_int_reg_34_addr_decoded = |
| 849 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_34_HW_ADDR; |
| 850 | clr_int_reg_35_addr_decoded = |
| 851 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_35_HW_ADDR; |
| 852 | clr_int_reg_36_addr_decoded = |
| 853 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_36_HW_ADDR; |
| 854 | clr_int_reg_37_addr_decoded = |
| 855 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_37_HW_ADDR; |
| 856 | clr_int_reg_38_addr_decoded = |
| 857 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_38_HW_ADDR; |
| 858 | clr_int_reg_39_addr_decoded = |
| 859 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_39_HW_ADDR; |
| 860 | clr_int_reg_40_addr_decoded = |
| 861 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_40_HW_ADDR; |
| 862 | clr_int_reg_41_addr_decoded = |
| 863 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_41_HW_ADDR; |
| 864 | clr_int_reg_42_addr_decoded = |
| 865 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_42_HW_ADDR; |
| 866 | clr_int_reg_43_addr_decoded = |
| 867 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_43_HW_ADDR; |
| 868 | clr_int_reg_44_addr_decoded = |
| 869 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_44_HW_ADDR; |
| 870 | clr_int_reg_45_addr_decoded = |
| 871 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_45_HW_ADDR; |
| 872 | clr_int_reg_46_addr_decoded = |
| 873 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_46_HW_ADDR; |
| 874 | clr_int_reg_47_addr_decoded = |
| 875 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_47_HW_ADDR; |
| 876 | clr_int_reg_48_addr_decoded = |
| 877 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_48_HW_ADDR; |
| 878 | clr_int_reg_49_addr_decoded = |
| 879 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_49_HW_ADDR; |
| 880 | clr_int_reg_50_addr_decoded = |
| 881 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_50_HW_ADDR; |
| 882 | clr_int_reg_51_addr_decoded = |
| 883 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_51_HW_ADDR; |
| 884 | clr_int_reg_52_addr_decoded = |
| 885 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_52_HW_ADDR; |
| 886 | clr_int_reg_53_addr_decoded = |
| 887 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_53_HW_ADDR; |
| 888 | clr_int_reg_54_addr_decoded = |
| 889 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_54_HW_ADDR; |
| 890 | clr_int_reg_55_addr_decoded = |
| 891 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_55_HW_ADDR; |
| 892 | clr_int_reg_56_addr_decoded = |
| 893 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_56_HW_ADDR; |
| 894 | clr_int_reg_57_addr_decoded = |
| 895 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_57_HW_ADDR; |
| 896 | clr_int_reg_58_addr_decoded = |
| 897 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_58_HW_ADDR; |
| 898 | clr_int_reg_59_addr_decoded = |
| 899 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_59_HW_ADDR; |
| 900 | clr_int_reg_62_addr_decoded = |
| 901 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_62_HW_ADDR; |
| 902 | clr_int_reg_63_addr_decoded = |
| 903 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_63_HW_ADDR; |
| 904 | interrupt_retry_timer_addr_decoded = |
| 905 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_RETRY_TIMER_HW_ADDR; |
| 906 | interrupt_state_status_1_addr_decoded = |
| 907 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_STATE_STATUS_1_HW_ADDR; |
| 908 | interrupt_state_status_2_addr_decoded = |
| 909 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_STATE_STATUS_2_HW_ADDR; |
| 910 | end |
| 911 | |
| 912 | default: |
| 913 | begin |
| 914 | interrupt_mapping_20_addr_decoded = 1'b0; |
| 915 | interrupt_mapping_21_addr_decoded = 1'b0; |
| 916 | interrupt_mapping_22_addr_decoded = 1'b0; |
| 917 | interrupt_mapping_23_addr_decoded = 1'b0; |
| 918 | interrupt_mapping_24_addr_decoded = 1'b0; |
| 919 | interrupt_mapping_25_addr_decoded = 1'b0; |
| 920 | interrupt_mapping_26_addr_decoded = 1'b0; |
| 921 | interrupt_mapping_27_addr_decoded = 1'b0; |
| 922 | interrupt_mapping_28_addr_decoded = 1'b0; |
| 923 | interrupt_mapping_29_addr_decoded = 1'b0; |
| 924 | interrupt_mapping_30_addr_decoded = 1'b0; |
| 925 | interrupt_mapping_31_addr_decoded = 1'b0; |
| 926 | interrupt_mapping_32_addr_decoded = 1'b0; |
| 927 | interrupt_mapping_33_addr_decoded = 1'b0; |
| 928 | interrupt_mapping_34_addr_decoded = 1'b0; |
| 929 | interrupt_mapping_35_addr_decoded = 1'b0; |
| 930 | interrupt_mapping_36_addr_decoded = 1'b0; |
| 931 | interrupt_mapping_37_addr_decoded = 1'b0; |
| 932 | interrupt_mapping_38_addr_decoded = 1'b0; |
| 933 | interrupt_mapping_39_addr_decoded = 1'b0; |
| 934 | interrupt_mapping_40_addr_decoded = 1'b0; |
| 935 | interrupt_mapping_41_addr_decoded = 1'b0; |
| 936 | interrupt_mapping_42_addr_decoded = 1'b0; |
| 937 | interrupt_mapping_43_addr_decoded = 1'b0; |
| 938 | interrupt_mapping_44_addr_decoded = 1'b0; |
| 939 | interrupt_mapping_45_addr_decoded = 1'b0; |
| 940 | interrupt_mapping_46_addr_decoded = 1'b0; |
| 941 | interrupt_mapping_47_addr_decoded = 1'b0; |
| 942 | interrupt_mapping_48_addr_decoded = 1'b0; |
| 943 | interrupt_mapping_49_addr_decoded = 1'b0; |
| 944 | interrupt_mapping_50_addr_decoded = 1'b0; |
| 945 | interrupt_mapping_51_addr_decoded = 1'b0; |
| 946 | interrupt_mapping_52_addr_decoded = 1'b0; |
| 947 | interrupt_mapping_53_addr_decoded = 1'b0; |
| 948 | interrupt_mapping_54_addr_decoded = 1'b0; |
| 949 | interrupt_mapping_55_addr_decoded = 1'b0; |
| 950 | interrupt_mapping_56_addr_decoded = 1'b0; |
| 951 | interrupt_mapping_57_addr_decoded = 1'b0; |
| 952 | interrupt_mapping_58_addr_decoded = 1'b0; |
| 953 | interrupt_mapping_59_addr_decoded = 1'b0; |
| 954 | interrupt_mapping_62_addr_decoded = 1'b0; |
| 955 | interrupt_mapping_63_addr_decoded = 1'b0; |
| 956 | clr_int_reg_20_addr_decoded = 1'b0; |
| 957 | clr_int_reg_21_addr_decoded = 1'b0; |
| 958 | clr_int_reg_22_addr_decoded = 1'b0; |
| 959 | clr_int_reg_23_addr_decoded = 1'b0; |
| 960 | clr_int_reg_24_addr_decoded = 1'b0; |
| 961 | clr_int_reg_25_addr_decoded = 1'b0; |
| 962 | clr_int_reg_26_addr_decoded = 1'b0; |
| 963 | clr_int_reg_27_addr_decoded = 1'b0; |
| 964 | clr_int_reg_28_addr_decoded = 1'b0; |
| 965 | clr_int_reg_29_addr_decoded = 1'b0; |
| 966 | clr_int_reg_30_addr_decoded = 1'b0; |
| 967 | clr_int_reg_31_addr_decoded = 1'b0; |
| 968 | clr_int_reg_32_addr_decoded = 1'b0; |
| 969 | clr_int_reg_33_addr_decoded = 1'b0; |
| 970 | clr_int_reg_34_addr_decoded = 1'b0; |
| 971 | clr_int_reg_35_addr_decoded = 1'b0; |
| 972 | clr_int_reg_36_addr_decoded = 1'b0; |
| 973 | clr_int_reg_37_addr_decoded = 1'b0; |
| 974 | clr_int_reg_38_addr_decoded = 1'b0; |
| 975 | clr_int_reg_39_addr_decoded = 1'b0; |
| 976 | clr_int_reg_40_addr_decoded = 1'b0; |
| 977 | clr_int_reg_41_addr_decoded = 1'b0; |
| 978 | clr_int_reg_42_addr_decoded = 1'b0; |
| 979 | clr_int_reg_43_addr_decoded = 1'b0; |
| 980 | clr_int_reg_44_addr_decoded = 1'b0; |
| 981 | clr_int_reg_45_addr_decoded = 1'b0; |
| 982 | clr_int_reg_46_addr_decoded = 1'b0; |
| 983 | clr_int_reg_47_addr_decoded = 1'b0; |
| 984 | clr_int_reg_48_addr_decoded = 1'b0; |
| 985 | clr_int_reg_49_addr_decoded = 1'b0; |
| 986 | clr_int_reg_50_addr_decoded = 1'b0; |
| 987 | clr_int_reg_51_addr_decoded = 1'b0; |
| 988 | clr_int_reg_52_addr_decoded = 1'b0; |
| 989 | clr_int_reg_53_addr_decoded = 1'b0; |
| 990 | clr_int_reg_54_addr_decoded = 1'b0; |
| 991 | clr_int_reg_55_addr_decoded = 1'b0; |
| 992 | clr_int_reg_56_addr_decoded = 1'b0; |
| 993 | clr_int_reg_57_addr_decoded = 1'b0; |
| 994 | clr_int_reg_58_addr_decoded = 1'b0; |
| 995 | clr_int_reg_59_addr_decoded = 1'b0; |
| 996 | clr_int_reg_62_addr_decoded = 1'b0; |
| 997 | clr_int_reg_63_addr_decoded = 1'b0; |
| 998 | interrupt_retry_timer_addr_decoded = 1'b0; |
| 999 | interrupt_state_status_1_addr_decoded = 1'b0; |
| 1000 | interrupt_state_status_2_addr_decoded = 1'b0; |
| 1001 | // vlint flag_system_call off |
| 1002 | // synopsys translate_off |
| 1003 | if(daemon_csrbus_valid) |
| 1004 | begin // axis tbcall_region |
| 1005 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_imu_iss_csr is bad"); `endif |
| 1006 | end // end of tbcall_region |
| 1007 | // synopsys translate_on |
| 1008 | // vlint flag_system_call on |
| 1009 | end |
| 1010 | endcase |
| 1011 | end |
| 1012 | |
| 1013 | //==================================================================== |
| 1014 | // Register violations |
| 1015 | //==================================================================== |
| 1016 | //----- reg_acc_vio: interrupt_mapping_20 |
| 1017 | reg interrupt_mapping_20_acc_vio; |
| 1018 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1019 | interrupt_mapping_20_addr_decoded or |
| 1020 | daemon_transaction_in_progress) |
| 1021 | begin |
| 1022 | if (daemon_transaction_in_progress | ~interrupt_mapping_20_addr_decoded) |
| 1023 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1024 | else |
| 1025 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1026 | // reads |
| 1027 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1028 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1029 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1030 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1031 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1032 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1033 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1034 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1035 | // writes |
| 1036 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1037 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1038 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1039 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1040 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1041 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1042 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1043 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1044 | |
| 1045 | default: |
| 1046 | begin |
| 1047 | interrupt_mapping_20_acc_vio = 1'b0; |
| 1048 | begin // axis tbcall_region |
| 1049 | // vlint flag_system_call off |
| 1050 | // synopsys translate_off |
| 1051 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_20"); `endif |
| 1052 | // synopsys translate_on |
| 1053 | // vlint flag_system_call on |
| 1054 | end // end of tbcall_region |
| 1055 | end |
| 1056 | endcase |
| 1057 | end |
| 1058 | //----- reg_acc_vio: interrupt_mapping_21 |
| 1059 | reg interrupt_mapping_21_acc_vio; |
| 1060 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1061 | interrupt_mapping_21_addr_decoded or |
| 1062 | daemon_transaction_in_progress) |
| 1063 | begin |
| 1064 | if (daemon_transaction_in_progress | ~interrupt_mapping_21_addr_decoded) |
| 1065 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1066 | else |
| 1067 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1068 | // reads |
| 1069 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1070 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1071 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1072 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1073 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1074 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1075 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1076 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1077 | // writes |
| 1078 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1079 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1080 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1081 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1082 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1083 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1084 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1085 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1086 | |
| 1087 | default: |
| 1088 | begin |
| 1089 | interrupt_mapping_21_acc_vio = 1'b0; |
| 1090 | begin // axis tbcall_region |
| 1091 | // vlint flag_system_call off |
| 1092 | // synopsys translate_off |
| 1093 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_21"); `endif |
| 1094 | // synopsys translate_on |
| 1095 | // vlint flag_system_call on |
| 1096 | end // end of tbcall_region |
| 1097 | end |
| 1098 | endcase |
| 1099 | end |
| 1100 | //----- reg_acc_vio: interrupt_mapping_22 |
| 1101 | reg interrupt_mapping_22_acc_vio; |
| 1102 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1103 | interrupt_mapping_22_addr_decoded or |
| 1104 | daemon_transaction_in_progress) |
| 1105 | begin |
| 1106 | if (daemon_transaction_in_progress | ~interrupt_mapping_22_addr_decoded) |
| 1107 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1108 | else |
| 1109 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1110 | // reads |
| 1111 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1112 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1113 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1114 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1115 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1116 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1117 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1118 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1119 | // writes |
| 1120 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1121 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1122 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1123 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1124 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1125 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1126 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1127 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1128 | |
| 1129 | default: |
| 1130 | begin |
| 1131 | interrupt_mapping_22_acc_vio = 1'b0; |
| 1132 | begin // axis tbcall_region |
| 1133 | // vlint flag_system_call off |
| 1134 | // synopsys translate_off |
| 1135 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_22"); `endif |
| 1136 | // synopsys translate_on |
| 1137 | // vlint flag_system_call on |
| 1138 | end // end of tbcall_region |
| 1139 | end |
| 1140 | endcase |
| 1141 | end |
| 1142 | //----- reg_acc_vio: interrupt_mapping_23 |
| 1143 | reg interrupt_mapping_23_acc_vio; |
| 1144 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1145 | interrupt_mapping_23_addr_decoded or |
| 1146 | daemon_transaction_in_progress) |
| 1147 | begin |
| 1148 | if (daemon_transaction_in_progress | ~interrupt_mapping_23_addr_decoded) |
| 1149 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1150 | else |
| 1151 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1152 | // reads |
| 1153 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1154 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1155 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1156 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1157 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1158 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1159 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1160 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1161 | // writes |
| 1162 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1163 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1164 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1165 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1166 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1167 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1168 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1169 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1170 | |
| 1171 | default: |
| 1172 | begin |
| 1173 | interrupt_mapping_23_acc_vio = 1'b0; |
| 1174 | begin // axis tbcall_region |
| 1175 | // vlint flag_system_call off |
| 1176 | // synopsys translate_off |
| 1177 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_23"); `endif |
| 1178 | // synopsys translate_on |
| 1179 | // vlint flag_system_call on |
| 1180 | end // end of tbcall_region |
| 1181 | end |
| 1182 | endcase |
| 1183 | end |
| 1184 | //----- reg_acc_vio: interrupt_mapping_24 |
| 1185 | reg interrupt_mapping_24_acc_vio; |
| 1186 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1187 | interrupt_mapping_24_addr_decoded or |
| 1188 | daemon_transaction_in_progress) |
| 1189 | begin |
| 1190 | if (daemon_transaction_in_progress | ~interrupt_mapping_24_addr_decoded) |
| 1191 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1192 | else |
| 1193 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1194 | // reads |
| 1195 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1196 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1197 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1198 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1199 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1200 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1201 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1202 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1203 | // writes |
| 1204 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1205 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1206 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1207 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1208 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1209 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1210 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1211 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1212 | |
| 1213 | default: |
| 1214 | begin |
| 1215 | interrupt_mapping_24_acc_vio = 1'b0; |
| 1216 | begin // axis tbcall_region |
| 1217 | // vlint flag_system_call off |
| 1218 | // synopsys translate_off |
| 1219 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_24"); `endif |
| 1220 | // synopsys translate_on |
| 1221 | // vlint flag_system_call on |
| 1222 | end // end of tbcall_region |
| 1223 | end |
| 1224 | endcase |
| 1225 | end |
| 1226 | //----- reg_acc_vio: interrupt_mapping_25 |
| 1227 | reg interrupt_mapping_25_acc_vio; |
| 1228 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1229 | interrupt_mapping_25_addr_decoded or |
| 1230 | daemon_transaction_in_progress) |
| 1231 | begin |
| 1232 | if (daemon_transaction_in_progress | ~interrupt_mapping_25_addr_decoded) |
| 1233 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1234 | else |
| 1235 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1236 | // reads |
| 1237 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1238 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1239 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1240 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1241 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1242 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1243 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1244 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1245 | // writes |
| 1246 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1247 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1248 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1249 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1250 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1251 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1252 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1253 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1254 | |
| 1255 | default: |
| 1256 | begin |
| 1257 | interrupt_mapping_25_acc_vio = 1'b0; |
| 1258 | begin // axis tbcall_region |
| 1259 | // vlint flag_system_call off |
| 1260 | // synopsys translate_off |
| 1261 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_25"); `endif |
| 1262 | // synopsys translate_on |
| 1263 | // vlint flag_system_call on |
| 1264 | end // end of tbcall_region |
| 1265 | end |
| 1266 | endcase |
| 1267 | end |
| 1268 | //----- reg_acc_vio: interrupt_mapping_26 |
| 1269 | reg interrupt_mapping_26_acc_vio; |
| 1270 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1271 | interrupt_mapping_26_addr_decoded or |
| 1272 | daemon_transaction_in_progress) |
| 1273 | begin |
| 1274 | if (daemon_transaction_in_progress | ~interrupt_mapping_26_addr_decoded) |
| 1275 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1276 | else |
| 1277 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1278 | // reads |
| 1279 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1280 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1281 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1282 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1283 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1284 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1285 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1286 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1287 | // writes |
| 1288 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1289 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1290 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1291 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1292 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1293 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1294 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1295 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1296 | |
| 1297 | default: |
| 1298 | begin |
| 1299 | interrupt_mapping_26_acc_vio = 1'b0; |
| 1300 | begin // axis tbcall_region |
| 1301 | // vlint flag_system_call off |
| 1302 | // synopsys translate_off |
| 1303 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_26"); `endif |
| 1304 | // synopsys translate_on |
| 1305 | // vlint flag_system_call on |
| 1306 | end // end of tbcall_region |
| 1307 | end |
| 1308 | endcase |
| 1309 | end |
| 1310 | //----- reg_acc_vio: interrupt_mapping_27 |
| 1311 | reg interrupt_mapping_27_acc_vio; |
| 1312 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1313 | interrupt_mapping_27_addr_decoded or |
| 1314 | daemon_transaction_in_progress) |
| 1315 | begin |
| 1316 | if (daemon_transaction_in_progress | ~interrupt_mapping_27_addr_decoded) |
| 1317 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1318 | else |
| 1319 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1320 | // reads |
| 1321 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1322 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1323 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1324 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1325 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1326 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1327 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1328 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1329 | // writes |
| 1330 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1331 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1332 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1333 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1334 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1335 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1336 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1337 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1338 | |
| 1339 | default: |
| 1340 | begin |
| 1341 | interrupt_mapping_27_acc_vio = 1'b0; |
| 1342 | begin // axis tbcall_region |
| 1343 | // vlint flag_system_call off |
| 1344 | // synopsys translate_off |
| 1345 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_27"); `endif |
| 1346 | // synopsys translate_on |
| 1347 | // vlint flag_system_call on |
| 1348 | end // end of tbcall_region |
| 1349 | end |
| 1350 | endcase |
| 1351 | end |
| 1352 | //----- reg_acc_vio: interrupt_mapping_28 |
| 1353 | reg interrupt_mapping_28_acc_vio; |
| 1354 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1355 | interrupt_mapping_28_addr_decoded or |
| 1356 | daemon_transaction_in_progress) |
| 1357 | begin |
| 1358 | if (daemon_transaction_in_progress | ~interrupt_mapping_28_addr_decoded) |
| 1359 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1360 | else |
| 1361 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1362 | // reads |
| 1363 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1364 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1365 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1366 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1367 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1368 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1369 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1370 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1371 | // writes |
| 1372 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1373 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1374 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1375 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1376 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1377 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1378 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1379 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1380 | |
| 1381 | default: |
| 1382 | begin |
| 1383 | interrupt_mapping_28_acc_vio = 1'b0; |
| 1384 | begin // axis tbcall_region |
| 1385 | // vlint flag_system_call off |
| 1386 | // synopsys translate_off |
| 1387 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_28"); `endif |
| 1388 | // synopsys translate_on |
| 1389 | // vlint flag_system_call on |
| 1390 | end // end of tbcall_region |
| 1391 | end |
| 1392 | endcase |
| 1393 | end |
| 1394 | //----- reg_acc_vio: interrupt_mapping_29 |
| 1395 | reg interrupt_mapping_29_acc_vio; |
| 1396 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1397 | interrupt_mapping_29_addr_decoded or |
| 1398 | daemon_transaction_in_progress) |
| 1399 | begin |
| 1400 | if (daemon_transaction_in_progress | ~interrupt_mapping_29_addr_decoded) |
| 1401 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1402 | else |
| 1403 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1404 | // reads |
| 1405 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1406 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1407 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1408 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1409 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1410 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1411 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1412 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1413 | // writes |
| 1414 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1415 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1416 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1417 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1418 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1419 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1420 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1421 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1422 | |
| 1423 | default: |
| 1424 | begin |
| 1425 | interrupt_mapping_29_acc_vio = 1'b0; |
| 1426 | begin // axis tbcall_region |
| 1427 | // vlint flag_system_call off |
| 1428 | // synopsys translate_off |
| 1429 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_29"); `endif |
| 1430 | // synopsys translate_on |
| 1431 | // vlint flag_system_call on |
| 1432 | end // end of tbcall_region |
| 1433 | end |
| 1434 | endcase |
| 1435 | end |
| 1436 | //----- reg_acc_vio: interrupt_mapping_30 |
| 1437 | reg interrupt_mapping_30_acc_vio; |
| 1438 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1439 | interrupt_mapping_30_addr_decoded or |
| 1440 | daemon_transaction_in_progress) |
| 1441 | begin |
| 1442 | if (daemon_transaction_in_progress | ~interrupt_mapping_30_addr_decoded) |
| 1443 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1444 | else |
| 1445 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1446 | // reads |
| 1447 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1448 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1449 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1450 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1451 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1452 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1453 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1454 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1455 | // writes |
| 1456 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1457 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1458 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1459 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1460 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1461 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1462 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1463 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1464 | |
| 1465 | default: |
| 1466 | begin |
| 1467 | interrupt_mapping_30_acc_vio = 1'b0; |
| 1468 | begin // axis tbcall_region |
| 1469 | // vlint flag_system_call off |
| 1470 | // synopsys translate_off |
| 1471 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_30"); `endif |
| 1472 | // synopsys translate_on |
| 1473 | // vlint flag_system_call on |
| 1474 | end // end of tbcall_region |
| 1475 | end |
| 1476 | endcase |
| 1477 | end |
| 1478 | //----- reg_acc_vio: interrupt_mapping_31 |
| 1479 | reg interrupt_mapping_31_acc_vio; |
| 1480 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1481 | interrupt_mapping_31_addr_decoded or |
| 1482 | daemon_transaction_in_progress) |
| 1483 | begin |
| 1484 | if (daemon_transaction_in_progress | ~interrupt_mapping_31_addr_decoded) |
| 1485 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1486 | else |
| 1487 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1488 | // reads |
| 1489 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1490 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1491 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1492 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1493 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1494 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1495 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1496 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1497 | // writes |
| 1498 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1499 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1500 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1501 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1502 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1503 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1504 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1505 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1506 | |
| 1507 | default: |
| 1508 | begin |
| 1509 | interrupt_mapping_31_acc_vio = 1'b0; |
| 1510 | begin // axis tbcall_region |
| 1511 | // vlint flag_system_call off |
| 1512 | // synopsys translate_off |
| 1513 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_31"); `endif |
| 1514 | // synopsys translate_on |
| 1515 | // vlint flag_system_call on |
| 1516 | end // end of tbcall_region |
| 1517 | end |
| 1518 | endcase |
| 1519 | end |
| 1520 | //----- reg_acc_vio: interrupt_mapping_32 |
| 1521 | reg interrupt_mapping_32_acc_vio; |
| 1522 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1523 | interrupt_mapping_32_addr_decoded or |
| 1524 | daemon_transaction_in_progress) |
| 1525 | begin |
| 1526 | if (daemon_transaction_in_progress | ~interrupt_mapping_32_addr_decoded) |
| 1527 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1528 | else |
| 1529 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1530 | // reads |
| 1531 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1532 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1533 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1534 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1535 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1536 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1537 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1538 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1539 | // writes |
| 1540 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1541 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1542 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1543 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1544 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1545 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1546 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1547 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1548 | |
| 1549 | default: |
| 1550 | begin |
| 1551 | interrupt_mapping_32_acc_vio = 1'b0; |
| 1552 | begin // axis tbcall_region |
| 1553 | // vlint flag_system_call off |
| 1554 | // synopsys translate_off |
| 1555 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_32"); `endif |
| 1556 | // synopsys translate_on |
| 1557 | // vlint flag_system_call on |
| 1558 | end // end of tbcall_region |
| 1559 | end |
| 1560 | endcase |
| 1561 | end |
| 1562 | //----- reg_acc_vio: interrupt_mapping_33 |
| 1563 | reg interrupt_mapping_33_acc_vio; |
| 1564 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1565 | interrupt_mapping_33_addr_decoded or |
| 1566 | daemon_transaction_in_progress) |
| 1567 | begin |
| 1568 | if (daemon_transaction_in_progress | ~interrupt_mapping_33_addr_decoded) |
| 1569 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1570 | else |
| 1571 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1572 | // reads |
| 1573 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1574 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1575 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1576 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1577 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1578 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1579 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1580 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1581 | // writes |
| 1582 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1583 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1584 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1585 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1586 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1587 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1588 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1589 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1590 | |
| 1591 | default: |
| 1592 | begin |
| 1593 | interrupt_mapping_33_acc_vio = 1'b0; |
| 1594 | begin // axis tbcall_region |
| 1595 | // vlint flag_system_call off |
| 1596 | // synopsys translate_off |
| 1597 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_33"); `endif |
| 1598 | // synopsys translate_on |
| 1599 | // vlint flag_system_call on |
| 1600 | end // end of tbcall_region |
| 1601 | end |
| 1602 | endcase |
| 1603 | end |
| 1604 | //----- reg_acc_vio: interrupt_mapping_34 |
| 1605 | reg interrupt_mapping_34_acc_vio; |
| 1606 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1607 | interrupt_mapping_34_addr_decoded or |
| 1608 | daemon_transaction_in_progress) |
| 1609 | begin |
| 1610 | if (daemon_transaction_in_progress | ~interrupt_mapping_34_addr_decoded) |
| 1611 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1612 | else |
| 1613 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1614 | // reads |
| 1615 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1616 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1617 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1618 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1619 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1620 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1621 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1622 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1623 | // writes |
| 1624 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1625 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1626 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1627 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1628 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1629 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1630 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1631 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1632 | |
| 1633 | default: |
| 1634 | begin |
| 1635 | interrupt_mapping_34_acc_vio = 1'b0; |
| 1636 | begin // axis tbcall_region |
| 1637 | // vlint flag_system_call off |
| 1638 | // synopsys translate_off |
| 1639 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_34"); `endif |
| 1640 | // synopsys translate_on |
| 1641 | // vlint flag_system_call on |
| 1642 | end // end of tbcall_region |
| 1643 | end |
| 1644 | endcase |
| 1645 | end |
| 1646 | //----- reg_acc_vio: interrupt_mapping_35 |
| 1647 | reg interrupt_mapping_35_acc_vio; |
| 1648 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1649 | interrupt_mapping_35_addr_decoded or |
| 1650 | daemon_transaction_in_progress) |
| 1651 | begin |
| 1652 | if (daemon_transaction_in_progress | ~interrupt_mapping_35_addr_decoded) |
| 1653 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1654 | else |
| 1655 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1656 | // reads |
| 1657 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1658 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1659 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1660 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1661 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1662 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1663 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1664 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1665 | // writes |
| 1666 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1667 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1668 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1669 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1670 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1671 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1672 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1673 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1674 | |
| 1675 | default: |
| 1676 | begin |
| 1677 | interrupt_mapping_35_acc_vio = 1'b0; |
| 1678 | begin // axis tbcall_region |
| 1679 | // vlint flag_system_call off |
| 1680 | // synopsys translate_off |
| 1681 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_35"); `endif |
| 1682 | // synopsys translate_on |
| 1683 | // vlint flag_system_call on |
| 1684 | end // end of tbcall_region |
| 1685 | end |
| 1686 | endcase |
| 1687 | end |
| 1688 | //----- reg_acc_vio: interrupt_mapping_36 |
| 1689 | reg interrupt_mapping_36_acc_vio; |
| 1690 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1691 | interrupt_mapping_36_addr_decoded or |
| 1692 | daemon_transaction_in_progress) |
| 1693 | begin |
| 1694 | if (daemon_transaction_in_progress | ~interrupt_mapping_36_addr_decoded) |
| 1695 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1696 | else |
| 1697 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1698 | // reads |
| 1699 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1700 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1701 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1702 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1703 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1704 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1705 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1706 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1707 | // writes |
| 1708 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1709 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1710 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1711 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1712 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1713 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1714 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1715 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1716 | |
| 1717 | default: |
| 1718 | begin |
| 1719 | interrupt_mapping_36_acc_vio = 1'b0; |
| 1720 | begin // axis tbcall_region |
| 1721 | // vlint flag_system_call off |
| 1722 | // synopsys translate_off |
| 1723 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_36"); `endif |
| 1724 | // synopsys translate_on |
| 1725 | // vlint flag_system_call on |
| 1726 | end // end of tbcall_region |
| 1727 | end |
| 1728 | endcase |
| 1729 | end |
| 1730 | //----- reg_acc_vio: interrupt_mapping_37 |
| 1731 | reg interrupt_mapping_37_acc_vio; |
| 1732 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1733 | interrupt_mapping_37_addr_decoded or |
| 1734 | daemon_transaction_in_progress) |
| 1735 | begin |
| 1736 | if (daemon_transaction_in_progress | ~interrupt_mapping_37_addr_decoded) |
| 1737 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1738 | else |
| 1739 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1740 | // reads |
| 1741 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1742 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1743 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1744 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1745 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1746 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1747 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1748 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1749 | // writes |
| 1750 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1751 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1752 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1753 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1754 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1755 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1756 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1757 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1758 | |
| 1759 | default: |
| 1760 | begin |
| 1761 | interrupt_mapping_37_acc_vio = 1'b0; |
| 1762 | begin // axis tbcall_region |
| 1763 | // vlint flag_system_call off |
| 1764 | // synopsys translate_off |
| 1765 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_37"); `endif |
| 1766 | // synopsys translate_on |
| 1767 | // vlint flag_system_call on |
| 1768 | end // end of tbcall_region |
| 1769 | end |
| 1770 | endcase |
| 1771 | end |
| 1772 | //----- reg_acc_vio: interrupt_mapping_38 |
| 1773 | reg interrupt_mapping_38_acc_vio; |
| 1774 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1775 | interrupt_mapping_38_addr_decoded or |
| 1776 | daemon_transaction_in_progress) |
| 1777 | begin |
| 1778 | if (daemon_transaction_in_progress | ~interrupt_mapping_38_addr_decoded) |
| 1779 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1780 | else |
| 1781 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1782 | // reads |
| 1783 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1784 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1785 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1786 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1787 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1788 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1789 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1790 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1791 | // writes |
| 1792 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1793 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1794 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1795 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1796 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1797 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1798 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1799 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1800 | |
| 1801 | default: |
| 1802 | begin |
| 1803 | interrupt_mapping_38_acc_vio = 1'b0; |
| 1804 | begin // axis tbcall_region |
| 1805 | // vlint flag_system_call off |
| 1806 | // synopsys translate_off |
| 1807 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_38"); `endif |
| 1808 | // synopsys translate_on |
| 1809 | // vlint flag_system_call on |
| 1810 | end // end of tbcall_region |
| 1811 | end |
| 1812 | endcase |
| 1813 | end |
| 1814 | //----- reg_acc_vio: interrupt_mapping_39 |
| 1815 | reg interrupt_mapping_39_acc_vio; |
| 1816 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1817 | interrupt_mapping_39_addr_decoded or |
| 1818 | daemon_transaction_in_progress) |
| 1819 | begin |
| 1820 | if (daemon_transaction_in_progress | ~interrupt_mapping_39_addr_decoded) |
| 1821 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1822 | else |
| 1823 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1824 | // reads |
| 1825 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1826 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1827 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1828 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1829 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1830 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1831 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1832 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1833 | // writes |
| 1834 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1835 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1836 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1837 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1838 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1839 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1840 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1841 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1842 | |
| 1843 | default: |
| 1844 | begin |
| 1845 | interrupt_mapping_39_acc_vio = 1'b0; |
| 1846 | begin // axis tbcall_region |
| 1847 | // vlint flag_system_call off |
| 1848 | // synopsys translate_off |
| 1849 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_39"); `endif |
| 1850 | // synopsys translate_on |
| 1851 | // vlint flag_system_call on |
| 1852 | end // end of tbcall_region |
| 1853 | end |
| 1854 | endcase |
| 1855 | end |
| 1856 | //----- reg_acc_vio: interrupt_mapping_40 |
| 1857 | reg interrupt_mapping_40_acc_vio; |
| 1858 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1859 | interrupt_mapping_40_addr_decoded or |
| 1860 | daemon_transaction_in_progress) |
| 1861 | begin |
| 1862 | if (daemon_transaction_in_progress | ~interrupt_mapping_40_addr_decoded) |
| 1863 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1864 | else |
| 1865 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1866 | // reads |
| 1867 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1868 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1869 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1870 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1871 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1872 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1873 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1874 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1875 | // writes |
| 1876 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1877 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1878 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1879 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1880 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1881 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1882 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1883 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1884 | |
| 1885 | default: |
| 1886 | begin |
| 1887 | interrupt_mapping_40_acc_vio = 1'b0; |
| 1888 | begin // axis tbcall_region |
| 1889 | // vlint flag_system_call off |
| 1890 | // synopsys translate_off |
| 1891 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_40"); `endif |
| 1892 | // synopsys translate_on |
| 1893 | // vlint flag_system_call on |
| 1894 | end // end of tbcall_region |
| 1895 | end |
| 1896 | endcase |
| 1897 | end |
| 1898 | //----- reg_acc_vio: interrupt_mapping_41 |
| 1899 | reg interrupt_mapping_41_acc_vio; |
| 1900 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1901 | interrupt_mapping_41_addr_decoded or |
| 1902 | daemon_transaction_in_progress) |
| 1903 | begin |
| 1904 | if (daemon_transaction_in_progress | ~interrupt_mapping_41_addr_decoded) |
| 1905 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1906 | else |
| 1907 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1908 | // reads |
| 1909 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1910 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1911 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1912 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1913 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1914 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1915 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1916 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1917 | // writes |
| 1918 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1919 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1920 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1921 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1922 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1923 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1924 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1925 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1926 | |
| 1927 | default: |
| 1928 | begin |
| 1929 | interrupt_mapping_41_acc_vio = 1'b0; |
| 1930 | begin // axis tbcall_region |
| 1931 | // vlint flag_system_call off |
| 1932 | // synopsys translate_off |
| 1933 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_41"); `endif |
| 1934 | // synopsys translate_on |
| 1935 | // vlint flag_system_call on |
| 1936 | end // end of tbcall_region |
| 1937 | end |
| 1938 | endcase |
| 1939 | end |
| 1940 | //----- reg_acc_vio: interrupt_mapping_42 |
| 1941 | reg interrupt_mapping_42_acc_vio; |
| 1942 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1943 | interrupt_mapping_42_addr_decoded or |
| 1944 | daemon_transaction_in_progress) |
| 1945 | begin |
| 1946 | if (daemon_transaction_in_progress | ~interrupt_mapping_42_addr_decoded) |
| 1947 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1948 | else |
| 1949 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1950 | // reads |
| 1951 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1952 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1953 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1954 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1955 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1956 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1957 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 1958 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1959 | // writes |
| 1960 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 1961 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1962 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 1963 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1964 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 1965 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1966 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 1967 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1968 | |
| 1969 | default: |
| 1970 | begin |
| 1971 | interrupt_mapping_42_acc_vio = 1'b0; |
| 1972 | begin // axis tbcall_region |
| 1973 | // vlint flag_system_call off |
| 1974 | // synopsys translate_off |
| 1975 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_42"); `endif |
| 1976 | // synopsys translate_on |
| 1977 | // vlint flag_system_call on |
| 1978 | end // end of tbcall_region |
| 1979 | end |
| 1980 | endcase |
| 1981 | end |
| 1982 | //----- reg_acc_vio: interrupt_mapping_43 |
| 1983 | reg interrupt_mapping_43_acc_vio; |
| 1984 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 1985 | interrupt_mapping_43_addr_decoded or |
| 1986 | daemon_transaction_in_progress) |
| 1987 | begin |
| 1988 | if (daemon_transaction_in_progress | ~interrupt_mapping_43_addr_decoded) |
| 1989 | interrupt_mapping_43_acc_vio = 1'b0; |
| 1990 | else |
| 1991 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 1992 | // reads |
| 1993 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 1994 | interrupt_mapping_43_acc_vio = 1'b0; |
| 1995 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 1996 | interrupt_mapping_43_acc_vio = 1'b0; |
| 1997 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 1998 | interrupt_mapping_43_acc_vio = 1'b0; |
| 1999 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2000 | interrupt_mapping_43_acc_vio = 1'b0; |
| 2001 | // writes |
| 2002 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2003 | interrupt_mapping_43_acc_vio = 1'b0; |
| 2004 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2005 | interrupt_mapping_43_acc_vio = 1'b0; |
| 2006 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2007 | interrupt_mapping_43_acc_vio = 1'b0; |
| 2008 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2009 | interrupt_mapping_43_acc_vio = 1'b0; |
| 2010 | |
| 2011 | default: |
| 2012 | begin |
| 2013 | interrupt_mapping_43_acc_vio = 1'b0; |
| 2014 | begin // axis tbcall_region |
| 2015 | // vlint flag_system_call off |
| 2016 | // synopsys translate_off |
| 2017 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_43"); `endif |
| 2018 | // synopsys translate_on |
| 2019 | // vlint flag_system_call on |
| 2020 | end // end of tbcall_region |
| 2021 | end |
| 2022 | endcase |
| 2023 | end |
| 2024 | //----- reg_acc_vio: interrupt_mapping_44 |
| 2025 | reg interrupt_mapping_44_acc_vio; |
| 2026 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2027 | interrupt_mapping_44_addr_decoded or |
| 2028 | daemon_transaction_in_progress) |
| 2029 | begin |
| 2030 | if (daemon_transaction_in_progress | ~interrupt_mapping_44_addr_decoded) |
| 2031 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2032 | else |
| 2033 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2034 | // reads |
| 2035 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2036 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2037 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2038 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2039 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2040 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2041 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2042 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2043 | // writes |
| 2044 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2045 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2046 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2047 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2048 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2049 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2050 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2051 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2052 | |
| 2053 | default: |
| 2054 | begin |
| 2055 | interrupt_mapping_44_acc_vio = 1'b0; |
| 2056 | begin // axis tbcall_region |
| 2057 | // vlint flag_system_call off |
| 2058 | // synopsys translate_off |
| 2059 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_44"); `endif |
| 2060 | // synopsys translate_on |
| 2061 | // vlint flag_system_call on |
| 2062 | end // end of tbcall_region |
| 2063 | end |
| 2064 | endcase |
| 2065 | end |
| 2066 | //----- reg_acc_vio: interrupt_mapping_45 |
| 2067 | reg interrupt_mapping_45_acc_vio; |
| 2068 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2069 | interrupt_mapping_45_addr_decoded or |
| 2070 | daemon_transaction_in_progress) |
| 2071 | begin |
| 2072 | if (daemon_transaction_in_progress | ~interrupt_mapping_45_addr_decoded) |
| 2073 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2074 | else |
| 2075 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2076 | // reads |
| 2077 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2078 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2079 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2080 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2081 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2082 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2083 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2084 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2085 | // writes |
| 2086 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2087 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2088 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2089 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2090 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2091 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2092 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2093 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2094 | |
| 2095 | default: |
| 2096 | begin |
| 2097 | interrupt_mapping_45_acc_vio = 1'b0; |
| 2098 | begin // axis tbcall_region |
| 2099 | // vlint flag_system_call off |
| 2100 | // synopsys translate_off |
| 2101 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_45"); `endif |
| 2102 | // synopsys translate_on |
| 2103 | // vlint flag_system_call on |
| 2104 | end // end of tbcall_region |
| 2105 | end |
| 2106 | endcase |
| 2107 | end |
| 2108 | //----- reg_acc_vio: interrupt_mapping_46 |
| 2109 | reg interrupt_mapping_46_acc_vio; |
| 2110 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2111 | interrupt_mapping_46_addr_decoded or |
| 2112 | daemon_transaction_in_progress) |
| 2113 | begin |
| 2114 | if (daemon_transaction_in_progress | ~interrupt_mapping_46_addr_decoded) |
| 2115 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2116 | else |
| 2117 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2118 | // reads |
| 2119 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2120 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2121 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2122 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2123 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2124 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2125 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2126 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2127 | // writes |
| 2128 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2129 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2130 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2131 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2132 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2133 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2134 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2135 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2136 | |
| 2137 | default: |
| 2138 | begin |
| 2139 | interrupt_mapping_46_acc_vio = 1'b0; |
| 2140 | begin // axis tbcall_region |
| 2141 | // vlint flag_system_call off |
| 2142 | // synopsys translate_off |
| 2143 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_46"); `endif |
| 2144 | // synopsys translate_on |
| 2145 | // vlint flag_system_call on |
| 2146 | end // end of tbcall_region |
| 2147 | end |
| 2148 | endcase |
| 2149 | end |
| 2150 | //----- reg_acc_vio: interrupt_mapping_47 |
| 2151 | reg interrupt_mapping_47_acc_vio; |
| 2152 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2153 | interrupt_mapping_47_addr_decoded or |
| 2154 | daemon_transaction_in_progress) |
| 2155 | begin |
| 2156 | if (daemon_transaction_in_progress | ~interrupt_mapping_47_addr_decoded) |
| 2157 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2158 | else |
| 2159 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2160 | // reads |
| 2161 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2162 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2163 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2164 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2165 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2166 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2167 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2168 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2169 | // writes |
| 2170 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2171 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2172 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2173 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2174 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2175 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2176 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2177 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2178 | |
| 2179 | default: |
| 2180 | begin |
| 2181 | interrupt_mapping_47_acc_vio = 1'b0; |
| 2182 | begin // axis tbcall_region |
| 2183 | // vlint flag_system_call off |
| 2184 | // synopsys translate_off |
| 2185 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_47"); `endif |
| 2186 | // synopsys translate_on |
| 2187 | // vlint flag_system_call on |
| 2188 | end // end of tbcall_region |
| 2189 | end |
| 2190 | endcase |
| 2191 | end |
| 2192 | //----- reg_acc_vio: interrupt_mapping_48 |
| 2193 | reg interrupt_mapping_48_acc_vio; |
| 2194 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2195 | interrupt_mapping_48_addr_decoded or |
| 2196 | daemon_transaction_in_progress) |
| 2197 | begin |
| 2198 | if (daemon_transaction_in_progress | ~interrupt_mapping_48_addr_decoded) |
| 2199 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2200 | else |
| 2201 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2202 | // reads |
| 2203 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2204 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2205 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2206 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2207 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2208 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2209 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2210 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2211 | // writes |
| 2212 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2213 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2214 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2215 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2216 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2217 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2218 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2219 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2220 | |
| 2221 | default: |
| 2222 | begin |
| 2223 | interrupt_mapping_48_acc_vio = 1'b0; |
| 2224 | begin // axis tbcall_region |
| 2225 | // vlint flag_system_call off |
| 2226 | // synopsys translate_off |
| 2227 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_48"); `endif |
| 2228 | // synopsys translate_on |
| 2229 | // vlint flag_system_call on |
| 2230 | end // end of tbcall_region |
| 2231 | end |
| 2232 | endcase |
| 2233 | end |
| 2234 | //----- reg_acc_vio: interrupt_mapping_49 |
| 2235 | reg interrupt_mapping_49_acc_vio; |
| 2236 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2237 | interrupt_mapping_49_addr_decoded or |
| 2238 | daemon_transaction_in_progress) |
| 2239 | begin |
| 2240 | if (daemon_transaction_in_progress | ~interrupt_mapping_49_addr_decoded) |
| 2241 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2242 | else |
| 2243 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2244 | // reads |
| 2245 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2246 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2247 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2248 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2249 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2250 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2251 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2252 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2253 | // writes |
| 2254 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2255 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2256 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2257 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2258 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2259 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2260 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2261 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2262 | |
| 2263 | default: |
| 2264 | begin |
| 2265 | interrupt_mapping_49_acc_vio = 1'b0; |
| 2266 | begin // axis tbcall_region |
| 2267 | // vlint flag_system_call off |
| 2268 | // synopsys translate_off |
| 2269 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_49"); `endif |
| 2270 | // synopsys translate_on |
| 2271 | // vlint flag_system_call on |
| 2272 | end // end of tbcall_region |
| 2273 | end |
| 2274 | endcase |
| 2275 | end |
| 2276 | //----- reg_acc_vio: interrupt_mapping_50 |
| 2277 | reg interrupt_mapping_50_acc_vio; |
| 2278 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2279 | interrupt_mapping_50_addr_decoded or |
| 2280 | daemon_transaction_in_progress) |
| 2281 | begin |
| 2282 | if (daemon_transaction_in_progress | ~interrupt_mapping_50_addr_decoded) |
| 2283 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2284 | else |
| 2285 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2286 | // reads |
| 2287 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2288 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2289 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2290 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2291 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2292 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2293 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2294 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2295 | // writes |
| 2296 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2297 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2298 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2299 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2300 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2301 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2302 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2303 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2304 | |
| 2305 | default: |
| 2306 | begin |
| 2307 | interrupt_mapping_50_acc_vio = 1'b0; |
| 2308 | begin // axis tbcall_region |
| 2309 | // vlint flag_system_call off |
| 2310 | // synopsys translate_off |
| 2311 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_50"); `endif |
| 2312 | // synopsys translate_on |
| 2313 | // vlint flag_system_call on |
| 2314 | end // end of tbcall_region |
| 2315 | end |
| 2316 | endcase |
| 2317 | end |
| 2318 | //----- reg_acc_vio: interrupt_mapping_51 |
| 2319 | reg interrupt_mapping_51_acc_vio; |
| 2320 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2321 | interrupt_mapping_51_addr_decoded or |
| 2322 | daemon_transaction_in_progress) |
| 2323 | begin |
| 2324 | if (daemon_transaction_in_progress | ~interrupt_mapping_51_addr_decoded) |
| 2325 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2326 | else |
| 2327 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2328 | // reads |
| 2329 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2330 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2331 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2332 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2333 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2334 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2335 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2336 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2337 | // writes |
| 2338 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2339 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2340 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2341 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2342 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2343 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2344 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2345 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2346 | |
| 2347 | default: |
| 2348 | begin |
| 2349 | interrupt_mapping_51_acc_vio = 1'b0; |
| 2350 | begin // axis tbcall_region |
| 2351 | // vlint flag_system_call off |
| 2352 | // synopsys translate_off |
| 2353 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_51"); `endif |
| 2354 | // synopsys translate_on |
| 2355 | // vlint flag_system_call on |
| 2356 | end // end of tbcall_region |
| 2357 | end |
| 2358 | endcase |
| 2359 | end |
| 2360 | //----- reg_acc_vio: interrupt_mapping_52 |
| 2361 | reg interrupt_mapping_52_acc_vio; |
| 2362 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2363 | interrupt_mapping_52_addr_decoded or |
| 2364 | daemon_transaction_in_progress) |
| 2365 | begin |
| 2366 | if (daemon_transaction_in_progress | ~interrupt_mapping_52_addr_decoded) |
| 2367 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2368 | else |
| 2369 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2370 | // reads |
| 2371 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2372 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2373 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2374 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2375 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2376 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2377 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2378 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2379 | // writes |
| 2380 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2381 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2382 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2383 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2384 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2385 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2386 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2387 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2388 | |
| 2389 | default: |
| 2390 | begin |
| 2391 | interrupt_mapping_52_acc_vio = 1'b0; |
| 2392 | begin // axis tbcall_region |
| 2393 | // vlint flag_system_call off |
| 2394 | // synopsys translate_off |
| 2395 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_52"); `endif |
| 2396 | // synopsys translate_on |
| 2397 | // vlint flag_system_call on |
| 2398 | end // end of tbcall_region |
| 2399 | end |
| 2400 | endcase |
| 2401 | end |
| 2402 | //----- reg_acc_vio: interrupt_mapping_53 |
| 2403 | reg interrupt_mapping_53_acc_vio; |
| 2404 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2405 | interrupt_mapping_53_addr_decoded or |
| 2406 | daemon_transaction_in_progress) |
| 2407 | begin |
| 2408 | if (daemon_transaction_in_progress | ~interrupt_mapping_53_addr_decoded) |
| 2409 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2410 | else |
| 2411 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2412 | // reads |
| 2413 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2414 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2415 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2416 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2417 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2418 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2419 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2420 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2421 | // writes |
| 2422 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2423 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2424 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2425 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2426 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2427 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2428 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2429 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2430 | |
| 2431 | default: |
| 2432 | begin |
| 2433 | interrupt_mapping_53_acc_vio = 1'b0; |
| 2434 | begin // axis tbcall_region |
| 2435 | // vlint flag_system_call off |
| 2436 | // synopsys translate_off |
| 2437 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_53"); `endif |
| 2438 | // synopsys translate_on |
| 2439 | // vlint flag_system_call on |
| 2440 | end // end of tbcall_region |
| 2441 | end |
| 2442 | endcase |
| 2443 | end |
| 2444 | //----- reg_acc_vio: interrupt_mapping_54 |
| 2445 | reg interrupt_mapping_54_acc_vio; |
| 2446 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2447 | interrupt_mapping_54_addr_decoded or |
| 2448 | daemon_transaction_in_progress) |
| 2449 | begin |
| 2450 | if (daemon_transaction_in_progress | ~interrupt_mapping_54_addr_decoded) |
| 2451 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2452 | else |
| 2453 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2454 | // reads |
| 2455 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2456 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2457 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2458 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2459 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2460 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2461 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2462 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2463 | // writes |
| 2464 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2465 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2466 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2467 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2468 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2469 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2470 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2471 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2472 | |
| 2473 | default: |
| 2474 | begin |
| 2475 | interrupt_mapping_54_acc_vio = 1'b0; |
| 2476 | begin // axis tbcall_region |
| 2477 | // vlint flag_system_call off |
| 2478 | // synopsys translate_off |
| 2479 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_54"); `endif |
| 2480 | // synopsys translate_on |
| 2481 | // vlint flag_system_call on |
| 2482 | end // end of tbcall_region |
| 2483 | end |
| 2484 | endcase |
| 2485 | end |
| 2486 | //----- reg_acc_vio: interrupt_mapping_55 |
| 2487 | reg interrupt_mapping_55_acc_vio; |
| 2488 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2489 | interrupt_mapping_55_addr_decoded or |
| 2490 | daemon_transaction_in_progress) |
| 2491 | begin |
| 2492 | if (daemon_transaction_in_progress | ~interrupt_mapping_55_addr_decoded) |
| 2493 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2494 | else |
| 2495 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2496 | // reads |
| 2497 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2498 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2499 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2500 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2501 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2502 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2503 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2504 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2505 | // writes |
| 2506 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2507 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2508 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2509 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2510 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2511 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2512 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2513 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2514 | |
| 2515 | default: |
| 2516 | begin |
| 2517 | interrupt_mapping_55_acc_vio = 1'b0; |
| 2518 | begin // axis tbcall_region |
| 2519 | // vlint flag_system_call off |
| 2520 | // synopsys translate_off |
| 2521 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_55"); `endif |
| 2522 | // synopsys translate_on |
| 2523 | // vlint flag_system_call on |
| 2524 | end // end of tbcall_region |
| 2525 | end |
| 2526 | endcase |
| 2527 | end |
| 2528 | //----- reg_acc_vio: interrupt_mapping_56 |
| 2529 | reg interrupt_mapping_56_acc_vio; |
| 2530 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2531 | interrupt_mapping_56_addr_decoded or |
| 2532 | daemon_transaction_in_progress) |
| 2533 | begin |
| 2534 | if (daemon_transaction_in_progress | ~interrupt_mapping_56_addr_decoded) |
| 2535 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2536 | else |
| 2537 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2538 | // reads |
| 2539 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2540 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2541 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2542 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2543 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2544 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2545 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2546 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2547 | // writes |
| 2548 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2549 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2550 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2551 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2552 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2553 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2554 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2555 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2556 | |
| 2557 | default: |
| 2558 | begin |
| 2559 | interrupt_mapping_56_acc_vio = 1'b0; |
| 2560 | begin // axis tbcall_region |
| 2561 | // vlint flag_system_call off |
| 2562 | // synopsys translate_off |
| 2563 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_56"); `endif |
| 2564 | // synopsys translate_on |
| 2565 | // vlint flag_system_call on |
| 2566 | end // end of tbcall_region |
| 2567 | end |
| 2568 | endcase |
| 2569 | end |
| 2570 | //----- reg_acc_vio: interrupt_mapping_57 |
| 2571 | reg interrupt_mapping_57_acc_vio; |
| 2572 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2573 | interrupt_mapping_57_addr_decoded or |
| 2574 | daemon_transaction_in_progress) |
| 2575 | begin |
| 2576 | if (daemon_transaction_in_progress | ~interrupt_mapping_57_addr_decoded) |
| 2577 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2578 | else |
| 2579 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2580 | // reads |
| 2581 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2582 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2583 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2584 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2585 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2586 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2587 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2588 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2589 | // writes |
| 2590 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2591 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2592 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2593 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2594 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2595 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2596 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2597 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2598 | |
| 2599 | default: |
| 2600 | begin |
| 2601 | interrupt_mapping_57_acc_vio = 1'b0; |
| 2602 | begin // axis tbcall_region |
| 2603 | // vlint flag_system_call off |
| 2604 | // synopsys translate_off |
| 2605 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_57"); `endif |
| 2606 | // synopsys translate_on |
| 2607 | // vlint flag_system_call on |
| 2608 | end // end of tbcall_region |
| 2609 | end |
| 2610 | endcase |
| 2611 | end |
| 2612 | //----- reg_acc_vio: interrupt_mapping_58 |
| 2613 | reg interrupt_mapping_58_acc_vio; |
| 2614 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2615 | interrupt_mapping_58_addr_decoded or |
| 2616 | daemon_transaction_in_progress) |
| 2617 | begin |
| 2618 | if (daemon_transaction_in_progress | ~interrupt_mapping_58_addr_decoded) |
| 2619 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2620 | else |
| 2621 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2622 | // reads |
| 2623 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2624 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2625 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2626 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2627 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2628 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2629 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2630 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2631 | // writes |
| 2632 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2633 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2634 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2635 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2636 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2637 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2638 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2639 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2640 | |
| 2641 | default: |
| 2642 | begin |
| 2643 | interrupt_mapping_58_acc_vio = 1'b0; |
| 2644 | begin // axis tbcall_region |
| 2645 | // vlint flag_system_call off |
| 2646 | // synopsys translate_off |
| 2647 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_58"); `endif |
| 2648 | // synopsys translate_on |
| 2649 | // vlint flag_system_call on |
| 2650 | end // end of tbcall_region |
| 2651 | end |
| 2652 | endcase |
| 2653 | end |
| 2654 | //----- reg_acc_vio: interrupt_mapping_59 |
| 2655 | reg interrupt_mapping_59_acc_vio; |
| 2656 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2657 | interrupt_mapping_59_addr_decoded or |
| 2658 | daemon_transaction_in_progress) |
| 2659 | begin |
| 2660 | if (daemon_transaction_in_progress | ~interrupt_mapping_59_addr_decoded) |
| 2661 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2662 | else |
| 2663 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2664 | // reads |
| 2665 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2666 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2667 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2668 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2669 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2670 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2671 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2672 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2673 | // writes |
| 2674 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2675 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2676 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2677 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2678 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2679 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2680 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2681 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2682 | |
| 2683 | default: |
| 2684 | begin |
| 2685 | interrupt_mapping_59_acc_vio = 1'b0; |
| 2686 | begin // axis tbcall_region |
| 2687 | // vlint flag_system_call off |
| 2688 | // synopsys translate_off |
| 2689 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_59"); `endif |
| 2690 | // synopsys translate_on |
| 2691 | // vlint flag_system_call on |
| 2692 | end // end of tbcall_region |
| 2693 | end |
| 2694 | endcase |
| 2695 | end |
| 2696 | //----- reg_acc_vio: interrupt_mapping_62 |
| 2697 | reg interrupt_mapping_62_acc_vio; |
| 2698 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2699 | interrupt_mapping_62_addr_decoded or |
| 2700 | daemon_transaction_in_progress) |
| 2701 | begin |
| 2702 | if (daemon_transaction_in_progress | ~interrupt_mapping_62_addr_decoded) |
| 2703 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2704 | else |
| 2705 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2706 | // reads |
| 2707 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2708 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2709 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2710 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2711 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2712 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2713 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2714 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2715 | // writes |
| 2716 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2717 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2718 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2719 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2720 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2721 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2722 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2723 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2724 | |
| 2725 | default: |
| 2726 | begin |
| 2727 | interrupt_mapping_62_acc_vio = 1'b0; |
| 2728 | begin // axis tbcall_region |
| 2729 | // vlint flag_system_call off |
| 2730 | // synopsys translate_off |
| 2731 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_62"); `endif |
| 2732 | // synopsys translate_on |
| 2733 | // vlint flag_system_call on |
| 2734 | end // end of tbcall_region |
| 2735 | end |
| 2736 | endcase |
| 2737 | end |
| 2738 | //----- reg_acc_vio: interrupt_mapping_63 |
| 2739 | reg interrupt_mapping_63_acc_vio; |
| 2740 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2741 | interrupt_mapping_63_addr_decoded or |
| 2742 | daemon_transaction_in_progress) |
| 2743 | begin |
| 2744 | if (daemon_transaction_in_progress | ~interrupt_mapping_63_addr_decoded) |
| 2745 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2746 | else |
| 2747 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2748 | // reads |
| 2749 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2750 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2751 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2752 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2753 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2754 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2755 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2756 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2757 | // writes |
| 2758 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2759 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2760 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2761 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2762 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2763 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2764 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2765 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2766 | |
| 2767 | default: |
| 2768 | begin |
| 2769 | interrupt_mapping_63_acc_vio = 1'b0; |
| 2770 | begin // axis tbcall_region |
| 2771 | // vlint flag_system_call off |
| 2772 | // synopsys translate_off |
| 2773 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_mapping_63"); `endif |
| 2774 | // synopsys translate_on |
| 2775 | // vlint flag_system_call on |
| 2776 | end // end of tbcall_region |
| 2777 | end |
| 2778 | endcase |
| 2779 | end |
| 2780 | //----- reg_acc_vio: clr_int_reg_20 |
| 2781 | reg clr_int_reg_20_acc_vio; |
| 2782 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2783 | clr_int_reg_20_addr_decoded or |
| 2784 | daemon_transaction_in_progress) |
| 2785 | begin |
| 2786 | if (daemon_transaction_in_progress | ~clr_int_reg_20_addr_decoded) |
| 2787 | clr_int_reg_20_acc_vio = 1'b0; |
| 2788 | else |
| 2789 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2790 | // reads |
| 2791 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2792 | clr_int_reg_20_acc_vio = 1'b0; |
| 2793 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2794 | clr_int_reg_20_acc_vio = 1'b0; |
| 2795 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2796 | clr_int_reg_20_acc_vio = 1'b0; |
| 2797 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2798 | clr_int_reg_20_acc_vio = 1'b0; |
| 2799 | // writes |
| 2800 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2801 | clr_int_reg_20_acc_vio = 1'b0; |
| 2802 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2803 | clr_int_reg_20_acc_vio = 1'b0; |
| 2804 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2805 | clr_int_reg_20_acc_vio = 1'b0; |
| 2806 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2807 | clr_int_reg_20_acc_vio = 1'b0; |
| 2808 | |
| 2809 | default: |
| 2810 | begin |
| 2811 | clr_int_reg_20_acc_vio = 1'b0; |
| 2812 | begin // axis tbcall_region |
| 2813 | // vlint flag_system_call off |
| 2814 | // synopsys translate_off |
| 2815 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_20"); `endif |
| 2816 | // synopsys translate_on |
| 2817 | // vlint flag_system_call on |
| 2818 | end // end of tbcall_region |
| 2819 | end |
| 2820 | endcase |
| 2821 | end |
| 2822 | //----- reg_acc_vio: clr_int_reg_21 |
| 2823 | reg clr_int_reg_21_acc_vio; |
| 2824 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2825 | clr_int_reg_21_addr_decoded or |
| 2826 | daemon_transaction_in_progress) |
| 2827 | begin |
| 2828 | if (daemon_transaction_in_progress | ~clr_int_reg_21_addr_decoded) |
| 2829 | clr_int_reg_21_acc_vio = 1'b0; |
| 2830 | else |
| 2831 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2832 | // reads |
| 2833 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2834 | clr_int_reg_21_acc_vio = 1'b0; |
| 2835 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2836 | clr_int_reg_21_acc_vio = 1'b0; |
| 2837 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2838 | clr_int_reg_21_acc_vio = 1'b0; |
| 2839 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2840 | clr_int_reg_21_acc_vio = 1'b0; |
| 2841 | // writes |
| 2842 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2843 | clr_int_reg_21_acc_vio = 1'b0; |
| 2844 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2845 | clr_int_reg_21_acc_vio = 1'b0; |
| 2846 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2847 | clr_int_reg_21_acc_vio = 1'b0; |
| 2848 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2849 | clr_int_reg_21_acc_vio = 1'b0; |
| 2850 | |
| 2851 | default: |
| 2852 | begin |
| 2853 | clr_int_reg_21_acc_vio = 1'b0; |
| 2854 | begin // axis tbcall_region |
| 2855 | // vlint flag_system_call off |
| 2856 | // synopsys translate_off |
| 2857 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_21"); `endif |
| 2858 | // synopsys translate_on |
| 2859 | // vlint flag_system_call on |
| 2860 | end // end of tbcall_region |
| 2861 | end |
| 2862 | endcase |
| 2863 | end |
| 2864 | //----- reg_acc_vio: clr_int_reg_22 |
| 2865 | reg clr_int_reg_22_acc_vio; |
| 2866 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2867 | clr_int_reg_22_addr_decoded or |
| 2868 | daemon_transaction_in_progress) |
| 2869 | begin |
| 2870 | if (daemon_transaction_in_progress | ~clr_int_reg_22_addr_decoded) |
| 2871 | clr_int_reg_22_acc_vio = 1'b0; |
| 2872 | else |
| 2873 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2874 | // reads |
| 2875 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2876 | clr_int_reg_22_acc_vio = 1'b0; |
| 2877 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2878 | clr_int_reg_22_acc_vio = 1'b0; |
| 2879 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2880 | clr_int_reg_22_acc_vio = 1'b0; |
| 2881 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2882 | clr_int_reg_22_acc_vio = 1'b0; |
| 2883 | // writes |
| 2884 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2885 | clr_int_reg_22_acc_vio = 1'b0; |
| 2886 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2887 | clr_int_reg_22_acc_vio = 1'b0; |
| 2888 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2889 | clr_int_reg_22_acc_vio = 1'b0; |
| 2890 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2891 | clr_int_reg_22_acc_vio = 1'b0; |
| 2892 | |
| 2893 | default: |
| 2894 | begin |
| 2895 | clr_int_reg_22_acc_vio = 1'b0; |
| 2896 | begin // axis tbcall_region |
| 2897 | // vlint flag_system_call off |
| 2898 | // synopsys translate_off |
| 2899 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_22"); `endif |
| 2900 | // synopsys translate_on |
| 2901 | // vlint flag_system_call on |
| 2902 | end // end of tbcall_region |
| 2903 | end |
| 2904 | endcase |
| 2905 | end |
| 2906 | //----- reg_acc_vio: clr_int_reg_23 |
| 2907 | reg clr_int_reg_23_acc_vio; |
| 2908 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2909 | clr_int_reg_23_addr_decoded or |
| 2910 | daemon_transaction_in_progress) |
| 2911 | begin |
| 2912 | if (daemon_transaction_in_progress | ~clr_int_reg_23_addr_decoded) |
| 2913 | clr_int_reg_23_acc_vio = 1'b0; |
| 2914 | else |
| 2915 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2916 | // reads |
| 2917 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2918 | clr_int_reg_23_acc_vio = 1'b0; |
| 2919 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2920 | clr_int_reg_23_acc_vio = 1'b0; |
| 2921 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2922 | clr_int_reg_23_acc_vio = 1'b0; |
| 2923 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2924 | clr_int_reg_23_acc_vio = 1'b0; |
| 2925 | // writes |
| 2926 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2927 | clr_int_reg_23_acc_vio = 1'b0; |
| 2928 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2929 | clr_int_reg_23_acc_vio = 1'b0; |
| 2930 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2931 | clr_int_reg_23_acc_vio = 1'b0; |
| 2932 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2933 | clr_int_reg_23_acc_vio = 1'b0; |
| 2934 | |
| 2935 | default: |
| 2936 | begin |
| 2937 | clr_int_reg_23_acc_vio = 1'b0; |
| 2938 | begin // axis tbcall_region |
| 2939 | // vlint flag_system_call off |
| 2940 | // synopsys translate_off |
| 2941 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_23"); `endif |
| 2942 | // synopsys translate_on |
| 2943 | // vlint flag_system_call on |
| 2944 | end // end of tbcall_region |
| 2945 | end |
| 2946 | endcase |
| 2947 | end |
| 2948 | //----- reg_acc_vio: clr_int_reg_24 |
| 2949 | reg clr_int_reg_24_acc_vio; |
| 2950 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2951 | clr_int_reg_24_addr_decoded or |
| 2952 | daemon_transaction_in_progress) |
| 2953 | begin |
| 2954 | if (daemon_transaction_in_progress | ~clr_int_reg_24_addr_decoded) |
| 2955 | clr_int_reg_24_acc_vio = 1'b0; |
| 2956 | else |
| 2957 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 2958 | // reads |
| 2959 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 2960 | clr_int_reg_24_acc_vio = 1'b0; |
| 2961 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 2962 | clr_int_reg_24_acc_vio = 1'b0; |
| 2963 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 2964 | clr_int_reg_24_acc_vio = 1'b0; |
| 2965 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 2966 | clr_int_reg_24_acc_vio = 1'b0; |
| 2967 | // writes |
| 2968 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 2969 | clr_int_reg_24_acc_vio = 1'b0; |
| 2970 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 2971 | clr_int_reg_24_acc_vio = 1'b0; |
| 2972 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 2973 | clr_int_reg_24_acc_vio = 1'b0; |
| 2974 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 2975 | clr_int_reg_24_acc_vio = 1'b0; |
| 2976 | |
| 2977 | default: |
| 2978 | begin |
| 2979 | clr_int_reg_24_acc_vio = 1'b0; |
| 2980 | begin // axis tbcall_region |
| 2981 | // vlint flag_system_call off |
| 2982 | // synopsys translate_off |
| 2983 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_24"); `endif |
| 2984 | // synopsys translate_on |
| 2985 | // vlint flag_system_call on |
| 2986 | end // end of tbcall_region |
| 2987 | end |
| 2988 | endcase |
| 2989 | end |
| 2990 | //----- reg_acc_vio: clr_int_reg_25 |
| 2991 | reg clr_int_reg_25_acc_vio; |
| 2992 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 2993 | clr_int_reg_25_addr_decoded or |
| 2994 | daemon_transaction_in_progress) |
| 2995 | begin |
| 2996 | if (daemon_transaction_in_progress | ~clr_int_reg_25_addr_decoded) |
| 2997 | clr_int_reg_25_acc_vio = 1'b0; |
| 2998 | else |
| 2999 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3000 | // reads |
| 3001 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3002 | clr_int_reg_25_acc_vio = 1'b0; |
| 3003 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3004 | clr_int_reg_25_acc_vio = 1'b0; |
| 3005 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3006 | clr_int_reg_25_acc_vio = 1'b0; |
| 3007 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3008 | clr_int_reg_25_acc_vio = 1'b0; |
| 3009 | // writes |
| 3010 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3011 | clr_int_reg_25_acc_vio = 1'b0; |
| 3012 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3013 | clr_int_reg_25_acc_vio = 1'b0; |
| 3014 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3015 | clr_int_reg_25_acc_vio = 1'b0; |
| 3016 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3017 | clr_int_reg_25_acc_vio = 1'b0; |
| 3018 | |
| 3019 | default: |
| 3020 | begin |
| 3021 | clr_int_reg_25_acc_vio = 1'b0; |
| 3022 | begin // axis tbcall_region |
| 3023 | // vlint flag_system_call off |
| 3024 | // synopsys translate_off |
| 3025 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_25"); `endif |
| 3026 | // synopsys translate_on |
| 3027 | // vlint flag_system_call on |
| 3028 | end // end of tbcall_region |
| 3029 | end |
| 3030 | endcase |
| 3031 | end |
| 3032 | //----- reg_acc_vio: clr_int_reg_26 |
| 3033 | reg clr_int_reg_26_acc_vio; |
| 3034 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3035 | clr_int_reg_26_addr_decoded or |
| 3036 | daemon_transaction_in_progress) |
| 3037 | begin |
| 3038 | if (daemon_transaction_in_progress | ~clr_int_reg_26_addr_decoded) |
| 3039 | clr_int_reg_26_acc_vio = 1'b0; |
| 3040 | else |
| 3041 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3042 | // reads |
| 3043 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3044 | clr_int_reg_26_acc_vio = 1'b0; |
| 3045 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3046 | clr_int_reg_26_acc_vio = 1'b0; |
| 3047 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3048 | clr_int_reg_26_acc_vio = 1'b0; |
| 3049 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3050 | clr_int_reg_26_acc_vio = 1'b0; |
| 3051 | // writes |
| 3052 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3053 | clr_int_reg_26_acc_vio = 1'b0; |
| 3054 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3055 | clr_int_reg_26_acc_vio = 1'b0; |
| 3056 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3057 | clr_int_reg_26_acc_vio = 1'b0; |
| 3058 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3059 | clr_int_reg_26_acc_vio = 1'b0; |
| 3060 | |
| 3061 | default: |
| 3062 | begin |
| 3063 | clr_int_reg_26_acc_vio = 1'b0; |
| 3064 | begin // axis tbcall_region |
| 3065 | // vlint flag_system_call off |
| 3066 | // synopsys translate_off |
| 3067 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_26"); `endif |
| 3068 | // synopsys translate_on |
| 3069 | // vlint flag_system_call on |
| 3070 | end // end of tbcall_region |
| 3071 | end |
| 3072 | endcase |
| 3073 | end |
| 3074 | //----- reg_acc_vio: clr_int_reg_27 |
| 3075 | reg clr_int_reg_27_acc_vio; |
| 3076 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3077 | clr_int_reg_27_addr_decoded or |
| 3078 | daemon_transaction_in_progress) |
| 3079 | begin |
| 3080 | if (daemon_transaction_in_progress | ~clr_int_reg_27_addr_decoded) |
| 3081 | clr_int_reg_27_acc_vio = 1'b0; |
| 3082 | else |
| 3083 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3084 | // reads |
| 3085 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3086 | clr_int_reg_27_acc_vio = 1'b0; |
| 3087 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3088 | clr_int_reg_27_acc_vio = 1'b0; |
| 3089 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3090 | clr_int_reg_27_acc_vio = 1'b0; |
| 3091 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3092 | clr_int_reg_27_acc_vio = 1'b0; |
| 3093 | // writes |
| 3094 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3095 | clr_int_reg_27_acc_vio = 1'b0; |
| 3096 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3097 | clr_int_reg_27_acc_vio = 1'b0; |
| 3098 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3099 | clr_int_reg_27_acc_vio = 1'b0; |
| 3100 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3101 | clr_int_reg_27_acc_vio = 1'b0; |
| 3102 | |
| 3103 | default: |
| 3104 | begin |
| 3105 | clr_int_reg_27_acc_vio = 1'b0; |
| 3106 | begin // axis tbcall_region |
| 3107 | // vlint flag_system_call off |
| 3108 | // synopsys translate_off |
| 3109 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_27"); `endif |
| 3110 | // synopsys translate_on |
| 3111 | // vlint flag_system_call on |
| 3112 | end // end of tbcall_region |
| 3113 | end |
| 3114 | endcase |
| 3115 | end |
| 3116 | //----- reg_acc_vio: clr_int_reg_28 |
| 3117 | reg clr_int_reg_28_acc_vio; |
| 3118 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3119 | clr_int_reg_28_addr_decoded or |
| 3120 | daemon_transaction_in_progress) |
| 3121 | begin |
| 3122 | if (daemon_transaction_in_progress | ~clr_int_reg_28_addr_decoded) |
| 3123 | clr_int_reg_28_acc_vio = 1'b0; |
| 3124 | else |
| 3125 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3126 | // reads |
| 3127 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3128 | clr_int_reg_28_acc_vio = 1'b0; |
| 3129 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3130 | clr_int_reg_28_acc_vio = 1'b0; |
| 3131 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3132 | clr_int_reg_28_acc_vio = 1'b0; |
| 3133 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3134 | clr_int_reg_28_acc_vio = 1'b0; |
| 3135 | // writes |
| 3136 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3137 | clr_int_reg_28_acc_vio = 1'b0; |
| 3138 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3139 | clr_int_reg_28_acc_vio = 1'b0; |
| 3140 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3141 | clr_int_reg_28_acc_vio = 1'b0; |
| 3142 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3143 | clr_int_reg_28_acc_vio = 1'b0; |
| 3144 | |
| 3145 | default: |
| 3146 | begin |
| 3147 | clr_int_reg_28_acc_vio = 1'b0; |
| 3148 | begin // axis tbcall_region |
| 3149 | // vlint flag_system_call off |
| 3150 | // synopsys translate_off |
| 3151 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_28"); `endif |
| 3152 | // synopsys translate_on |
| 3153 | // vlint flag_system_call on |
| 3154 | end // end of tbcall_region |
| 3155 | end |
| 3156 | endcase |
| 3157 | end |
| 3158 | //----- reg_acc_vio: clr_int_reg_29 |
| 3159 | reg clr_int_reg_29_acc_vio; |
| 3160 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3161 | clr_int_reg_29_addr_decoded or |
| 3162 | daemon_transaction_in_progress) |
| 3163 | begin |
| 3164 | if (daemon_transaction_in_progress | ~clr_int_reg_29_addr_decoded) |
| 3165 | clr_int_reg_29_acc_vio = 1'b0; |
| 3166 | else |
| 3167 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3168 | // reads |
| 3169 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3170 | clr_int_reg_29_acc_vio = 1'b0; |
| 3171 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3172 | clr_int_reg_29_acc_vio = 1'b0; |
| 3173 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3174 | clr_int_reg_29_acc_vio = 1'b0; |
| 3175 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3176 | clr_int_reg_29_acc_vio = 1'b0; |
| 3177 | // writes |
| 3178 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3179 | clr_int_reg_29_acc_vio = 1'b0; |
| 3180 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3181 | clr_int_reg_29_acc_vio = 1'b0; |
| 3182 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3183 | clr_int_reg_29_acc_vio = 1'b0; |
| 3184 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3185 | clr_int_reg_29_acc_vio = 1'b0; |
| 3186 | |
| 3187 | default: |
| 3188 | begin |
| 3189 | clr_int_reg_29_acc_vio = 1'b0; |
| 3190 | begin // axis tbcall_region |
| 3191 | // vlint flag_system_call off |
| 3192 | // synopsys translate_off |
| 3193 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_29"); `endif |
| 3194 | // synopsys translate_on |
| 3195 | // vlint flag_system_call on |
| 3196 | end // end of tbcall_region |
| 3197 | end |
| 3198 | endcase |
| 3199 | end |
| 3200 | //----- reg_acc_vio: clr_int_reg_30 |
| 3201 | reg clr_int_reg_30_acc_vio; |
| 3202 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3203 | clr_int_reg_30_addr_decoded or |
| 3204 | daemon_transaction_in_progress) |
| 3205 | begin |
| 3206 | if (daemon_transaction_in_progress | ~clr_int_reg_30_addr_decoded) |
| 3207 | clr_int_reg_30_acc_vio = 1'b0; |
| 3208 | else |
| 3209 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3210 | // reads |
| 3211 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3212 | clr_int_reg_30_acc_vio = 1'b0; |
| 3213 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3214 | clr_int_reg_30_acc_vio = 1'b0; |
| 3215 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3216 | clr_int_reg_30_acc_vio = 1'b0; |
| 3217 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3218 | clr_int_reg_30_acc_vio = 1'b0; |
| 3219 | // writes |
| 3220 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3221 | clr_int_reg_30_acc_vio = 1'b0; |
| 3222 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3223 | clr_int_reg_30_acc_vio = 1'b0; |
| 3224 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3225 | clr_int_reg_30_acc_vio = 1'b0; |
| 3226 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3227 | clr_int_reg_30_acc_vio = 1'b0; |
| 3228 | |
| 3229 | default: |
| 3230 | begin |
| 3231 | clr_int_reg_30_acc_vio = 1'b0; |
| 3232 | begin // axis tbcall_region |
| 3233 | // vlint flag_system_call off |
| 3234 | // synopsys translate_off |
| 3235 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_30"); `endif |
| 3236 | // synopsys translate_on |
| 3237 | // vlint flag_system_call on |
| 3238 | end // end of tbcall_region |
| 3239 | end |
| 3240 | endcase |
| 3241 | end |
| 3242 | //----- reg_acc_vio: clr_int_reg_31 |
| 3243 | reg clr_int_reg_31_acc_vio; |
| 3244 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3245 | clr_int_reg_31_addr_decoded or |
| 3246 | daemon_transaction_in_progress) |
| 3247 | begin |
| 3248 | if (daemon_transaction_in_progress | ~clr_int_reg_31_addr_decoded) |
| 3249 | clr_int_reg_31_acc_vio = 1'b0; |
| 3250 | else |
| 3251 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3252 | // reads |
| 3253 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3254 | clr_int_reg_31_acc_vio = 1'b0; |
| 3255 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3256 | clr_int_reg_31_acc_vio = 1'b0; |
| 3257 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3258 | clr_int_reg_31_acc_vio = 1'b0; |
| 3259 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3260 | clr_int_reg_31_acc_vio = 1'b0; |
| 3261 | // writes |
| 3262 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3263 | clr_int_reg_31_acc_vio = 1'b0; |
| 3264 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3265 | clr_int_reg_31_acc_vio = 1'b0; |
| 3266 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3267 | clr_int_reg_31_acc_vio = 1'b0; |
| 3268 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3269 | clr_int_reg_31_acc_vio = 1'b0; |
| 3270 | |
| 3271 | default: |
| 3272 | begin |
| 3273 | clr_int_reg_31_acc_vio = 1'b0; |
| 3274 | begin // axis tbcall_region |
| 3275 | // vlint flag_system_call off |
| 3276 | // synopsys translate_off |
| 3277 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_31"); `endif |
| 3278 | // synopsys translate_on |
| 3279 | // vlint flag_system_call on |
| 3280 | end // end of tbcall_region |
| 3281 | end |
| 3282 | endcase |
| 3283 | end |
| 3284 | //----- reg_acc_vio: clr_int_reg_32 |
| 3285 | reg clr_int_reg_32_acc_vio; |
| 3286 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3287 | clr_int_reg_32_addr_decoded or |
| 3288 | daemon_transaction_in_progress) |
| 3289 | begin |
| 3290 | if (daemon_transaction_in_progress | ~clr_int_reg_32_addr_decoded) |
| 3291 | clr_int_reg_32_acc_vio = 1'b0; |
| 3292 | else |
| 3293 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3294 | // reads |
| 3295 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3296 | clr_int_reg_32_acc_vio = 1'b0; |
| 3297 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3298 | clr_int_reg_32_acc_vio = 1'b0; |
| 3299 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3300 | clr_int_reg_32_acc_vio = 1'b0; |
| 3301 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3302 | clr_int_reg_32_acc_vio = 1'b0; |
| 3303 | // writes |
| 3304 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3305 | clr_int_reg_32_acc_vio = 1'b0; |
| 3306 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3307 | clr_int_reg_32_acc_vio = 1'b0; |
| 3308 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3309 | clr_int_reg_32_acc_vio = 1'b0; |
| 3310 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3311 | clr_int_reg_32_acc_vio = 1'b0; |
| 3312 | |
| 3313 | default: |
| 3314 | begin |
| 3315 | clr_int_reg_32_acc_vio = 1'b0; |
| 3316 | begin // axis tbcall_region |
| 3317 | // vlint flag_system_call off |
| 3318 | // synopsys translate_off |
| 3319 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_32"); `endif |
| 3320 | // synopsys translate_on |
| 3321 | // vlint flag_system_call on |
| 3322 | end // end of tbcall_region |
| 3323 | end |
| 3324 | endcase |
| 3325 | end |
| 3326 | //----- reg_acc_vio: clr_int_reg_33 |
| 3327 | reg clr_int_reg_33_acc_vio; |
| 3328 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3329 | clr_int_reg_33_addr_decoded or |
| 3330 | daemon_transaction_in_progress) |
| 3331 | begin |
| 3332 | if (daemon_transaction_in_progress | ~clr_int_reg_33_addr_decoded) |
| 3333 | clr_int_reg_33_acc_vio = 1'b0; |
| 3334 | else |
| 3335 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3336 | // reads |
| 3337 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3338 | clr_int_reg_33_acc_vio = 1'b0; |
| 3339 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3340 | clr_int_reg_33_acc_vio = 1'b0; |
| 3341 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3342 | clr_int_reg_33_acc_vio = 1'b0; |
| 3343 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3344 | clr_int_reg_33_acc_vio = 1'b0; |
| 3345 | // writes |
| 3346 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3347 | clr_int_reg_33_acc_vio = 1'b0; |
| 3348 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3349 | clr_int_reg_33_acc_vio = 1'b0; |
| 3350 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3351 | clr_int_reg_33_acc_vio = 1'b0; |
| 3352 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3353 | clr_int_reg_33_acc_vio = 1'b0; |
| 3354 | |
| 3355 | default: |
| 3356 | begin |
| 3357 | clr_int_reg_33_acc_vio = 1'b0; |
| 3358 | begin // axis tbcall_region |
| 3359 | // vlint flag_system_call off |
| 3360 | // synopsys translate_off |
| 3361 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_33"); `endif |
| 3362 | // synopsys translate_on |
| 3363 | // vlint flag_system_call on |
| 3364 | end // end of tbcall_region |
| 3365 | end |
| 3366 | endcase |
| 3367 | end |
| 3368 | //----- reg_acc_vio: clr_int_reg_34 |
| 3369 | reg clr_int_reg_34_acc_vio; |
| 3370 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3371 | clr_int_reg_34_addr_decoded or |
| 3372 | daemon_transaction_in_progress) |
| 3373 | begin |
| 3374 | if (daemon_transaction_in_progress | ~clr_int_reg_34_addr_decoded) |
| 3375 | clr_int_reg_34_acc_vio = 1'b0; |
| 3376 | else |
| 3377 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3378 | // reads |
| 3379 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3380 | clr_int_reg_34_acc_vio = 1'b0; |
| 3381 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3382 | clr_int_reg_34_acc_vio = 1'b0; |
| 3383 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3384 | clr_int_reg_34_acc_vio = 1'b0; |
| 3385 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3386 | clr_int_reg_34_acc_vio = 1'b0; |
| 3387 | // writes |
| 3388 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3389 | clr_int_reg_34_acc_vio = 1'b0; |
| 3390 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3391 | clr_int_reg_34_acc_vio = 1'b0; |
| 3392 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3393 | clr_int_reg_34_acc_vio = 1'b0; |
| 3394 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3395 | clr_int_reg_34_acc_vio = 1'b0; |
| 3396 | |
| 3397 | default: |
| 3398 | begin |
| 3399 | clr_int_reg_34_acc_vio = 1'b0; |
| 3400 | begin // axis tbcall_region |
| 3401 | // vlint flag_system_call off |
| 3402 | // synopsys translate_off |
| 3403 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_34"); `endif |
| 3404 | // synopsys translate_on |
| 3405 | // vlint flag_system_call on |
| 3406 | end // end of tbcall_region |
| 3407 | end |
| 3408 | endcase |
| 3409 | end |
| 3410 | //----- reg_acc_vio: clr_int_reg_35 |
| 3411 | reg clr_int_reg_35_acc_vio; |
| 3412 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3413 | clr_int_reg_35_addr_decoded or |
| 3414 | daemon_transaction_in_progress) |
| 3415 | begin |
| 3416 | if (daemon_transaction_in_progress | ~clr_int_reg_35_addr_decoded) |
| 3417 | clr_int_reg_35_acc_vio = 1'b0; |
| 3418 | else |
| 3419 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3420 | // reads |
| 3421 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3422 | clr_int_reg_35_acc_vio = 1'b0; |
| 3423 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3424 | clr_int_reg_35_acc_vio = 1'b0; |
| 3425 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3426 | clr_int_reg_35_acc_vio = 1'b0; |
| 3427 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3428 | clr_int_reg_35_acc_vio = 1'b0; |
| 3429 | // writes |
| 3430 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3431 | clr_int_reg_35_acc_vio = 1'b0; |
| 3432 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3433 | clr_int_reg_35_acc_vio = 1'b0; |
| 3434 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3435 | clr_int_reg_35_acc_vio = 1'b0; |
| 3436 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3437 | clr_int_reg_35_acc_vio = 1'b0; |
| 3438 | |
| 3439 | default: |
| 3440 | begin |
| 3441 | clr_int_reg_35_acc_vio = 1'b0; |
| 3442 | begin // axis tbcall_region |
| 3443 | // vlint flag_system_call off |
| 3444 | // synopsys translate_off |
| 3445 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_35"); `endif |
| 3446 | // synopsys translate_on |
| 3447 | // vlint flag_system_call on |
| 3448 | end // end of tbcall_region |
| 3449 | end |
| 3450 | endcase |
| 3451 | end |
| 3452 | //----- reg_acc_vio: clr_int_reg_36 |
| 3453 | reg clr_int_reg_36_acc_vio; |
| 3454 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3455 | clr_int_reg_36_addr_decoded or |
| 3456 | daemon_transaction_in_progress) |
| 3457 | begin |
| 3458 | if (daemon_transaction_in_progress | ~clr_int_reg_36_addr_decoded) |
| 3459 | clr_int_reg_36_acc_vio = 1'b0; |
| 3460 | else |
| 3461 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3462 | // reads |
| 3463 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3464 | clr_int_reg_36_acc_vio = 1'b0; |
| 3465 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3466 | clr_int_reg_36_acc_vio = 1'b0; |
| 3467 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3468 | clr_int_reg_36_acc_vio = 1'b0; |
| 3469 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3470 | clr_int_reg_36_acc_vio = 1'b0; |
| 3471 | // writes |
| 3472 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3473 | clr_int_reg_36_acc_vio = 1'b0; |
| 3474 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3475 | clr_int_reg_36_acc_vio = 1'b0; |
| 3476 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3477 | clr_int_reg_36_acc_vio = 1'b0; |
| 3478 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3479 | clr_int_reg_36_acc_vio = 1'b0; |
| 3480 | |
| 3481 | default: |
| 3482 | begin |
| 3483 | clr_int_reg_36_acc_vio = 1'b0; |
| 3484 | begin // axis tbcall_region |
| 3485 | // vlint flag_system_call off |
| 3486 | // synopsys translate_off |
| 3487 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_36"); `endif |
| 3488 | // synopsys translate_on |
| 3489 | // vlint flag_system_call on |
| 3490 | end // end of tbcall_region |
| 3491 | end |
| 3492 | endcase |
| 3493 | end |
| 3494 | //----- reg_acc_vio: clr_int_reg_37 |
| 3495 | reg clr_int_reg_37_acc_vio; |
| 3496 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3497 | clr_int_reg_37_addr_decoded or |
| 3498 | daemon_transaction_in_progress) |
| 3499 | begin |
| 3500 | if (daemon_transaction_in_progress | ~clr_int_reg_37_addr_decoded) |
| 3501 | clr_int_reg_37_acc_vio = 1'b0; |
| 3502 | else |
| 3503 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3504 | // reads |
| 3505 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3506 | clr_int_reg_37_acc_vio = 1'b0; |
| 3507 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3508 | clr_int_reg_37_acc_vio = 1'b0; |
| 3509 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3510 | clr_int_reg_37_acc_vio = 1'b0; |
| 3511 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3512 | clr_int_reg_37_acc_vio = 1'b0; |
| 3513 | // writes |
| 3514 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3515 | clr_int_reg_37_acc_vio = 1'b0; |
| 3516 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3517 | clr_int_reg_37_acc_vio = 1'b0; |
| 3518 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3519 | clr_int_reg_37_acc_vio = 1'b0; |
| 3520 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3521 | clr_int_reg_37_acc_vio = 1'b0; |
| 3522 | |
| 3523 | default: |
| 3524 | begin |
| 3525 | clr_int_reg_37_acc_vio = 1'b0; |
| 3526 | begin // axis tbcall_region |
| 3527 | // vlint flag_system_call off |
| 3528 | // synopsys translate_off |
| 3529 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_37"); `endif |
| 3530 | // synopsys translate_on |
| 3531 | // vlint flag_system_call on |
| 3532 | end // end of tbcall_region |
| 3533 | end |
| 3534 | endcase |
| 3535 | end |
| 3536 | //----- reg_acc_vio: clr_int_reg_38 |
| 3537 | reg clr_int_reg_38_acc_vio; |
| 3538 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3539 | clr_int_reg_38_addr_decoded or |
| 3540 | daemon_transaction_in_progress) |
| 3541 | begin |
| 3542 | if (daemon_transaction_in_progress | ~clr_int_reg_38_addr_decoded) |
| 3543 | clr_int_reg_38_acc_vio = 1'b0; |
| 3544 | else |
| 3545 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3546 | // reads |
| 3547 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3548 | clr_int_reg_38_acc_vio = 1'b0; |
| 3549 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3550 | clr_int_reg_38_acc_vio = 1'b0; |
| 3551 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3552 | clr_int_reg_38_acc_vio = 1'b0; |
| 3553 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3554 | clr_int_reg_38_acc_vio = 1'b0; |
| 3555 | // writes |
| 3556 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3557 | clr_int_reg_38_acc_vio = 1'b0; |
| 3558 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3559 | clr_int_reg_38_acc_vio = 1'b0; |
| 3560 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3561 | clr_int_reg_38_acc_vio = 1'b0; |
| 3562 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3563 | clr_int_reg_38_acc_vio = 1'b0; |
| 3564 | |
| 3565 | default: |
| 3566 | begin |
| 3567 | clr_int_reg_38_acc_vio = 1'b0; |
| 3568 | begin // axis tbcall_region |
| 3569 | // vlint flag_system_call off |
| 3570 | // synopsys translate_off |
| 3571 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_38"); `endif |
| 3572 | // synopsys translate_on |
| 3573 | // vlint flag_system_call on |
| 3574 | end // end of tbcall_region |
| 3575 | end |
| 3576 | endcase |
| 3577 | end |
| 3578 | //----- reg_acc_vio: clr_int_reg_39 |
| 3579 | reg clr_int_reg_39_acc_vio; |
| 3580 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3581 | clr_int_reg_39_addr_decoded or |
| 3582 | daemon_transaction_in_progress) |
| 3583 | begin |
| 3584 | if (daemon_transaction_in_progress | ~clr_int_reg_39_addr_decoded) |
| 3585 | clr_int_reg_39_acc_vio = 1'b0; |
| 3586 | else |
| 3587 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3588 | // reads |
| 3589 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3590 | clr_int_reg_39_acc_vio = 1'b0; |
| 3591 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3592 | clr_int_reg_39_acc_vio = 1'b0; |
| 3593 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3594 | clr_int_reg_39_acc_vio = 1'b0; |
| 3595 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3596 | clr_int_reg_39_acc_vio = 1'b0; |
| 3597 | // writes |
| 3598 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3599 | clr_int_reg_39_acc_vio = 1'b0; |
| 3600 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3601 | clr_int_reg_39_acc_vio = 1'b0; |
| 3602 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3603 | clr_int_reg_39_acc_vio = 1'b0; |
| 3604 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3605 | clr_int_reg_39_acc_vio = 1'b0; |
| 3606 | |
| 3607 | default: |
| 3608 | begin |
| 3609 | clr_int_reg_39_acc_vio = 1'b0; |
| 3610 | begin // axis tbcall_region |
| 3611 | // vlint flag_system_call off |
| 3612 | // synopsys translate_off |
| 3613 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_39"); `endif |
| 3614 | // synopsys translate_on |
| 3615 | // vlint flag_system_call on |
| 3616 | end // end of tbcall_region |
| 3617 | end |
| 3618 | endcase |
| 3619 | end |
| 3620 | //----- reg_acc_vio: clr_int_reg_40 |
| 3621 | reg clr_int_reg_40_acc_vio; |
| 3622 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3623 | clr_int_reg_40_addr_decoded or |
| 3624 | daemon_transaction_in_progress) |
| 3625 | begin |
| 3626 | if (daemon_transaction_in_progress | ~clr_int_reg_40_addr_decoded) |
| 3627 | clr_int_reg_40_acc_vio = 1'b0; |
| 3628 | else |
| 3629 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3630 | // reads |
| 3631 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3632 | clr_int_reg_40_acc_vio = 1'b0; |
| 3633 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3634 | clr_int_reg_40_acc_vio = 1'b0; |
| 3635 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3636 | clr_int_reg_40_acc_vio = 1'b0; |
| 3637 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3638 | clr_int_reg_40_acc_vio = 1'b0; |
| 3639 | // writes |
| 3640 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3641 | clr_int_reg_40_acc_vio = 1'b0; |
| 3642 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3643 | clr_int_reg_40_acc_vio = 1'b0; |
| 3644 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3645 | clr_int_reg_40_acc_vio = 1'b0; |
| 3646 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3647 | clr_int_reg_40_acc_vio = 1'b0; |
| 3648 | |
| 3649 | default: |
| 3650 | begin |
| 3651 | clr_int_reg_40_acc_vio = 1'b0; |
| 3652 | begin // axis tbcall_region |
| 3653 | // vlint flag_system_call off |
| 3654 | // synopsys translate_off |
| 3655 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_40"); `endif |
| 3656 | // synopsys translate_on |
| 3657 | // vlint flag_system_call on |
| 3658 | end // end of tbcall_region |
| 3659 | end |
| 3660 | endcase |
| 3661 | end |
| 3662 | //----- reg_acc_vio: clr_int_reg_41 |
| 3663 | reg clr_int_reg_41_acc_vio; |
| 3664 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3665 | clr_int_reg_41_addr_decoded or |
| 3666 | daemon_transaction_in_progress) |
| 3667 | begin |
| 3668 | if (daemon_transaction_in_progress | ~clr_int_reg_41_addr_decoded) |
| 3669 | clr_int_reg_41_acc_vio = 1'b0; |
| 3670 | else |
| 3671 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3672 | // reads |
| 3673 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3674 | clr_int_reg_41_acc_vio = 1'b0; |
| 3675 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3676 | clr_int_reg_41_acc_vio = 1'b0; |
| 3677 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3678 | clr_int_reg_41_acc_vio = 1'b0; |
| 3679 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3680 | clr_int_reg_41_acc_vio = 1'b0; |
| 3681 | // writes |
| 3682 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3683 | clr_int_reg_41_acc_vio = 1'b0; |
| 3684 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3685 | clr_int_reg_41_acc_vio = 1'b0; |
| 3686 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3687 | clr_int_reg_41_acc_vio = 1'b0; |
| 3688 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3689 | clr_int_reg_41_acc_vio = 1'b0; |
| 3690 | |
| 3691 | default: |
| 3692 | begin |
| 3693 | clr_int_reg_41_acc_vio = 1'b0; |
| 3694 | begin // axis tbcall_region |
| 3695 | // vlint flag_system_call off |
| 3696 | // synopsys translate_off |
| 3697 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_41"); `endif |
| 3698 | // synopsys translate_on |
| 3699 | // vlint flag_system_call on |
| 3700 | end // end of tbcall_region |
| 3701 | end |
| 3702 | endcase |
| 3703 | end |
| 3704 | //----- reg_acc_vio: clr_int_reg_42 |
| 3705 | reg clr_int_reg_42_acc_vio; |
| 3706 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3707 | clr_int_reg_42_addr_decoded or |
| 3708 | daemon_transaction_in_progress) |
| 3709 | begin |
| 3710 | if (daemon_transaction_in_progress | ~clr_int_reg_42_addr_decoded) |
| 3711 | clr_int_reg_42_acc_vio = 1'b0; |
| 3712 | else |
| 3713 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3714 | // reads |
| 3715 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3716 | clr_int_reg_42_acc_vio = 1'b0; |
| 3717 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3718 | clr_int_reg_42_acc_vio = 1'b0; |
| 3719 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3720 | clr_int_reg_42_acc_vio = 1'b0; |
| 3721 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3722 | clr_int_reg_42_acc_vio = 1'b0; |
| 3723 | // writes |
| 3724 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3725 | clr_int_reg_42_acc_vio = 1'b0; |
| 3726 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3727 | clr_int_reg_42_acc_vio = 1'b0; |
| 3728 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3729 | clr_int_reg_42_acc_vio = 1'b0; |
| 3730 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3731 | clr_int_reg_42_acc_vio = 1'b0; |
| 3732 | |
| 3733 | default: |
| 3734 | begin |
| 3735 | clr_int_reg_42_acc_vio = 1'b0; |
| 3736 | begin // axis tbcall_region |
| 3737 | // vlint flag_system_call off |
| 3738 | // synopsys translate_off |
| 3739 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_42"); `endif |
| 3740 | // synopsys translate_on |
| 3741 | // vlint flag_system_call on |
| 3742 | end // end of tbcall_region |
| 3743 | end |
| 3744 | endcase |
| 3745 | end |
| 3746 | //----- reg_acc_vio: clr_int_reg_43 |
| 3747 | reg clr_int_reg_43_acc_vio; |
| 3748 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3749 | clr_int_reg_43_addr_decoded or |
| 3750 | daemon_transaction_in_progress) |
| 3751 | begin |
| 3752 | if (daemon_transaction_in_progress | ~clr_int_reg_43_addr_decoded) |
| 3753 | clr_int_reg_43_acc_vio = 1'b0; |
| 3754 | else |
| 3755 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3756 | // reads |
| 3757 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3758 | clr_int_reg_43_acc_vio = 1'b0; |
| 3759 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3760 | clr_int_reg_43_acc_vio = 1'b0; |
| 3761 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3762 | clr_int_reg_43_acc_vio = 1'b0; |
| 3763 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3764 | clr_int_reg_43_acc_vio = 1'b0; |
| 3765 | // writes |
| 3766 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3767 | clr_int_reg_43_acc_vio = 1'b0; |
| 3768 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3769 | clr_int_reg_43_acc_vio = 1'b0; |
| 3770 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3771 | clr_int_reg_43_acc_vio = 1'b0; |
| 3772 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3773 | clr_int_reg_43_acc_vio = 1'b0; |
| 3774 | |
| 3775 | default: |
| 3776 | begin |
| 3777 | clr_int_reg_43_acc_vio = 1'b0; |
| 3778 | begin // axis tbcall_region |
| 3779 | // vlint flag_system_call off |
| 3780 | // synopsys translate_off |
| 3781 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_43"); `endif |
| 3782 | // synopsys translate_on |
| 3783 | // vlint flag_system_call on |
| 3784 | end // end of tbcall_region |
| 3785 | end |
| 3786 | endcase |
| 3787 | end |
| 3788 | //----- reg_acc_vio: clr_int_reg_44 |
| 3789 | reg clr_int_reg_44_acc_vio; |
| 3790 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3791 | clr_int_reg_44_addr_decoded or |
| 3792 | daemon_transaction_in_progress) |
| 3793 | begin |
| 3794 | if (daemon_transaction_in_progress | ~clr_int_reg_44_addr_decoded) |
| 3795 | clr_int_reg_44_acc_vio = 1'b0; |
| 3796 | else |
| 3797 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3798 | // reads |
| 3799 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3800 | clr_int_reg_44_acc_vio = 1'b0; |
| 3801 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3802 | clr_int_reg_44_acc_vio = 1'b0; |
| 3803 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3804 | clr_int_reg_44_acc_vio = 1'b0; |
| 3805 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3806 | clr_int_reg_44_acc_vio = 1'b0; |
| 3807 | // writes |
| 3808 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3809 | clr_int_reg_44_acc_vio = 1'b0; |
| 3810 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3811 | clr_int_reg_44_acc_vio = 1'b0; |
| 3812 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3813 | clr_int_reg_44_acc_vio = 1'b0; |
| 3814 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3815 | clr_int_reg_44_acc_vio = 1'b0; |
| 3816 | |
| 3817 | default: |
| 3818 | begin |
| 3819 | clr_int_reg_44_acc_vio = 1'b0; |
| 3820 | begin // axis tbcall_region |
| 3821 | // vlint flag_system_call off |
| 3822 | // synopsys translate_off |
| 3823 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_44"); `endif |
| 3824 | // synopsys translate_on |
| 3825 | // vlint flag_system_call on |
| 3826 | end // end of tbcall_region |
| 3827 | end |
| 3828 | endcase |
| 3829 | end |
| 3830 | //----- reg_acc_vio: clr_int_reg_45 |
| 3831 | reg clr_int_reg_45_acc_vio; |
| 3832 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3833 | clr_int_reg_45_addr_decoded or |
| 3834 | daemon_transaction_in_progress) |
| 3835 | begin |
| 3836 | if (daemon_transaction_in_progress | ~clr_int_reg_45_addr_decoded) |
| 3837 | clr_int_reg_45_acc_vio = 1'b0; |
| 3838 | else |
| 3839 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3840 | // reads |
| 3841 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3842 | clr_int_reg_45_acc_vio = 1'b0; |
| 3843 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3844 | clr_int_reg_45_acc_vio = 1'b0; |
| 3845 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3846 | clr_int_reg_45_acc_vio = 1'b0; |
| 3847 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3848 | clr_int_reg_45_acc_vio = 1'b0; |
| 3849 | // writes |
| 3850 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3851 | clr_int_reg_45_acc_vio = 1'b0; |
| 3852 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3853 | clr_int_reg_45_acc_vio = 1'b0; |
| 3854 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3855 | clr_int_reg_45_acc_vio = 1'b0; |
| 3856 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3857 | clr_int_reg_45_acc_vio = 1'b0; |
| 3858 | |
| 3859 | default: |
| 3860 | begin |
| 3861 | clr_int_reg_45_acc_vio = 1'b0; |
| 3862 | begin // axis tbcall_region |
| 3863 | // vlint flag_system_call off |
| 3864 | // synopsys translate_off |
| 3865 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_45"); `endif |
| 3866 | // synopsys translate_on |
| 3867 | // vlint flag_system_call on |
| 3868 | end // end of tbcall_region |
| 3869 | end |
| 3870 | endcase |
| 3871 | end |
| 3872 | //----- reg_acc_vio: clr_int_reg_46 |
| 3873 | reg clr_int_reg_46_acc_vio; |
| 3874 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3875 | clr_int_reg_46_addr_decoded or |
| 3876 | daemon_transaction_in_progress) |
| 3877 | begin |
| 3878 | if (daemon_transaction_in_progress | ~clr_int_reg_46_addr_decoded) |
| 3879 | clr_int_reg_46_acc_vio = 1'b0; |
| 3880 | else |
| 3881 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3882 | // reads |
| 3883 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3884 | clr_int_reg_46_acc_vio = 1'b0; |
| 3885 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3886 | clr_int_reg_46_acc_vio = 1'b0; |
| 3887 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3888 | clr_int_reg_46_acc_vio = 1'b0; |
| 3889 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3890 | clr_int_reg_46_acc_vio = 1'b0; |
| 3891 | // writes |
| 3892 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3893 | clr_int_reg_46_acc_vio = 1'b0; |
| 3894 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3895 | clr_int_reg_46_acc_vio = 1'b0; |
| 3896 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3897 | clr_int_reg_46_acc_vio = 1'b0; |
| 3898 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3899 | clr_int_reg_46_acc_vio = 1'b0; |
| 3900 | |
| 3901 | default: |
| 3902 | begin |
| 3903 | clr_int_reg_46_acc_vio = 1'b0; |
| 3904 | begin // axis tbcall_region |
| 3905 | // vlint flag_system_call off |
| 3906 | // synopsys translate_off |
| 3907 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_46"); `endif |
| 3908 | // synopsys translate_on |
| 3909 | // vlint flag_system_call on |
| 3910 | end // end of tbcall_region |
| 3911 | end |
| 3912 | endcase |
| 3913 | end |
| 3914 | //----- reg_acc_vio: clr_int_reg_47 |
| 3915 | reg clr_int_reg_47_acc_vio; |
| 3916 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3917 | clr_int_reg_47_addr_decoded or |
| 3918 | daemon_transaction_in_progress) |
| 3919 | begin |
| 3920 | if (daemon_transaction_in_progress | ~clr_int_reg_47_addr_decoded) |
| 3921 | clr_int_reg_47_acc_vio = 1'b0; |
| 3922 | else |
| 3923 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3924 | // reads |
| 3925 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3926 | clr_int_reg_47_acc_vio = 1'b0; |
| 3927 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3928 | clr_int_reg_47_acc_vio = 1'b0; |
| 3929 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3930 | clr_int_reg_47_acc_vio = 1'b0; |
| 3931 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3932 | clr_int_reg_47_acc_vio = 1'b0; |
| 3933 | // writes |
| 3934 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3935 | clr_int_reg_47_acc_vio = 1'b0; |
| 3936 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3937 | clr_int_reg_47_acc_vio = 1'b0; |
| 3938 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3939 | clr_int_reg_47_acc_vio = 1'b0; |
| 3940 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3941 | clr_int_reg_47_acc_vio = 1'b0; |
| 3942 | |
| 3943 | default: |
| 3944 | begin |
| 3945 | clr_int_reg_47_acc_vio = 1'b0; |
| 3946 | begin // axis tbcall_region |
| 3947 | // vlint flag_system_call off |
| 3948 | // synopsys translate_off |
| 3949 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_47"); `endif |
| 3950 | // synopsys translate_on |
| 3951 | // vlint flag_system_call on |
| 3952 | end // end of tbcall_region |
| 3953 | end |
| 3954 | endcase |
| 3955 | end |
| 3956 | //----- reg_acc_vio: clr_int_reg_48 |
| 3957 | reg clr_int_reg_48_acc_vio; |
| 3958 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 3959 | clr_int_reg_48_addr_decoded or |
| 3960 | daemon_transaction_in_progress) |
| 3961 | begin |
| 3962 | if (daemon_transaction_in_progress | ~clr_int_reg_48_addr_decoded) |
| 3963 | clr_int_reg_48_acc_vio = 1'b0; |
| 3964 | else |
| 3965 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 3966 | // reads |
| 3967 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 3968 | clr_int_reg_48_acc_vio = 1'b0; |
| 3969 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 3970 | clr_int_reg_48_acc_vio = 1'b0; |
| 3971 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 3972 | clr_int_reg_48_acc_vio = 1'b0; |
| 3973 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 3974 | clr_int_reg_48_acc_vio = 1'b0; |
| 3975 | // writes |
| 3976 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 3977 | clr_int_reg_48_acc_vio = 1'b0; |
| 3978 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 3979 | clr_int_reg_48_acc_vio = 1'b0; |
| 3980 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 3981 | clr_int_reg_48_acc_vio = 1'b0; |
| 3982 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 3983 | clr_int_reg_48_acc_vio = 1'b0; |
| 3984 | |
| 3985 | default: |
| 3986 | begin |
| 3987 | clr_int_reg_48_acc_vio = 1'b0; |
| 3988 | begin // axis tbcall_region |
| 3989 | // vlint flag_system_call off |
| 3990 | // synopsys translate_off |
| 3991 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_48"); `endif |
| 3992 | // synopsys translate_on |
| 3993 | // vlint flag_system_call on |
| 3994 | end // end of tbcall_region |
| 3995 | end |
| 3996 | endcase |
| 3997 | end |
| 3998 | //----- reg_acc_vio: clr_int_reg_49 |
| 3999 | reg clr_int_reg_49_acc_vio; |
| 4000 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4001 | clr_int_reg_49_addr_decoded or |
| 4002 | daemon_transaction_in_progress) |
| 4003 | begin |
| 4004 | if (daemon_transaction_in_progress | ~clr_int_reg_49_addr_decoded) |
| 4005 | clr_int_reg_49_acc_vio = 1'b0; |
| 4006 | else |
| 4007 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4008 | // reads |
| 4009 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4010 | clr_int_reg_49_acc_vio = 1'b0; |
| 4011 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4012 | clr_int_reg_49_acc_vio = 1'b0; |
| 4013 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4014 | clr_int_reg_49_acc_vio = 1'b0; |
| 4015 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4016 | clr_int_reg_49_acc_vio = 1'b0; |
| 4017 | // writes |
| 4018 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4019 | clr_int_reg_49_acc_vio = 1'b0; |
| 4020 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4021 | clr_int_reg_49_acc_vio = 1'b0; |
| 4022 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4023 | clr_int_reg_49_acc_vio = 1'b0; |
| 4024 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4025 | clr_int_reg_49_acc_vio = 1'b0; |
| 4026 | |
| 4027 | default: |
| 4028 | begin |
| 4029 | clr_int_reg_49_acc_vio = 1'b0; |
| 4030 | begin // axis tbcall_region |
| 4031 | // vlint flag_system_call off |
| 4032 | // synopsys translate_off |
| 4033 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_49"); `endif |
| 4034 | // synopsys translate_on |
| 4035 | // vlint flag_system_call on |
| 4036 | end // end of tbcall_region |
| 4037 | end |
| 4038 | endcase |
| 4039 | end |
| 4040 | //----- reg_acc_vio: clr_int_reg_50 |
| 4041 | reg clr_int_reg_50_acc_vio; |
| 4042 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4043 | clr_int_reg_50_addr_decoded or |
| 4044 | daemon_transaction_in_progress) |
| 4045 | begin |
| 4046 | if (daemon_transaction_in_progress | ~clr_int_reg_50_addr_decoded) |
| 4047 | clr_int_reg_50_acc_vio = 1'b0; |
| 4048 | else |
| 4049 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4050 | // reads |
| 4051 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4052 | clr_int_reg_50_acc_vio = 1'b0; |
| 4053 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4054 | clr_int_reg_50_acc_vio = 1'b0; |
| 4055 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4056 | clr_int_reg_50_acc_vio = 1'b0; |
| 4057 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4058 | clr_int_reg_50_acc_vio = 1'b0; |
| 4059 | // writes |
| 4060 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4061 | clr_int_reg_50_acc_vio = 1'b0; |
| 4062 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4063 | clr_int_reg_50_acc_vio = 1'b0; |
| 4064 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4065 | clr_int_reg_50_acc_vio = 1'b0; |
| 4066 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4067 | clr_int_reg_50_acc_vio = 1'b0; |
| 4068 | |
| 4069 | default: |
| 4070 | begin |
| 4071 | clr_int_reg_50_acc_vio = 1'b0; |
| 4072 | begin // axis tbcall_region |
| 4073 | // vlint flag_system_call off |
| 4074 | // synopsys translate_off |
| 4075 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_50"); `endif |
| 4076 | // synopsys translate_on |
| 4077 | // vlint flag_system_call on |
| 4078 | end // end of tbcall_region |
| 4079 | end |
| 4080 | endcase |
| 4081 | end |
| 4082 | //----- reg_acc_vio: clr_int_reg_51 |
| 4083 | reg clr_int_reg_51_acc_vio; |
| 4084 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4085 | clr_int_reg_51_addr_decoded or |
| 4086 | daemon_transaction_in_progress) |
| 4087 | begin |
| 4088 | if (daemon_transaction_in_progress | ~clr_int_reg_51_addr_decoded) |
| 4089 | clr_int_reg_51_acc_vio = 1'b0; |
| 4090 | else |
| 4091 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4092 | // reads |
| 4093 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4094 | clr_int_reg_51_acc_vio = 1'b0; |
| 4095 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4096 | clr_int_reg_51_acc_vio = 1'b0; |
| 4097 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4098 | clr_int_reg_51_acc_vio = 1'b0; |
| 4099 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4100 | clr_int_reg_51_acc_vio = 1'b0; |
| 4101 | // writes |
| 4102 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4103 | clr_int_reg_51_acc_vio = 1'b0; |
| 4104 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4105 | clr_int_reg_51_acc_vio = 1'b0; |
| 4106 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4107 | clr_int_reg_51_acc_vio = 1'b0; |
| 4108 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4109 | clr_int_reg_51_acc_vio = 1'b0; |
| 4110 | |
| 4111 | default: |
| 4112 | begin |
| 4113 | clr_int_reg_51_acc_vio = 1'b0; |
| 4114 | begin // axis tbcall_region |
| 4115 | // vlint flag_system_call off |
| 4116 | // synopsys translate_off |
| 4117 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_51"); `endif |
| 4118 | // synopsys translate_on |
| 4119 | // vlint flag_system_call on |
| 4120 | end // end of tbcall_region |
| 4121 | end |
| 4122 | endcase |
| 4123 | end |
| 4124 | //----- reg_acc_vio: clr_int_reg_52 |
| 4125 | reg clr_int_reg_52_acc_vio; |
| 4126 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4127 | clr_int_reg_52_addr_decoded or |
| 4128 | daemon_transaction_in_progress) |
| 4129 | begin |
| 4130 | if (daemon_transaction_in_progress | ~clr_int_reg_52_addr_decoded) |
| 4131 | clr_int_reg_52_acc_vio = 1'b0; |
| 4132 | else |
| 4133 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4134 | // reads |
| 4135 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4136 | clr_int_reg_52_acc_vio = 1'b0; |
| 4137 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4138 | clr_int_reg_52_acc_vio = 1'b0; |
| 4139 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4140 | clr_int_reg_52_acc_vio = 1'b0; |
| 4141 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4142 | clr_int_reg_52_acc_vio = 1'b0; |
| 4143 | // writes |
| 4144 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4145 | clr_int_reg_52_acc_vio = 1'b0; |
| 4146 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4147 | clr_int_reg_52_acc_vio = 1'b0; |
| 4148 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4149 | clr_int_reg_52_acc_vio = 1'b0; |
| 4150 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4151 | clr_int_reg_52_acc_vio = 1'b0; |
| 4152 | |
| 4153 | default: |
| 4154 | begin |
| 4155 | clr_int_reg_52_acc_vio = 1'b0; |
| 4156 | begin // axis tbcall_region |
| 4157 | // vlint flag_system_call off |
| 4158 | // synopsys translate_off |
| 4159 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_52"); `endif |
| 4160 | // synopsys translate_on |
| 4161 | // vlint flag_system_call on |
| 4162 | end // end of tbcall_region |
| 4163 | end |
| 4164 | endcase |
| 4165 | end |
| 4166 | //----- reg_acc_vio: clr_int_reg_53 |
| 4167 | reg clr_int_reg_53_acc_vio; |
| 4168 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4169 | clr_int_reg_53_addr_decoded or |
| 4170 | daemon_transaction_in_progress) |
| 4171 | begin |
| 4172 | if (daemon_transaction_in_progress | ~clr_int_reg_53_addr_decoded) |
| 4173 | clr_int_reg_53_acc_vio = 1'b0; |
| 4174 | else |
| 4175 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4176 | // reads |
| 4177 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4178 | clr_int_reg_53_acc_vio = 1'b0; |
| 4179 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4180 | clr_int_reg_53_acc_vio = 1'b0; |
| 4181 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4182 | clr_int_reg_53_acc_vio = 1'b0; |
| 4183 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4184 | clr_int_reg_53_acc_vio = 1'b0; |
| 4185 | // writes |
| 4186 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4187 | clr_int_reg_53_acc_vio = 1'b0; |
| 4188 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4189 | clr_int_reg_53_acc_vio = 1'b0; |
| 4190 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4191 | clr_int_reg_53_acc_vio = 1'b0; |
| 4192 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4193 | clr_int_reg_53_acc_vio = 1'b0; |
| 4194 | |
| 4195 | default: |
| 4196 | begin |
| 4197 | clr_int_reg_53_acc_vio = 1'b0; |
| 4198 | begin // axis tbcall_region |
| 4199 | // vlint flag_system_call off |
| 4200 | // synopsys translate_off |
| 4201 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_53"); `endif |
| 4202 | // synopsys translate_on |
| 4203 | // vlint flag_system_call on |
| 4204 | end // end of tbcall_region |
| 4205 | end |
| 4206 | endcase |
| 4207 | end |
| 4208 | //----- reg_acc_vio: clr_int_reg_54 |
| 4209 | reg clr_int_reg_54_acc_vio; |
| 4210 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4211 | clr_int_reg_54_addr_decoded or |
| 4212 | daemon_transaction_in_progress) |
| 4213 | begin |
| 4214 | if (daemon_transaction_in_progress | ~clr_int_reg_54_addr_decoded) |
| 4215 | clr_int_reg_54_acc_vio = 1'b0; |
| 4216 | else |
| 4217 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4218 | // reads |
| 4219 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4220 | clr_int_reg_54_acc_vio = 1'b0; |
| 4221 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4222 | clr_int_reg_54_acc_vio = 1'b0; |
| 4223 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4224 | clr_int_reg_54_acc_vio = 1'b0; |
| 4225 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4226 | clr_int_reg_54_acc_vio = 1'b0; |
| 4227 | // writes |
| 4228 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4229 | clr_int_reg_54_acc_vio = 1'b0; |
| 4230 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4231 | clr_int_reg_54_acc_vio = 1'b0; |
| 4232 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4233 | clr_int_reg_54_acc_vio = 1'b0; |
| 4234 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4235 | clr_int_reg_54_acc_vio = 1'b0; |
| 4236 | |
| 4237 | default: |
| 4238 | begin |
| 4239 | clr_int_reg_54_acc_vio = 1'b0; |
| 4240 | begin // axis tbcall_region |
| 4241 | // vlint flag_system_call off |
| 4242 | // synopsys translate_off |
| 4243 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_54"); `endif |
| 4244 | // synopsys translate_on |
| 4245 | // vlint flag_system_call on |
| 4246 | end // end of tbcall_region |
| 4247 | end |
| 4248 | endcase |
| 4249 | end |
| 4250 | //----- reg_acc_vio: clr_int_reg_55 |
| 4251 | reg clr_int_reg_55_acc_vio; |
| 4252 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4253 | clr_int_reg_55_addr_decoded or |
| 4254 | daemon_transaction_in_progress) |
| 4255 | begin |
| 4256 | if (daemon_transaction_in_progress | ~clr_int_reg_55_addr_decoded) |
| 4257 | clr_int_reg_55_acc_vio = 1'b0; |
| 4258 | else |
| 4259 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4260 | // reads |
| 4261 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4262 | clr_int_reg_55_acc_vio = 1'b0; |
| 4263 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4264 | clr_int_reg_55_acc_vio = 1'b0; |
| 4265 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4266 | clr_int_reg_55_acc_vio = 1'b0; |
| 4267 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4268 | clr_int_reg_55_acc_vio = 1'b0; |
| 4269 | // writes |
| 4270 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4271 | clr_int_reg_55_acc_vio = 1'b0; |
| 4272 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4273 | clr_int_reg_55_acc_vio = 1'b0; |
| 4274 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4275 | clr_int_reg_55_acc_vio = 1'b0; |
| 4276 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4277 | clr_int_reg_55_acc_vio = 1'b0; |
| 4278 | |
| 4279 | default: |
| 4280 | begin |
| 4281 | clr_int_reg_55_acc_vio = 1'b0; |
| 4282 | begin // axis tbcall_region |
| 4283 | // vlint flag_system_call off |
| 4284 | // synopsys translate_off |
| 4285 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_55"); `endif |
| 4286 | // synopsys translate_on |
| 4287 | // vlint flag_system_call on |
| 4288 | end // end of tbcall_region |
| 4289 | end |
| 4290 | endcase |
| 4291 | end |
| 4292 | //----- reg_acc_vio: clr_int_reg_56 |
| 4293 | reg clr_int_reg_56_acc_vio; |
| 4294 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4295 | clr_int_reg_56_addr_decoded or |
| 4296 | daemon_transaction_in_progress) |
| 4297 | begin |
| 4298 | if (daemon_transaction_in_progress | ~clr_int_reg_56_addr_decoded) |
| 4299 | clr_int_reg_56_acc_vio = 1'b0; |
| 4300 | else |
| 4301 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4302 | // reads |
| 4303 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4304 | clr_int_reg_56_acc_vio = 1'b0; |
| 4305 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4306 | clr_int_reg_56_acc_vio = 1'b0; |
| 4307 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4308 | clr_int_reg_56_acc_vio = 1'b0; |
| 4309 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4310 | clr_int_reg_56_acc_vio = 1'b0; |
| 4311 | // writes |
| 4312 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4313 | clr_int_reg_56_acc_vio = 1'b0; |
| 4314 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4315 | clr_int_reg_56_acc_vio = 1'b0; |
| 4316 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4317 | clr_int_reg_56_acc_vio = 1'b0; |
| 4318 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4319 | clr_int_reg_56_acc_vio = 1'b0; |
| 4320 | |
| 4321 | default: |
| 4322 | begin |
| 4323 | clr_int_reg_56_acc_vio = 1'b0; |
| 4324 | begin // axis tbcall_region |
| 4325 | // vlint flag_system_call off |
| 4326 | // synopsys translate_off |
| 4327 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_56"); `endif |
| 4328 | // synopsys translate_on |
| 4329 | // vlint flag_system_call on |
| 4330 | end // end of tbcall_region |
| 4331 | end |
| 4332 | endcase |
| 4333 | end |
| 4334 | //----- reg_acc_vio: clr_int_reg_57 |
| 4335 | reg clr_int_reg_57_acc_vio; |
| 4336 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4337 | clr_int_reg_57_addr_decoded or |
| 4338 | daemon_transaction_in_progress) |
| 4339 | begin |
| 4340 | if (daemon_transaction_in_progress | ~clr_int_reg_57_addr_decoded) |
| 4341 | clr_int_reg_57_acc_vio = 1'b0; |
| 4342 | else |
| 4343 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4344 | // reads |
| 4345 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4346 | clr_int_reg_57_acc_vio = 1'b0; |
| 4347 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4348 | clr_int_reg_57_acc_vio = 1'b0; |
| 4349 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4350 | clr_int_reg_57_acc_vio = 1'b0; |
| 4351 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4352 | clr_int_reg_57_acc_vio = 1'b0; |
| 4353 | // writes |
| 4354 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4355 | clr_int_reg_57_acc_vio = 1'b0; |
| 4356 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4357 | clr_int_reg_57_acc_vio = 1'b0; |
| 4358 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4359 | clr_int_reg_57_acc_vio = 1'b0; |
| 4360 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4361 | clr_int_reg_57_acc_vio = 1'b0; |
| 4362 | |
| 4363 | default: |
| 4364 | begin |
| 4365 | clr_int_reg_57_acc_vio = 1'b0; |
| 4366 | begin // axis tbcall_region |
| 4367 | // vlint flag_system_call off |
| 4368 | // synopsys translate_off |
| 4369 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_57"); `endif |
| 4370 | // synopsys translate_on |
| 4371 | // vlint flag_system_call on |
| 4372 | end // end of tbcall_region |
| 4373 | end |
| 4374 | endcase |
| 4375 | end |
| 4376 | //----- reg_acc_vio: clr_int_reg_58 |
| 4377 | reg clr_int_reg_58_acc_vio; |
| 4378 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4379 | clr_int_reg_58_addr_decoded or |
| 4380 | daemon_transaction_in_progress) |
| 4381 | begin |
| 4382 | if (daemon_transaction_in_progress | ~clr_int_reg_58_addr_decoded) |
| 4383 | clr_int_reg_58_acc_vio = 1'b0; |
| 4384 | else |
| 4385 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4386 | // reads |
| 4387 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4388 | clr_int_reg_58_acc_vio = 1'b0; |
| 4389 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4390 | clr_int_reg_58_acc_vio = 1'b0; |
| 4391 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4392 | clr_int_reg_58_acc_vio = 1'b0; |
| 4393 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4394 | clr_int_reg_58_acc_vio = 1'b0; |
| 4395 | // writes |
| 4396 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4397 | clr_int_reg_58_acc_vio = 1'b0; |
| 4398 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4399 | clr_int_reg_58_acc_vio = 1'b0; |
| 4400 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4401 | clr_int_reg_58_acc_vio = 1'b0; |
| 4402 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4403 | clr_int_reg_58_acc_vio = 1'b0; |
| 4404 | |
| 4405 | default: |
| 4406 | begin |
| 4407 | clr_int_reg_58_acc_vio = 1'b0; |
| 4408 | begin // axis tbcall_region |
| 4409 | // vlint flag_system_call off |
| 4410 | // synopsys translate_off |
| 4411 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_58"); `endif |
| 4412 | // synopsys translate_on |
| 4413 | // vlint flag_system_call on |
| 4414 | end // end of tbcall_region |
| 4415 | end |
| 4416 | endcase |
| 4417 | end |
| 4418 | //----- reg_acc_vio: clr_int_reg_59 |
| 4419 | reg clr_int_reg_59_acc_vio; |
| 4420 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4421 | clr_int_reg_59_addr_decoded or |
| 4422 | daemon_transaction_in_progress) |
| 4423 | begin |
| 4424 | if (daemon_transaction_in_progress | ~clr_int_reg_59_addr_decoded) |
| 4425 | clr_int_reg_59_acc_vio = 1'b0; |
| 4426 | else |
| 4427 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4428 | // reads |
| 4429 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4430 | clr_int_reg_59_acc_vio = 1'b0; |
| 4431 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4432 | clr_int_reg_59_acc_vio = 1'b0; |
| 4433 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4434 | clr_int_reg_59_acc_vio = 1'b0; |
| 4435 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4436 | clr_int_reg_59_acc_vio = 1'b0; |
| 4437 | // writes |
| 4438 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4439 | clr_int_reg_59_acc_vio = 1'b0; |
| 4440 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4441 | clr_int_reg_59_acc_vio = 1'b0; |
| 4442 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4443 | clr_int_reg_59_acc_vio = 1'b0; |
| 4444 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4445 | clr_int_reg_59_acc_vio = 1'b0; |
| 4446 | |
| 4447 | default: |
| 4448 | begin |
| 4449 | clr_int_reg_59_acc_vio = 1'b0; |
| 4450 | begin // axis tbcall_region |
| 4451 | // vlint flag_system_call off |
| 4452 | // synopsys translate_off |
| 4453 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_59"); `endif |
| 4454 | // synopsys translate_on |
| 4455 | // vlint flag_system_call on |
| 4456 | end // end of tbcall_region |
| 4457 | end |
| 4458 | endcase |
| 4459 | end |
| 4460 | //----- reg_acc_vio: clr_int_reg_62 |
| 4461 | reg clr_int_reg_62_acc_vio; |
| 4462 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4463 | clr_int_reg_62_addr_decoded or |
| 4464 | daemon_transaction_in_progress) |
| 4465 | begin |
| 4466 | if (daemon_transaction_in_progress | ~clr_int_reg_62_addr_decoded) |
| 4467 | clr_int_reg_62_acc_vio = 1'b0; |
| 4468 | else |
| 4469 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4470 | // reads |
| 4471 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4472 | clr_int_reg_62_acc_vio = 1'b0; |
| 4473 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4474 | clr_int_reg_62_acc_vio = 1'b0; |
| 4475 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4476 | clr_int_reg_62_acc_vio = 1'b0; |
| 4477 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4478 | clr_int_reg_62_acc_vio = 1'b0; |
| 4479 | // writes |
| 4480 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4481 | clr_int_reg_62_acc_vio = 1'b0; |
| 4482 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4483 | clr_int_reg_62_acc_vio = 1'b0; |
| 4484 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4485 | clr_int_reg_62_acc_vio = 1'b0; |
| 4486 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4487 | clr_int_reg_62_acc_vio = 1'b0; |
| 4488 | |
| 4489 | default: |
| 4490 | begin |
| 4491 | clr_int_reg_62_acc_vio = 1'b0; |
| 4492 | begin // axis tbcall_region |
| 4493 | // vlint flag_system_call off |
| 4494 | // synopsys translate_off |
| 4495 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_62"); `endif |
| 4496 | // synopsys translate_on |
| 4497 | // vlint flag_system_call on |
| 4498 | end // end of tbcall_region |
| 4499 | end |
| 4500 | endcase |
| 4501 | end |
| 4502 | //----- reg_acc_vio: clr_int_reg_63 |
| 4503 | reg clr_int_reg_63_acc_vio; |
| 4504 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4505 | clr_int_reg_63_addr_decoded or |
| 4506 | daemon_transaction_in_progress) |
| 4507 | begin |
| 4508 | if (daemon_transaction_in_progress | ~clr_int_reg_63_addr_decoded) |
| 4509 | clr_int_reg_63_acc_vio = 1'b0; |
| 4510 | else |
| 4511 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4512 | // reads |
| 4513 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4514 | clr_int_reg_63_acc_vio = 1'b0; |
| 4515 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4516 | clr_int_reg_63_acc_vio = 1'b0; |
| 4517 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4518 | clr_int_reg_63_acc_vio = 1'b0; |
| 4519 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4520 | clr_int_reg_63_acc_vio = 1'b0; |
| 4521 | // writes |
| 4522 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4523 | clr_int_reg_63_acc_vio = 1'b0; |
| 4524 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4525 | clr_int_reg_63_acc_vio = 1'b0; |
| 4526 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4527 | clr_int_reg_63_acc_vio = 1'b0; |
| 4528 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4529 | clr_int_reg_63_acc_vio = 1'b0; |
| 4530 | |
| 4531 | default: |
| 4532 | begin |
| 4533 | clr_int_reg_63_acc_vio = 1'b0; |
| 4534 | begin // axis tbcall_region |
| 4535 | // vlint flag_system_call off |
| 4536 | // synopsys translate_off |
| 4537 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_clr_int_reg_63"); `endif |
| 4538 | // synopsys translate_on |
| 4539 | // vlint flag_system_call on |
| 4540 | end // end of tbcall_region |
| 4541 | end |
| 4542 | endcase |
| 4543 | end |
| 4544 | //----- reg_acc_vio: interrupt_retry_timer |
| 4545 | reg interrupt_retry_timer_acc_vio; |
| 4546 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4547 | interrupt_retry_timer_addr_decoded or |
| 4548 | daemon_transaction_in_progress) |
| 4549 | begin |
| 4550 | if (daemon_transaction_in_progress | ~interrupt_retry_timer_addr_decoded) |
| 4551 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4552 | else |
| 4553 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4554 | // reads |
| 4555 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4556 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4557 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4558 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4559 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4560 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4561 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4562 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4563 | // writes |
| 4564 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4565 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4566 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4567 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4568 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4569 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4570 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4571 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4572 | |
| 4573 | default: |
| 4574 | begin |
| 4575 | interrupt_retry_timer_acc_vio = 1'b0; |
| 4576 | begin // axis tbcall_region |
| 4577 | // vlint flag_system_call off |
| 4578 | // synopsys translate_off |
| 4579 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_retry_timer"); `endif |
| 4580 | // synopsys translate_on |
| 4581 | // vlint flag_system_call on |
| 4582 | end // end of tbcall_region |
| 4583 | end |
| 4584 | endcase |
| 4585 | end |
| 4586 | //----- reg_acc_vio: interrupt_state_status_1 |
| 4587 | reg interrupt_state_status_1_acc_vio; |
| 4588 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4589 | interrupt_state_status_1_addr_decoded or |
| 4590 | daemon_transaction_in_progress) |
| 4591 | begin |
| 4592 | if (daemon_transaction_in_progress | ~interrupt_state_status_1_addr_decoded) |
| 4593 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4594 | else |
| 4595 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4596 | // reads |
| 4597 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4598 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4599 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4600 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4601 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4602 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4603 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4604 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4605 | // writes |
| 4606 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4607 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4608 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4609 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4610 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4611 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4612 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4613 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4614 | |
| 4615 | default: |
| 4616 | begin |
| 4617 | interrupt_state_status_1_acc_vio = 1'b0; |
| 4618 | begin // axis tbcall_region |
| 4619 | // vlint flag_system_call off |
| 4620 | // synopsys translate_off |
| 4621 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_state_status_1"); `endif |
| 4622 | // synopsys translate_on |
| 4623 | // vlint flag_system_call on |
| 4624 | end // end of tbcall_region |
| 4625 | end |
| 4626 | endcase |
| 4627 | end |
| 4628 | //----- reg_acc_vio: interrupt_state_status_2 |
| 4629 | reg interrupt_state_status_2_acc_vio; |
| 4630 | always @(csrbus_src_bus or daemon_csrbus_wr or |
| 4631 | interrupt_state_status_2_addr_decoded or |
| 4632 | daemon_transaction_in_progress) |
| 4633 | begin |
| 4634 | if (daemon_transaction_in_progress | ~interrupt_state_status_2_addr_decoded) |
| 4635 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4636 | else |
| 4637 | case ({csrbus_src_bus, daemon_csrbus_wr}) |
| 4638 | // reads |
| 4639 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: |
| 4640 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4641 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: |
| 4642 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4643 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: |
| 4644 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4645 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: |
| 4646 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4647 | // writes |
| 4648 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: |
| 4649 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4650 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: |
| 4651 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4652 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: |
| 4653 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4654 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: |
| 4655 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4656 | |
| 4657 | default: |
| 4658 | begin |
| 4659 | interrupt_state_status_2_acc_vio = 1'b0; |
| 4660 | begin // axis tbcall_region |
| 4661 | // vlint flag_system_call off |
| 4662 | // synopsys translate_off |
| 4663 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_iss_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_iss_csr_a_interrupt_state_status_2"); `endif |
| 4664 | // synopsys translate_on |
| 4665 | // vlint flag_system_call on |
| 4666 | end // end of tbcall_region |
| 4667 | end |
| 4668 | endcase |
| 4669 | end |
| 4670 | |
| 4671 | //==================================================================== |
| 4672 | // Status: daemon_csrbus_mapped / csrbus_acc_vio |
| 4673 | //==================================================================== |
| 4674 | //----- OUTPUT: daemon_csrbus_mapped |
| 4675 | assign daemon_csrbus_mapped = clocked_valid_pulse & |
| 4676 | ( |
| 4677 | interrupt_mapping_20_addr_decoded | |
| 4678 | interrupt_mapping_21_addr_decoded | |
| 4679 | interrupt_mapping_22_addr_decoded | |
| 4680 | interrupt_mapping_23_addr_decoded | |
| 4681 | interrupt_mapping_24_addr_decoded | |
| 4682 | interrupt_mapping_25_addr_decoded | |
| 4683 | interrupt_mapping_26_addr_decoded | |
| 4684 | interrupt_mapping_27_addr_decoded | |
| 4685 | interrupt_mapping_28_addr_decoded | |
| 4686 | interrupt_mapping_29_addr_decoded | |
| 4687 | interrupt_mapping_30_addr_decoded | |
| 4688 | interrupt_mapping_31_addr_decoded | |
| 4689 | interrupt_mapping_32_addr_decoded | |
| 4690 | interrupt_mapping_33_addr_decoded | |
| 4691 | interrupt_mapping_34_addr_decoded | |
| 4692 | interrupt_mapping_35_addr_decoded | |
| 4693 | interrupt_mapping_36_addr_decoded | |
| 4694 | interrupt_mapping_37_addr_decoded | |
| 4695 | interrupt_mapping_38_addr_decoded | |
| 4696 | interrupt_mapping_39_addr_decoded | |
| 4697 | interrupt_mapping_40_addr_decoded | |
| 4698 | interrupt_mapping_41_addr_decoded | |
| 4699 | interrupt_mapping_42_addr_decoded | |
| 4700 | interrupt_mapping_43_addr_decoded | |
| 4701 | interrupt_mapping_44_addr_decoded | |
| 4702 | interrupt_mapping_45_addr_decoded | |
| 4703 | interrupt_mapping_46_addr_decoded | |
| 4704 | interrupt_mapping_47_addr_decoded | |
| 4705 | interrupt_mapping_48_addr_decoded | |
| 4706 | interrupt_mapping_49_addr_decoded | |
| 4707 | interrupt_mapping_50_addr_decoded | |
| 4708 | interrupt_mapping_51_addr_decoded | |
| 4709 | interrupt_mapping_52_addr_decoded | |
| 4710 | interrupt_mapping_53_addr_decoded | |
| 4711 | interrupt_mapping_54_addr_decoded | |
| 4712 | interrupt_mapping_55_addr_decoded | |
| 4713 | interrupt_mapping_56_addr_decoded | |
| 4714 | interrupt_mapping_57_addr_decoded | |
| 4715 | interrupt_mapping_58_addr_decoded | |
| 4716 | interrupt_mapping_59_addr_decoded | |
| 4717 | interrupt_mapping_62_addr_decoded | |
| 4718 | interrupt_mapping_63_addr_decoded | |
| 4719 | clr_int_reg_20_addr_decoded | |
| 4720 | clr_int_reg_21_addr_decoded | |
| 4721 | clr_int_reg_22_addr_decoded | |
| 4722 | clr_int_reg_23_addr_decoded | |
| 4723 | clr_int_reg_24_addr_decoded | |
| 4724 | clr_int_reg_25_addr_decoded | |
| 4725 | clr_int_reg_26_addr_decoded | |
| 4726 | clr_int_reg_27_addr_decoded | |
| 4727 | clr_int_reg_28_addr_decoded | |
| 4728 | clr_int_reg_29_addr_decoded | |
| 4729 | clr_int_reg_30_addr_decoded | |
| 4730 | clr_int_reg_31_addr_decoded | |
| 4731 | clr_int_reg_32_addr_decoded | |
| 4732 | clr_int_reg_33_addr_decoded | |
| 4733 | clr_int_reg_34_addr_decoded | |
| 4734 | clr_int_reg_35_addr_decoded | |
| 4735 | clr_int_reg_36_addr_decoded | |
| 4736 | clr_int_reg_37_addr_decoded | |
| 4737 | clr_int_reg_38_addr_decoded | |
| 4738 | clr_int_reg_39_addr_decoded | |
| 4739 | clr_int_reg_40_addr_decoded | |
| 4740 | clr_int_reg_41_addr_decoded | |
| 4741 | clr_int_reg_42_addr_decoded | |
| 4742 | clr_int_reg_43_addr_decoded | |
| 4743 | clr_int_reg_44_addr_decoded | |
| 4744 | clr_int_reg_45_addr_decoded | |
| 4745 | clr_int_reg_46_addr_decoded | |
| 4746 | clr_int_reg_47_addr_decoded | |
| 4747 | clr_int_reg_48_addr_decoded | |
| 4748 | clr_int_reg_49_addr_decoded | |
| 4749 | clr_int_reg_50_addr_decoded | |
| 4750 | clr_int_reg_51_addr_decoded | |
| 4751 | clr_int_reg_52_addr_decoded | |
| 4752 | clr_int_reg_53_addr_decoded | |
| 4753 | clr_int_reg_54_addr_decoded | |
| 4754 | clr_int_reg_55_addr_decoded | |
| 4755 | clr_int_reg_56_addr_decoded | |
| 4756 | clr_int_reg_57_addr_decoded | |
| 4757 | clr_int_reg_58_addr_decoded | |
| 4758 | clr_int_reg_59_addr_decoded | |
| 4759 | clr_int_reg_62_addr_decoded | |
| 4760 | clr_int_reg_63_addr_decoded | |
| 4761 | interrupt_retry_timer_addr_decoded | |
| 4762 | interrupt_state_status_1_addr_decoded | |
| 4763 | interrupt_state_status_2_addr_decoded |
| 4764 | ); |
| 4765 | |
| 4766 | |
| 4767 | // daemon_csrbus_mapped gets asserted after fixed number of cycles |
| 4768 | // after daemon_csrbus_valid become high |
| 4769 | /* 0in assert_together -name mapped_after_valid |
| 4770 | -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1)) |
| 4771 | -follower $0in_rising_edge(daemon_csrbus_mapped) |
| 4772 | -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid") |
| 4773 | -module dmu_imu_iss_addr_decode |
| 4774 | -clock clk |
| 4775 | -active $0in_rising_edge(daemon_csrbus_mapped) |
| 4776 | */ |
| 4777 | |
| 4778 | // daemon_csrbus_mapped is a pulse |
| 4779 | /* 0in assert_timer -name daemon_csrbus_mapped_pulse |
| 4780 | -var daemon_csrbus_mapped -max 1 |
| 4781 | -message "daemon_csrbus_mapped pulse length is not 1" |
| 4782 | -module dmu_imu_iss_addr_decode |
| 4783 | -clock clk |
| 4784 | */ |
| 4785 | //----- OUTPUT: csrbus_acc_vio |
| 4786 | assign csrbus_acc_vio = clocked_valid_pulse & |
| 4787 | interrupt_mapping_20_acc_vio | |
| 4788 | interrupt_mapping_21_acc_vio | |
| 4789 | interrupt_mapping_22_acc_vio | |
| 4790 | interrupt_mapping_23_acc_vio | |
| 4791 | interrupt_mapping_24_acc_vio | |
| 4792 | interrupt_mapping_25_acc_vio | |
| 4793 | interrupt_mapping_26_acc_vio | |
| 4794 | interrupt_mapping_27_acc_vio | |
| 4795 | interrupt_mapping_28_acc_vio | |
| 4796 | interrupt_mapping_29_acc_vio | |
| 4797 | interrupt_mapping_30_acc_vio | |
| 4798 | interrupt_mapping_31_acc_vio | |
| 4799 | interrupt_mapping_32_acc_vio | |
| 4800 | interrupt_mapping_33_acc_vio | |
| 4801 | interrupt_mapping_34_acc_vio | |
| 4802 | interrupt_mapping_35_acc_vio | |
| 4803 | interrupt_mapping_36_acc_vio | |
| 4804 | interrupt_mapping_37_acc_vio | |
| 4805 | interrupt_mapping_38_acc_vio | |
| 4806 | interrupt_mapping_39_acc_vio | |
| 4807 | interrupt_mapping_40_acc_vio | |
| 4808 | interrupt_mapping_41_acc_vio | |
| 4809 | interrupt_mapping_42_acc_vio | |
| 4810 | interrupt_mapping_43_acc_vio | |
| 4811 | interrupt_mapping_44_acc_vio | |
| 4812 | interrupt_mapping_45_acc_vio | |
| 4813 | interrupt_mapping_46_acc_vio | |
| 4814 | interrupt_mapping_47_acc_vio | |
| 4815 | interrupt_mapping_48_acc_vio | |
| 4816 | interrupt_mapping_49_acc_vio | |
| 4817 | interrupt_mapping_50_acc_vio | |
| 4818 | interrupt_mapping_51_acc_vio | |
| 4819 | interrupt_mapping_52_acc_vio | |
| 4820 | interrupt_mapping_53_acc_vio | |
| 4821 | interrupt_mapping_54_acc_vio | |
| 4822 | interrupt_mapping_55_acc_vio | |
| 4823 | interrupt_mapping_56_acc_vio | |
| 4824 | interrupt_mapping_57_acc_vio | |
| 4825 | interrupt_mapping_58_acc_vio | |
| 4826 | interrupt_mapping_59_acc_vio | |
| 4827 | interrupt_mapping_62_acc_vio | |
| 4828 | interrupt_mapping_63_acc_vio | |
| 4829 | clr_int_reg_20_acc_vio | |
| 4830 | clr_int_reg_21_acc_vio | |
| 4831 | clr_int_reg_22_acc_vio | |
| 4832 | clr_int_reg_23_acc_vio | |
| 4833 | clr_int_reg_24_acc_vio | |
| 4834 | clr_int_reg_25_acc_vio | |
| 4835 | clr_int_reg_26_acc_vio | |
| 4836 | clr_int_reg_27_acc_vio | |
| 4837 | clr_int_reg_28_acc_vio | |
| 4838 | clr_int_reg_29_acc_vio | |
| 4839 | clr_int_reg_30_acc_vio | |
| 4840 | clr_int_reg_31_acc_vio | |
| 4841 | clr_int_reg_32_acc_vio | |
| 4842 | clr_int_reg_33_acc_vio | |
| 4843 | clr_int_reg_34_acc_vio | |
| 4844 | clr_int_reg_35_acc_vio | |
| 4845 | clr_int_reg_36_acc_vio | |
| 4846 | clr_int_reg_37_acc_vio | |
| 4847 | clr_int_reg_38_acc_vio | |
| 4848 | clr_int_reg_39_acc_vio | |
| 4849 | clr_int_reg_40_acc_vio | |
| 4850 | clr_int_reg_41_acc_vio | |
| 4851 | clr_int_reg_42_acc_vio | |
| 4852 | clr_int_reg_43_acc_vio | |
| 4853 | clr_int_reg_44_acc_vio | |
| 4854 | clr_int_reg_45_acc_vio | |
| 4855 | clr_int_reg_46_acc_vio | |
| 4856 | clr_int_reg_47_acc_vio | |
| 4857 | clr_int_reg_48_acc_vio | |
| 4858 | clr_int_reg_49_acc_vio | |
| 4859 | clr_int_reg_50_acc_vio | |
| 4860 | clr_int_reg_51_acc_vio | |
| 4861 | clr_int_reg_52_acc_vio | |
| 4862 | clr_int_reg_53_acc_vio | |
| 4863 | clr_int_reg_54_acc_vio | |
| 4864 | clr_int_reg_55_acc_vio | |
| 4865 | clr_int_reg_56_acc_vio | |
| 4866 | clr_int_reg_57_acc_vio | |
| 4867 | clr_int_reg_58_acc_vio | |
| 4868 | clr_int_reg_59_acc_vio | |
| 4869 | clr_int_reg_62_acc_vio | |
| 4870 | clr_int_reg_63_acc_vio | |
| 4871 | interrupt_retry_timer_acc_vio | |
| 4872 | interrupt_state_status_1_acc_vio | |
| 4873 | interrupt_state_status_2_acc_vio; |
| 4874 | |
| 4875 | //==================================================================== |
| 4876 | // Select |
| 4877 | //==================================================================== |
| 4878 | always @(posedge clk) |
| 4879 | begin |
| 4880 | if(~rst_l) |
| 4881 | begin |
| 4882 | interrupt_mapping_20_select_pulse <= 1'b0; |
| 4883 | interrupt_mapping_21_select_pulse <= 1'b0; |
| 4884 | interrupt_mapping_22_select_pulse <= 1'b0; |
| 4885 | interrupt_mapping_23_select_pulse <= 1'b0; |
| 4886 | interrupt_mapping_24_select_pulse <= 1'b0; |
| 4887 | interrupt_mapping_25_select_pulse <= 1'b0; |
| 4888 | interrupt_mapping_26_select_pulse <= 1'b0; |
| 4889 | interrupt_mapping_27_select_pulse <= 1'b0; |
| 4890 | interrupt_mapping_28_select_pulse <= 1'b0; |
| 4891 | interrupt_mapping_29_select_pulse <= 1'b0; |
| 4892 | interrupt_mapping_30_select_pulse <= 1'b0; |
| 4893 | interrupt_mapping_31_select_pulse <= 1'b0; |
| 4894 | interrupt_mapping_32_select_pulse <= 1'b0; |
| 4895 | interrupt_mapping_33_select_pulse <= 1'b0; |
| 4896 | interrupt_mapping_34_select_pulse <= 1'b0; |
| 4897 | interrupt_mapping_35_select_pulse <= 1'b0; |
| 4898 | interrupt_mapping_36_select_pulse <= 1'b0; |
| 4899 | interrupt_mapping_37_select_pulse <= 1'b0; |
| 4900 | interrupt_mapping_38_select_pulse <= 1'b0; |
| 4901 | interrupt_mapping_39_select_pulse <= 1'b0; |
| 4902 | interrupt_mapping_40_select_pulse <= 1'b0; |
| 4903 | interrupt_mapping_41_select_pulse <= 1'b0; |
| 4904 | interrupt_mapping_42_select_pulse <= 1'b0; |
| 4905 | interrupt_mapping_43_select_pulse <= 1'b0; |
| 4906 | interrupt_mapping_44_select_pulse <= 1'b0; |
| 4907 | interrupt_mapping_45_select_pulse <= 1'b0; |
| 4908 | interrupt_mapping_46_select_pulse <= 1'b0; |
| 4909 | interrupt_mapping_47_select_pulse <= 1'b0; |
| 4910 | interrupt_mapping_48_select_pulse <= 1'b0; |
| 4911 | interrupt_mapping_49_select_pulse <= 1'b0; |
| 4912 | interrupt_mapping_50_select_pulse <= 1'b0; |
| 4913 | interrupt_mapping_51_select_pulse <= 1'b0; |
| 4914 | interrupt_mapping_52_select_pulse <= 1'b0; |
| 4915 | interrupt_mapping_53_select_pulse <= 1'b0; |
| 4916 | interrupt_mapping_54_select_pulse <= 1'b0; |
| 4917 | interrupt_mapping_55_select_pulse <= 1'b0; |
| 4918 | interrupt_mapping_56_select_pulse <= 1'b0; |
| 4919 | interrupt_mapping_57_select_pulse <= 1'b0; |
| 4920 | interrupt_mapping_58_select_pulse <= 1'b0; |
| 4921 | interrupt_mapping_59_select_pulse <= 1'b0; |
| 4922 | interrupt_mapping_62_select_pulse <= 1'b0; |
| 4923 | interrupt_mapping_63_select_pulse <= 1'b0; |
| 4924 | clr_int_reg_20_select <= 1'b0; |
| 4925 | clr_int_reg_21_select <= 1'b0; |
| 4926 | clr_int_reg_22_select <= 1'b0; |
| 4927 | clr_int_reg_23_select <= 1'b0; |
| 4928 | clr_int_reg_24_select <= 1'b0; |
| 4929 | clr_int_reg_25_select <= 1'b0; |
| 4930 | clr_int_reg_26_select <= 1'b0; |
| 4931 | clr_int_reg_27_select <= 1'b0; |
| 4932 | clr_int_reg_28_select <= 1'b0; |
| 4933 | clr_int_reg_29_select <= 1'b0; |
| 4934 | clr_int_reg_30_select <= 1'b0; |
| 4935 | clr_int_reg_31_select <= 1'b0; |
| 4936 | clr_int_reg_32_select <= 1'b0; |
| 4937 | clr_int_reg_33_select <= 1'b0; |
| 4938 | clr_int_reg_34_select <= 1'b0; |
| 4939 | clr_int_reg_35_select <= 1'b0; |
| 4940 | clr_int_reg_36_select <= 1'b0; |
| 4941 | clr_int_reg_37_select <= 1'b0; |
| 4942 | clr_int_reg_38_select <= 1'b0; |
| 4943 | clr_int_reg_39_select <= 1'b0; |
| 4944 | clr_int_reg_40_select <= 1'b0; |
| 4945 | clr_int_reg_41_select <= 1'b0; |
| 4946 | clr_int_reg_42_select <= 1'b0; |
| 4947 | clr_int_reg_43_select <= 1'b0; |
| 4948 | clr_int_reg_44_select <= 1'b0; |
| 4949 | clr_int_reg_45_select <= 1'b0; |
| 4950 | clr_int_reg_46_select <= 1'b0; |
| 4951 | clr_int_reg_47_select <= 1'b0; |
| 4952 | clr_int_reg_48_select <= 1'b0; |
| 4953 | clr_int_reg_49_select <= 1'b0; |
| 4954 | clr_int_reg_50_select <= 1'b0; |
| 4955 | clr_int_reg_51_select <= 1'b0; |
| 4956 | clr_int_reg_52_select <= 1'b0; |
| 4957 | clr_int_reg_53_select <= 1'b0; |
| 4958 | clr_int_reg_54_select <= 1'b0; |
| 4959 | clr_int_reg_55_select <= 1'b0; |
| 4960 | clr_int_reg_56_select <= 1'b0; |
| 4961 | clr_int_reg_57_select <= 1'b0; |
| 4962 | clr_int_reg_58_select <= 1'b0; |
| 4963 | clr_int_reg_59_select <= 1'b0; |
| 4964 | clr_int_reg_62_select <= 1'b0; |
| 4965 | clr_int_reg_63_select <= 1'b0; |
| 4966 | interrupt_retry_timer_select_pulse <= 1'b0; |
| 4967 | interrupt_state_status_1_select <= 1'b0; |
| 4968 | interrupt_state_status_2_select <= 1'b0; |
| 4969 | end |
| 4970 | else |
| 4971 | begin |
| 4972 | interrupt_mapping_20_select_pulse <= |
| 4973 | ~interrupt_mapping_20_acc_vio & |
| 4974 | clocked_valid_pulse & |
| 4975 | interrupt_mapping_20_addr_decoded; |
| 4976 | |
| 4977 | interrupt_mapping_21_select_pulse <= |
| 4978 | ~interrupt_mapping_21_acc_vio & |
| 4979 | clocked_valid_pulse & |
| 4980 | interrupt_mapping_21_addr_decoded; |
| 4981 | |
| 4982 | interrupt_mapping_22_select_pulse <= |
| 4983 | ~interrupt_mapping_22_acc_vio & |
| 4984 | clocked_valid_pulse & |
| 4985 | interrupt_mapping_22_addr_decoded; |
| 4986 | |
| 4987 | interrupt_mapping_23_select_pulse <= |
| 4988 | ~interrupt_mapping_23_acc_vio & |
| 4989 | clocked_valid_pulse & |
| 4990 | interrupt_mapping_23_addr_decoded; |
| 4991 | |
| 4992 | interrupt_mapping_24_select_pulse <= |
| 4993 | ~interrupt_mapping_24_acc_vio & |
| 4994 | clocked_valid_pulse & |
| 4995 | interrupt_mapping_24_addr_decoded; |
| 4996 | |
| 4997 | interrupt_mapping_25_select_pulse <= |
| 4998 | ~interrupt_mapping_25_acc_vio & |
| 4999 | clocked_valid_pulse & |
| 5000 | interrupt_mapping_25_addr_decoded; |
| 5001 | |
| 5002 | interrupt_mapping_26_select_pulse <= |
| 5003 | ~interrupt_mapping_26_acc_vio & |
| 5004 | clocked_valid_pulse & |
| 5005 | interrupt_mapping_26_addr_decoded; |
| 5006 | |
| 5007 | interrupt_mapping_27_select_pulse <= |
| 5008 | ~interrupt_mapping_27_acc_vio & |
| 5009 | clocked_valid_pulse & |
| 5010 | interrupt_mapping_27_addr_decoded; |
| 5011 | |
| 5012 | interrupt_mapping_28_select_pulse <= |
| 5013 | ~interrupt_mapping_28_acc_vio & |
| 5014 | clocked_valid_pulse & |
| 5015 | interrupt_mapping_28_addr_decoded; |
| 5016 | |
| 5017 | interrupt_mapping_29_select_pulse <= |
| 5018 | ~interrupt_mapping_29_acc_vio & |
| 5019 | clocked_valid_pulse & |
| 5020 | interrupt_mapping_29_addr_decoded; |
| 5021 | |
| 5022 | interrupt_mapping_30_select_pulse <= |
| 5023 | ~interrupt_mapping_30_acc_vio & |
| 5024 | clocked_valid_pulse & |
| 5025 | interrupt_mapping_30_addr_decoded; |
| 5026 | |
| 5027 | interrupt_mapping_31_select_pulse <= |
| 5028 | ~interrupt_mapping_31_acc_vio & |
| 5029 | clocked_valid_pulse & |
| 5030 | interrupt_mapping_31_addr_decoded; |
| 5031 | |
| 5032 | interrupt_mapping_32_select_pulse <= |
| 5033 | ~interrupt_mapping_32_acc_vio & |
| 5034 | clocked_valid_pulse & |
| 5035 | interrupt_mapping_32_addr_decoded; |
| 5036 | |
| 5037 | interrupt_mapping_33_select_pulse <= |
| 5038 | ~interrupt_mapping_33_acc_vio & |
| 5039 | clocked_valid_pulse & |
| 5040 | interrupt_mapping_33_addr_decoded; |
| 5041 | |
| 5042 | interrupt_mapping_34_select_pulse <= |
| 5043 | ~interrupt_mapping_34_acc_vio & |
| 5044 | clocked_valid_pulse & |
| 5045 | interrupt_mapping_34_addr_decoded; |
| 5046 | |
| 5047 | interrupt_mapping_35_select_pulse <= |
| 5048 | ~interrupt_mapping_35_acc_vio & |
| 5049 | clocked_valid_pulse & |
| 5050 | interrupt_mapping_35_addr_decoded; |
| 5051 | |
| 5052 | interrupt_mapping_36_select_pulse <= |
| 5053 | ~interrupt_mapping_36_acc_vio & |
| 5054 | clocked_valid_pulse & |
| 5055 | interrupt_mapping_36_addr_decoded; |
| 5056 | |
| 5057 | interrupt_mapping_37_select_pulse <= |
| 5058 | ~interrupt_mapping_37_acc_vio & |
| 5059 | clocked_valid_pulse & |
| 5060 | interrupt_mapping_37_addr_decoded; |
| 5061 | |
| 5062 | interrupt_mapping_38_select_pulse <= |
| 5063 | ~interrupt_mapping_38_acc_vio & |
| 5064 | clocked_valid_pulse & |
| 5065 | interrupt_mapping_38_addr_decoded; |
| 5066 | |
| 5067 | interrupt_mapping_39_select_pulse <= |
| 5068 | ~interrupt_mapping_39_acc_vio & |
| 5069 | clocked_valid_pulse & |
| 5070 | interrupt_mapping_39_addr_decoded; |
| 5071 | |
| 5072 | interrupt_mapping_40_select_pulse <= |
| 5073 | ~interrupt_mapping_40_acc_vio & |
| 5074 | clocked_valid_pulse & |
| 5075 | interrupt_mapping_40_addr_decoded; |
| 5076 | |
| 5077 | interrupt_mapping_41_select_pulse <= |
| 5078 | ~interrupt_mapping_41_acc_vio & |
| 5079 | clocked_valid_pulse & |
| 5080 | interrupt_mapping_41_addr_decoded; |
| 5081 | |
| 5082 | interrupt_mapping_42_select_pulse <= |
| 5083 | ~interrupt_mapping_42_acc_vio & |
| 5084 | clocked_valid_pulse & |
| 5085 | interrupt_mapping_42_addr_decoded; |
| 5086 | |
| 5087 | interrupt_mapping_43_select_pulse <= |
| 5088 | ~interrupt_mapping_43_acc_vio & |
| 5089 | clocked_valid_pulse & |
| 5090 | interrupt_mapping_43_addr_decoded; |
| 5091 | |
| 5092 | interrupt_mapping_44_select_pulse <= |
| 5093 | ~interrupt_mapping_44_acc_vio & |
| 5094 | clocked_valid_pulse & |
| 5095 | interrupt_mapping_44_addr_decoded; |
| 5096 | |
| 5097 | interrupt_mapping_45_select_pulse <= |
| 5098 | ~interrupt_mapping_45_acc_vio & |
| 5099 | clocked_valid_pulse & |
| 5100 | interrupt_mapping_45_addr_decoded; |
| 5101 | |
| 5102 | interrupt_mapping_46_select_pulse <= |
| 5103 | ~interrupt_mapping_46_acc_vio & |
| 5104 | clocked_valid_pulse & |
| 5105 | interrupt_mapping_46_addr_decoded; |
| 5106 | |
| 5107 | interrupt_mapping_47_select_pulse <= |
| 5108 | ~interrupt_mapping_47_acc_vio & |
| 5109 | clocked_valid_pulse & |
| 5110 | interrupt_mapping_47_addr_decoded; |
| 5111 | |
| 5112 | interrupt_mapping_48_select_pulse <= |
| 5113 | ~interrupt_mapping_48_acc_vio & |
| 5114 | clocked_valid_pulse & |
| 5115 | interrupt_mapping_48_addr_decoded; |
| 5116 | |
| 5117 | interrupt_mapping_49_select_pulse <= |
| 5118 | ~interrupt_mapping_49_acc_vio & |
| 5119 | clocked_valid_pulse & |
| 5120 | interrupt_mapping_49_addr_decoded; |
| 5121 | |
| 5122 | interrupt_mapping_50_select_pulse <= |
| 5123 | ~interrupt_mapping_50_acc_vio & |
| 5124 | clocked_valid_pulse & |
| 5125 | interrupt_mapping_50_addr_decoded; |
| 5126 | |
| 5127 | interrupt_mapping_51_select_pulse <= |
| 5128 | ~interrupt_mapping_51_acc_vio & |
| 5129 | clocked_valid_pulse & |
| 5130 | interrupt_mapping_51_addr_decoded; |
| 5131 | |
| 5132 | interrupt_mapping_52_select_pulse <= |
| 5133 | ~interrupt_mapping_52_acc_vio & |
| 5134 | clocked_valid_pulse & |
| 5135 | interrupt_mapping_52_addr_decoded; |
| 5136 | |
| 5137 | interrupt_mapping_53_select_pulse <= |
| 5138 | ~interrupt_mapping_53_acc_vio & |
| 5139 | clocked_valid_pulse & |
| 5140 | interrupt_mapping_53_addr_decoded; |
| 5141 | |
| 5142 | interrupt_mapping_54_select_pulse <= |
| 5143 | ~interrupt_mapping_54_acc_vio & |
| 5144 | clocked_valid_pulse & |
| 5145 | interrupt_mapping_54_addr_decoded; |
| 5146 | |
| 5147 | interrupt_mapping_55_select_pulse <= |
| 5148 | ~interrupt_mapping_55_acc_vio & |
| 5149 | clocked_valid_pulse & |
| 5150 | interrupt_mapping_55_addr_decoded; |
| 5151 | |
| 5152 | interrupt_mapping_56_select_pulse <= |
| 5153 | ~interrupt_mapping_56_acc_vio & |
| 5154 | clocked_valid_pulse & |
| 5155 | interrupt_mapping_56_addr_decoded; |
| 5156 | |
| 5157 | interrupt_mapping_57_select_pulse <= |
| 5158 | ~interrupt_mapping_57_acc_vio & |
| 5159 | clocked_valid_pulse & |
| 5160 | interrupt_mapping_57_addr_decoded; |
| 5161 | |
| 5162 | interrupt_mapping_58_select_pulse <= |
| 5163 | ~interrupt_mapping_58_acc_vio & |
| 5164 | clocked_valid_pulse & |
| 5165 | interrupt_mapping_58_addr_decoded; |
| 5166 | |
| 5167 | interrupt_mapping_59_select_pulse <= |
| 5168 | ~interrupt_mapping_59_acc_vio & |
| 5169 | clocked_valid_pulse & |
| 5170 | interrupt_mapping_59_addr_decoded; |
| 5171 | |
| 5172 | interrupt_mapping_62_select_pulse <= |
| 5173 | ~interrupt_mapping_62_acc_vio & |
| 5174 | clocked_valid_pulse & |
| 5175 | interrupt_mapping_62_addr_decoded; |
| 5176 | |
| 5177 | interrupt_mapping_63_select_pulse <= |
| 5178 | ~interrupt_mapping_63_acc_vio & |
| 5179 | clocked_valid_pulse & |
| 5180 | interrupt_mapping_63_addr_decoded; |
| 5181 | |
| 5182 | clr_int_reg_20_select <= |
| 5183 | ~clr_int_reg_20_acc_vio & |
| 5184 | clr_int_reg_20_addr_decoded; |
| 5185 | |
| 5186 | clr_int_reg_21_select <= |
| 5187 | ~clr_int_reg_21_acc_vio & |
| 5188 | clr_int_reg_21_addr_decoded; |
| 5189 | |
| 5190 | clr_int_reg_22_select <= |
| 5191 | ~clr_int_reg_22_acc_vio & |
| 5192 | clr_int_reg_22_addr_decoded; |
| 5193 | |
| 5194 | clr_int_reg_23_select <= |
| 5195 | ~clr_int_reg_23_acc_vio & |
| 5196 | clr_int_reg_23_addr_decoded; |
| 5197 | |
| 5198 | clr_int_reg_24_select <= |
| 5199 | ~clr_int_reg_24_acc_vio & |
| 5200 | clr_int_reg_24_addr_decoded; |
| 5201 | |
| 5202 | clr_int_reg_25_select <= |
| 5203 | ~clr_int_reg_25_acc_vio & |
| 5204 | clr_int_reg_25_addr_decoded; |
| 5205 | |
| 5206 | clr_int_reg_26_select <= |
| 5207 | ~clr_int_reg_26_acc_vio & |
| 5208 | clr_int_reg_26_addr_decoded; |
| 5209 | |
| 5210 | clr_int_reg_27_select <= |
| 5211 | ~clr_int_reg_27_acc_vio & |
| 5212 | clr_int_reg_27_addr_decoded; |
| 5213 | |
| 5214 | clr_int_reg_28_select <= |
| 5215 | ~clr_int_reg_28_acc_vio & |
| 5216 | clr_int_reg_28_addr_decoded; |
| 5217 | |
| 5218 | clr_int_reg_29_select <= |
| 5219 | ~clr_int_reg_29_acc_vio & |
| 5220 | clr_int_reg_29_addr_decoded; |
| 5221 | |
| 5222 | clr_int_reg_30_select <= |
| 5223 | ~clr_int_reg_30_acc_vio & |
| 5224 | clr_int_reg_30_addr_decoded; |
| 5225 | |
| 5226 | clr_int_reg_31_select <= |
| 5227 | ~clr_int_reg_31_acc_vio & |
| 5228 | clr_int_reg_31_addr_decoded; |
| 5229 | |
| 5230 | clr_int_reg_32_select <= |
| 5231 | ~clr_int_reg_32_acc_vio & |
| 5232 | clr_int_reg_32_addr_decoded; |
| 5233 | |
| 5234 | clr_int_reg_33_select <= |
| 5235 | ~clr_int_reg_33_acc_vio & |
| 5236 | clr_int_reg_33_addr_decoded; |
| 5237 | |
| 5238 | clr_int_reg_34_select <= |
| 5239 | ~clr_int_reg_34_acc_vio & |
| 5240 | clr_int_reg_34_addr_decoded; |
| 5241 | |
| 5242 | clr_int_reg_35_select <= |
| 5243 | ~clr_int_reg_35_acc_vio & |
| 5244 | clr_int_reg_35_addr_decoded; |
| 5245 | |
| 5246 | clr_int_reg_36_select <= |
| 5247 | ~clr_int_reg_36_acc_vio & |
| 5248 | clr_int_reg_36_addr_decoded; |
| 5249 | |
| 5250 | clr_int_reg_37_select <= |
| 5251 | ~clr_int_reg_37_acc_vio & |
| 5252 | clr_int_reg_37_addr_decoded; |
| 5253 | |
| 5254 | clr_int_reg_38_select <= |
| 5255 | ~clr_int_reg_38_acc_vio & |
| 5256 | clr_int_reg_38_addr_decoded; |
| 5257 | |
| 5258 | clr_int_reg_39_select <= |
| 5259 | ~clr_int_reg_39_acc_vio & |
| 5260 | clr_int_reg_39_addr_decoded; |
| 5261 | |
| 5262 | clr_int_reg_40_select <= |
| 5263 | ~clr_int_reg_40_acc_vio & |
| 5264 | clr_int_reg_40_addr_decoded; |
| 5265 | |
| 5266 | clr_int_reg_41_select <= |
| 5267 | ~clr_int_reg_41_acc_vio & |
| 5268 | clr_int_reg_41_addr_decoded; |
| 5269 | |
| 5270 | clr_int_reg_42_select <= |
| 5271 | ~clr_int_reg_42_acc_vio & |
| 5272 | clr_int_reg_42_addr_decoded; |
| 5273 | |
| 5274 | clr_int_reg_43_select <= |
| 5275 | ~clr_int_reg_43_acc_vio & |
| 5276 | clr_int_reg_43_addr_decoded; |
| 5277 | |
| 5278 | clr_int_reg_44_select <= |
| 5279 | ~clr_int_reg_44_acc_vio & |
| 5280 | clr_int_reg_44_addr_decoded; |
| 5281 | |
| 5282 | clr_int_reg_45_select <= |
| 5283 | ~clr_int_reg_45_acc_vio & |
| 5284 | clr_int_reg_45_addr_decoded; |
| 5285 | |
| 5286 | clr_int_reg_46_select <= |
| 5287 | ~clr_int_reg_46_acc_vio & |
| 5288 | clr_int_reg_46_addr_decoded; |
| 5289 | |
| 5290 | clr_int_reg_47_select <= |
| 5291 | ~clr_int_reg_47_acc_vio & |
| 5292 | clr_int_reg_47_addr_decoded; |
| 5293 | |
| 5294 | clr_int_reg_48_select <= |
| 5295 | ~clr_int_reg_48_acc_vio & |
| 5296 | clr_int_reg_48_addr_decoded; |
| 5297 | |
| 5298 | clr_int_reg_49_select <= |
| 5299 | ~clr_int_reg_49_acc_vio & |
| 5300 | clr_int_reg_49_addr_decoded; |
| 5301 | |
| 5302 | clr_int_reg_50_select <= |
| 5303 | ~clr_int_reg_50_acc_vio & |
| 5304 | clr_int_reg_50_addr_decoded; |
| 5305 | |
| 5306 | clr_int_reg_51_select <= |
| 5307 | ~clr_int_reg_51_acc_vio & |
| 5308 | clr_int_reg_51_addr_decoded; |
| 5309 | |
| 5310 | clr_int_reg_52_select <= |
| 5311 | ~clr_int_reg_52_acc_vio & |
| 5312 | clr_int_reg_52_addr_decoded; |
| 5313 | |
| 5314 | clr_int_reg_53_select <= |
| 5315 | ~clr_int_reg_53_acc_vio & |
| 5316 | clr_int_reg_53_addr_decoded; |
| 5317 | |
| 5318 | clr_int_reg_54_select <= |
| 5319 | ~clr_int_reg_54_acc_vio & |
| 5320 | clr_int_reg_54_addr_decoded; |
| 5321 | |
| 5322 | clr_int_reg_55_select <= |
| 5323 | ~clr_int_reg_55_acc_vio & |
| 5324 | clr_int_reg_55_addr_decoded; |
| 5325 | |
| 5326 | clr_int_reg_56_select <= |
| 5327 | ~clr_int_reg_56_acc_vio & |
| 5328 | clr_int_reg_56_addr_decoded; |
| 5329 | |
| 5330 | clr_int_reg_57_select <= |
| 5331 | ~clr_int_reg_57_acc_vio & |
| 5332 | clr_int_reg_57_addr_decoded; |
| 5333 | |
| 5334 | clr_int_reg_58_select <= |
| 5335 | ~clr_int_reg_58_acc_vio & |
| 5336 | clr_int_reg_58_addr_decoded; |
| 5337 | |
| 5338 | clr_int_reg_59_select <= |
| 5339 | ~clr_int_reg_59_acc_vio & |
| 5340 | clr_int_reg_59_addr_decoded; |
| 5341 | |
| 5342 | clr_int_reg_62_select <= |
| 5343 | ~clr_int_reg_62_acc_vio & |
| 5344 | clr_int_reg_62_addr_decoded; |
| 5345 | |
| 5346 | clr_int_reg_63_select <= |
| 5347 | ~clr_int_reg_63_acc_vio & |
| 5348 | clr_int_reg_63_addr_decoded; |
| 5349 | |
| 5350 | interrupt_retry_timer_select_pulse <= |
| 5351 | ~interrupt_retry_timer_acc_vio & |
| 5352 | clocked_valid_pulse & |
| 5353 | interrupt_retry_timer_addr_decoded; |
| 5354 | |
| 5355 | interrupt_state_status_1_select <= |
| 5356 | ~interrupt_state_status_1_acc_vio & |
| 5357 | interrupt_state_status_1_addr_decoded; |
| 5358 | |
| 5359 | interrupt_state_status_2_select <= |
| 5360 | ~interrupt_state_status_2_acc_vio & |
| 5361 | interrupt_state_status_2_addr_decoded; |
| 5362 | |
| 5363 | end |
| 5364 | end |
| 5365 | |
| 5366 | //==================================================================== |
| 5367 | // daemon_csrbus_wr / daemon_csrbus_wr_data |
| 5368 | //==================================================================== |
| 5369 | always @(posedge clk) |
| 5370 | begin |
| 5371 | if(~rst_l) |
| 5372 | begin |
| 5373 | daemon_csrbus_wr_out <= 1'b0; |
| 5374 | daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0; |
| 5375 | end |
| 5376 | else |
| 5377 | begin |
| 5378 | daemon_csrbus_wr_out <= daemon_csrbus_wr; |
| 5379 | daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data; |
| 5380 | end |
| 5381 | end |
| 5382 | |
| 5383 | //==================================================================== |
| 5384 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming |
| 5385 | //==================================================================== |
| 5386 | |
| 5387 | //==================================================================== |
| 5388 | // OUTPUT: daemon_csrbus_done (pipelining) |
| 5389 | //==================================================================== |
| 5390 | //----- DONE for internal/extern registers |
| 5391 | reg stage_1_daemon_csrbus_done_internal_0; |
| 5392 | reg stage_2_daemon_csrbus_done_internal_0; |
| 5393 | |
| 5394 | always @(posedge clk) |
| 5395 | begin |
| 5396 | if(~rst_l) |
| 5397 | begin |
| 5398 | stage_1_daemon_csrbus_done_internal_0 <= 1'b0; |
| 5399 | end |
| 5400 | else |
| 5401 | begin |
| 5402 | stage_1_daemon_csrbus_done_internal_0 <= |
| 5403 | interrupt_mapping_20_select_pulse | |
| 5404 | interrupt_mapping_21_select_pulse | |
| 5405 | interrupt_mapping_22_select_pulse | |
| 5406 | interrupt_mapping_23_select_pulse | |
| 5407 | interrupt_mapping_24_select_pulse | |
| 5408 | interrupt_mapping_25_select_pulse | |
| 5409 | interrupt_mapping_26_select_pulse | |
| 5410 | interrupt_mapping_27_select_pulse | |
| 5411 | interrupt_mapping_28_select_pulse | |
| 5412 | interrupt_mapping_29_select_pulse | |
| 5413 | interrupt_mapping_30_select_pulse | |
| 5414 | interrupt_mapping_31_select_pulse | |
| 5415 | interrupt_mapping_32_select_pulse | |
| 5416 | interrupt_mapping_33_select_pulse | |
| 5417 | interrupt_mapping_34_select_pulse | |
| 5418 | interrupt_mapping_35_select_pulse | |
| 5419 | interrupt_mapping_36_select_pulse | |
| 5420 | interrupt_mapping_37_select_pulse | |
| 5421 | interrupt_mapping_38_select_pulse | |
| 5422 | interrupt_mapping_39_select_pulse | |
| 5423 | interrupt_mapping_40_select_pulse | |
| 5424 | interrupt_mapping_41_select_pulse | |
| 5425 | interrupt_mapping_42_select_pulse | |
| 5426 | interrupt_mapping_43_select_pulse | |
| 5427 | interrupt_mapping_44_select_pulse | |
| 5428 | interrupt_mapping_45_select_pulse | |
| 5429 | interrupt_mapping_46_select_pulse | |
| 5430 | interrupt_mapping_47_select_pulse | |
| 5431 | interrupt_mapping_48_select_pulse | |
| 5432 | interrupt_mapping_49_select_pulse | |
| 5433 | interrupt_mapping_50_select_pulse | |
| 5434 | interrupt_mapping_51_select_pulse | |
| 5435 | interrupt_mapping_52_select_pulse | |
| 5436 | interrupt_mapping_53_select_pulse | |
| 5437 | interrupt_mapping_54_select_pulse | |
| 5438 | interrupt_mapping_55_select_pulse | |
| 5439 | interrupt_mapping_56_select_pulse | |
| 5440 | interrupt_mapping_57_select_pulse | |
| 5441 | interrupt_mapping_58_select_pulse | |
| 5442 | interrupt_mapping_59_select_pulse | |
| 5443 | interrupt_mapping_62_select_pulse | |
| 5444 | interrupt_mapping_63_select_pulse | |
| 5445 | interrupt_retry_timer_select_pulse | |
| 5446 | clr_int_reg_20_select & clocked_valid_pulse | |
| 5447 | clr_int_reg_21_select & clocked_valid_pulse | |
| 5448 | clr_int_reg_22_select & clocked_valid_pulse | |
| 5449 | clr_int_reg_23_select & clocked_valid_pulse | |
| 5450 | clr_int_reg_24_select & clocked_valid_pulse | |
| 5451 | clr_int_reg_25_select & clocked_valid_pulse | |
| 5452 | clr_int_reg_26_select & clocked_valid_pulse | |
| 5453 | clr_int_reg_27_select & clocked_valid_pulse | |
| 5454 | clr_int_reg_28_select & clocked_valid_pulse | |
| 5455 | clr_int_reg_29_select & clocked_valid_pulse | |
| 5456 | clr_int_reg_30_select & clocked_valid_pulse | |
| 5457 | clr_int_reg_31_select & clocked_valid_pulse | |
| 5458 | clr_int_reg_32_select & clocked_valid_pulse | |
| 5459 | clr_int_reg_33_select & clocked_valid_pulse | |
| 5460 | clr_int_reg_34_select & clocked_valid_pulse | |
| 5461 | clr_int_reg_35_select & clocked_valid_pulse | |
| 5462 | clr_int_reg_36_select & clocked_valid_pulse | |
| 5463 | clr_int_reg_37_select & clocked_valid_pulse | |
| 5464 | clr_int_reg_38_select & clocked_valid_pulse | |
| 5465 | clr_int_reg_39_select & clocked_valid_pulse | |
| 5466 | clr_int_reg_40_select & clocked_valid_pulse | |
| 5467 | clr_int_reg_41_select & clocked_valid_pulse | |
| 5468 | clr_int_reg_42_select & clocked_valid_pulse | |
| 5469 | clr_int_reg_43_select & clocked_valid_pulse | |
| 5470 | clr_int_reg_44_select & clocked_valid_pulse | |
| 5471 | clr_int_reg_45_select & clocked_valid_pulse | |
| 5472 | clr_int_reg_46_select & clocked_valid_pulse | |
| 5473 | clr_int_reg_47_select & clocked_valid_pulse | |
| 5474 | clr_int_reg_48_select & clocked_valid_pulse | |
| 5475 | clr_int_reg_49_select & clocked_valid_pulse | |
| 5476 | clr_int_reg_50_select & clocked_valid_pulse | |
| 5477 | clr_int_reg_51_select & clocked_valid_pulse | |
| 5478 | clr_int_reg_52_select & clocked_valid_pulse | |
| 5479 | clr_int_reg_53_select & clocked_valid_pulse | |
| 5480 | clr_int_reg_54_select & clocked_valid_pulse | |
| 5481 | clr_int_reg_55_select & clocked_valid_pulse | |
| 5482 | clr_int_reg_56_select & clocked_valid_pulse | |
| 5483 | clr_int_reg_57_select & clocked_valid_pulse | |
| 5484 | clr_int_reg_58_select & clocked_valid_pulse | |
| 5485 | clr_int_reg_59_select & clocked_valid_pulse | |
| 5486 | clr_int_reg_62_select & clocked_valid_pulse | |
| 5487 | clr_int_reg_63_select & clocked_valid_pulse | |
| 5488 | interrupt_state_status_1_select & clocked_valid_pulse | |
| 5489 | interrupt_state_status_2_select & clocked_valid_pulse; |
| 5490 | end |
| 5491 | if(~rst_l) |
| 5492 | begin |
| 5493 | stage_2_daemon_csrbus_done_internal_0 <= 1'b0; |
| 5494 | end |
| 5495 | else |
| 5496 | begin |
| 5497 | stage_2_daemon_csrbus_done_internal_0 <= |
| 5498 | stage_1_daemon_csrbus_done_internal_0; |
| 5499 | end |
| 5500 | end |
| 5501 | |
| 5502 | //----- OUTPUT: daemon_csrbus_done |
| 5503 | assign daemon_csrbus_done = daemon_csrbus_valid & |
| 5504 | ( |
| 5505 | stage_2_daemon_csrbus_done_internal_0 |
| 5506 | ); |
| 5507 | |
| 5508 | // daemon_csrbus_done gets asserted only when csrbus_valid is high |
| 5509 | /* 0in assert -name daemon_csrbus_done_high |
| 5510 | -var daemon_csrbus_valid -active daemon_csrbus_done |
| 5511 | -message "csrbus_done got asserted while csrbus_valid is low" |
| 5512 | -module dmu_imu_iss_addr_decode |
| 5513 | -clock clk |
| 5514 | */ |
| 5515 | |
| 5516 | // daemon_csrbus_done is a pulse |
| 5517 | /* 0in assert_timer -name daemon_csrbus_done_pulse |
| 5518 | -var daemon_csrbus_done -max 1 |
| 5519 | -message "csrbus_done pulse length is not 1" |
| 5520 | -module dmu_imu_iss_addr_decode |
| 5521 | -clock clk |
| 5522 | */ |
| 5523 | |
| 5524 | endmodule // dmu_imu_iss_addr_decode |