| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_iss_csr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_iss_csr |
| 36 | ( |
| 37 | clk, |
| 38 | csrbus_addr, |
| 39 | csrbus_wr_data, |
| 40 | csrbus_wr, |
| 41 | csrbus_valid, |
| 42 | csrbus_mapped, |
| 43 | csrbus_done, |
| 44 | csrbus_read_data, |
| 45 | rst_l, |
| 46 | csrbus_src_bus, |
| 47 | csrbus_acc_vio, |
| 48 | instance_id, |
| 49 | ext_wr, |
| 50 | interrupt_mapping_20_mdo_mode_hw_read, |
| 51 | interrupt_mapping_20_v_hw_read, |
| 52 | interrupt_mapping_20_t_id_hw_read, |
| 53 | interrupt_mapping_20_int_cntrl_num_hw_read, |
| 54 | interrupt_mapping_21_mdo_mode_hw_read, |
| 55 | interrupt_mapping_21_v_hw_read, |
| 56 | interrupt_mapping_21_t_id_hw_read, |
| 57 | interrupt_mapping_21_int_cntrl_num_hw_read, |
| 58 | interrupt_mapping_22_mdo_mode_hw_read, |
| 59 | interrupt_mapping_22_v_hw_read, |
| 60 | interrupt_mapping_22_t_id_hw_read, |
| 61 | interrupt_mapping_22_int_cntrl_num_hw_read, |
| 62 | interrupt_mapping_23_mdo_mode_hw_read, |
| 63 | interrupt_mapping_23_v_hw_read, |
| 64 | interrupt_mapping_23_t_id_hw_read, |
| 65 | interrupt_mapping_23_int_cntrl_num_hw_read, |
| 66 | interrupt_mapping_24_mdo_mode_hw_read, |
| 67 | interrupt_mapping_24_v_hw_read, |
| 68 | interrupt_mapping_24_t_id_hw_read, |
| 69 | interrupt_mapping_24_int_cntrl_num_hw_read, |
| 70 | interrupt_mapping_25_mdo_mode_hw_read, |
| 71 | interrupt_mapping_25_v_hw_read, |
| 72 | interrupt_mapping_25_t_id_hw_read, |
| 73 | interrupt_mapping_25_int_cntrl_num_hw_read, |
| 74 | interrupt_mapping_26_mdo_mode_hw_read, |
| 75 | interrupt_mapping_26_v_hw_read, |
| 76 | interrupt_mapping_26_t_id_hw_read, |
| 77 | interrupt_mapping_26_int_cntrl_num_hw_read, |
| 78 | interrupt_mapping_27_mdo_mode_hw_read, |
| 79 | interrupt_mapping_27_v_hw_read, |
| 80 | interrupt_mapping_27_t_id_hw_read, |
| 81 | interrupt_mapping_27_int_cntrl_num_hw_read, |
| 82 | interrupt_mapping_28_mdo_mode_hw_read, |
| 83 | interrupt_mapping_28_v_hw_read, |
| 84 | interrupt_mapping_28_t_id_hw_read, |
| 85 | interrupt_mapping_28_int_cntrl_num_hw_read, |
| 86 | interrupt_mapping_29_mdo_mode_hw_read, |
| 87 | interrupt_mapping_29_v_hw_read, |
| 88 | interrupt_mapping_29_t_id_hw_read, |
| 89 | interrupt_mapping_29_int_cntrl_num_hw_read, |
| 90 | interrupt_mapping_30_mdo_mode_hw_read, |
| 91 | interrupt_mapping_30_v_hw_read, |
| 92 | interrupt_mapping_30_t_id_hw_read, |
| 93 | interrupt_mapping_30_int_cntrl_num_hw_read, |
| 94 | interrupt_mapping_31_mdo_mode_hw_read, |
| 95 | interrupt_mapping_31_v_hw_read, |
| 96 | interrupt_mapping_31_t_id_hw_read, |
| 97 | interrupt_mapping_31_int_cntrl_num_hw_read, |
| 98 | interrupt_mapping_32_mdo_mode_hw_read, |
| 99 | interrupt_mapping_32_v_hw_read, |
| 100 | interrupt_mapping_32_t_id_hw_read, |
| 101 | interrupt_mapping_32_int_cntrl_num_hw_read, |
| 102 | interrupt_mapping_33_mdo_mode_hw_read, |
| 103 | interrupt_mapping_33_v_hw_read, |
| 104 | interrupt_mapping_33_t_id_hw_read, |
| 105 | interrupt_mapping_33_int_cntrl_num_hw_read, |
| 106 | interrupt_mapping_34_mdo_mode_hw_read, |
| 107 | interrupt_mapping_34_v_hw_read, |
| 108 | interrupt_mapping_34_t_id_hw_read, |
| 109 | interrupt_mapping_34_int_cntrl_num_hw_read, |
| 110 | interrupt_mapping_35_mdo_mode_hw_read, |
| 111 | interrupt_mapping_35_v_hw_read, |
| 112 | interrupt_mapping_35_t_id_hw_read, |
| 113 | interrupt_mapping_35_int_cntrl_num_hw_read, |
| 114 | interrupt_mapping_36_mdo_mode_hw_read, |
| 115 | interrupt_mapping_36_v_hw_read, |
| 116 | interrupt_mapping_36_t_id_hw_read, |
| 117 | interrupt_mapping_36_int_cntrl_num_hw_read, |
| 118 | interrupt_mapping_37_mdo_mode_hw_read, |
| 119 | interrupt_mapping_37_v_hw_read, |
| 120 | interrupt_mapping_37_t_id_hw_read, |
| 121 | interrupt_mapping_37_int_cntrl_num_hw_read, |
| 122 | interrupt_mapping_38_mdo_mode_hw_read, |
| 123 | interrupt_mapping_38_v_hw_read, |
| 124 | interrupt_mapping_38_t_id_hw_read, |
| 125 | interrupt_mapping_38_int_cntrl_num_hw_read, |
| 126 | interrupt_mapping_39_mdo_mode_hw_read, |
| 127 | interrupt_mapping_39_v_hw_read, |
| 128 | interrupt_mapping_39_t_id_hw_read, |
| 129 | interrupt_mapping_39_int_cntrl_num_hw_read, |
| 130 | interrupt_mapping_40_mdo_mode_hw_read, |
| 131 | interrupt_mapping_40_v_hw_read, |
| 132 | interrupt_mapping_40_t_id_hw_read, |
| 133 | interrupt_mapping_40_int_cntrl_num_hw_read, |
| 134 | interrupt_mapping_41_mdo_mode_hw_read, |
| 135 | interrupt_mapping_41_v_hw_read, |
| 136 | interrupt_mapping_41_t_id_hw_read, |
| 137 | interrupt_mapping_41_int_cntrl_num_hw_read, |
| 138 | interrupt_mapping_42_mdo_mode_hw_read, |
| 139 | interrupt_mapping_42_v_hw_read, |
| 140 | interrupt_mapping_42_t_id_hw_read, |
| 141 | interrupt_mapping_42_int_cntrl_num_hw_read, |
| 142 | interrupt_mapping_43_mdo_mode_hw_read, |
| 143 | interrupt_mapping_43_v_hw_read, |
| 144 | interrupt_mapping_43_t_id_hw_read, |
| 145 | interrupt_mapping_43_int_cntrl_num_hw_read, |
| 146 | interrupt_mapping_44_mdo_mode_hw_read, |
| 147 | interrupt_mapping_44_v_hw_read, |
| 148 | interrupt_mapping_44_t_id_hw_read, |
| 149 | interrupt_mapping_44_int_cntrl_num_hw_read, |
| 150 | interrupt_mapping_45_mdo_mode_hw_read, |
| 151 | interrupt_mapping_45_v_hw_read, |
| 152 | interrupt_mapping_45_t_id_hw_read, |
| 153 | interrupt_mapping_45_int_cntrl_num_hw_read, |
| 154 | interrupt_mapping_46_mdo_mode_hw_read, |
| 155 | interrupt_mapping_46_v_hw_read, |
| 156 | interrupt_mapping_46_t_id_hw_read, |
| 157 | interrupt_mapping_46_int_cntrl_num_hw_read, |
| 158 | interrupt_mapping_47_mdo_mode_hw_read, |
| 159 | interrupt_mapping_47_v_hw_read, |
| 160 | interrupt_mapping_47_t_id_hw_read, |
| 161 | interrupt_mapping_47_int_cntrl_num_hw_read, |
| 162 | interrupt_mapping_48_mdo_mode_hw_read, |
| 163 | interrupt_mapping_48_v_hw_read, |
| 164 | interrupt_mapping_48_t_id_hw_read, |
| 165 | interrupt_mapping_48_int_cntrl_num_hw_read, |
| 166 | interrupt_mapping_49_mdo_mode_hw_read, |
| 167 | interrupt_mapping_49_v_hw_read, |
| 168 | interrupt_mapping_49_t_id_hw_read, |
| 169 | interrupt_mapping_49_int_cntrl_num_hw_read, |
| 170 | interrupt_mapping_50_mdo_mode_hw_read, |
| 171 | interrupt_mapping_50_v_hw_read, |
| 172 | interrupt_mapping_50_t_id_hw_read, |
| 173 | interrupt_mapping_50_int_cntrl_num_hw_read, |
| 174 | interrupt_mapping_51_mdo_mode_hw_read, |
| 175 | interrupt_mapping_51_v_hw_read, |
| 176 | interrupt_mapping_51_t_id_hw_read, |
| 177 | interrupt_mapping_51_int_cntrl_num_hw_read, |
| 178 | interrupt_mapping_52_mdo_mode_hw_read, |
| 179 | interrupt_mapping_52_v_hw_read, |
| 180 | interrupt_mapping_52_t_id_hw_read, |
| 181 | interrupt_mapping_52_int_cntrl_num_hw_read, |
| 182 | interrupt_mapping_53_mdo_mode_hw_read, |
| 183 | interrupt_mapping_53_v_hw_read, |
| 184 | interrupt_mapping_53_t_id_hw_read, |
| 185 | interrupt_mapping_53_int_cntrl_num_hw_read, |
| 186 | interrupt_mapping_54_mdo_mode_hw_read, |
| 187 | interrupt_mapping_54_v_hw_read, |
| 188 | interrupt_mapping_54_t_id_hw_read, |
| 189 | interrupt_mapping_54_int_cntrl_num_hw_read, |
| 190 | interrupt_mapping_55_mdo_mode_hw_read, |
| 191 | interrupt_mapping_55_v_hw_read, |
| 192 | interrupt_mapping_55_t_id_hw_read, |
| 193 | interrupt_mapping_55_int_cntrl_num_hw_read, |
| 194 | interrupt_mapping_56_mdo_mode_hw_read, |
| 195 | interrupt_mapping_56_v_hw_read, |
| 196 | interrupt_mapping_56_t_id_hw_read, |
| 197 | interrupt_mapping_56_int_cntrl_num_hw_read, |
| 198 | interrupt_mapping_57_mdo_mode_hw_read, |
| 199 | interrupt_mapping_57_v_hw_read, |
| 200 | interrupt_mapping_57_t_id_hw_read, |
| 201 | interrupt_mapping_57_int_cntrl_num_hw_read, |
| 202 | interrupt_mapping_58_mdo_mode_hw_read, |
| 203 | interrupt_mapping_58_v_hw_read, |
| 204 | interrupt_mapping_58_t_id_hw_read, |
| 205 | interrupt_mapping_58_int_cntrl_num_hw_read, |
| 206 | interrupt_mapping_59_mdo_mode_hw_read, |
| 207 | interrupt_mapping_59_v_hw_read, |
| 208 | interrupt_mapping_59_t_id_hw_read, |
| 209 | interrupt_mapping_59_int_cntrl_num_hw_read, |
| 210 | interrupt_mapping_62_mdo_mode_hw_read, |
| 211 | interrupt_mapping_62_v_hw_read, |
| 212 | interrupt_mapping_62_t_id_hw_read, |
| 213 | interrupt_mapping_62_int_cntrl_num_hw_read, |
| 214 | interrupt_mapping_63_mdo_mode_hw_read, |
| 215 | interrupt_mapping_63_v_hw_read, |
| 216 | interrupt_mapping_63_t_id_hw_read, |
| 217 | interrupt_mapping_63_int_cntrl_num_hw_read, |
| 218 | clr_int_reg_20_int_state_ext_wr_data, |
| 219 | clr_int_reg_20_ext_select, |
| 220 | clr_int_reg_20_int_state_ext_read_data, |
| 221 | clr_int_reg_21_int_state_ext_wr_data, |
| 222 | clr_int_reg_21_ext_select, |
| 223 | clr_int_reg_21_int_state_ext_read_data, |
| 224 | clr_int_reg_22_int_state_ext_wr_data, |
| 225 | clr_int_reg_22_ext_select, |
| 226 | clr_int_reg_22_int_state_ext_read_data, |
| 227 | clr_int_reg_23_int_state_ext_wr_data, |
| 228 | clr_int_reg_23_ext_select, |
| 229 | clr_int_reg_23_int_state_ext_read_data, |
| 230 | clr_int_reg_24_int_state_ext_wr_data, |
| 231 | clr_int_reg_24_ext_select, |
| 232 | clr_int_reg_24_int_state_ext_read_data, |
| 233 | clr_int_reg_25_int_state_ext_wr_data, |
| 234 | clr_int_reg_25_ext_select, |
| 235 | clr_int_reg_25_int_state_ext_read_data, |
| 236 | clr_int_reg_26_int_state_ext_wr_data, |
| 237 | clr_int_reg_26_ext_select, |
| 238 | clr_int_reg_26_int_state_ext_read_data, |
| 239 | clr_int_reg_27_int_state_ext_wr_data, |
| 240 | clr_int_reg_27_ext_select, |
| 241 | clr_int_reg_27_int_state_ext_read_data, |
| 242 | clr_int_reg_28_int_state_ext_wr_data, |
| 243 | clr_int_reg_28_ext_select, |
| 244 | clr_int_reg_28_int_state_ext_read_data, |
| 245 | clr_int_reg_29_int_state_ext_wr_data, |
| 246 | clr_int_reg_29_ext_select, |
| 247 | clr_int_reg_29_int_state_ext_read_data, |
| 248 | clr_int_reg_30_int_state_ext_wr_data, |
| 249 | clr_int_reg_30_ext_select, |
| 250 | clr_int_reg_30_int_state_ext_read_data, |
| 251 | clr_int_reg_31_int_state_ext_wr_data, |
| 252 | clr_int_reg_31_ext_select, |
| 253 | clr_int_reg_31_int_state_ext_read_data, |
| 254 | clr_int_reg_32_int_state_ext_wr_data, |
| 255 | clr_int_reg_32_ext_select, |
| 256 | clr_int_reg_32_int_state_ext_read_data, |
| 257 | clr_int_reg_33_int_state_ext_wr_data, |
| 258 | clr_int_reg_33_ext_select, |
| 259 | clr_int_reg_33_int_state_ext_read_data, |
| 260 | clr_int_reg_34_int_state_ext_wr_data, |
| 261 | clr_int_reg_34_ext_select, |
| 262 | clr_int_reg_34_int_state_ext_read_data, |
| 263 | clr_int_reg_35_int_state_ext_wr_data, |
| 264 | clr_int_reg_35_ext_select, |
| 265 | clr_int_reg_35_int_state_ext_read_data, |
| 266 | clr_int_reg_36_int_state_ext_wr_data, |
| 267 | clr_int_reg_36_ext_select, |
| 268 | clr_int_reg_36_int_state_ext_read_data, |
| 269 | clr_int_reg_37_int_state_ext_wr_data, |
| 270 | clr_int_reg_37_ext_select, |
| 271 | clr_int_reg_37_int_state_ext_read_data, |
| 272 | clr_int_reg_38_int_state_ext_wr_data, |
| 273 | clr_int_reg_38_ext_select, |
| 274 | clr_int_reg_38_int_state_ext_read_data, |
| 275 | clr_int_reg_39_int_state_ext_wr_data, |
| 276 | clr_int_reg_39_ext_select, |
| 277 | clr_int_reg_39_int_state_ext_read_data, |
| 278 | clr_int_reg_40_int_state_ext_wr_data, |
| 279 | clr_int_reg_40_ext_select, |
| 280 | clr_int_reg_40_int_state_ext_read_data, |
| 281 | clr_int_reg_41_int_state_ext_wr_data, |
| 282 | clr_int_reg_41_ext_select, |
| 283 | clr_int_reg_41_int_state_ext_read_data, |
| 284 | clr_int_reg_42_int_state_ext_wr_data, |
| 285 | clr_int_reg_42_ext_select, |
| 286 | clr_int_reg_42_int_state_ext_read_data, |
| 287 | clr_int_reg_43_int_state_ext_wr_data, |
| 288 | clr_int_reg_43_ext_select, |
| 289 | clr_int_reg_43_int_state_ext_read_data, |
| 290 | clr_int_reg_44_int_state_ext_wr_data, |
| 291 | clr_int_reg_44_ext_select, |
| 292 | clr_int_reg_44_int_state_ext_read_data, |
| 293 | clr_int_reg_45_int_state_ext_wr_data, |
| 294 | clr_int_reg_45_ext_select, |
| 295 | clr_int_reg_45_int_state_ext_read_data, |
| 296 | clr_int_reg_46_int_state_ext_wr_data, |
| 297 | clr_int_reg_46_ext_select, |
| 298 | clr_int_reg_46_int_state_ext_read_data, |
| 299 | clr_int_reg_47_int_state_ext_wr_data, |
| 300 | clr_int_reg_47_ext_select, |
| 301 | clr_int_reg_47_int_state_ext_read_data, |
| 302 | clr_int_reg_48_int_state_ext_wr_data, |
| 303 | clr_int_reg_48_ext_select, |
| 304 | clr_int_reg_48_int_state_ext_read_data, |
| 305 | clr_int_reg_49_int_state_ext_wr_data, |
| 306 | clr_int_reg_49_ext_select, |
| 307 | clr_int_reg_49_int_state_ext_read_data, |
| 308 | clr_int_reg_50_int_state_ext_wr_data, |
| 309 | clr_int_reg_50_ext_select, |
| 310 | clr_int_reg_50_int_state_ext_read_data, |
| 311 | clr_int_reg_51_int_state_ext_wr_data, |
| 312 | clr_int_reg_51_ext_select, |
| 313 | clr_int_reg_51_int_state_ext_read_data, |
| 314 | clr_int_reg_52_int_state_ext_wr_data, |
| 315 | clr_int_reg_52_ext_select, |
| 316 | clr_int_reg_52_int_state_ext_read_data, |
| 317 | clr_int_reg_53_int_state_ext_wr_data, |
| 318 | clr_int_reg_53_ext_select, |
| 319 | clr_int_reg_53_int_state_ext_read_data, |
| 320 | clr_int_reg_54_int_state_ext_wr_data, |
| 321 | clr_int_reg_54_ext_select, |
| 322 | clr_int_reg_54_int_state_ext_read_data, |
| 323 | clr_int_reg_55_int_state_ext_wr_data, |
| 324 | clr_int_reg_55_ext_select, |
| 325 | clr_int_reg_55_int_state_ext_read_data, |
| 326 | clr_int_reg_56_int_state_ext_wr_data, |
| 327 | clr_int_reg_56_ext_select, |
| 328 | clr_int_reg_56_int_state_ext_read_data, |
| 329 | clr_int_reg_57_int_state_ext_wr_data, |
| 330 | clr_int_reg_57_ext_select, |
| 331 | clr_int_reg_57_int_state_ext_read_data, |
| 332 | clr_int_reg_58_int_state_ext_wr_data, |
| 333 | clr_int_reg_58_ext_select, |
| 334 | clr_int_reg_58_int_state_ext_read_data, |
| 335 | clr_int_reg_59_int_state_ext_wr_data, |
| 336 | clr_int_reg_59_ext_select, |
| 337 | clr_int_reg_59_int_state_ext_read_data, |
| 338 | clr_int_reg_62_int_state_ext_wr_data, |
| 339 | clr_int_reg_62_ext_select, |
| 340 | clr_int_reg_62_int_state_ext_read_data, |
| 341 | clr_int_reg_63_int_state_ext_wr_data, |
| 342 | clr_int_reg_63_ext_select, |
| 343 | clr_int_reg_63_int_state_ext_read_data, |
| 344 | interrupt_retry_timer_limit_hw_read, |
| 345 | interrupt_state_status_1_state_ext_read_data, |
| 346 | interrupt_state_status_2_state_ext_read_data |
| 347 | ); |
| 348 | |
| 349 | //==================================================== |
| 350 | // Polarity declarations |
| 351 | //==================================================== |
| 352 | input clk; // Clock signal |
| 353 | input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus |
| 354 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 355 | input csrbus_wr; // Read/Write signal |
| 356 | input csrbus_valid; // Valid address |
| 357 | output csrbus_mapped; // Address is mapped |
| 358 | output csrbus_done; // Operation is done |
| 359 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus |
| 360 | input rst_l; // Reset signal |
| 361 | input [1:0] csrbus_src_bus; // Source bus |
| 362 | output csrbus_acc_vio; // Violation signal |
| 363 | input instance_id; // Instance ID |
| 364 | output ext_wr; // When one, csr operation is a write. When zero, operation is a |
| 365 | // read. |
| 366 | output interrupt_mapping_20_mdo_mode_hw_read; // This signal provides the |
| 367 | // current value of |
| 368 | // interrupt_mapping_20_mdo_mode. |
| 369 | output interrupt_mapping_20_v_hw_read; // This signal provides the current |
| 370 | // value of interrupt_mapping_20_v. |
| 371 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_INT_SLC] interrupt_mapping_20_t_id_hw_read; |
| 372 | // This signal provides the current value of interrupt_mapping_20_t_id. |
| 373 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_20_int_cntrl_num_hw_read; |
| 374 | // This signal provides the current value of |
| 375 | // interrupt_mapping_20_int_cntrl_num. |
| 376 | output interrupt_mapping_21_mdo_mode_hw_read; // This signal provides the |
| 377 | // current value of |
| 378 | // interrupt_mapping_21_mdo_mode. |
| 379 | output interrupt_mapping_21_v_hw_read; // This signal provides the current |
| 380 | // value of interrupt_mapping_21_v. |
| 381 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_INT_SLC] interrupt_mapping_21_t_id_hw_read; |
| 382 | // This signal provides the current value of interrupt_mapping_21_t_id. |
| 383 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_21_int_cntrl_num_hw_read; |
| 384 | // This signal provides the current value of |
| 385 | // interrupt_mapping_21_int_cntrl_num. |
| 386 | output interrupt_mapping_22_mdo_mode_hw_read; // This signal provides the |
| 387 | // current value of |
| 388 | // interrupt_mapping_22_mdo_mode. |
| 389 | output interrupt_mapping_22_v_hw_read; // This signal provides the current |
| 390 | // value of interrupt_mapping_22_v. |
| 391 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_INT_SLC] interrupt_mapping_22_t_id_hw_read; |
| 392 | // This signal provides the current value of interrupt_mapping_22_t_id. |
| 393 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_22_int_cntrl_num_hw_read; |
| 394 | // This signal provides the current value of |
| 395 | // interrupt_mapping_22_int_cntrl_num. |
| 396 | output interrupt_mapping_23_mdo_mode_hw_read; // This signal provides the |
| 397 | // current value of |
| 398 | // interrupt_mapping_23_mdo_mode. |
| 399 | output interrupt_mapping_23_v_hw_read; // This signal provides the current |
| 400 | // value of interrupt_mapping_23_v. |
| 401 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_INT_SLC] interrupt_mapping_23_t_id_hw_read; |
| 402 | // This signal provides the current value of interrupt_mapping_23_t_id. |
| 403 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_23_int_cntrl_num_hw_read; |
| 404 | // This signal provides the current value of |
| 405 | // interrupt_mapping_23_int_cntrl_num. |
| 406 | output interrupt_mapping_24_mdo_mode_hw_read; // This signal provides the |
| 407 | // current value of |
| 408 | // interrupt_mapping_24_mdo_mode. |
| 409 | output interrupt_mapping_24_v_hw_read; // This signal provides the current |
| 410 | // value of interrupt_mapping_24_v. |
| 411 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_INT_SLC] interrupt_mapping_24_t_id_hw_read; |
| 412 | // This signal provides the current value of interrupt_mapping_24_t_id. |
| 413 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_24_int_cntrl_num_hw_read; |
| 414 | // This signal provides the current value of |
| 415 | // interrupt_mapping_24_int_cntrl_num. |
| 416 | output interrupt_mapping_25_mdo_mode_hw_read; // This signal provides the |
| 417 | // current value of |
| 418 | // interrupt_mapping_25_mdo_mode. |
| 419 | output interrupt_mapping_25_v_hw_read; // This signal provides the current |
| 420 | // value of interrupt_mapping_25_v. |
| 421 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_INT_SLC] interrupt_mapping_25_t_id_hw_read; |
| 422 | // This signal provides the current value of interrupt_mapping_25_t_id. |
| 423 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_25_int_cntrl_num_hw_read; |
| 424 | // This signal provides the current value of |
| 425 | // interrupt_mapping_25_int_cntrl_num. |
| 426 | output interrupt_mapping_26_mdo_mode_hw_read; // This signal provides the |
| 427 | // current value of |
| 428 | // interrupt_mapping_26_mdo_mode. |
| 429 | output interrupt_mapping_26_v_hw_read; // This signal provides the current |
| 430 | // value of interrupt_mapping_26_v. |
| 431 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_INT_SLC] interrupt_mapping_26_t_id_hw_read; |
| 432 | // This signal provides the current value of interrupt_mapping_26_t_id. |
| 433 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_26_int_cntrl_num_hw_read; |
| 434 | // This signal provides the current value of |
| 435 | // interrupt_mapping_26_int_cntrl_num. |
| 436 | output interrupt_mapping_27_mdo_mode_hw_read; // This signal provides the |
| 437 | // current value of |
| 438 | // interrupt_mapping_27_mdo_mode. |
| 439 | output interrupt_mapping_27_v_hw_read; // This signal provides the current |
| 440 | // value of interrupt_mapping_27_v. |
| 441 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_INT_SLC] interrupt_mapping_27_t_id_hw_read; |
| 442 | // This signal provides the current value of interrupt_mapping_27_t_id. |
| 443 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_27_int_cntrl_num_hw_read; |
| 444 | // This signal provides the current value of |
| 445 | // interrupt_mapping_27_int_cntrl_num. |
| 446 | output interrupt_mapping_28_mdo_mode_hw_read; // This signal provides the |
| 447 | // current value of |
| 448 | // interrupt_mapping_28_mdo_mode. |
| 449 | output interrupt_mapping_28_v_hw_read; // This signal provides the current |
| 450 | // value of interrupt_mapping_28_v. |
| 451 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_INT_SLC] interrupt_mapping_28_t_id_hw_read; |
| 452 | // This signal provides the current value of interrupt_mapping_28_t_id. |
| 453 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_28_int_cntrl_num_hw_read; |
| 454 | // This signal provides the current value of |
| 455 | // interrupt_mapping_28_int_cntrl_num. |
| 456 | output interrupt_mapping_29_mdo_mode_hw_read; // This signal provides the |
| 457 | // current value of |
| 458 | // interrupt_mapping_29_mdo_mode. |
| 459 | output interrupt_mapping_29_v_hw_read; // This signal provides the current |
| 460 | // value of interrupt_mapping_29_v. |
| 461 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_INT_SLC] interrupt_mapping_29_t_id_hw_read; |
| 462 | // This signal provides the current value of interrupt_mapping_29_t_id. |
| 463 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_29_int_cntrl_num_hw_read; |
| 464 | // This signal provides the current value of |
| 465 | // interrupt_mapping_29_int_cntrl_num. |
| 466 | output interrupt_mapping_30_mdo_mode_hw_read; // This signal provides the |
| 467 | // current value of |
| 468 | // interrupt_mapping_30_mdo_mode. |
| 469 | output interrupt_mapping_30_v_hw_read; // This signal provides the current |
| 470 | // value of interrupt_mapping_30_v. |
| 471 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_INT_SLC] interrupt_mapping_30_t_id_hw_read; |
| 472 | // This signal provides the current value of interrupt_mapping_30_t_id. |
| 473 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_30_int_cntrl_num_hw_read; |
| 474 | // This signal provides the current value of |
| 475 | // interrupt_mapping_30_int_cntrl_num. |
| 476 | output interrupt_mapping_31_mdo_mode_hw_read; // This signal provides the |
| 477 | // current value of |
| 478 | // interrupt_mapping_31_mdo_mode. |
| 479 | output interrupt_mapping_31_v_hw_read; // This signal provides the current |
| 480 | // value of interrupt_mapping_31_v. |
| 481 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_INT_SLC] interrupt_mapping_31_t_id_hw_read; |
| 482 | // This signal provides the current value of interrupt_mapping_31_t_id. |
| 483 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_31_int_cntrl_num_hw_read; |
| 484 | // This signal provides the current value of |
| 485 | // interrupt_mapping_31_int_cntrl_num. |
| 486 | output interrupt_mapping_32_mdo_mode_hw_read; // This signal provides the |
| 487 | // current value of |
| 488 | // interrupt_mapping_32_mdo_mode. |
| 489 | output interrupt_mapping_32_v_hw_read; // This signal provides the current |
| 490 | // value of interrupt_mapping_32_v. |
| 491 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_INT_SLC] interrupt_mapping_32_t_id_hw_read; |
| 492 | // This signal provides the current value of interrupt_mapping_32_t_id. |
| 493 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_32_int_cntrl_num_hw_read; |
| 494 | // This signal provides the current value of |
| 495 | // interrupt_mapping_32_int_cntrl_num. |
| 496 | output interrupt_mapping_33_mdo_mode_hw_read; // This signal provides the |
| 497 | // current value of |
| 498 | // interrupt_mapping_33_mdo_mode. |
| 499 | output interrupt_mapping_33_v_hw_read; // This signal provides the current |
| 500 | // value of interrupt_mapping_33_v. |
| 501 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_INT_SLC] interrupt_mapping_33_t_id_hw_read; |
| 502 | // This signal provides the current value of interrupt_mapping_33_t_id. |
| 503 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_33_int_cntrl_num_hw_read; |
| 504 | // This signal provides the current value of |
| 505 | // interrupt_mapping_33_int_cntrl_num. |
| 506 | output interrupt_mapping_34_mdo_mode_hw_read; // This signal provides the |
| 507 | // current value of |
| 508 | // interrupt_mapping_34_mdo_mode. |
| 509 | output interrupt_mapping_34_v_hw_read; // This signal provides the current |
| 510 | // value of interrupt_mapping_34_v. |
| 511 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_INT_SLC] interrupt_mapping_34_t_id_hw_read; |
| 512 | // This signal provides the current value of interrupt_mapping_34_t_id. |
| 513 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_34_int_cntrl_num_hw_read; |
| 514 | // This signal provides the current value of |
| 515 | // interrupt_mapping_34_int_cntrl_num. |
| 516 | output interrupt_mapping_35_mdo_mode_hw_read; // This signal provides the |
| 517 | // current value of |
| 518 | // interrupt_mapping_35_mdo_mode. |
| 519 | output interrupt_mapping_35_v_hw_read; // This signal provides the current |
| 520 | // value of interrupt_mapping_35_v. |
| 521 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_INT_SLC] interrupt_mapping_35_t_id_hw_read; |
| 522 | // This signal provides the current value of interrupt_mapping_35_t_id. |
| 523 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_35_int_cntrl_num_hw_read; |
| 524 | // This signal provides the current value of |
| 525 | // interrupt_mapping_35_int_cntrl_num. |
| 526 | output interrupt_mapping_36_mdo_mode_hw_read; // This signal provides the |
| 527 | // current value of |
| 528 | // interrupt_mapping_36_mdo_mode. |
| 529 | output interrupt_mapping_36_v_hw_read; // This signal provides the current |
| 530 | // value of interrupt_mapping_36_v. |
| 531 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_INT_SLC] interrupt_mapping_36_t_id_hw_read; |
| 532 | // This signal provides the current value of interrupt_mapping_36_t_id. |
| 533 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_36_int_cntrl_num_hw_read; |
| 534 | // This signal provides the current value of |
| 535 | // interrupt_mapping_36_int_cntrl_num. |
| 536 | output interrupt_mapping_37_mdo_mode_hw_read; // This signal provides the |
| 537 | // current value of |
| 538 | // interrupt_mapping_37_mdo_mode. |
| 539 | output interrupt_mapping_37_v_hw_read; // This signal provides the current |
| 540 | // value of interrupt_mapping_37_v. |
| 541 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_INT_SLC] interrupt_mapping_37_t_id_hw_read; |
| 542 | // This signal provides the current value of interrupt_mapping_37_t_id. |
| 543 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_37_int_cntrl_num_hw_read; |
| 544 | // This signal provides the current value of |
| 545 | // interrupt_mapping_37_int_cntrl_num. |
| 546 | output interrupt_mapping_38_mdo_mode_hw_read; // This signal provides the |
| 547 | // current value of |
| 548 | // interrupt_mapping_38_mdo_mode. |
| 549 | output interrupt_mapping_38_v_hw_read; // This signal provides the current |
| 550 | // value of interrupt_mapping_38_v. |
| 551 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_INT_SLC] interrupt_mapping_38_t_id_hw_read; |
| 552 | // This signal provides the current value of interrupt_mapping_38_t_id. |
| 553 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_38_int_cntrl_num_hw_read; |
| 554 | // This signal provides the current value of |
| 555 | // interrupt_mapping_38_int_cntrl_num. |
| 556 | output interrupt_mapping_39_mdo_mode_hw_read; // This signal provides the |
| 557 | // current value of |
| 558 | // interrupt_mapping_39_mdo_mode. |
| 559 | output interrupt_mapping_39_v_hw_read; // This signal provides the current |
| 560 | // value of interrupt_mapping_39_v. |
| 561 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_INT_SLC] interrupt_mapping_39_t_id_hw_read; |
| 562 | // This signal provides the current value of interrupt_mapping_39_t_id. |
| 563 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_39_int_cntrl_num_hw_read; |
| 564 | // This signal provides the current value of |
| 565 | // interrupt_mapping_39_int_cntrl_num. |
| 566 | output interrupt_mapping_40_mdo_mode_hw_read; // This signal provides the |
| 567 | // current value of |
| 568 | // interrupt_mapping_40_mdo_mode. |
| 569 | output interrupt_mapping_40_v_hw_read; // This signal provides the current |
| 570 | // value of interrupt_mapping_40_v. |
| 571 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_INT_SLC] interrupt_mapping_40_t_id_hw_read; |
| 572 | // This signal provides the current value of interrupt_mapping_40_t_id. |
| 573 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_40_int_cntrl_num_hw_read; |
| 574 | // This signal provides the current value of |
| 575 | // interrupt_mapping_40_int_cntrl_num. |
| 576 | output interrupt_mapping_41_mdo_mode_hw_read; // This signal provides the |
| 577 | // current value of |
| 578 | // interrupt_mapping_41_mdo_mode. |
| 579 | output interrupt_mapping_41_v_hw_read; // This signal provides the current |
| 580 | // value of interrupt_mapping_41_v. |
| 581 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_INT_SLC] interrupt_mapping_41_t_id_hw_read; |
| 582 | // This signal provides the current value of interrupt_mapping_41_t_id. |
| 583 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_41_int_cntrl_num_hw_read; |
| 584 | // This signal provides the current value of |
| 585 | // interrupt_mapping_41_int_cntrl_num. |
| 586 | output interrupt_mapping_42_mdo_mode_hw_read; // This signal provides the |
| 587 | // current value of |
| 588 | // interrupt_mapping_42_mdo_mode. |
| 589 | output interrupt_mapping_42_v_hw_read; // This signal provides the current |
| 590 | // value of interrupt_mapping_42_v. |
| 591 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC] interrupt_mapping_42_t_id_hw_read; |
| 592 | // This signal provides the current value of interrupt_mapping_42_t_id. |
| 593 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_42_int_cntrl_num_hw_read; |
| 594 | // This signal provides the current value of |
| 595 | // interrupt_mapping_42_int_cntrl_num. |
| 596 | output interrupt_mapping_43_mdo_mode_hw_read; // This signal provides the |
| 597 | // current value of |
| 598 | // interrupt_mapping_43_mdo_mode. |
| 599 | output interrupt_mapping_43_v_hw_read; // This signal provides the current |
| 600 | // value of interrupt_mapping_43_v. |
| 601 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_INT_SLC] interrupt_mapping_43_t_id_hw_read; |
| 602 | // This signal provides the current value of interrupt_mapping_43_t_id. |
| 603 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_43_int_cntrl_num_hw_read; |
| 604 | // This signal provides the current value of |
| 605 | // interrupt_mapping_43_int_cntrl_num. |
| 606 | output interrupt_mapping_44_mdo_mode_hw_read; // This signal provides the |
| 607 | // current value of |
| 608 | // interrupt_mapping_44_mdo_mode. |
| 609 | output interrupt_mapping_44_v_hw_read; // This signal provides the current |
| 610 | // value of interrupt_mapping_44_v. |
| 611 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_INT_SLC] interrupt_mapping_44_t_id_hw_read; |
| 612 | // This signal provides the current value of interrupt_mapping_44_t_id. |
| 613 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_44_int_cntrl_num_hw_read; |
| 614 | // This signal provides the current value of |
| 615 | // interrupt_mapping_44_int_cntrl_num. |
| 616 | output interrupt_mapping_45_mdo_mode_hw_read; // This signal provides the |
| 617 | // current value of |
| 618 | // interrupt_mapping_45_mdo_mode. |
| 619 | output interrupt_mapping_45_v_hw_read; // This signal provides the current |
| 620 | // value of interrupt_mapping_45_v. |
| 621 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_INT_SLC] interrupt_mapping_45_t_id_hw_read; |
| 622 | // This signal provides the current value of interrupt_mapping_45_t_id. |
| 623 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_45_int_cntrl_num_hw_read; |
| 624 | // This signal provides the current value of |
| 625 | // interrupt_mapping_45_int_cntrl_num. |
| 626 | output interrupt_mapping_46_mdo_mode_hw_read; // This signal provides the |
| 627 | // current value of |
| 628 | // interrupt_mapping_46_mdo_mode. |
| 629 | output interrupt_mapping_46_v_hw_read; // This signal provides the current |
| 630 | // value of interrupt_mapping_46_v. |
| 631 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_INT_SLC] interrupt_mapping_46_t_id_hw_read; |
| 632 | // This signal provides the current value of interrupt_mapping_46_t_id. |
| 633 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_46_int_cntrl_num_hw_read; |
| 634 | // This signal provides the current value of |
| 635 | // interrupt_mapping_46_int_cntrl_num. |
| 636 | output interrupt_mapping_47_mdo_mode_hw_read; // This signal provides the |
| 637 | // current value of |
| 638 | // interrupt_mapping_47_mdo_mode. |
| 639 | output interrupt_mapping_47_v_hw_read; // This signal provides the current |
| 640 | // value of interrupt_mapping_47_v. |
| 641 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_INT_SLC] interrupt_mapping_47_t_id_hw_read; |
| 642 | // This signal provides the current value of interrupt_mapping_47_t_id. |
| 643 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_47_int_cntrl_num_hw_read; |
| 644 | // This signal provides the current value of |
| 645 | // interrupt_mapping_47_int_cntrl_num. |
| 646 | output interrupt_mapping_48_mdo_mode_hw_read; // This signal provides the |
| 647 | // current value of |
| 648 | // interrupt_mapping_48_mdo_mode. |
| 649 | output interrupt_mapping_48_v_hw_read; // This signal provides the current |
| 650 | // value of interrupt_mapping_48_v. |
| 651 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_INT_SLC] interrupt_mapping_48_t_id_hw_read; |
| 652 | // This signal provides the current value of interrupt_mapping_48_t_id. |
| 653 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_48_int_cntrl_num_hw_read; |
| 654 | // This signal provides the current value of |
| 655 | // interrupt_mapping_48_int_cntrl_num. |
| 656 | output interrupt_mapping_49_mdo_mode_hw_read; // This signal provides the |
| 657 | // current value of |
| 658 | // interrupt_mapping_49_mdo_mode. |
| 659 | output interrupt_mapping_49_v_hw_read; // This signal provides the current |
| 660 | // value of interrupt_mapping_49_v. |
| 661 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_INT_SLC] interrupt_mapping_49_t_id_hw_read; |
| 662 | // This signal provides the current value of interrupt_mapping_49_t_id. |
| 663 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_49_int_cntrl_num_hw_read; |
| 664 | // This signal provides the current value of |
| 665 | // interrupt_mapping_49_int_cntrl_num. |
| 666 | output interrupt_mapping_50_mdo_mode_hw_read; // This signal provides the |
| 667 | // current value of |
| 668 | // interrupt_mapping_50_mdo_mode. |
| 669 | output interrupt_mapping_50_v_hw_read; // This signal provides the current |
| 670 | // value of interrupt_mapping_50_v. |
| 671 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_INT_SLC] interrupt_mapping_50_t_id_hw_read; |
| 672 | // This signal provides the current value of interrupt_mapping_50_t_id. |
| 673 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_50_int_cntrl_num_hw_read; |
| 674 | // This signal provides the current value of |
| 675 | // interrupt_mapping_50_int_cntrl_num. |
| 676 | output interrupt_mapping_51_mdo_mode_hw_read; // This signal provides the |
| 677 | // current value of |
| 678 | // interrupt_mapping_51_mdo_mode. |
| 679 | output interrupt_mapping_51_v_hw_read; // This signal provides the current |
| 680 | // value of interrupt_mapping_51_v. |
| 681 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_INT_SLC] interrupt_mapping_51_t_id_hw_read; |
| 682 | // This signal provides the current value of interrupt_mapping_51_t_id. |
| 683 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_51_int_cntrl_num_hw_read; |
| 684 | // This signal provides the current value of |
| 685 | // interrupt_mapping_51_int_cntrl_num. |
| 686 | output interrupt_mapping_52_mdo_mode_hw_read; // This signal provides the |
| 687 | // current value of |
| 688 | // interrupt_mapping_52_mdo_mode. |
| 689 | output interrupt_mapping_52_v_hw_read; // This signal provides the current |
| 690 | // value of interrupt_mapping_52_v. |
| 691 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_INT_SLC] interrupt_mapping_52_t_id_hw_read; |
| 692 | // This signal provides the current value of interrupt_mapping_52_t_id. |
| 693 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_52_int_cntrl_num_hw_read; |
| 694 | // This signal provides the current value of |
| 695 | // interrupt_mapping_52_int_cntrl_num. |
| 696 | output interrupt_mapping_53_mdo_mode_hw_read; // This signal provides the |
| 697 | // current value of |
| 698 | // interrupt_mapping_53_mdo_mode. |
| 699 | output interrupt_mapping_53_v_hw_read; // This signal provides the current |
| 700 | // value of interrupt_mapping_53_v. |
| 701 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_INT_SLC] interrupt_mapping_53_t_id_hw_read; |
| 702 | // This signal provides the current value of interrupt_mapping_53_t_id. |
| 703 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_53_int_cntrl_num_hw_read; |
| 704 | // This signal provides the current value of |
| 705 | // interrupt_mapping_53_int_cntrl_num. |
| 706 | output interrupt_mapping_54_mdo_mode_hw_read; // This signal provides the |
| 707 | // current value of |
| 708 | // interrupt_mapping_54_mdo_mode. |
| 709 | output interrupt_mapping_54_v_hw_read; // This signal provides the current |
| 710 | // value of interrupt_mapping_54_v. |
| 711 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_INT_SLC] interrupt_mapping_54_t_id_hw_read; |
| 712 | // This signal provides the current value of interrupt_mapping_54_t_id. |
| 713 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_54_int_cntrl_num_hw_read; |
| 714 | // This signal provides the current value of |
| 715 | // interrupt_mapping_54_int_cntrl_num. |
| 716 | output interrupt_mapping_55_mdo_mode_hw_read; // This signal provides the |
| 717 | // current value of |
| 718 | // interrupt_mapping_55_mdo_mode. |
| 719 | output interrupt_mapping_55_v_hw_read; // This signal provides the current |
| 720 | // value of interrupt_mapping_55_v. |
| 721 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_INT_SLC] interrupt_mapping_55_t_id_hw_read; |
| 722 | // This signal provides the current value of interrupt_mapping_55_t_id. |
| 723 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_55_int_cntrl_num_hw_read; |
| 724 | // This signal provides the current value of |
| 725 | // interrupt_mapping_55_int_cntrl_num. |
| 726 | output interrupt_mapping_56_mdo_mode_hw_read; // This signal provides the |
| 727 | // current value of |
| 728 | // interrupt_mapping_56_mdo_mode. |
| 729 | output interrupt_mapping_56_v_hw_read; // This signal provides the current |
| 730 | // value of interrupt_mapping_56_v. |
| 731 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_INT_SLC] interrupt_mapping_56_t_id_hw_read; |
| 732 | // This signal provides the current value of interrupt_mapping_56_t_id. |
| 733 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_56_int_cntrl_num_hw_read; |
| 734 | // This signal provides the current value of |
| 735 | // interrupt_mapping_56_int_cntrl_num. |
| 736 | output interrupt_mapping_57_mdo_mode_hw_read; // This signal provides the |
| 737 | // current value of |
| 738 | // interrupt_mapping_57_mdo_mode. |
| 739 | output interrupt_mapping_57_v_hw_read; // This signal provides the current |
| 740 | // value of interrupt_mapping_57_v. |
| 741 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_INT_SLC] interrupt_mapping_57_t_id_hw_read; |
| 742 | // This signal provides the current value of interrupt_mapping_57_t_id. |
| 743 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_57_int_cntrl_num_hw_read; |
| 744 | // This signal provides the current value of |
| 745 | // interrupt_mapping_57_int_cntrl_num. |
| 746 | output interrupt_mapping_58_mdo_mode_hw_read; // This signal provides the |
| 747 | // current value of |
| 748 | // interrupt_mapping_58_mdo_mode. |
| 749 | output interrupt_mapping_58_v_hw_read; // This signal provides the current |
| 750 | // value of interrupt_mapping_58_v. |
| 751 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_INT_SLC] interrupt_mapping_58_t_id_hw_read; |
| 752 | // This signal provides the current value of interrupt_mapping_58_t_id. |
| 753 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_58_int_cntrl_num_hw_read; |
| 754 | // This signal provides the current value of |
| 755 | // interrupt_mapping_58_int_cntrl_num. |
| 756 | output interrupt_mapping_59_mdo_mode_hw_read; // This signal provides the |
| 757 | // current value of |
| 758 | // interrupt_mapping_59_mdo_mode. |
| 759 | output interrupt_mapping_59_v_hw_read; // This signal provides the current |
| 760 | // value of interrupt_mapping_59_v. |
| 761 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_INT_SLC] interrupt_mapping_59_t_id_hw_read; |
| 762 | // This signal provides the current value of interrupt_mapping_59_t_id. |
| 763 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_59_int_cntrl_num_hw_read; |
| 764 | // This signal provides the current value of |
| 765 | // interrupt_mapping_59_int_cntrl_num. |
| 766 | output interrupt_mapping_62_mdo_mode_hw_read; // This signal provides the |
| 767 | // current value of |
| 768 | // interrupt_mapping_62_mdo_mode. |
| 769 | output interrupt_mapping_62_v_hw_read; // This signal provides the current |
| 770 | // value of interrupt_mapping_62_v. |
| 771 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_INT_SLC] interrupt_mapping_62_t_id_hw_read; |
| 772 | // This signal provides the current value of interrupt_mapping_62_t_id. |
| 773 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_62_int_cntrl_num_hw_read; |
| 774 | // This signal provides the current value of |
| 775 | // interrupt_mapping_62_int_cntrl_num. |
| 776 | output interrupt_mapping_63_mdo_mode_hw_read; // This signal provides the |
| 777 | // current value of |
| 778 | // interrupt_mapping_63_mdo_mode. |
| 779 | output interrupt_mapping_63_v_hw_read; // This signal provides the current |
| 780 | // value of interrupt_mapping_63_v. |
| 781 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_INT_SLC] interrupt_mapping_63_t_id_hw_read; |
| 782 | // This signal provides the current value of interrupt_mapping_63_t_id. |
| 783 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_63_int_cntrl_num_hw_read; |
| 784 | // This signal provides the current value of |
| 785 | // interrupt_mapping_63_int_cntrl_num. |
| 786 | output [1:0] clr_int_reg_20_int_state_ext_wr_data; // Provides SW write data |
| 787 | // for external register |
| 788 | // "clr_int_reg_20", field |
| 789 | // "int_state" |
| 790 | output clr_int_reg_20_ext_select; // When set, register clr_int_reg_20 is |
| 791 | // selected. This signal is a pulse. |
| 792 | input [1:0] clr_int_reg_20_int_state_ext_read_data; // Ext read data (decode) |
| 793 | output [1:0] clr_int_reg_21_int_state_ext_wr_data; // Provides SW write data |
| 794 | // for external register |
| 795 | // "clr_int_reg_21", field |
| 796 | // "int_state" |
| 797 | output clr_int_reg_21_ext_select; // When set, register clr_int_reg_21 is |
| 798 | // selected. This signal is a pulse. |
| 799 | input [1:0] clr_int_reg_21_int_state_ext_read_data; // Ext read data (decode) |
| 800 | output [1:0] clr_int_reg_22_int_state_ext_wr_data; // Provides SW write data |
| 801 | // for external register |
| 802 | // "clr_int_reg_22", field |
| 803 | // "int_state" |
| 804 | output clr_int_reg_22_ext_select; // When set, register clr_int_reg_22 is |
| 805 | // selected. This signal is a pulse. |
| 806 | input [1:0] clr_int_reg_22_int_state_ext_read_data; // Ext read data (decode) |
| 807 | output [1:0] clr_int_reg_23_int_state_ext_wr_data; // Provides SW write data |
| 808 | // for external register |
| 809 | // "clr_int_reg_23", field |
| 810 | // "int_state" |
| 811 | output clr_int_reg_23_ext_select; // When set, register clr_int_reg_23 is |
| 812 | // selected. This signal is a pulse. |
| 813 | input [1:0] clr_int_reg_23_int_state_ext_read_data; // Ext read data (decode) |
| 814 | output [1:0] clr_int_reg_24_int_state_ext_wr_data; // Provides SW write data |
| 815 | // for external register |
| 816 | // "clr_int_reg_24", field |
| 817 | // "int_state" |
| 818 | output clr_int_reg_24_ext_select; // When set, register clr_int_reg_24 is |
| 819 | // selected. This signal is a pulse. |
| 820 | input [1:0] clr_int_reg_24_int_state_ext_read_data; // Ext read data (decode) |
| 821 | output [1:0] clr_int_reg_25_int_state_ext_wr_data; // Provides SW write data |
| 822 | // for external register |
| 823 | // "clr_int_reg_25", field |
| 824 | // "int_state" |
| 825 | output clr_int_reg_25_ext_select; // When set, register clr_int_reg_25 is |
| 826 | // selected. This signal is a pulse. |
| 827 | input [1:0] clr_int_reg_25_int_state_ext_read_data; // Ext read data (decode) |
| 828 | output [1:0] clr_int_reg_26_int_state_ext_wr_data; // Provides SW write data |
| 829 | // for external register |
| 830 | // "clr_int_reg_26", field |
| 831 | // "int_state" |
| 832 | output clr_int_reg_26_ext_select; // When set, register clr_int_reg_26 is |
| 833 | // selected. This signal is a pulse. |
| 834 | input [1:0] clr_int_reg_26_int_state_ext_read_data; // Ext read data (decode) |
| 835 | output [1:0] clr_int_reg_27_int_state_ext_wr_data; // Provides SW write data |
| 836 | // for external register |
| 837 | // "clr_int_reg_27", field |
| 838 | // "int_state" |
| 839 | output clr_int_reg_27_ext_select; // When set, register clr_int_reg_27 is |
| 840 | // selected. This signal is a pulse. |
| 841 | input [1:0] clr_int_reg_27_int_state_ext_read_data; // Ext read data (decode) |
| 842 | output [1:0] clr_int_reg_28_int_state_ext_wr_data; // Provides SW write data |
| 843 | // for external register |
| 844 | // "clr_int_reg_28", field |
| 845 | // "int_state" |
| 846 | output clr_int_reg_28_ext_select; // When set, register clr_int_reg_28 is |
| 847 | // selected. This signal is a pulse. |
| 848 | input [1:0] clr_int_reg_28_int_state_ext_read_data; // Ext read data (decode) |
| 849 | output [1:0] clr_int_reg_29_int_state_ext_wr_data; // Provides SW write data |
| 850 | // for external register |
| 851 | // "clr_int_reg_29", field |
| 852 | // "int_state" |
| 853 | output clr_int_reg_29_ext_select; // When set, register clr_int_reg_29 is |
| 854 | // selected. This signal is a pulse. |
| 855 | input [1:0] clr_int_reg_29_int_state_ext_read_data; // Ext read data (decode) |
| 856 | output [1:0] clr_int_reg_30_int_state_ext_wr_data; // Provides SW write data |
| 857 | // for external register |
| 858 | // "clr_int_reg_30", field |
| 859 | // "int_state" |
| 860 | output clr_int_reg_30_ext_select; // When set, register clr_int_reg_30 is |
| 861 | // selected. This signal is a pulse. |
| 862 | input [1:0] clr_int_reg_30_int_state_ext_read_data; // Ext read data (decode) |
| 863 | output [1:0] clr_int_reg_31_int_state_ext_wr_data; // Provides SW write data |
| 864 | // for external register |
| 865 | // "clr_int_reg_31", field |
| 866 | // "int_state" |
| 867 | output clr_int_reg_31_ext_select; // When set, register clr_int_reg_31 is |
| 868 | // selected. This signal is a pulse. |
| 869 | input [1:0] clr_int_reg_31_int_state_ext_read_data; // Ext read data (decode) |
| 870 | output [1:0] clr_int_reg_32_int_state_ext_wr_data; // Provides SW write data |
| 871 | // for external register |
| 872 | // "clr_int_reg_32", field |
| 873 | // "int_state" |
| 874 | output clr_int_reg_32_ext_select; // When set, register clr_int_reg_32 is |
| 875 | // selected. This signal is a pulse. |
| 876 | input [1:0] clr_int_reg_32_int_state_ext_read_data; // Ext read data (decode) |
| 877 | output [1:0] clr_int_reg_33_int_state_ext_wr_data; // Provides SW write data |
| 878 | // for external register |
| 879 | // "clr_int_reg_33", field |
| 880 | // "int_state" |
| 881 | output clr_int_reg_33_ext_select; // When set, register clr_int_reg_33 is |
| 882 | // selected. This signal is a pulse. |
| 883 | input [1:0] clr_int_reg_33_int_state_ext_read_data; // Ext read data (decode) |
| 884 | output [1:0] clr_int_reg_34_int_state_ext_wr_data; // Provides SW write data |
| 885 | // for external register |
| 886 | // "clr_int_reg_34", field |
| 887 | // "int_state" |
| 888 | output clr_int_reg_34_ext_select; // When set, register clr_int_reg_34 is |
| 889 | // selected. This signal is a pulse. |
| 890 | input [1:0] clr_int_reg_34_int_state_ext_read_data; // Ext read data (decode) |
| 891 | output [1:0] clr_int_reg_35_int_state_ext_wr_data; // Provides SW write data |
| 892 | // for external register |
| 893 | // "clr_int_reg_35", field |
| 894 | // "int_state" |
| 895 | output clr_int_reg_35_ext_select; // When set, register clr_int_reg_35 is |
| 896 | // selected. This signal is a pulse. |
| 897 | input [1:0] clr_int_reg_35_int_state_ext_read_data; // Ext read data (decode) |
| 898 | output [1:0] clr_int_reg_36_int_state_ext_wr_data; // Provides SW write data |
| 899 | // for external register |
| 900 | // "clr_int_reg_36", field |
| 901 | // "int_state" |
| 902 | output clr_int_reg_36_ext_select; // When set, register clr_int_reg_36 is |
| 903 | // selected. This signal is a pulse. |
| 904 | input [1:0] clr_int_reg_36_int_state_ext_read_data; // Ext read data (decode) |
| 905 | output [1:0] clr_int_reg_37_int_state_ext_wr_data; // Provides SW write data |
| 906 | // for external register |
| 907 | // "clr_int_reg_37", field |
| 908 | // "int_state" |
| 909 | output clr_int_reg_37_ext_select; // When set, register clr_int_reg_37 is |
| 910 | // selected. This signal is a pulse. |
| 911 | input [1:0] clr_int_reg_37_int_state_ext_read_data; // Ext read data (decode) |
| 912 | output [1:0] clr_int_reg_38_int_state_ext_wr_data; // Provides SW write data |
| 913 | // for external register |
| 914 | // "clr_int_reg_38", field |
| 915 | // "int_state" |
| 916 | output clr_int_reg_38_ext_select; // When set, register clr_int_reg_38 is |
| 917 | // selected. This signal is a pulse. |
| 918 | input [1:0] clr_int_reg_38_int_state_ext_read_data; // Ext read data (decode) |
| 919 | output [1:0] clr_int_reg_39_int_state_ext_wr_data; // Provides SW write data |
| 920 | // for external register |
| 921 | // "clr_int_reg_39", field |
| 922 | // "int_state" |
| 923 | output clr_int_reg_39_ext_select; // When set, register clr_int_reg_39 is |
| 924 | // selected. This signal is a pulse. |
| 925 | input [1:0] clr_int_reg_39_int_state_ext_read_data; // Ext read data (decode) |
| 926 | output [1:0] clr_int_reg_40_int_state_ext_wr_data; // Provides SW write data |
| 927 | // for external register |
| 928 | // "clr_int_reg_40", field |
| 929 | // "int_state" |
| 930 | output clr_int_reg_40_ext_select; // When set, register clr_int_reg_40 is |
| 931 | // selected. This signal is a pulse. |
| 932 | input [1:0] clr_int_reg_40_int_state_ext_read_data; // Ext read data (decode) |
| 933 | output [1:0] clr_int_reg_41_int_state_ext_wr_data; // Provides SW write data |
| 934 | // for external register |
| 935 | // "clr_int_reg_41", field |
| 936 | // "int_state" |
| 937 | output clr_int_reg_41_ext_select; // When set, register clr_int_reg_41 is |
| 938 | // selected. This signal is a pulse. |
| 939 | input [1:0] clr_int_reg_41_int_state_ext_read_data; // Ext read data (decode) |
| 940 | output [1:0] clr_int_reg_42_int_state_ext_wr_data; // Provides SW write data |
| 941 | // for external register |
| 942 | // "clr_int_reg_42", field |
| 943 | // "int_state" |
| 944 | output clr_int_reg_42_ext_select; // When set, register clr_int_reg_42 is |
| 945 | // selected. This signal is a pulse. |
| 946 | input [1:0] clr_int_reg_42_int_state_ext_read_data; // Ext read data (decode) |
| 947 | output [1:0] clr_int_reg_43_int_state_ext_wr_data; // Provides SW write data |
| 948 | // for external register |
| 949 | // "clr_int_reg_43", field |
| 950 | // "int_state" |
| 951 | output clr_int_reg_43_ext_select; // When set, register clr_int_reg_43 is |
| 952 | // selected. This signal is a pulse. |
| 953 | input [1:0] clr_int_reg_43_int_state_ext_read_data; // Ext read data (decode) |
| 954 | output [1:0] clr_int_reg_44_int_state_ext_wr_data; // Provides SW write data |
| 955 | // for external register |
| 956 | // "clr_int_reg_44", field |
| 957 | // "int_state" |
| 958 | output clr_int_reg_44_ext_select; // When set, register clr_int_reg_44 is |
| 959 | // selected. This signal is a pulse. |
| 960 | input [1:0] clr_int_reg_44_int_state_ext_read_data; // Ext read data (decode) |
| 961 | output [1:0] clr_int_reg_45_int_state_ext_wr_data; // Provides SW write data |
| 962 | // for external register |
| 963 | // "clr_int_reg_45", field |
| 964 | // "int_state" |
| 965 | output clr_int_reg_45_ext_select; // When set, register clr_int_reg_45 is |
| 966 | // selected. This signal is a pulse. |
| 967 | input [1:0] clr_int_reg_45_int_state_ext_read_data; // Ext read data (decode) |
| 968 | output [1:0] clr_int_reg_46_int_state_ext_wr_data; // Provides SW write data |
| 969 | // for external register |
| 970 | // "clr_int_reg_46", field |
| 971 | // "int_state" |
| 972 | output clr_int_reg_46_ext_select; // When set, register clr_int_reg_46 is |
| 973 | // selected. This signal is a pulse. |
| 974 | input [1:0] clr_int_reg_46_int_state_ext_read_data; // Ext read data (decode) |
| 975 | output [1:0] clr_int_reg_47_int_state_ext_wr_data; // Provides SW write data |
| 976 | // for external register |
| 977 | // "clr_int_reg_47", field |
| 978 | // "int_state" |
| 979 | output clr_int_reg_47_ext_select; // When set, register clr_int_reg_47 is |
| 980 | // selected. This signal is a pulse. |
| 981 | input [1:0] clr_int_reg_47_int_state_ext_read_data; // Ext read data (decode) |
| 982 | output [1:0] clr_int_reg_48_int_state_ext_wr_data; // Provides SW write data |
| 983 | // for external register |
| 984 | // "clr_int_reg_48", field |
| 985 | // "int_state" |
| 986 | output clr_int_reg_48_ext_select; // When set, register clr_int_reg_48 is |
| 987 | // selected. This signal is a pulse. |
| 988 | input [1:0] clr_int_reg_48_int_state_ext_read_data; // Ext read data (decode) |
| 989 | output [1:0] clr_int_reg_49_int_state_ext_wr_data; // Provides SW write data |
| 990 | // for external register |
| 991 | // "clr_int_reg_49", field |
| 992 | // "int_state" |
| 993 | output clr_int_reg_49_ext_select; // When set, register clr_int_reg_49 is |
| 994 | // selected. This signal is a pulse. |
| 995 | input [1:0] clr_int_reg_49_int_state_ext_read_data; // Ext read data (decode) |
| 996 | output [1:0] clr_int_reg_50_int_state_ext_wr_data; // Provides SW write data |
| 997 | // for external register |
| 998 | // "clr_int_reg_50", field |
| 999 | // "int_state" |
| 1000 | output clr_int_reg_50_ext_select; // When set, register clr_int_reg_50 is |
| 1001 | // selected. This signal is a pulse. |
| 1002 | input [1:0] clr_int_reg_50_int_state_ext_read_data; // Ext read data (decode) |
| 1003 | output [1:0] clr_int_reg_51_int_state_ext_wr_data; // Provides SW write data |
| 1004 | // for external register |
| 1005 | // "clr_int_reg_51", field |
| 1006 | // "int_state" |
| 1007 | output clr_int_reg_51_ext_select; // When set, register clr_int_reg_51 is |
| 1008 | // selected. This signal is a pulse. |
| 1009 | input [1:0] clr_int_reg_51_int_state_ext_read_data; // Ext read data (decode) |
| 1010 | output [1:0] clr_int_reg_52_int_state_ext_wr_data; // Provides SW write data |
| 1011 | // for external register |
| 1012 | // "clr_int_reg_52", field |
| 1013 | // "int_state" |
| 1014 | output clr_int_reg_52_ext_select; // When set, register clr_int_reg_52 is |
| 1015 | // selected. This signal is a pulse. |
| 1016 | input [1:0] clr_int_reg_52_int_state_ext_read_data; // Ext read data (decode) |
| 1017 | output [1:0] clr_int_reg_53_int_state_ext_wr_data; // Provides SW write data |
| 1018 | // for external register |
| 1019 | // "clr_int_reg_53", field |
| 1020 | // "int_state" |
| 1021 | output clr_int_reg_53_ext_select; // When set, register clr_int_reg_53 is |
| 1022 | // selected. This signal is a pulse. |
| 1023 | input [1:0] clr_int_reg_53_int_state_ext_read_data; // Ext read data (decode) |
| 1024 | output [1:0] clr_int_reg_54_int_state_ext_wr_data; // Provides SW write data |
| 1025 | // for external register |
| 1026 | // "clr_int_reg_54", field |
| 1027 | // "int_state" |
| 1028 | output clr_int_reg_54_ext_select; // When set, register clr_int_reg_54 is |
| 1029 | // selected. This signal is a pulse. |
| 1030 | input [1:0] clr_int_reg_54_int_state_ext_read_data; // Ext read data (decode) |
| 1031 | output [1:0] clr_int_reg_55_int_state_ext_wr_data; // Provides SW write data |
| 1032 | // for external register |
| 1033 | // "clr_int_reg_55", field |
| 1034 | // "int_state" |
| 1035 | output clr_int_reg_55_ext_select; // When set, register clr_int_reg_55 is |
| 1036 | // selected. This signal is a pulse. |
| 1037 | input [1:0] clr_int_reg_55_int_state_ext_read_data; // Ext read data (decode) |
| 1038 | output [1:0] clr_int_reg_56_int_state_ext_wr_data; // Provides SW write data |
| 1039 | // for external register |
| 1040 | // "clr_int_reg_56", field |
| 1041 | // "int_state" |
| 1042 | output clr_int_reg_56_ext_select; // When set, register clr_int_reg_56 is |
| 1043 | // selected. This signal is a pulse. |
| 1044 | input [1:0] clr_int_reg_56_int_state_ext_read_data; // Ext read data (decode) |
| 1045 | output [1:0] clr_int_reg_57_int_state_ext_wr_data; // Provides SW write data |
| 1046 | // for external register |
| 1047 | // "clr_int_reg_57", field |
| 1048 | // "int_state" |
| 1049 | output clr_int_reg_57_ext_select; // When set, register clr_int_reg_57 is |
| 1050 | // selected. This signal is a pulse. |
| 1051 | input [1:0] clr_int_reg_57_int_state_ext_read_data; // Ext read data (decode) |
| 1052 | output [1:0] clr_int_reg_58_int_state_ext_wr_data; // Provides SW write data |
| 1053 | // for external register |
| 1054 | // "clr_int_reg_58", field |
| 1055 | // "int_state" |
| 1056 | output clr_int_reg_58_ext_select; // When set, register clr_int_reg_58 is |
| 1057 | // selected. This signal is a pulse. |
| 1058 | input [1:0] clr_int_reg_58_int_state_ext_read_data; // Ext read data (decode) |
| 1059 | output [1:0] clr_int_reg_59_int_state_ext_wr_data; // Provides SW write data |
| 1060 | // for external register |
| 1061 | // "clr_int_reg_59", field |
| 1062 | // "int_state" |
| 1063 | output clr_int_reg_59_ext_select; // When set, register clr_int_reg_59 is |
| 1064 | // selected. This signal is a pulse. |
| 1065 | input [1:0] clr_int_reg_59_int_state_ext_read_data; // Ext read data (decode) |
| 1066 | output [1:0] clr_int_reg_62_int_state_ext_wr_data; // Provides SW write data |
| 1067 | // for external register |
| 1068 | // "clr_int_reg_62", field |
| 1069 | // "int_state" |
| 1070 | output clr_int_reg_62_ext_select; // When set, register clr_int_reg_62 is |
| 1071 | // selected. This signal is a pulse. |
| 1072 | input [1:0] clr_int_reg_62_int_state_ext_read_data; // Ext read data (decode) |
| 1073 | output [1:0] clr_int_reg_63_int_state_ext_wr_data; // Provides SW write data |
| 1074 | // for external register |
| 1075 | // "clr_int_reg_63", field |
| 1076 | // "int_state" |
| 1077 | output clr_int_reg_63_ext_select; // When set, register clr_int_reg_63 is |
| 1078 | // selected. This signal is a pulse. |
| 1079 | input [1:0] clr_int_reg_63_int_state_ext_read_data; // Ext read data (decode) |
| 1080 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_INT_SLC] interrupt_retry_timer_limit_hw_read; |
| 1081 | // This signal provides the current value of interrupt_retry_timer_limit. |
| 1082 | input [23:0] interrupt_state_status_1_state_ext_read_data; // Ext read data |
| 1083 | // (decode) |
| 1084 | input [63:0] interrupt_state_status_2_state_ext_read_data; // Ext read data |
| 1085 | // (decode) |
| 1086 | |
| 1087 | //==================================================== |
| 1088 | // Type declarations |
| 1089 | //==================================================== |
| 1090 | wire clk; // Clock signal |
| 1091 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus |
| 1092 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 1093 | wire csrbus_wr; // Read/Write signal |
| 1094 | wire csrbus_valid; // Valid address |
| 1095 | wire csrbus_mapped; // Address is mapped |
| 1096 | wire csrbus_done; // Operation is done |
| 1097 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus |
| 1098 | wire rst_l; // Reset signal |
| 1099 | wire [1:0] csrbus_src_bus; // Source bus |
| 1100 | wire csrbus_acc_vio; // Violation signal |
| 1101 | wire instance_id; // Instance ID |
| 1102 | wire ext_wr; // When one, csr operation is a write. When zero, operation is a |
| 1103 | // read. |
| 1104 | wire interrupt_mapping_20_mdo_mode_hw_read; // This signal provides the current |
| 1105 | // value of |
| 1106 | // interrupt_mapping_20_mdo_mode. |
| 1107 | wire interrupt_mapping_20_v_hw_read; // This signal provides the current value |
| 1108 | // of interrupt_mapping_20_v. |
| 1109 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_INT_SLC] interrupt_mapping_20_t_id_hw_read; |
| 1110 | // This signal provides the current value of interrupt_mapping_20_t_id. |
| 1111 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_20_int_cntrl_num_hw_read; |
| 1112 | // This signal provides the current value of |
| 1113 | // interrupt_mapping_20_int_cntrl_num. |
| 1114 | wire interrupt_mapping_21_mdo_mode_hw_read; // This signal provides the current |
| 1115 | // value of |
| 1116 | // interrupt_mapping_21_mdo_mode. |
| 1117 | wire interrupt_mapping_21_v_hw_read; // This signal provides the current value |
| 1118 | // of interrupt_mapping_21_v. |
| 1119 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_INT_SLC] interrupt_mapping_21_t_id_hw_read; |
| 1120 | // This signal provides the current value of interrupt_mapping_21_t_id. |
| 1121 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_21_int_cntrl_num_hw_read; |
| 1122 | // This signal provides the current value of |
| 1123 | // interrupt_mapping_21_int_cntrl_num. |
| 1124 | wire interrupt_mapping_22_mdo_mode_hw_read; // This signal provides the current |
| 1125 | // value of |
| 1126 | // interrupt_mapping_22_mdo_mode. |
| 1127 | wire interrupt_mapping_22_v_hw_read; // This signal provides the current value |
| 1128 | // of interrupt_mapping_22_v. |
| 1129 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_INT_SLC] interrupt_mapping_22_t_id_hw_read; |
| 1130 | // This signal provides the current value of interrupt_mapping_22_t_id. |
| 1131 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_22_int_cntrl_num_hw_read; |
| 1132 | // This signal provides the current value of |
| 1133 | // interrupt_mapping_22_int_cntrl_num. |
| 1134 | wire interrupt_mapping_23_mdo_mode_hw_read; // This signal provides the current |
| 1135 | // value of |
| 1136 | // interrupt_mapping_23_mdo_mode. |
| 1137 | wire interrupt_mapping_23_v_hw_read; // This signal provides the current value |
| 1138 | // of interrupt_mapping_23_v. |
| 1139 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_INT_SLC] interrupt_mapping_23_t_id_hw_read; |
| 1140 | // This signal provides the current value of interrupt_mapping_23_t_id. |
| 1141 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_23_int_cntrl_num_hw_read; |
| 1142 | // This signal provides the current value of |
| 1143 | // interrupt_mapping_23_int_cntrl_num. |
| 1144 | wire interrupt_mapping_24_mdo_mode_hw_read; // This signal provides the current |
| 1145 | // value of |
| 1146 | // interrupt_mapping_24_mdo_mode. |
| 1147 | wire interrupt_mapping_24_v_hw_read; // This signal provides the current value |
| 1148 | // of interrupt_mapping_24_v. |
| 1149 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_INT_SLC] interrupt_mapping_24_t_id_hw_read; |
| 1150 | // This signal provides the current value of interrupt_mapping_24_t_id. |
| 1151 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_24_int_cntrl_num_hw_read; |
| 1152 | // This signal provides the current value of |
| 1153 | // interrupt_mapping_24_int_cntrl_num. |
| 1154 | wire interrupt_mapping_25_mdo_mode_hw_read; // This signal provides the current |
| 1155 | // value of |
| 1156 | // interrupt_mapping_25_mdo_mode. |
| 1157 | wire interrupt_mapping_25_v_hw_read; // This signal provides the current value |
| 1158 | // of interrupt_mapping_25_v. |
| 1159 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_INT_SLC] interrupt_mapping_25_t_id_hw_read; |
| 1160 | // This signal provides the current value of interrupt_mapping_25_t_id. |
| 1161 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_25_int_cntrl_num_hw_read; |
| 1162 | // This signal provides the current value of |
| 1163 | // interrupt_mapping_25_int_cntrl_num. |
| 1164 | wire interrupt_mapping_26_mdo_mode_hw_read; // This signal provides the current |
| 1165 | // value of |
| 1166 | // interrupt_mapping_26_mdo_mode. |
| 1167 | wire interrupt_mapping_26_v_hw_read; // This signal provides the current value |
| 1168 | // of interrupt_mapping_26_v. |
| 1169 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_INT_SLC] interrupt_mapping_26_t_id_hw_read; |
| 1170 | // This signal provides the current value of interrupt_mapping_26_t_id. |
| 1171 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_26_int_cntrl_num_hw_read; |
| 1172 | // This signal provides the current value of |
| 1173 | // interrupt_mapping_26_int_cntrl_num. |
| 1174 | wire interrupt_mapping_27_mdo_mode_hw_read; // This signal provides the current |
| 1175 | // value of |
| 1176 | // interrupt_mapping_27_mdo_mode. |
| 1177 | wire interrupt_mapping_27_v_hw_read; // This signal provides the current value |
| 1178 | // of interrupt_mapping_27_v. |
| 1179 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_INT_SLC] interrupt_mapping_27_t_id_hw_read; |
| 1180 | // This signal provides the current value of interrupt_mapping_27_t_id. |
| 1181 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_27_int_cntrl_num_hw_read; |
| 1182 | // This signal provides the current value of |
| 1183 | // interrupt_mapping_27_int_cntrl_num. |
| 1184 | wire interrupt_mapping_28_mdo_mode_hw_read; // This signal provides the current |
| 1185 | // value of |
| 1186 | // interrupt_mapping_28_mdo_mode. |
| 1187 | wire interrupt_mapping_28_v_hw_read; // This signal provides the current value |
| 1188 | // of interrupt_mapping_28_v. |
| 1189 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_INT_SLC] interrupt_mapping_28_t_id_hw_read; |
| 1190 | // This signal provides the current value of interrupt_mapping_28_t_id. |
| 1191 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_28_int_cntrl_num_hw_read; |
| 1192 | // This signal provides the current value of |
| 1193 | // interrupt_mapping_28_int_cntrl_num. |
| 1194 | wire interrupt_mapping_29_mdo_mode_hw_read; // This signal provides the current |
| 1195 | // value of |
| 1196 | // interrupt_mapping_29_mdo_mode. |
| 1197 | wire interrupt_mapping_29_v_hw_read; // This signal provides the current value |
| 1198 | // of interrupt_mapping_29_v. |
| 1199 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_INT_SLC] interrupt_mapping_29_t_id_hw_read; |
| 1200 | // This signal provides the current value of interrupt_mapping_29_t_id. |
| 1201 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_29_int_cntrl_num_hw_read; |
| 1202 | // This signal provides the current value of |
| 1203 | // interrupt_mapping_29_int_cntrl_num. |
| 1204 | wire interrupt_mapping_30_mdo_mode_hw_read; // This signal provides the current |
| 1205 | // value of |
| 1206 | // interrupt_mapping_30_mdo_mode. |
| 1207 | wire interrupt_mapping_30_v_hw_read; // This signal provides the current value |
| 1208 | // of interrupt_mapping_30_v. |
| 1209 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_INT_SLC] interrupt_mapping_30_t_id_hw_read; |
| 1210 | // This signal provides the current value of interrupt_mapping_30_t_id. |
| 1211 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_30_int_cntrl_num_hw_read; |
| 1212 | // This signal provides the current value of |
| 1213 | // interrupt_mapping_30_int_cntrl_num. |
| 1214 | wire interrupt_mapping_31_mdo_mode_hw_read; // This signal provides the current |
| 1215 | // value of |
| 1216 | // interrupt_mapping_31_mdo_mode. |
| 1217 | wire interrupt_mapping_31_v_hw_read; // This signal provides the current value |
| 1218 | // of interrupt_mapping_31_v. |
| 1219 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_INT_SLC] interrupt_mapping_31_t_id_hw_read; |
| 1220 | // This signal provides the current value of interrupt_mapping_31_t_id. |
| 1221 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_31_int_cntrl_num_hw_read; |
| 1222 | // This signal provides the current value of |
| 1223 | // interrupt_mapping_31_int_cntrl_num. |
| 1224 | wire interrupt_mapping_32_mdo_mode_hw_read; // This signal provides the current |
| 1225 | // value of |
| 1226 | // interrupt_mapping_32_mdo_mode. |
| 1227 | wire interrupt_mapping_32_v_hw_read; // This signal provides the current value |
| 1228 | // of interrupt_mapping_32_v. |
| 1229 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_INT_SLC] interrupt_mapping_32_t_id_hw_read; |
| 1230 | // This signal provides the current value of interrupt_mapping_32_t_id. |
| 1231 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_32_int_cntrl_num_hw_read; |
| 1232 | // This signal provides the current value of |
| 1233 | // interrupt_mapping_32_int_cntrl_num. |
| 1234 | wire interrupt_mapping_33_mdo_mode_hw_read; // This signal provides the current |
| 1235 | // value of |
| 1236 | // interrupt_mapping_33_mdo_mode. |
| 1237 | wire interrupt_mapping_33_v_hw_read; // This signal provides the current value |
| 1238 | // of interrupt_mapping_33_v. |
| 1239 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_INT_SLC] interrupt_mapping_33_t_id_hw_read; |
| 1240 | // This signal provides the current value of interrupt_mapping_33_t_id. |
| 1241 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_33_int_cntrl_num_hw_read; |
| 1242 | // This signal provides the current value of |
| 1243 | // interrupt_mapping_33_int_cntrl_num. |
| 1244 | wire interrupt_mapping_34_mdo_mode_hw_read; // This signal provides the current |
| 1245 | // value of |
| 1246 | // interrupt_mapping_34_mdo_mode. |
| 1247 | wire interrupt_mapping_34_v_hw_read; // This signal provides the current value |
| 1248 | // of interrupt_mapping_34_v. |
| 1249 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_INT_SLC] interrupt_mapping_34_t_id_hw_read; |
| 1250 | // This signal provides the current value of interrupt_mapping_34_t_id. |
| 1251 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_34_int_cntrl_num_hw_read; |
| 1252 | // This signal provides the current value of |
| 1253 | // interrupt_mapping_34_int_cntrl_num. |
| 1254 | wire interrupt_mapping_35_mdo_mode_hw_read; // This signal provides the current |
| 1255 | // value of |
| 1256 | // interrupt_mapping_35_mdo_mode. |
| 1257 | wire interrupt_mapping_35_v_hw_read; // This signal provides the current value |
| 1258 | // of interrupt_mapping_35_v. |
| 1259 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_INT_SLC] interrupt_mapping_35_t_id_hw_read; |
| 1260 | // This signal provides the current value of interrupt_mapping_35_t_id. |
| 1261 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_35_int_cntrl_num_hw_read; |
| 1262 | // This signal provides the current value of |
| 1263 | // interrupt_mapping_35_int_cntrl_num. |
| 1264 | wire interrupt_mapping_36_mdo_mode_hw_read; // This signal provides the current |
| 1265 | // value of |
| 1266 | // interrupt_mapping_36_mdo_mode. |
| 1267 | wire interrupt_mapping_36_v_hw_read; // This signal provides the current value |
| 1268 | // of interrupt_mapping_36_v. |
| 1269 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_INT_SLC] interrupt_mapping_36_t_id_hw_read; |
| 1270 | // This signal provides the current value of interrupt_mapping_36_t_id. |
| 1271 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_36_int_cntrl_num_hw_read; |
| 1272 | // This signal provides the current value of |
| 1273 | // interrupt_mapping_36_int_cntrl_num. |
| 1274 | wire interrupt_mapping_37_mdo_mode_hw_read; // This signal provides the current |
| 1275 | // value of |
| 1276 | // interrupt_mapping_37_mdo_mode. |
| 1277 | wire interrupt_mapping_37_v_hw_read; // This signal provides the current value |
| 1278 | // of interrupt_mapping_37_v. |
| 1279 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_INT_SLC] interrupt_mapping_37_t_id_hw_read; |
| 1280 | // This signal provides the current value of interrupt_mapping_37_t_id. |
| 1281 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_37_int_cntrl_num_hw_read; |
| 1282 | // This signal provides the current value of |
| 1283 | // interrupt_mapping_37_int_cntrl_num. |
| 1284 | wire interrupt_mapping_38_mdo_mode_hw_read; // This signal provides the current |
| 1285 | // value of |
| 1286 | // interrupt_mapping_38_mdo_mode. |
| 1287 | wire interrupt_mapping_38_v_hw_read; // This signal provides the current value |
| 1288 | // of interrupt_mapping_38_v. |
| 1289 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_INT_SLC] interrupt_mapping_38_t_id_hw_read; |
| 1290 | // This signal provides the current value of interrupt_mapping_38_t_id. |
| 1291 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_38_int_cntrl_num_hw_read; |
| 1292 | // This signal provides the current value of |
| 1293 | // interrupt_mapping_38_int_cntrl_num. |
| 1294 | wire interrupt_mapping_39_mdo_mode_hw_read; // This signal provides the current |
| 1295 | // value of |
| 1296 | // interrupt_mapping_39_mdo_mode. |
| 1297 | wire interrupt_mapping_39_v_hw_read; // This signal provides the current value |
| 1298 | // of interrupt_mapping_39_v. |
| 1299 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_INT_SLC] interrupt_mapping_39_t_id_hw_read; |
| 1300 | // This signal provides the current value of interrupt_mapping_39_t_id. |
| 1301 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_39_int_cntrl_num_hw_read; |
| 1302 | // This signal provides the current value of |
| 1303 | // interrupt_mapping_39_int_cntrl_num. |
| 1304 | wire interrupt_mapping_40_mdo_mode_hw_read; // This signal provides the current |
| 1305 | // value of |
| 1306 | // interrupt_mapping_40_mdo_mode. |
| 1307 | wire interrupt_mapping_40_v_hw_read; // This signal provides the current value |
| 1308 | // of interrupt_mapping_40_v. |
| 1309 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_INT_SLC] interrupt_mapping_40_t_id_hw_read; |
| 1310 | // This signal provides the current value of interrupt_mapping_40_t_id. |
| 1311 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_40_int_cntrl_num_hw_read; |
| 1312 | // This signal provides the current value of |
| 1313 | // interrupt_mapping_40_int_cntrl_num. |
| 1314 | wire interrupt_mapping_41_mdo_mode_hw_read; // This signal provides the current |
| 1315 | // value of |
| 1316 | // interrupt_mapping_41_mdo_mode. |
| 1317 | wire interrupt_mapping_41_v_hw_read; // This signal provides the current value |
| 1318 | // of interrupt_mapping_41_v. |
| 1319 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_INT_SLC] interrupt_mapping_41_t_id_hw_read; |
| 1320 | // This signal provides the current value of interrupt_mapping_41_t_id. |
| 1321 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_41_int_cntrl_num_hw_read; |
| 1322 | // This signal provides the current value of |
| 1323 | // interrupt_mapping_41_int_cntrl_num. |
| 1324 | wire interrupt_mapping_42_mdo_mode_hw_read; // This signal provides the current |
| 1325 | // value of |
| 1326 | // interrupt_mapping_42_mdo_mode. |
| 1327 | wire interrupt_mapping_42_v_hw_read; // This signal provides the current value |
| 1328 | // of interrupt_mapping_42_v. |
| 1329 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC] interrupt_mapping_42_t_id_hw_read; |
| 1330 | // This signal provides the current value of interrupt_mapping_42_t_id. |
| 1331 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_42_int_cntrl_num_hw_read; |
| 1332 | // This signal provides the current value of |
| 1333 | // interrupt_mapping_42_int_cntrl_num. |
| 1334 | wire interrupt_mapping_43_mdo_mode_hw_read; // This signal provides the current |
| 1335 | // value of |
| 1336 | // interrupt_mapping_43_mdo_mode. |
| 1337 | wire interrupt_mapping_43_v_hw_read; // This signal provides the current value |
| 1338 | // of interrupt_mapping_43_v. |
| 1339 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_INT_SLC] interrupt_mapping_43_t_id_hw_read; |
| 1340 | // This signal provides the current value of interrupt_mapping_43_t_id. |
| 1341 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_43_int_cntrl_num_hw_read; |
| 1342 | // This signal provides the current value of |
| 1343 | // interrupt_mapping_43_int_cntrl_num. |
| 1344 | wire interrupt_mapping_44_mdo_mode_hw_read; // This signal provides the current |
| 1345 | // value of |
| 1346 | // interrupt_mapping_44_mdo_mode. |
| 1347 | wire interrupt_mapping_44_v_hw_read; // This signal provides the current value |
| 1348 | // of interrupt_mapping_44_v. |
| 1349 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_INT_SLC] interrupt_mapping_44_t_id_hw_read; |
| 1350 | // This signal provides the current value of interrupt_mapping_44_t_id. |
| 1351 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_44_int_cntrl_num_hw_read; |
| 1352 | // This signal provides the current value of |
| 1353 | // interrupt_mapping_44_int_cntrl_num. |
| 1354 | wire interrupt_mapping_45_mdo_mode_hw_read; // This signal provides the current |
| 1355 | // value of |
| 1356 | // interrupt_mapping_45_mdo_mode. |
| 1357 | wire interrupt_mapping_45_v_hw_read; // This signal provides the current value |
| 1358 | // of interrupt_mapping_45_v. |
| 1359 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_INT_SLC] interrupt_mapping_45_t_id_hw_read; |
| 1360 | // This signal provides the current value of interrupt_mapping_45_t_id. |
| 1361 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_45_int_cntrl_num_hw_read; |
| 1362 | // This signal provides the current value of |
| 1363 | // interrupt_mapping_45_int_cntrl_num. |
| 1364 | wire interrupt_mapping_46_mdo_mode_hw_read; // This signal provides the current |
| 1365 | // value of |
| 1366 | // interrupt_mapping_46_mdo_mode. |
| 1367 | wire interrupt_mapping_46_v_hw_read; // This signal provides the current value |
| 1368 | // of interrupt_mapping_46_v. |
| 1369 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_INT_SLC] interrupt_mapping_46_t_id_hw_read; |
| 1370 | // This signal provides the current value of interrupt_mapping_46_t_id. |
| 1371 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_46_int_cntrl_num_hw_read; |
| 1372 | // This signal provides the current value of |
| 1373 | // interrupt_mapping_46_int_cntrl_num. |
| 1374 | wire interrupt_mapping_47_mdo_mode_hw_read; // This signal provides the current |
| 1375 | // value of |
| 1376 | // interrupt_mapping_47_mdo_mode. |
| 1377 | wire interrupt_mapping_47_v_hw_read; // This signal provides the current value |
| 1378 | // of interrupt_mapping_47_v. |
| 1379 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_INT_SLC] interrupt_mapping_47_t_id_hw_read; |
| 1380 | // This signal provides the current value of interrupt_mapping_47_t_id. |
| 1381 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_47_int_cntrl_num_hw_read; |
| 1382 | // This signal provides the current value of |
| 1383 | // interrupt_mapping_47_int_cntrl_num. |
| 1384 | wire interrupt_mapping_48_mdo_mode_hw_read; // This signal provides the current |
| 1385 | // value of |
| 1386 | // interrupt_mapping_48_mdo_mode. |
| 1387 | wire interrupt_mapping_48_v_hw_read; // This signal provides the current value |
| 1388 | // of interrupt_mapping_48_v. |
| 1389 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_INT_SLC] interrupt_mapping_48_t_id_hw_read; |
| 1390 | // This signal provides the current value of interrupt_mapping_48_t_id. |
| 1391 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_48_int_cntrl_num_hw_read; |
| 1392 | // This signal provides the current value of |
| 1393 | // interrupt_mapping_48_int_cntrl_num. |
| 1394 | wire interrupt_mapping_49_mdo_mode_hw_read; // This signal provides the current |
| 1395 | // value of |
| 1396 | // interrupt_mapping_49_mdo_mode. |
| 1397 | wire interrupt_mapping_49_v_hw_read; // This signal provides the current value |
| 1398 | // of interrupt_mapping_49_v. |
| 1399 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_INT_SLC] interrupt_mapping_49_t_id_hw_read; |
| 1400 | // This signal provides the current value of interrupt_mapping_49_t_id. |
| 1401 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_49_int_cntrl_num_hw_read; |
| 1402 | // This signal provides the current value of |
| 1403 | // interrupt_mapping_49_int_cntrl_num. |
| 1404 | wire interrupt_mapping_50_mdo_mode_hw_read; // This signal provides the current |
| 1405 | // value of |
| 1406 | // interrupt_mapping_50_mdo_mode. |
| 1407 | wire interrupt_mapping_50_v_hw_read; // This signal provides the current value |
| 1408 | // of interrupt_mapping_50_v. |
| 1409 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_INT_SLC] interrupt_mapping_50_t_id_hw_read; |
| 1410 | // This signal provides the current value of interrupt_mapping_50_t_id. |
| 1411 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_50_int_cntrl_num_hw_read; |
| 1412 | // This signal provides the current value of |
| 1413 | // interrupt_mapping_50_int_cntrl_num. |
| 1414 | wire interrupt_mapping_51_mdo_mode_hw_read; // This signal provides the current |
| 1415 | // value of |
| 1416 | // interrupt_mapping_51_mdo_mode. |
| 1417 | wire interrupt_mapping_51_v_hw_read; // This signal provides the current value |
| 1418 | // of interrupt_mapping_51_v. |
| 1419 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_INT_SLC] interrupt_mapping_51_t_id_hw_read; |
| 1420 | // This signal provides the current value of interrupt_mapping_51_t_id. |
| 1421 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_51_int_cntrl_num_hw_read; |
| 1422 | // This signal provides the current value of |
| 1423 | // interrupt_mapping_51_int_cntrl_num. |
| 1424 | wire interrupt_mapping_52_mdo_mode_hw_read; // This signal provides the current |
| 1425 | // value of |
| 1426 | // interrupt_mapping_52_mdo_mode. |
| 1427 | wire interrupt_mapping_52_v_hw_read; // This signal provides the current value |
| 1428 | // of interrupt_mapping_52_v. |
| 1429 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_INT_SLC] interrupt_mapping_52_t_id_hw_read; |
| 1430 | // This signal provides the current value of interrupt_mapping_52_t_id. |
| 1431 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_52_int_cntrl_num_hw_read; |
| 1432 | // This signal provides the current value of |
| 1433 | // interrupt_mapping_52_int_cntrl_num. |
| 1434 | wire interrupt_mapping_53_mdo_mode_hw_read; // This signal provides the current |
| 1435 | // value of |
| 1436 | // interrupt_mapping_53_mdo_mode. |
| 1437 | wire interrupt_mapping_53_v_hw_read; // This signal provides the current value |
| 1438 | // of interrupt_mapping_53_v. |
| 1439 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_INT_SLC] interrupt_mapping_53_t_id_hw_read; |
| 1440 | // This signal provides the current value of interrupt_mapping_53_t_id. |
| 1441 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_53_int_cntrl_num_hw_read; |
| 1442 | // This signal provides the current value of |
| 1443 | // interrupt_mapping_53_int_cntrl_num. |
| 1444 | wire interrupt_mapping_54_mdo_mode_hw_read; // This signal provides the current |
| 1445 | // value of |
| 1446 | // interrupt_mapping_54_mdo_mode. |
| 1447 | wire interrupt_mapping_54_v_hw_read; // This signal provides the current value |
| 1448 | // of interrupt_mapping_54_v. |
| 1449 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_INT_SLC] interrupt_mapping_54_t_id_hw_read; |
| 1450 | // This signal provides the current value of interrupt_mapping_54_t_id. |
| 1451 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_54_int_cntrl_num_hw_read; |
| 1452 | // This signal provides the current value of |
| 1453 | // interrupt_mapping_54_int_cntrl_num. |
| 1454 | wire interrupt_mapping_55_mdo_mode_hw_read; // This signal provides the current |
| 1455 | // value of |
| 1456 | // interrupt_mapping_55_mdo_mode. |
| 1457 | wire interrupt_mapping_55_v_hw_read; // This signal provides the current value |
| 1458 | // of interrupt_mapping_55_v. |
| 1459 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_INT_SLC] interrupt_mapping_55_t_id_hw_read; |
| 1460 | // This signal provides the current value of interrupt_mapping_55_t_id. |
| 1461 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_55_int_cntrl_num_hw_read; |
| 1462 | // This signal provides the current value of |
| 1463 | // interrupt_mapping_55_int_cntrl_num. |
| 1464 | wire interrupt_mapping_56_mdo_mode_hw_read; // This signal provides the current |
| 1465 | // value of |
| 1466 | // interrupt_mapping_56_mdo_mode. |
| 1467 | wire interrupt_mapping_56_v_hw_read; // This signal provides the current value |
| 1468 | // of interrupt_mapping_56_v. |
| 1469 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_INT_SLC] interrupt_mapping_56_t_id_hw_read; |
| 1470 | // This signal provides the current value of interrupt_mapping_56_t_id. |
| 1471 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_56_int_cntrl_num_hw_read; |
| 1472 | // This signal provides the current value of |
| 1473 | // interrupt_mapping_56_int_cntrl_num. |
| 1474 | wire interrupt_mapping_57_mdo_mode_hw_read; // This signal provides the current |
| 1475 | // value of |
| 1476 | // interrupt_mapping_57_mdo_mode. |
| 1477 | wire interrupt_mapping_57_v_hw_read; // This signal provides the current value |
| 1478 | // of interrupt_mapping_57_v. |
| 1479 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_INT_SLC] interrupt_mapping_57_t_id_hw_read; |
| 1480 | // This signal provides the current value of interrupt_mapping_57_t_id. |
| 1481 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_57_int_cntrl_num_hw_read; |
| 1482 | // This signal provides the current value of |
| 1483 | // interrupt_mapping_57_int_cntrl_num. |
| 1484 | wire interrupt_mapping_58_mdo_mode_hw_read; // This signal provides the current |
| 1485 | // value of |
| 1486 | // interrupt_mapping_58_mdo_mode. |
| 1487 | wire interrupt_mapping_58_v_hw_read; // This signal provides the current value |
| 1488 | // of interrupt_mapping_58_v. |
| 1489 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_INT_SLC] interrupt_mapping_58_t_id_hw_read; |
| 1490 | // This signal provides the current value of interrupt_mapping_58_t_id. |
| 1491 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_58_int_cntrl_num_hw_read; |
| 1492 | // This signal provides the current value of |
| 1493 | // interrupt_mapping_58_int_cntrl_num. |
| 1494 | wire interrupt_mapping_59_mdo_mode_hw_read; // This signal provides the current |
| 1495 | // value of |
| 1496 | // interrupt_mapping_59_mdo_mode. |
| 1497 | wire interrupt_mapping_59_v_hw_read; // This signal provides the current value |
| 1498 | // of interrupt_mapping_59_v. |
| 1499 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_INT_SLC] interrupt_mapping_59_t_id_hw_read; |
| 1500 | // This signal provides the current value of interrupt_mapping_59_t_id. |
| 1501 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_59_int_cntrl_num_hw_read; |
| 1502 | // This signal provides the current value of |
| 1503 | // interrupt_mapping_59_int_cntrl_num. |
| 1504 | wire interrupt_mapping_62_mdo_mode_hw_read; // This signal provides the current |
| 1505 | // value of |
| 1506 | // interrupt_mapping_62_mdo_mode. |
| 1507 | wire interrupt_mapping_62_v_hw_read; // This signal provides the current value |
| 1508 | // of interrupt_mapping_62_v. |
| 1509 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_INT_SLC] interrupt_mapping_62_t_id_hw_read; |
| 1510 | // This signal provides the current value of interrupt_mapping_62_t_id. |
| 1511 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_62_int_cntrl_num_hw_read; |
| 1512 | // This signal provides the current value of |
| 1513 | // interrupt_mapping_62_int_cntrl_num. |
| 1514 | wire interrupt_mapping_63_mdo_mode_hw_read; // This signal provides the current |
| 1515 | // value of |
| 1516 | // interrupt_mapping_63_mdo_mode. |
| 1517 | wire interrupt_mapping_63_v_hw_read; // This signal provides the current value |
| 1518 | // of interrupt_mapping_63_v. |
| 1519 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_INT_SLC] interrupt_mapping_63_t_id_hw_read; |
| 1520 | // This signal provides the current value of interrupt_mapping_63_t_id. |
| 1521 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_63_int_cntrl_num_hw_read; |
| 1522 | // This signal provides the current value of |
| 1523 | // interrupt_mapping_63_int_cntrl_num. |
| 1524 | wire [1:0] clr_int_reg_20_int_state_ext_wr_data; // Provides SW write data for |
| 1525 | // external register |
| 1526 | // "clr_int_reg_20", field |
| 1527 | // "int_state" |
| 1528 | wire clr_int_reg_20_ext_select; // When set, register clr_int_reg_20 is |
| 1529 | // selected. This signal is a pulse. |
| 1530 | wire [1:0] clr_int_reg_20_int_state_ext_read_data; // Ext read data (decode) |
| 1531 | wire [1:0] clr_int_reg_21_int_state_ext_wr_data; // Provides SW write data for |
| 1532 | // external register |
| 1533 | // "clr_int_reg_21", field |
| 1534 | // "int_state" |
| 1535 | wire clr_int_reg_21_ext_select; // When set, register clr_int_reg_21 is |
| 1536 | // selected. This signal is a pulse. |
| 1537 | wire [1:0] clr_int_reg_21_int_state_ext_read_data; // Ext read data (decode) |
| 1538 | wire [1:0] clr_int_reg_22_int_state_ext_wr_data; // Provides SW write data for |
| 1539 | // external register |
| 1540 | // "clr_int_reg_22", field |
| 1541 | // "int_state" |
| 1542 | wire clr_int_reg_22_ext_select; // When set, register clr_int_reg_22 is |
| 1543 | // selected. This signal is a pulse. |
| 1544 | wire [1:0] clr_int_reg_22_int_state_ext_read_data; // Ext read data (decode) |
| 1545 | wire [1:0] clr_int_reg_23_int_state_ext_wr_data; // Provides SW write data for |
| 1546 | // external register |
| 1547 | // "clr_int_reg_23", field |
| 1548 | // "int_state" |
| 1549 | wire clr_int_reg_23_ext_select; // When set, register clr_int_reg_23 is |
| 1550 | // selected. This signal is a pulse. |
| 1551 | wire [1:0] clr_int_reg_23_int_state_ext_read_data; // Ext read data (decode) |
| 1552 | wire [1:0] clr_int_reg_24_int_state_ext_wr_data; // Provides SW write data for |
| 1553 | // external register |
| 1554 | // "clr_int_reg_24", field |
| 1555 | // "int_state" |
| 1556 | wire clr_int_reg_24_ext_select; // When set, register clr_int_reg_24 is |
| 1557 | // selected. This signal is a pulse. |
| 1558 | wire [1:0] clr_int_reg_24_int_state_ext_read_data; // Ext read data (decode) |
| 1559 | wire [1:0] clr_int_reg_25_int_state_ext_wr_data; // Provides SW write data for |
| 1560 | // external register |
| 1561 | // "clr_int_reg_25", field |
| 1562 | // "int_state" |
| 1563 | wire clr_int_reg_25_ext_select; // When set, register clr_int_reg_25 is |
| 1564 | // selected. This signal is a pulse. |
| 1565 | wire [1:0] clr_int_reg_25_int_state_ext_read_data; // Ext read data (decode) |
| 1566 | wire [1:0] clr_int_reg_26_int_state_ext_wr_data; // Provides SW write data for |
| 1567 | // external register |
| 1568 | // "clr_int_reg_26", field |
| 1569 | // "int_state" |
| 1570 | wire clr_int_reg_26_ext_select; // When set, register clr_int_reg_26 is |
| 1571 | // selected. This signal is a pulse. |
| 1572 | wire [1:0] clr_int_reg_26_int_state_ext_read_data; // Ext read data (decode) |
| 1573 | wire [1:0] clr_int_reg_27_int_state_ext_wr_data; // Provides SW write data for |
| 1574 | // external register |
| 1575 | // "clr_int_reg_27", field |
| 1576 | // "int_state" |
| 1577 | wire clr_int_reg_27_ext_select; // When set, register clr_int_reg_27 is |
| 1578 | // selected. This signal is a pulse. |
| 1579 | wire [1:0] clr_int_reg_27_int_state_ext_read_data; // Ext read data (decode) |
| 1580 | wire [1:0] clr_int_reg_28_int_state_ext_wr_data; // Provides SW write data for |
| 1581 | // external register |
| 1582 | // "clr_int_reg_28", field |
| 1583 | // "int_state" |
| 1584 | wire clr_int_reg_28_ext_select; // When set, register clr_int_reg_28 is |
| 1585 | // selected. This signal is a pulse. |
| 1586 | wire [1:0] clr_int_reg_28_int_state_ext_read_data; // Ext read data (decode) |
| 1587 | wire [1:0] clr_int_reg_29_int_state_ext_wr_data; // Provides SW write data for |
| 1588 | // external register |
| 1589 | // "clr_int_reg_29", field |
| 1590 | // "int_state" |
| 1591 | wire clr_int_reg_29_ext_select; // When set, register clr_int_reg_29 is |
| 1592 | // selected. This signal is a pulse. |
| 1593 | wire [1:0] clr_int_reg_29_int_state_ext_read_data; // Ext read data (decode) |
| 1594 | wire [1:0] clr_int_reg_30_int_state_ext_wr_data; // Provides SW write data for |
| 1595 | // external register |
| 1596 | // "clr_int_reg_30", field |
| 1597 | // "int_state" |
| 1598 | wire clr_int_reg_30_ext_select; // When set, register clr_int_reg_30 is |
| 1599 | // selected. This signal is a pulse. |
| 1600 | wire [1:0] clr_int_reg_30_int_state_ext_read_data; // Ext read data (decode) |
| 1601 | wire [1:0] clr_int_reg_31_int_state_ext_wr_data; // Provides SW write data for |
| 1602 | // external register |
| 1603 | // "clr_int_reg_31", field |
| 1604 | // "int_state" |
| 1605 | wire clr_int_reg_31_ext_select; // When set, register clr_int_reg_31 is |
| 1606 | // selected. This signal is a pulse. |
| 1607 | wire [1:0] clr_int_reg_31_int_state_ext_read_data; // Ext read data (decode) |
| 1608 | wire [1:0] clr_int_reg_32_int_state_ext_wr_data; // Provides SW write data for |
| 1609 | // external register |
| 1610 | // "clr_int_reg_32", field |
| 1611 | // "int_state" |
| 1612 | wire clr_int_reg_32_ext_select; // When set, register clr_int_reg_32 is |
| 1613 | // selected. This signal is a pulse. |
| 1614 | wire [1:0] clr_int_reg_32_int_state_ext_read_data; // Ext read data (decode) |
| 1615 | wire [1:0] clr_int_reg_33_int_state_ext_wr_data; // Provides SW write data for |
| 1616 | // external register |
| 1617 | // "clr_int_reg_33", field |
| 1618 | // "int_state" |
| 1619 | wire clr_int_reg_33_ext_select; // When set, register clr_int_reg_33 is |
| 1620 | // selected. This signal is a pulse. |
| 1621 | wire [1:0] clr_int_reg_33_int_state_ext_read_data; // Ext read data (decode) |
| 1622 | wire [1:0] clr_int_reg_34_int_state_ext_wr_data; // Provides SW write data for |
| 1623 | // external register |
| 1624 | // "clr_int_reg_34", field |
| 1625 | // "int_state" |
| 1626 | wire clr_int_reg_34_ext_select; // When set, register clr_int_reg_34 is |
| 1627 | // selected. This signal is a pulse. |
| 1628 | wire [1:0] clr_int_reg_34_int_state_ext_read_data; // Ext read data (decode) |
| 1629 | wire [1:0] clr_int_reg_35_int_state_ext_wr_data; // Provides SW write data for |
| 1630 | // external register |
| 1631 | // "clr_int_reg_35", field |
| 1632 | // "int_state" |
| 1633 | wire clr_int_reg_35_ext_select; // When set, register clr_int_reg_35 is |
| 1634 | // selected. This signal is a pulse. |
| 1635 | wire [1:0] clr_int_reg_35_int_state_ext_read_data; // Ext read data (decode) |
| 1636 | wire [1:0] clr_int_reg_36_int_state_ext_wr_data; // Provides SW write data for |
| 1637 | // external register |
| 1638 | // "clr_int_reg_36", field |
| 1639 | // "int_state" |
| 1640 | wire clr_int_reg_36_ext_select; // When set, register clr_int_reg_36 is |
| 1641 | // selected. This signal is a pulse. |
| 1642 | wire [1:0] clr_int_reg_36_int_state_ext_read_data; // Ext read data (decode) |
| 1643 | wire [1:0] clr_int_reg_37_int_state_ext_wr_data; // Provides SW write data for |
| 1644 | // external register |
| 1645 | // "clr_int_reg_37", field |
| 1646 | // "int_state" |
| 1647 | wire clr_int_reg_37_ext_select; // When set, register clr_int_reg_37 is |
| 1648 | // selected. This signal is a pulse. |
| 1649 | wire [1:0] clr_int_reg_37_int_state_ext_read_data; // Ext read data (decode) |
| 1650 | wire [1:0] clr_int_reg_38_int_state_ext_wr_data; // Provides SW write data for |
| 1651 | // external register |
| 1652 | // "clr_int_reg_38", field |
| 1653 | // "int_state" |
| 1654 | wire clr_int_reg_38_ext_select; // When set, register clr_int_reg_38 is |
| 1655 | // selected. This signal is a pulse. |
| 1656 | wire [1:0] clr_int_reg_38_int_state_ext_read_data; // Ext read data (decode) |
| 1657 | wire [1:0] clr_int_reg_39_int_state_ext_wr_data; // Provides SW write data for |
| 1658 | // external register |
| 1659 | // "clr_int_reg_39", field |
| 1660 | // "int_state" |
| 1661 | wire clr_int_reg_39_ext_select; // When set, register clr_int_reg_39 is |
| 1662 | // selected. This signal is a pulse. |
| 1663 | wire [1:0] clr_int_reg_39_int_state_ext_read_data; // Ext read data (decode) |
| 1664 | wire [1:0] clr_int_reg_40_int_state_ext_wr_data; // Provides SW write data for |
| 1665 | // external register |
| 1666 | // "clr_int_reg_40", field |
| 1667 | // "int_state" |
| 1668 | wire clr_int_reg_40_ext_select; // When set, register clr_int_reg_40 is |
| 1669 | // selected. This signal is a pulse. |
| 1670 | wire [1:0] clr_int_reg_40_int_state_ext_read_data; // Ext read data (decode) |
| 1671 | wire [1:0] clr_int_reg_41_int_state_ext_wr_data; // Provides SW write data for |
| 1672 | // external register |
| 1673 | // "clr_int_reg_41", field |
| 1674 | // "int_state" |
| 1675 | wire clr_int_reg_41_ext_select; // When set, register clr_int_reg_41 is |
| 1676 | // selected. This signal is a pulse. |
| 1677 | wire [1:0] clr_int_reg_41_int_state_ext_read_data; // Ext read data (decode) |
| 1678 | wire [1:0] clr_int_reg_42_int_state_ext_wr_data; // Provides SW write data for |
| 1679 | // external register |
| 1680 | // "clr_int_reg_42", field |
| 1681 | // "int_state" |
| 1682 | wire clr_int_reg_42_ext_select; // When set, register clr_int_reg_42 is |
| 1683 | // selected. This signal is a pulse. |
| 1684 | wire [1:0] clr_int_reg_42_int_state_ext_read_data; // Ext read data (decode) |
| 1685 | wire [1:0] clr_int_reg_43_int_state_ext_wr_data; // Provides SW write data for |
| 1686 | // external register |
| 1687 | // "clr_int_reg_43", field |
| 1688 | // "int_state" |
| 1689 | wire clr_int_reg_43_ext_select; // When set, register clr_int_reg_43 is |
| 1690 | // selected. This signal is a pulse. |
| 1691 | wire [1:0] clr_int_reg_43_int_state_ext_read_data; // Ext read data (decode) |
| 1692 | wire [1:0] clr_int_reg_44_int_state_ext_wr_data; // Provides SW write data for |
| 1693 | // external register |
| 1694 | // "clr_int_reg_44", field |
| 1695 | // "int_state" |
| 1696 | wire clr_int_reg_44_ext_select; // When set, register clr_int_reg_44 is |
| 1697 | // selected. This signal is a pulse. |
| 1698 | wire [1:0] clr_int_reg_44_int_state_ext_read_data; // Ext read data (decode) |
| 1699 | wire [1:0] clr_int_reg_45_int_state_ext_wr_data; // Provides SW write data for |
| 1700 | // external register |
| 1701 | // "clr_int_reg_45", field |
| 1702 | // "int_state" |
| 1703 | wire clr_int_reg_45_ext_select; // When set, register clr_int_reg_45 is |
| 1704 | // selected. This signal is a pulse. |
| 1705 | wire [1:0] clr_int_reg_45_int_state_ext_read_data; // Ext read data (decode) |
| 1706 | wire [1:0] clr_int_reg_46_int_state_ext_wr_data; // Provides SW write data for |
| 1707 | // external register |
| 1708 | // "clr_int_reg_46", field |
| 1709 | // "int_state" |
| 1710 | wire clr_int_reg_46_ext_select; // When set, register clr_int_reg_46 is |
| 1711 | // selected. This signal is a pulse. |
| 1712 | wire [1:0] clr_int_reg_46_int_state_ext_read_data; // Ext read data (decode) |
| 1713 | wire [1:0] clr_int_reg_47_int_state_ext_wr_data; // Provides SW write data for |
| 1714 | // external register |
| 1715 | // "clr_int_reg_47", field |
| 1716 | // "int_state" |
| 1717 | wire clr_int_reg_47_ext_select; // When set, register clr_int_reg_47 is |
| 1718 | // selected. This signal is a pulse. |
| 1719 | wire [1:0] clr_int_reg_47_int_state_ext_read_data; // Ext read data (decode) |
| 1720 | wire [1:0] clr_int_reg_48_int_state_ext_wr_data; // Provides SW write data for |
| 1721 | // external register |
| 1722 | // "clr_int_reg_48", field |
| 1723 | // "int_state" |
| 1724 | wire clr_int_reg_48_ext_select; // When set, register clr_int_reg_48 is |
| 1725 | // selected. This signal is a pulse. |
| 1726 | wire [1:0] clr_int_reg_48_int_state_ext_read_data; // Ext read data (decode) |
| 1727 | wire [1:0] clr_int_reg_49_int_state_ext_wr_data; // Provides SW write data for |
| 1728 | // external register |
| 1729 | // "clr_int_reg_49", field |
| 1730 | // "int_state" |
| 1731 | wire clr_int_reg_49_ext_select; // When set, register clr_int_reg_49 is |
| 1732 | // selected. This signal is a pulse. |
| 1733 | wire [1:0] clr_int_reg_49_int_state_ext_read_data; // Ext read data (decode) |
| 1734 | wire [1:0] clr_int_reg_50_int_state_ext_wr_data; // Provides SW write data for |
| 1735 | // external register |
| 1736 | // "clr_int_reg_50", field |
| 1737 | // "int_state" |
| 1738 | wire clr_int_reg_50_ext_select; // When set, register clr_int_reg_50 is |
| 1739 | // selected. This signal is a pulse. |
| 1740 | wire [1:0] clr_int_reg_50_int_state_ext_read_data; // Ext read data (decode) |
| 1741 | wire [1:0] clr_int_reg_51_int_state_ext_wr_data; // Provides SW write data for |
| 1742 | // external register |
| 1743 | // "clr_int_reg_51", field |
| 1744 | // "int_state" |
| 1745 | wire clr_int_reg_51_ext_select; // When set, register clr_int_reg_51 is |
| 1746 | // selected. This signal is a pulse. |
| 1747 | wire [1:0] clr_int_reg_51_int_state_ext_read_data; // Ext read data (decode) |
| 1748 | wire [1:0] clr_int_reg_52_int_state_ext_wr_data; // Provides SW write data for |
| 1749 | // external register |
| 1750 | // "clr_int_reg_52", field |
| 1751 | // "int_state" |
| 1752 | wire clr_int_reg_52_ext_select; // When set, register clr_int_reg_52 is |
| 1753 | // selected. This signal is a pulse. |
| 1754 | wire [1:0] clr_int_reg_52_int_state_ext_read_data; // Ext read data (decode) |
| 1755 | wire [1:0] clr_int_reg_53_int_state_ext_wr_data; // Provides SW write data for |
| 1756 | // external register |
| 1757 | // "clr_int_reg_53", field |
| 1758 | // "int_state" |
| 1759 | wire clr_int_reg_53_ext_select; // When set, register clr_int_reg_53 is |
| 1760 | // selected. This signal is a pulse. |
| 1761 | wire [1:0] clr_int_reg_53_int_state_ext_read_data; // Ext read data (decode) |
| 1762 | wire [1:0] clr_int_reg_54_int_state_ext_wr_data; // Provides SW write data for |
| 1763 | // external register |
| 1764 | // "clr_int_reg_54", field |
| 1765 | // "int_state" |
| 1766 | wire clr_int_reg_54_ext_select; // When set, register clr_int_reg_54 is |
| 1767 | // selected. This signal is a pulse. |
| 1768 | wire [1:0] clr_int_reg_54_int_state_ext_read_data; // Ext read data (decode) |
| 1769 | wire [1:0] clr_int_reg_55_int_state_ext_wr_data; // Provides SW write data for |
| 1770 | // external register |
| 1771 | // "clr_int_reg_55", field |
| 1772 | // "int_state" |
| 1773 | wire clr_int_reg_55_ext_select; // When set, register clr_int_reg_55 is |
| 1774 | // selected. This signal is a pulse. |
| 1775 | wire [1:0] clr_int_reg_55_int_state_ext_read_data; // Ext read data (decode) |
| 1776 | wire [1:0] clr_int_reg_56_int_state_ext_wr_data; // Provides SW write data for |
| 1777 | // external register |
| 1778 | // "clr_int_reg_56", field |
| 1779 | // "int_state" |
| 1780 | wire clr_int_reg_56_ext_select; // When set, register clr_int_reg_56 is |
| 1781 | // selected. This signal is a pulse. |
| 1782 | wire [1:0] clr_int_reg_56_int_state_ext_read_data; // Ext read data (decode) |
| 1783 | wire [1:0] clr_int_reg_57_int_state_ext_wr_data; // Provides SW write data for |
| 1784 | // external register |
| 1785 | // "clr_int_reg_57", field |
| 1786 | // "int_state" |
| 1787 | wire clr_int_reg_57_ext_select; // When set, register clr_int_reg_57 is |
| 1788 | // selected. This signal is a pulse. |
| 1789 | wire [1:0] clr_int_reg_57_int_state_ext_read_data; // Ext read data (decode) |
| 1790 | wire [1:0] clr_int_reg_58_int_state_ext_wr_data; // Provides SW write data for |
| 1791 | // external register |
| 1792 | // "clr_int_reg_58", field |
| 1793 | // "int_state" |
| 1794 | wire clr_int_reg_58_ext_select; // When set, register clr_int_reg_58 is |
| 1795 | // selected. This signal is a pulse. |
| 1796 | wire [1:0] clr_int_reg_58_int_state_ext_read_data; // Ext read data (decode) |
| 1797 | wire [1:0] clr_int_reg_59_int_state_ext_wr_data; // Provides SW write data for |
| 1798 | // external register |
| 1799 | // "clr_int_reg_59", field |
| 1800 | // "int_state" |
| 1801 | wire clr_int_reg_59_ext_select; // When set, register clr_int_reg_59 is |
| 1802 | // selected. This signal is a pulse. |
| 1803 | wire [1:0] clr_int_reg_59_int_state_ext_read_data; // Ext read data (decode) |
| 1804 | wire [1:0] clr_int_reg_62_int_state_ext_wr_data; // Provides SW write data for |
| 1805 | // external register |
| 1806 | // "clr_int_reg_62", field |
| 1807 | // "int_state" |
| 1808 | wire clr_int_reg_62_ext_select; // When set, register clr_int_reg_62 is |
| 1809 | // selected. This signal is a pulse. |
| 1810 | wire [1:0] clr_int_reg_62_int_state_ext_read_data; // Ext read data (decode) |
| 1811 | wire [1:0] clr_int_reg_63_int_state_ext_wr_data; // Provides SW write data for |
| 1812 | // external register |
| 1813 | // "clr_int_reg_63", field |
| 1814 | // "int_state" |
| 1815 | wire clr_int_reg_63_ext_select; // When set, register clr_int_reg_63 is |
| 1816 | // selected. This signal is a pulse. |
| 1817 | wire [1:0] clr_int_reg_63_int_state_ext_read_data; // Ext read data (decode) |
| 1818 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_INT_SLC] interrupt_retry_timer_limit_hw_read; |
| 1819 | // This signal provides the current value of interrupt_retry_timer_limit. |
| 1820 | wire [23:0] interrupt_state_status_1_state_ext_read_data; // Ext read data |
| 1821 | // (decode) |
| 1822 | wire [63:0] interrupt_state_status_2_state_ext_read_data; // Ext read data |
| 1823 | // (decode) |
| 1824 | |
| 1825 | //==================================================== |
| 1826 | // Logic |
| 1827 | //==================================================== |
| 1828 | wire daemon_transaction_in_progress; |
| 1829 | wire daemon_csrbus_mapped; |
| 1830 | wire daemon_csrbus_valid; |
| 1831 | // vlint flag_dangling_net_within_module off |
| 1832 | // vlint flag_net_has_no_load off |
| 1833 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp; |
| 1834 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; |
| 1835 | // vlint flag_dangling_net_within_module on |
| 1836 | // vlint flag_net_has_no_load on |
| 1837 | wire daemon_csrbus_done; |
| 1838 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr; |
| 1839 | wire daemon_csrbus_wr_tmp; |
| 1840 | wire daemon_csrbus_wr; |
| 1841 | |
| 1842 | //summit modcovoff -bepgnv |
| 1843 | pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon ( |
| 1844 | .daemon_csrbus_valid (daemon_csrbus_valid), |
| 1845 | .daemon_csrbus_mapped (daemon_csrbus_mapped), |
| 1846 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp), |
| 1847 | .daemon_csrbus_done (daemon_csrbus_done), |
| 1848 | .daemon_csrbus_addr (daemon_csrbus_addr), |
| 1849 | .daemon_csrbus_wr (daemon_csrbus_wr_tmp), |
| 1850 | .daemon_transaction_in_progress (daemon_transaction_in_progress), |
| 1851 | // synopsys translate_off |
| 1852 | .clk(clk), |
| 1853 | .csrbus_read_data (csrbus_read_data), |
| 1854 | .rst_l (rst_l), |
| 1855 | // synopsys translate_on |
| 1856 | .csrbus_valid (csrbus_valid), |
| 1857 | .csrbus_mapped (csrbus_mapped), |
| 1858 | .csrbus_wr_data (csrbus_wr_data), |
| 1859 | .csrbus_done (csrbus_done), |
| 1860 | .csrbus_addr (csrbus_addr), |
| 1861 | .csrbus_wr (csrbus_wr) |
| 1862 | ); |
| 1863 | //summit modcovon -bepgnv |
| 1864 | |
| 1865 | //==================================================================== |
| 1866 | // Address decode |
| 1867 | //==================================================================== |
| 1868 | wire interrupt_mapping_20_select_pulse; |
| 1869 | wire interrupt_mapping_21_select_pulse; |
| 1870 | wire interrupt_mapping_22_select_pulse; |
| 1871 | wire interrupt_mapping_23_select_pulse; |
| 1872 | wire interrupt_mapping_24_select_pulse; |
| 1873 | wire interrupt_mapping_25_select_pulse; |
| 1874 | wire interrupt_mapping_26_select_pulse; |
| 1875 | wire interrupt_mapping_27_select_pulse; |
| 1876 | wire interrupt_mapping_28_select_pulse; |
| 1877 | wire interrupt_mapping_29_select_pulse; |
| 1878 | wire interrupt_mapping_30_select_pulse; |
| 1879 | wire interrupt_mapping_31_select_pulse; |
| 1880 | wire interrupt_mapping_32_select_pulse; |
| 1881 | wire interrupt_mapping_33_select_pulse; |
| 1882 | wire interrupt_mapping_34_select_pulse; |
| 1883 | wire interrupt_mapping_35_select_pulse; |
| 1884 | wire interrupt_mapping_36_select_pulse; |
| 1885 | wire interrupt_mapping_37_select_pulse; |
| 1886 | wire interrupt_mapping_38_select_pulse; |
| 1887 | wire interrupt_mapping_39_select_pulse; |
| 1888 | wire interrupt_mapping_40_select_pulse; |
| 1889 | wire interrupt_mapping_41_select_pulse; |
| 1890 | wire interrupt_mapping_42_select_pulse; |
| 1891 | wire interrupt_mapping_43_select_pulse; |
| 1892 | wire interrupt_mapping_44_select_pulse; |
| 1893 | wire interrupt_mapping_45_select_pulse; |
| 1894 | wire interrupt_mapping_46_select_pulse; |
| 1895 | wire interrupt_mapping_47_select_pulse; |
| 1896 | wire interrupt_mapping_48_select_pulse; |
| 1897 | wire interrupt_mapping_49_select_pulse; |
| 1898 | wire interrupt_mapping_50_select_pulse; |
| 1899 | wire interrupt_mapping_51_select_pulse; |
| 1900 | wire interrupt_mapping_52_select_pulse; |
| 1901 | wire interrupt_mapping_53_select_pulse; |
| 1902 | wire interrupt_mapping_54_select_pulse; |
| 1903 | wire interrupt_mapping_55_select_pulse; |
| 1904 | wire interrupt_mapping_56_select_pulse; |
| 1905 | wire interrupt_mapping_57_select_pulse; |
| 1906 | wire interrupt_mapping_58_select_pulse; |
| 1907 | wire interrupt_mapping_59_select_pulse; |
| 1908 | wire interrupt_mapping_62_select_pulse; |
| 1909 | wire interrupt_mapping_63_select_pulse; |
| 1910 | wire clr_int_reg_20_select; |
| 1911 | wire clr_int_reg_21_select; |
| 1912 | wire clr_int_reg_22_select; |
| 1913 | wire clr_int_reg_23_select; |
| 1914 | wire clr_int_reg_24_select; |
| 1915 | wire clr_int_reg_25_select; |
| 1916 | wire clr_int_reg_26_select; |
| 1917 | wire clr_int_reg_27_select; |
| 1918 | wire clr_int_reg_28_select; |
| 1919 | wire clr_int_reg_29_select; |
| 1920 | wire clr_int_reg_30_select; |
| 1921 | wire clr_int_reg_31_select; |
| 1922 | wire clr_int_reg_32_select; |
| 1923 | wire clr_int_reg_33_select; |
| 1924 | wire clr_int_reg_34_select; |
| 1925 | wire clr_int_reg_35_select; |
| 1926 | wire clr_int_reg_36_select; |
| 1927 | wire clr_int_reg_37_select; |
| 1928 | wire clr_int_reg_38_select; |
| 1929 | wire clr_int_reg_39_select; |
| 1930 | wire clr_int_reg_40_select; |
| 1931 | wire clr_int_reg_41_select; |
| 1932 | wire clr_int_reg_42_select; |
| 1933 | wire clr_int_reg_43_select; |
| 1934 | wire clr_int_reg_44_select; |
| 1935 | wire clr_int_reg_45_select; |
| 1936 | wire clr_int_reg_46_select; |
| 1937 | wire clr_int_reg_47_select; |
| 1938 | wire clr_int_reg_48_select; |
| 1939 | wire clr_int_reg_49_select; |
| 1940 | wire clr_int_reg_50_select; |
| 1941 | wire clr_int_reg_51_select; |
| 1942 | wire clr_int_reg_52_select; |
| 1943 | wire clr_int_reg_53_select; |
| 1944 | wire clr_int_reg_54_select; |
| 1945 | wire clr_int_reg_55_select; |
| 1946 | wire clr_int_reg_56_select; |
| 1947 | wire clr_int_reg_57_select; |
| 1948 | wire clr_int_reg_58_select; |
| 1949 | wire clr_int_reg_59_select; |
| 1950 | wire clr_int_reg_62_select; |
| 1951 | wire clr_int_reg_63_select; |
| 1952 | wire interrupt_retry_timer_select_pulse; |
| 1953 | wire interrupt_state_status_1_select; |
| 1954 | wire interrupt_state_status_2_select; |
| 1955 | |
| 1956 | dmu_imu_iss_addr_decode dmu_imu_iss_addr_decode |
| 1957 | ( |
| 1958 | .clk (clk), |
| 1959 | .rst_l (rst_l), |
| 1960 | .daemon_csrbus_valid (daemon_csrbus_valid), |
| 1961 | .daemon_csrbus_addr (daemon_csrbus_addr), |
| 1962 | .csrbus_src_bus (csrbus_src_bus), |
| 1963 | .daemon_csrbus_wr (daemon_csrbus_wr_tmp), |
| 1964 | .daemon_csrbus_wr_out (daemon_csrbus_wr), |
| 1965 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp), |
| 1966 | .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data), |
| 1967 | .daemon_csrbus_mapped (daemon_csrbus_mapped), |
| 1968 | .csrbus_acc_vio (csrbus_acc_vio), |
| 1969 | .daemon_transaction_in_progress (daemon_transaction_in_progress), |
| 1970 | .instance_id (instance_id), |
| 1971 | .daemon_csrbus_done (daemon_csrbus_done), |
| 1972 | .interrupt_mapping_20_select_pulse (interrupt_mapping_20_select_pulse), |
| 1973 | .interrupt_mapping_21_select_pulse (interrupt_mapping_21_select_pulse), |
| 1974 | .interrupt_mapping_22_select_pulse (interrupt_mapping_22_select_pulse), |
| 1975 | .interrupt_mapping_23_select_pulse (interrupt_mapping_23_select_pulse), |
| 1976 | .interrupt_mapping_24_select_pulse (interrupt_mapping_24_select_pulse), |
| 1977 | .interrupt_mapping_25_select_pulse (interrupt_mapping_25_select_pulse), |
| 1978 | .interrupt_mapping_26_select_pulse (interrupt_mapping_26_select_pulse), |
| 1979 | .interrupt_mapping_27_select_pulse (interrupt_mapping_27_select_pulse), |
| 1980 | .interrupt_mapping_28_select_pulse (interrupt_mapping_28_select_pulse), |
| 1981 | .interrupt_mapping_29_select_pulse (interrupt_mapping_29_select_pulse), |
| 1982 | .interrupt_mapping_30_select_pulse (interrupt_mapping_30_select_pulse), |
| 1983 | .interrupt_mapping_31_select_pulse (interrupt_mapping_31_select_pulse), |
| 1984 | .interrupt_mapping_32_select_pulse (interrupt_mapping_32_select_pulse), |
| 1985 | .interrupt_mapping_33_select_pulse (interrupt_mapping_33_select_pulse), |
| 1986 | .interrupt_mapping_34_select_pulse (interrupt_mapping_34_select_pulse), |
| 1987 | .interrupt_mapping_35_select_pulse (interrupt_mapping_35_select_pulse), |
| 1988 | .interrupt_mapping_36_select_pulse (interrupt_mapping_36_select_pulse), |
| 1989 | .interrupt_mapping_37_select_pulse (interrupt_mapping_37_select_pulse), |
| 1990 | .interrupt_mapping_38_select_pulse (interrupt_mapping_38_select_pulse), |
| 1991 | .interrupt_mapping_39_select_pulse (interrupt_mapping_39_select_pulse), |
| 1992 | .interrupt_mapping_40_select_pulse (interrupt_mapping_40_select_pulse), |
| 1993 | .interrupt_mapping_41_select_pulse (interrupt_mapping_41_select_pulse), |
| 1994 | .interrupt_mapping_42_select_pulse (interrupt_mapping_42_select_pulse), |
| 1995 | .interrupt_mapping_43_select_pulse (interrupt_mapping_43_select_pulse), |
| 1996 | .interrupt_mapping_44_select_pulse (interrupt_mapping_44_select_pulse), |
| 1997 | .interrupt_mapping_45_select_pulse (interrupt_mapping_45_select_pulse), |
| 1998 | .interrupt_mapping_46_select_pulse (interrupt_mapping_46_select_pulse), |
| 1999 | .interrupt_mapping_47_select_pulse (interrupt_mapping_47_select_pulse), |
| 2000 | .interrupt_mapping_48_select_pulse (interrupt_mapping_48_select_pulse), |
| 2001 | .interrupt_mapping_49_select_pulse (interrupt_mapping_49_select_pulse), |
| 2002 | .interrupt_mapping_50_select_pulse (interrupt_mapping_50_select_pulse), |
| 2003 | .interrupt_mapping_51_select_pulse (interrupt_mapping_51_select_pulse), |
| 2004 | .interrupt_mapping_52_select_pulse (interrupt_mapping_52_select_pulse), |
| 2005 | .interrupt_mapping_53_select_pulse (interrupt_mapping_53_select_pulse), |
| 2006 | .interrupt_mapping_54_select_pulse (interrupt_mapping_54_select_pulse), |
| 2007 | .interrupt_mapping_55_select_pulse (interrupt_mapping_55_select_pulse), |
| 2008 | .interrupt_mapping_56_select_pulse (interrupt_mapping_56_select_pulse), |
| 2009 | .interrupt_mapping_57_select_pulse (interrupt_mapping_57_select_pulse), |
| 2010 | .interrupt_mapping_58_select_pulse (interrupt_mapping_58_select_pulse), |
| 2011 | .interrupt_mapping_59_select_pulse (interrupt_mapping_59_select_pulse), |
| 2012 | .interrupt_mapping_62_select_pulse (interrupt_mapping_62_select_pulse), |
| 2013 | .interrupt_mapping_63_select_pulse (interrupt_mapping_63_select_pulse), |
| 2014 | .clr_int_reg_20_select (clr_int_reg_20_select), |
| 2015 | .clr_int_reg_21_select (clr_int_reg_21_select), |
| 2016 | .clr_int_reg_22_select (clr_int_reg_22_select), |
| 2017 | .clr_int_reg_23_select (clr_int_reg_23_select), |
| 2018 | .clr_int_reg_24_select (clr_int_reg_24_select), |
| 2019 | .clr_int_reg_25_select (clr_int_reg_25_select), |
| 2020 | .clr_int_reg_26_select (clr_int_reg_26_select), |
| 2021 | .clr_int_reg_27_select (clr_int_reg_27_select), |
| 2022 | .clr_int_reg_28_select (clr_int_reg_28_select), |
| 2023 | .clr_int_reg_29_select (clr_int_reg_29_select), |
| 2024 | .clr_int_reg_30_select (clr_int_reg_30_select), |
| 2025 | .clr_int_reg_31_select (clr_int_reg_31_select), |
| 2026 | .clr_int_reg_32_select (clr_int_reg_32_select), |
| 2027 | .clr_int_reg_33_select (clr_int_reg_33_select), |
| 2028 | .clr_int_reg_34_select (clr_int_reg_34_select), |
| 2029 | .clr_int_reg_35_select (clr_int_reg_35_select), |
| 2030 | .clr_int_reg_36_select (clr_int_reg_36_select), |
| 2031 | .clr_int_reg_37_select (clr_int_reg_37_select), |
| 2032 | .clr_int_reg_38_select (clr_int_reg_38_select), |
| 2033 | .clr_int_reg_39_select (clr_int_reg_39_select), |
| 2034 | .clr_int_reg_40_select (clr_int_reg_40_select), |
| 2035 | .clr_int_reg_41_select (clr_int_reg_41_select), |
| 2036 | .clr_int_reg_42_select (clr_int_reg_42_select), |
| 2037 | .clr_int_reg_43_select (clr_int_reg_43_select), |
| 2038 | .clr_int_reg_44_select (clr_int_reg_44_select), |
| 2039 | .clr_int_reg_45_select (clr_int_reg_45_select), |
| 2040 | .clr_int_reg_46_select (clr_int_reg_46_select), |
| 2041 | .clr_int_reg_47_select (clr_int_reg_47_select), |
| 2042 | .clr_int_reg_48_select (clr_int_reg_48_select), |
| 2043 | .clr_int_reg_49_select (clr_int_reg_49_select), |
| 2044 | .clr_int_reg_50_select (clr_int_reg_50_select), |
| 2045 | .clr_int_reg_51_select (clr_int_reg_51_select), |
| 2046 | .clr_int_reg_52_select (clr_int_reg_52_select), |
| 2047 | .clr_int_reg_53_select (clr_int_reg_53_select), |
| 2048 | .clr_int_reg_54_select (clr_int_reg_54_select), |
| 2049 | .clr_int_reg_55_select (clr_int_reg_55_select), |
| 2050 | .clr_int_reg_56_select (clr_int_reg_56_select), |
| 2051 | .clr_int_reg_57_select (clr_int_reg_57_select), |
| 2052 | .clr_int_reg_58_select (clr_int_reg_58_select), |
| 2053 | .clr_int_reg_59_select (clr_int_reg_59_select), |
| 2054 | .clr_int_reg_62_select (clr_int_reg_62_select), |
| 2055 | .clr_int_reg_63_select (clr_int_reg_63_select), |
| 2056 | .interrupt_retry_timer_select_pulse (interrupt_retry_timer_select_pulse), |
| 2057 | .interrupt_state_status_1_select (interrupt_state_status_1_select), |
| 2058 | .interrupt_state_status_2_select (interrupt_state_status_2_select) |
| 2059 | ); |
| 2060 | |
| 2061 | //==================================================================== |
| 2062 | // OUTPUT: csrbus_read_data (pipelining) |
| 2063 | //==================================================================== |
| 2064 | //----- connecting wires |
| 2065 | wire stage_mux_only_rst_l; |
| 2066 | wire stage_mux_only_daemon_csrbus_wr; |
| 2067 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data; |
| 2068 | |
| 2069 | //----- Stage: 1 / Grp: default_grp (87 inputs / 1 outputs) |
| 2070 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out; |
| 2071 | wire default_grp_interrupt_mapping_20_select_pulse; |
| 2072 | wire default_grp_interrupt_mapping_21_select_pulse; |
| 2073 | wire default_grp_interrupt_mapping_22_select_pulse; |
| 2074 | wire default_grp_interrupt_mapping_23_select_pulse; |
| 2075 | wire default_grp_interrupt_mapping_24_select_pulse; |
| 2076 | wire default_grp_interrupt_mapping_25_select_pulse; |
| 2077 | wire default_grp_interrupt_mapping_26_select_pulse; |
| 2078 | wire default_grp_interrupt_mapping_27_select_pulse; |
| 2079 | wire default_grp_interrupt_mapping_28_select_pulse; |
| 2080 | wire default_grp_interrupt_mapping_29_select_pulse; |
| 2081 | wire default_grp_interrupt_mapping_30_select_pulse; |
| 2082 | wire default_grp_interrupt_mapping_31_select_pulse; |
| 2083 | wire default_grp_interrupt_mapping_32_select_pulse; |
| 2084 | wire default_grp_interrupt_mapping_33_select_pulse; |
| 2085 | wire default_grp_interrupt_mapping_34_select_pulse; |
| 2086 | wire default_grp_interrupt_mapping_35_select_pulse; |
| 2087 | wire default_grp_interrupt_mapping_36_select_pulse; |
| 2088 | wire default_grp_interrupt_mapping_37_select_pulse; |
| 2089 | wire default_grp_interrupt_mapping_38_select_pulse; |
| 2090 | wire default_grp_interrupt_mapping_39_select_pulse; |
| 2091 | wire default_grp_interrupt_mapping_40_select_pulse; |
| 2092 | wire default_grp_interrupt_mapping_41_select_pulse; |
| 2093 | wire default_grp_interrupt_mapping_42_select_pulse; |
| 2094 | wire default_grp_interrupt_mapping_43_select_pulse; |
| 2095 | wire default_grp_interrupt_mapping_44_select_pulse; |
| 2096 | wire default_grp_interrupt_mapping_45_select_pulse; |
| 2097 | wire default_grp_interrupt_mapping_46_select_pulse; |
| 2098 | wire default_grp_interrupt_mapping_47_select_pulse; |
| 2099 | wire default_grp_interrupt_mapping_48_select_pulse; |
| 2100 | wire default_grp_interrupt_mapping_49_select_pulse; |
| 2101 | wire default_grp_interrupt_mapping_50_select_pulse; |
| 2102 | wire default_grp_interrupt_mapping_51_select_pulse; |
| 2103 | wire default_grp_interrupt_mapping_52_select_pulse; |
| 2104 | wire default_grp_interrupt_mapping_53_select_pulse; |
| 2105 | wire default_grp_interrupt_mapping_54_select_pulse; |
| 2106 | wire default_grp_interrupt_mapping_55_select_pulse; |
| 2107 | wire default_grp_interrupt_mapping_56_select_pulse; |
| 2108 | wire default_grp_interrupt_mapping_57_select_pulse; |
| 2109 | wire default_grp_interrupt_mapping_58_select_pulse; |
| 2110 | wire default_grp_interrupt_mapping_59_select_pulse; |
| 2111 | wire default_grp_interrupt_mapping_62_select_pulse; |
| 2112 | wire default_grp_interrupt_mapping_63_select_pulse; |
| 2113 | wire default_grp_clr_int_reg_20_select; |
| 2114 | wire default_grp_clr_int_reg_21_select; |
| 2115 | wire default_grp_clr_int_reg_22_select; |
| 2116 | wire default_grp_clr_int_reg_23_select; |
| 2117 | wire default_grp_clr_int_reg_24_select; |
| 2118 | wire default_grp_clr_int_reg_25_select; |
| 2119 | wire default_grp_clr_int_reg_26_select; |
| 2120 | wire default_grp_clr_int_reg_27_select; |
| 2121 | wire default_grp_clr_int_reg_28_select; |
| 2122 | wire default_grp_clr_int_reg_29_select; |
| 2123 | wire default_grp_clr_int_reg_30_select; |
| 2124 | wire default_grp_clr_int_reg_31_select; |
| 2125 | wire default_grp_clr_int_reg_32_select; |
| 2126 | wire default_grp_clr_int_reg_33_select; |
| 2127 | wire default_grp_clr_int_reg_34_select; |
| 2128 | wire default_grp_clr_int_reg_35_select; |
| 2129 | wire default_grp_clr_int_reg_36_select; |
| 2130 | wire default_grp_clr_int_reg_37_select; |
| 2131 | wire default_grp_clr_int_reg_38_select; |
| 2132 | wire default_grp_clr_int_reg_39_select; |
| 2133 | wire default_grp_clr_int_reg_40_select; |
| 2134 | wire default_grp_clr_int_reg_41_select; |
| 2135 | wire default_grp_clr_int_reg_42_select; |
| 2136 | wire default_grp_clr_int_reg_43_select; |
| 2137 | wire default_grp_clr_int_reg_44_select; |
| 2138 | wire default_grp_clr_int_reg_45_select; |
| 2139 | wire default_grp_clr_int_reg_46_select; |
| 2140 | wire default_grp_clr_int_reg_47_select; |
| 2141 | wire default_grp_clr_int_reg_48_select; |
| 2142 | wire default_grp_clr_int_reg_49_select; |
| 2143 | wire default_grp_clr_int_reg_50_select; |
| 2144 | wire default_grp_clr_int_reg_51_select; |
| 2145 | wire default_grp_clr_int_reg_52_select; |
| 2146 | wire default_grp_clr_int_reg_53_select; |
| 2147 | wire default_grp_clr_int_reg_54_select; |
| 2148 | wire default_grp_clr_int_reg_55_select; |
| 2149 | wire default_grp_clr_int_reg_56_select; |
| 2150 | wire default_grp_clr_int_reg_57_select; |
| 2151 | wire default_grp_clr_int_reg_58_select; |
| 2152 | wire default_grp_clr_int_reg_59_select; |
| 2153 | wire default_grp_clr_int_reg_62_select; |
| 2154 | wire default_grp_clr_int_reg_63_select; |
| 2155 | wire default_grp_interrupt_retry_timer_select_pulse; |
| 2156 | wire default_grp_interrupt_state_status_1_select; |
| 2157 | wire default_grp_interrupt_state_status_2_select; |
| 2158 | |
| 2159 | dmu_imu_iss_default_grp dmu_imu_iss_default_grp |
| 2160 | ( |
| 2161 | .clk (clk), |
| 2162 | .interrupt_mapping_20_mdo_mode_hw_read (interrupt_mapping_20_mdo_mode_hw_read), |
| 2163 | .interrupt_mapping_20_v_hw_read (interrupt_mapping_20_v_hw_read), |
| 2164 | .interrupt_mapping_20_t_id_hw_read (interrupt_mapping_20_t_id_hw_read), |
| 2165 | .interrupt_mapping_20_int_cntrl_num_hw_read (interrupt_mapping_20_int_cntrl_num_hw_read), |
| 2166 | .interrupt_mapping_20_select_pulse (default_grp_interrupt_mapping_20_select_pulse), |
| 2167 | .interrupt_mapping_21_mdo_mode_hw_read (interrupt_mapping_21_mdo_mode_hw_read), |
| 2168 | .interrupt_mapping_21_v_hw_read (interrupt_mapping_21_v_hw_read), |
| 2169 | .interrupt_mapping_21_t_id_hw_read (interrupt_mapping_21_t_id_hw_read), |
| 2170 | .interrupt_mapping_21_int_cntrl_num_hw_read (interrupt_mapping_21_int_cntrl_num_hw_read), |
| 2171 | .interrupt_mapping_21_select_pulse (default_grp_interrupt_mapping_21_select_pulse), |
| 2172 | .interrupt_mapping_22_mdo_mode_hw_read (interrupt_mapping_22_mdo_mode_hw_read), |
| 2173 | .interrupt_mapping_22_v_hw_read (interrupt_mapping_22_v_hw_read), |
| 2174 | .interrupt_mapping_22_t_id_hw_read (interrupt_mapping_22_t_id_hw_read), |
| 2175 | .interrupt_mapping_22_int_cntrl_num_hw_read (interrupt_mapping_22_int_cntrl_num_hw_read), |
| 2176 | .interrupt_mapping_22_select_pulse (default_grp_interrupt_mapping_22_select_pulse), |
| 2177 | .interrupt_mapping_23_mdo_mode_hw_read (interrupt_mapping_23_mdo_mode_hw_read), |
| 2178 | .interrupt_mapping_23_v_hw_read (interrupt_mapping_23_v_hw_read), |
| 2179 | .interrupt_mapping_23_t_id_hw_read (interrupt_mapping_23_t_id_hw_read), |
| 2180 | .interrupt_mapping_23_int_cntrl_num_hw_read (interrupt_mapping_23_int_cntrl_num_hw_read), |
| 2181 | .interrupt_mapping_23_select_pulse (default_grp_interrupt_mapping_23_select_pulse), |
| 2182 | .interrupt_mapping_24_mdo_mode_hw_read (interrupt_mapping_24_mdo_mode_hw_read), |
| 2183 | .interrupt_mapping_24_v_hw_read (interrupt_mapping_24_v_hw_read), |
| 2184 | .interrupt_mapping_24_t_id_hw_read (interrupt_mapping_24_t_id_hw_read), |
| 2185 | .interrupt_mapping_24_int_cntrl_num_hw_read (interrupt_mapping_24_int_cntrl_num_hw_read), |
| 2186 | .interrupt_mapping_24_select_pulse (default_grp_interrupt_mapping_24_select_pulse), |
| 2187 | .interrupt_mapping_25_mdo_mode_hw_read (interrupt_mapping_25_mdo_mode_hw_read), |
| 2188 | .interrupt_mapping_25_v_hw_read (interrupt_mapping_25_v_hw_read), |
| 2189 | .interrupt_mapping_25_t_id_hw_read (interrupt_mapping_25_t_id_hw_read), |
| 2190 | .interrupt_mapping_25_int_cntrl_num_hw_read (interrupt_mapping_25_int_cntrl_num_hw_read), |
| 2191 | .interrupt_mapping_25_select_pulse (default_grp_interrupt_mapping_25_select_pulse), |
| 2192 | .interrupt_mapping_26_mdo_mode_hw_read (interrupt_mapping_26_mdo_mode_hw_read), |
| 2193 | .interrupt_mapping_26_v_hw_read (interrupt_mapping_26_v_hw_read), |
| 2194 | .interrupt_mapping_26_t_id_hw_read (interrupt_mapping_26_t_id_hw_read), |
| 2195 | .interrupt_mapping_26_int_cntrl_num_hw_read (interrupt_mapping_26_int_cntrl_num_hw_read), |
| 2196 | .interrupt_mapping_26_select_pulse (default_grp_interrupt_mapping_26_select_pulse), |
| 2197 | .interrupt_mapping_27_mdo_mode_hw_read (interrupt_mapping_27_mdo_mode_hw_read), |
| 2198 | .interrupt_mapping_27_v_hw_read (interrupt_mapping_27_v_hw_read), |
| 2199 | .interrupt_mapping_27_t_id_hw_read (interrupt_mapping_27_t_id_hw_read), |
| 2200 | .interrupt_mapping_27_int_cntrl_num_hw_read (interrupt_mapping_27_int_cntrl_num_hw_read), |
| 2201 | .interrupt_mapping_27_select_pulse (default_grp_interrupt_mapping_27_select_pulse), |
| 2202 | .interrupt_mapping_28_mdo_mode_hw_read (interrupt_mapping_28_mdo_mode_hw_read), |
| 2203 | .interrupt_mapping_28_v_hw_read (interrupt_mapping_28_v_hw_read), |
| 2204 | .interrupt_mapping_28_t_id_hw_read (interrupt_mapping_28_t_id_hw_read), |
| 2205 | .interrupt_mapping_28_int_cntrl_num_hw_read (interrupt_mapping_28_int_cntrl_num_hw_read), |
| 2206 | .interrupt_mapping_28_select_pulse (default_grp_interrupt_mapping_28_select_pulse), |
| 2207 | .interrupt_mapping_29_mdo_mode_hw_read (interrupt_mapping_29_mdo_mode_hw_read), |
| 2208 | .interrupt_mapping_29_v_hw_read (interrupt_mapping_29_v_hw_read), |
| 2209 | .interrupt_mapping_29_t_id_hw_read (interrupt_mapping_29_t_id_hw_read), |
| 2210 | .interrupt_mapping_29_int_cntrl_num_hw_read (interrupt_mapping_29_int_cntrl_num_hw_read), |
| 2211 | .interrupt_mapping_29_select_pulse (default_grp_interrupt_mapping_29_select_pulse), |
| 2212 | .interrupt_mapping_30_mdo_mode_hw_read (interrupt_mapping_30_mdo_mode_hw_read), |
| 2213 | .interrupt_mapping_30_v_hw_read (interrupt_mapping_30_v_hw_read), |
| 2214 | .interrupt_mapping_30_t_id_hw_read (interrupt_mapping_30_t_id_hw_read), |
| 2215 | .interrupt_mapping_30_int_cntrl_num_hw_read (interrupt_mapping_30_int_cntrl_num_hw_read), |
| 2216 | .interrupt_mapping_30_select_pulse (default_grp_interrupt_mapping_30_select_pulse), |
| 2217 | .interrupt_mapping_31_mdo_mode_hw_read (interrupt_mapping_31_mdo_mode_hw_read), |
| 2218 | .interrupt_mapping_31_v_hw_read (interrupt_mapping_31_v_hw_read), |
| 2219 | .interrupt_mapping_31_t_id_hw_read (interrupt_mapping_31_t_id_hw_read), |
| 2220 | .interrupt_mapping_31_int_cntrl_num_hw_read (interrupt_mapping_31_int_cntrl_num_hw_read), |
| 2221 | .interrupt_mapping_31_select_pulse (default_grp_interrupt_mapping_31_select_pulse), |
| 2222 | .interrupt_mapping_32_mdo_mode_hw_read (interrupt_mapping_32_mdo_mode_hw_read), |
| 2223 | .interrupt_mapping_32_v_hw_read (interrupt_mapping_32_v_hw_read), |
| 2224 | .interrupt_mapping_32_t_id_hw_read (interrupt_mapping_32_t_id_hw_read), |
| 2225 | .interrupt_mapping_32_int_cntrl_num_hw_read (interrupt_mapping_32_int_cntrl_num_hw_read), |
| 2226 | .interrupt_mapping_32_select_pulse (default_grp_interrupt_mapping_32_select_pulse), |
| 2227 | .interrupt_mapping_33_mdo_mode_hw_read (interrupt_mapping_33_mdo_mode_hw_read), |
| 2228 | .interrupt_mapping_33_v_hw_read (interrupt_mapping_33_v_hw_read), |
| 2229 | .interrupt_mapping_33_t_id_hw_read (interrupt_mapping_33_t_id_hw_read), |
| 2230 | .interrupt_mapping_33_int_cntrl_num_hw_read (interrupt_mapping_33_int_cntrl_num_hw_read), |
| 2231 | .interrupt_mapping_33_select_pulse (default_grp_interrupt_mapping_33_select_pulse), |
| 2232 | .interrupt_mapping_34_mdo_mode_hw_read (interrupt_mapping_34_mdo_mode_hw_read), |
| 2233 | .interrupt_mapping_34_v_hw_read (interrupt_mapping_34_v_hw_read), |
| 2234 | .interrupt_mapping_34_t_id_hw_read (interrupt_mapping_34_t_id_hw_read), |
| 2235 | .interrupt_mapping_34_int_cntrl_num_hw_read (interrupt_mapping_34_int_cntrl_num_hw_read), |
| 2236 | .interrupt_mapping_34_select_pulse (default_grp_interrupt_mapping_34_select_pulse), |
| 2237 | .interrupt_mapping_35_mdo_mode_hw_read (interrupt_mapping_35_mdo_mode_hw_read), |
| 2238 | .interrupt_mapping_35_v_hw_read (interrupt_mapping_35_v_hw_read), |
| 2239 | .interrupt_mapping_35_t_id_hw_read (interrupt_mapping_35_t_id_hw_read), |
| 2240 | .interrupt_mapping_35_int_cntrl_num_hw_read (interrupt_mapping_35_int_cntrl_num_hw_read), |
| 2241 | .interrupt_mapping_35_select_pulse (default_grp_interrupt_mapping_35_select_pulse), |
| 2242 | .interrupt_mapping_36_mdo_mode_hw_read (interrupt_mapping_36_mdo_mode_hw_read), |
| 2243 | .interrupt_mapping_36_v_hw_read (interrupt_mapping_36_v_hw_read), |
| 2244 | .interrupt_mapping_36_t_id_hw_read (interrupt_mapping_36_t_id_hw_read), |
| 2245 | .interrupt_mapping_36_int_cntrl_num_hw_read (interrupt_mapping_36_int_cntrl_num_hw_read), |
| 2246 | .interrupt_mapping_36_select_pulse (default_grp_interrupt_mapping_36_select_pulse), |
| 2247 | .interrupt_mapping_37_mdo_mode_hw_read (interrupt_mapping_37_mdo_mode_hw_read), |
| 2248 | .interrupt_mapping_37_v_hw_read (interrupt_mapping_37_v_hw_read), |
| 2249 | .interrupt_mapping_37_t_id_hw_read (interrupt_mapping_37_t_id_hw_read), |
| 2250 | .interrupt_mapping_37_int_cntrl_num_hw_read (interrupt_mapping_37_int_cntrl_num_hw_read), |
| 2251 | .interrupt_mapping_37_select_pulse (default_grp_interrupt_mapping_37_select_pulse), |
| 2252 | .interrupt_mapping_38_mdo_mode_hw_read (interrupt_mapping_38_mdo_mode_hw_read), |
| 2253 | .interrupt_mapping_38_v_hw_read (interrupt_mapping_38_v_hw_read), |
| 2254 | .interrupt_mapping_38_t_id_hw_read (interrupt_mapping_38_t_id_hw_read), |
| 2255 | .interrupt_mapping_38_int_cntrl_num_hw_read (interrupt_mapping_38_int_cntrl_num_hw_read), |
| 2256 | .interrupt_mapping_38_select_pulse (default_grp_interrupt_mapping_38_select_pulse), |
| 2257 | .interrupt_mapping_39_mdo_mode_hw_read (interrupt_mapping_39_mdo_mode_hw_read), |
| 2258 | .interrupt_mapping_39_v_hw_read (interrupt_mapping_39_v_hw_read), |
| 2259 | .interrupt_mapping_39_t_id_hw_read (interrupt_mapping_39_t_id_hw_read), |
| 2260 | .interrupt_mapping_39_int_cntrl_num_hw_read (interrupt_mapping_39_int_cntrl_num_hw_read), |
| 2261 | .interrupt_mapping_39_select_pulse (default_grp_interrupt_mapping_39_select_pulse), |
| 2262 | .interrupt_mapping_40_mdo_mode_hw_read (interrupt_mapping_40_mdo_mode_hw_read), |
| 2263 | .interrupt_mapping_40_v_hw_read (interrupt_mapping_40_v_hw_read), |
| 2264 | .interrupt_mapping_40_t_id_hw_read (interrupt_mapping_40_t_id_hw_read), |
| 2265 | .interrupt_mapping_40_int_cntrl_num_hw_read (interrupt_mapping_40_int_cntrl_num_hw_read), |
| 2266 | .interrupt_mapping_40_select_pulse (default_grp_interrupt_mapping_40_select_pulse), |
| 2267 | .interrupt_mapping_41_mdo_mode_hw_read (interrupt_mapping_41_mdo_mode_hw_read), |
| 2268 | .interrupt_mapping_41_v_hw_read (interrupt_mapping_41_v_hw_read), |
| 2269 | .interrupt_mapping_41_t_id_hw_read (interrupt_mapping_41_t_id_hw_read), |
| 2270 | .interrupt_mapping_41_int_cntrl_num_hw_read (interrupt_mapping_41_int_cntrl_num_hw_read), |
| 2271 | .interrupt_mapping_41_select_pulse (default_grp_interrupt_mapping_41_select_pulse), |
| 2272 | .interrupt_mapping_42_mdo_mode_hw_read (interrupt_mapping_42_mdo_mode_hw_read), |
| 2273 | .interrupt_mapping_42_v_hw_read (interrupt_mapping_42_v_hw_read), |
| 2274 | .interrupt_mapping_42_t_id_hw_read (interrupt_mapping_42_t_id_hw_read), |
| 2275 | .interrupt_mapping_42_int_cntrl_num_hw_read (interrupt_mapping_42_int_cntrl_num_hw_read), |
| 2276 | .interrupt_mapping_42_select_pulse (default_grp_interrupt_mapping_42_select_pulse), |
| 2277 | .interrupt_mapping_43_mdo_mode_hw_read (interrupt_mapping_43_mdo_mode_hw_read), |
| 2278 | .interrupt_mapping_43_v_hw_read (interrupt_mapping_43_v_hw_read), |
| 2279 | .interrupt_mapping_43_t_id_hw_read (interrupt_mapping_43_t_id_hw_read), |
| 2280 | .interrupt_mapping_43_int_cntrl_num_hw_read (interrupt_mapping_43_int_cntrl_num_hw_read), |
| 2281 | .interrupt_mapping_43_select_pulse (default_grp_interrupt_mapping_43_select_pulse), |
| 2282 | .interrupt_mapping_44_mdo_mode_hw_read (interrupt_mapping_44_mdo_mode_hw_read), |
| 2283 | .interrupt_mapping_44_v_hw_read (interrupt_mapping_44_v_hw_read), |
| 2284 | .interrupt_mapping_44_t_id_hw_read (interrupt_mapping_44_t_id_hw_read), |
| 2285 | .interrupt_mapping_44_int_cntrl_num_hw_read (interrupt_mapping_44_int_cntrl_num_hw_read), |
| 2286 | .interrupt_mapping_44_select_pulse (default_grp_interrupt_mapping_44_select_pulse), |
| 2287 | .interrupt_mapping_45_mdo_mode_hw_read (interrupt_mapping_45_mdo_mode_hw_read), |
| 2288 | .interrupt_mapping_45_v_hw_read (interrupt_mapping_45_v_hw_read), |
| 2289 | .interrupt_mapping_45_t_id_hw_read (interrupt_mapping_45_t_id_hw_read), |
| 2290 | .interrupt_mapping_45_int_cntrl_num_hw_read (interrupt_mapping_45_int_cntrl_num_hw_read), |
| 2291 | .interrupt_mapping_45_select_pulse (default_grp_interrupt_mapping_45_select_pulse), |
| 2292 | .interrupt_mapping_46_mdo_mode_hw_read (interrupt_mapping_46_mdo_mode_hw_read), |
| 2293 | .interrupt_mapping_46_v_hw_read (interrupt_mapping_46_v_hw_read), |
| 2294 | .interrupt_mapping_46_t_id_hw_read (interrupt_mapping_46_t_id_hw_read), |
| 2295 | .interrupt_mapping_46_int_cntrl_num_hw_read (interrupt_mapping_46_int_cntrl_num_hw_read), |
| 2296 | .interrupt_mapping_46_select_pulse (default_grp_interrupt_mapping_46_select_pulse), |
| 2297 | .interrupt_mapping_47_mdo_mode_hw_read (interrupt_mapping_47_mdo_mode_hw_read), |
| 2298 | .interrupt_mapping_47_v_hw_read (interrupt_mapping_47_v_hw_read), |
| 2299 | .interrupt_mapping_47_t_id_hw_read (interrupt_mapping_47_t_id_hw_read), |
| 2300 | .interrupt_mapping_47_int_cntrl_num_hw_read (interrupt_mapping_47_int_cntrl_num_hw_read), |
| 2301 | .interrupt_mapping_47_select_pulse (default_grp_interrupt_mapping_47_select_pulse), |
| 2302 | .interrupt_mapping_48_mdo_mode_hw_read (interrupt_mapping_48_mdo_mode_hw_read), |
| 2303 | .interrupt_mapping_48_v_hw_read (interrupt_mapping_48_v_hw_read), |
| 2304 | .interrupt_mapping_48_t_id_hw_read (interrupt_mapping_48_t_id_hw_read), |
| 2305 | .interrupt_mapping_48_int_cntrl_num_hw_read (interrupt_mapping_48_int_cntrl_num_hw_read), |
| 2306 | .interrupt_mapping_48_select_pulse (default_grp_interrupt_mapping_48_select_pulse), |
| 2307 | .interrupt_mapping_49_mdo_mode_hw_read (interrupt_mapping_49_mdo_mode_hw_read), |
| 2308 | .interrupt_mapping_49_v_hw_read (interrupt_mapping_49_v_hw_read), |
| 2309 | .interrupt_mapping_49_t_id_hw_read (interrupt_mapping_49_t_id_hw_read), |
| 2310 | .interrupt_mapping_49_int_cntrl_num_hw_read (interrupt_mapping_49_int_cntrl_num_hw_read), |
| 2311 | .interrupt_mapping_49_select_pulse (default_grp_interrupt_mapping_49_select_pulse), |
| 2312 | .interrupt_mapping_50_mdo_mode_hw_read (interrupt_mapping_50_mdo_mode_hw_read), |
| 2313 | .interrupt_mapping_50_v_hw_read (interrupt_mapping_50_v_hw_read), |
| 2314 | .interrupt_mapping_50_t_id_hw_read (interrupt_mapping_50_t_id_hw_read), |
| 2315 | .interrupt_mapping_50_int_cntrl_num_hw_read (interrupt_mapping_50_int_cntrl_num_hw_read), |
| 2316 | .interrupt_mapping_50_select_pulse (default_grp_interrupt_mapping_50_select_pulse), |
| 2317 | .interrupt_mapping_51_mdo_mode_hw_read (interrupt_mapping_51_mdo_mode_hw_read), |
| 2318 | .interrupt_mapping_51_v_hw_read (interrupt_mapping_51_v_hw_read), |
| 2319 | .interrupt_mapping_51_t_id_hw_read (interrupt_mapping_51_t_id_hw_read), |
| 2320 | .interrupt_mapping_51_int_cntrl_num_hw_read (interrupt_mapping_51_int_cntrl_num_hw_read), |
| 2321 | .interrupt_mapping_51_select_pulse (default_grp_interrupt_mapping_51_select_pulse), |
| 2322 | .interrupt_mapping_52_mdo_mode_hw_read (interrupt_mapping_52_mdo_mode_hw_read), |
| 2323 | .interrupt_mapping_52_v_hw_read (interrupt_mapping_52_v_hw_read), |
| 2324 | .interrupt_mapping_52_t_id_hw_read (interrupt_mapping_52_t_id_hw_read), |
| 2325 | .interrupt_mapping_52_int_cntrl_num_hw_read (interrupt_mapping_52_int_cntrl_num_hw_read), |
| 2326 | .interrupt_mapping_52_select_pulse (default_grp_interrupt_mapping_52_select_pulse), |
| 2327 | .interrupt_mapping_53_mdo_mode_hw_read (interrupt_mapping_53_mdo_mode_hw_read), |
| 2328 | .interrupt_mapping_53_v_hw_read (interrupt_mapping_53_v_hw_read), |
| 2329 | .interrupt_mapping_53_t_id_hw_read (interrupt_mapping_53_t_id_hw_read), |
| 2330 | .interrupt_mapping_53_int_cntrl_num_hw_read (interrupt_mapping_53_int_cntrl_num_hw_read), |
| 2331 | .interrupt_mapping_53_select_pulse (default_grp_interrupt_mapping_53_select_pulse), |
| 2332 | .interrupt_mapping_54_mdo_mode_hw_read (interrupt_mapping_54_mdo_mode_hw_read), |
| 2333 | .interrupt_mapping_54_v_hw_read (interrupt_mapping_54_v_hw_read), |
| 2334 | .interrupt_mapping_54_t_id_hw_read (interrupt_mapping_54_t_id_hw_read), |
| 2335 | .interrupt_mapping_54_int_cntrl_num_hw_read (interrupt_mapping_54_int_cntrl_num_hw_read), |
| 2336 | .interrupt_mapping_54_select_pulse (default_grp_interrupt_mapping_54_select_pulse), |
| 2337 | .interrupt_mapping_55_mdo_mode_hw_read (interrupt_mapping_55_mdo_mode_hw_read), |
| 2338 | .interrupt_mapping_55_v_hw_read (interrupt_mapping_55_v_hw_read), |
| 2339 | .interrupt_mapping_55_t_id_hw_read (interrupt_mapping_55_t_id_hw_read), |
| 2340 | .interrupt_mapping_55_int_cntrl_num_hw_read (interrupt_mapping_55_int_cntrl_num_hw_read), |
| 2341 | .interrupt_mapping_55_select_pulse (default_grp_interrupt_mapping_55_select_pulse), |
| 2342 | .interrupt_mapping_56_mdo_mode_hw_read (interrupt_mapping_56_mdo_mode_hw_read), |
| 2343 | .interrupt_mapping_56_v_hw_read (interrupt_mapping_56_v_hw_read), |
| 2344 | .interrupt_mapping_56_t_id_hw_read (interrupt_mapping_56_t_id_hw_read), |
| 2345 | .interrupt_mapping_56_int_cntrl_num_hw_read (interrupt_mapping_56_int_cntrl_num_hw_read), |
| 2346 | .interrupt_mapping_56_select_pulse (default_grp_interrupt_mapping_56_select_pulse), |
| 2347 | .interrupt_mapping_57_mdo_mode_hw_read (interrupt_mapping_57_mdo_mode_hw_read), |
| 2348 | .interrupt_mapping_57_v_hw_read (interrupt_mapping_57_v_hw_read), |
| 2349 | .interrupt_mapping_57_t_id_hw_read (interrupt_mapping_57_t_id_hw_read), |
| 2350 | .interrupt_mapping_57_int_cntrl_num_hw_read (interrupt_mapping_57_int_cntrl_num_hw_read), |
| 2351 | .interrupt_mapping_57_select_pulse (default_grp_interrupt_mapping_57_select_pulse), |
| 2352 | .interrupt_mapping_58_mdo_mode_hw_read (interrupt_mapping_58_mdo_mode_hw_read), |
| 2353 | .interrupt_mapping_58_v_hw_read (interrupt_mapping_58_v_hw_read), |
| 2354 | .interrupt_mapping_58_t_id_hw_read (interrupt_mapping_58_t_id_hw_read), |
| 2355 | .interrupt_mapping_58_int_cntrl_num_hw_read (interrupt_mapping_58_int_cntrl_num_hw_read), |
| 2356 | .interrupt_mapping_58_select_pulse (default_grp_interrupt_mapping_58_select_pulse), |
| 2357 | .interrupt_mapping_59_mdo_mode_hw_read (interrupt_mapping_59_mdo_mode_hw_read), |
| 2358 | .interrupt_mapping_59_v_hw_read (interrupt_mapping_59_v_hw_read), |
| 2359 | .interrupt_mapping_59_t_id_hw_read (interrupt_mapping_59_t_id_hw_read), |
| 2360 | .interrupt_mapping_59_int_cntrl_num_hw_read (interrupt_mapping_59_int_cntrl_num_hw_read), |
| 2361 | .interrupt_mapping_59_select_pulse (default_grp_interrupt_mapping_59_select_pulse), |
| 2362 | .interrupt_mapping_62_mdo_mode_hw_read (interrupt_mapping_62_mdo_mode_hw_read), |
| 2363 | .interrupt_mapping_62_v_hw_read (interrupt_mapping_62_v_hw_read), |
| 2364 | .interrupt_mapping_62_t_id_hw_read (interrupt_mapping_62_t_id_hw_read), |
| 2365 | .interrupt_mapping_62_int_cntrl_num_hw_read (interrupt_mapping_62_int_cntrl_num_hw_read), |
| 2366 | .interrupt_mapping_62_select_pulse (default_grp_interrupt_mapping_62_select_pulse), |
| 2367 | .interrupt_mapping_63_mdo_mode_hw_read (interrupt_mapping_63_mdo_mode_hw_read), |
| 2368 | .interrupt_mapping_63_v_hw_read (interrupt_mapping_63_v_hw_read), |
| 2369 | .interrupt_mapping_63_t_id_hw_read (interrupt_mapping_63_t_id_hw_read), |
| 2370 | .interrupt_mapping_63_int_cntrl_num_hw_read (interrupt_mapping_63_int_cntrl_num_hw_read), |
| 2371 | .interrupt_mapping_63_select_pulse (default_grp_interrupt_mapping_63_select_pulse), |
| 2372 | .clr_int_reg_20_ext_select (clr_int_reg_20_ext_select), |
| 2373 | .clr_int_reg_20_select (default_grp_clr_int_reg_20_select), |
| 2374 | .clr_int_reg_20_ext_read_data |
| 2375 | ( |
| 2376 | { |
| 2377 | 62'b0, |
| 2378 | clr_int_reg_20_int_state_ext_read_data |
| 2379 | }), |
| 2380 | .clr_int_reg_20_int_state_ext_wr_data (clr_int_reg_20_int_state_ext_wr_data), |
| 2381 | .clr_int_reg_21_ext_select (clr_int_reg_21_ext_select), |
| 2382 | .clr_int_reg_21_select (default_grp_clr_int_reg_21_select), |
| 2383 | .clr_int_reg_21_ext_read_data |
| 2384 | ( |
| 2385 | { |
| 2386 | 62'b0, |
| 2387 | clr_int_reg_21_int_state_ext_read_data |
| 2388 | }), |
| 2389 | .clr_int_reg_21_int_state_ext_wr_data (clr_int_reg_21_int_state_ext_wr_data), |
| 2390 | .clr_int_reg_22_ext_select (clr_int_reg_22_ext_select), |
| 2391 | .clr_int_reg_22_select (default_grp_clr_int_reg_22_select), |
| 2392 | .clr_int_reg_22_ext_read_data |
| 2393 | ( |
| 2394 | { |
| 2395 | 62'b0, |
| 2396 | clr_int_reg_22_int_state_ext_read_data |
| 2397 | }), |
| 2398 | .clr_int_reg_22_int_state_ext_wr_data (clr_int_reg_22_int_state_ext_wr_data), |
| 2399 | .clr_int_reg_23_ext_select (clr_int_reg_23_ext_select), |
| 2400 | .clr_int_reg_23_select (default_grp_clr_int_reg_23_select), |
| 2401 | .clr_int_reg_23_ext_read_data |
| 2402 | ( |
| 2403 | { |
| 2404 | 62'b0, |
| 2405 | clr_int_reg_23_int_state_ext_read_data |
| 2406 | }), |
| 2407 | .clr_int_reg_23_int_state_ext_wr_data (clr_int_reg_23_int_state_ext_wr_data), |
| 2408 | .clr_int_reg_24_ext_select (clr_int_reg_24_ext_select), |
| 2409 | .clr_int_reg_24_select (default_grp_clr_int_reg_24_select), |
| 2410 | .clr_int_reg_24_ext_read_data |
| 2411 | ( |
| 2412 | { |
| 2413 | 62'b0, |
| 2414 | clr_int_reg_24_int_state_ext_read_data |
| 2415 | }), |
| 2416 | .clr_int_reg_24_int_state_ext_wr_data (clr_int_reg_24_int_state_ext_wr_data), |
| 2417 | .clr_int_reg_25_ext_select (clr_int_reg_25_ext_select), |
| 2418 | .clr_int_reg_25_select (default_grp_clr_int_reg_25_select), |
| 2419 | .clr_int_reg_25_ext_read_data |
| 2420 | ( |
| 2421 | { |
| 2422 | 62'b0, |
| 2423 | clr_int_reg_25_int_state_ext_read_data |
| 2424 | }), |
| 2425 | .clr_int_reg_25_int_state_ext_wr_data (clr_int_reg_25_int_state_ext_wr_data), |
| 2426 | .clr_int_reg_26_ext_select (clr_int_reg_26_ext_select), |
| 2427 | .clr_int_reg_26_select (default_grp_clr_int_reg_26_select), |
| 2428 | .clr_int_reg_26_ext_read_data |
| 2429 | ( |
| 2430 | { |
| 2431 | 62'b0, |
| 2432 | clr_int_reg_26_int_state_ext_read_data |
| 2433 | }), |
| 2434 | .clr_int_reg_26_int_state_ext_wr_data (clr_int_reg_26_int_state_ext_wr_data), |
| 2435 | .clr_int_reg_27_ext_select (clr_int_reg_27_ext_select), |
| 2436 | .clr_int_reg_27_select (default_grp_clr_int_reg_27_select), |
| 2437 | .clr_int_reg_27_ext_read_data |
| 2438 | ( |
| 2439 | { |
| 2440 | 62'b0, |
| 2441 | clr_int_reg_27_int_state_ext_read_data |
| 2442 | }), |
| 2443 | .clr_int_reg_27_int_state_ext_wr_data (clr_int_reg_27_int_state_ext_wr_data), |
| 2444 | .clr_int_reg_28_ext_select (clr_int_reg_28_ext_select), |
| 2445 | .clr_int_reg_28_select (default_grp_clr_int_reg_28_select), |
| 2446 | .clr_int_reg_28_ext_read_data |
| 2447 | ( |
| 2448 | { |
| 2449 | 62'b0, |
| 2450 | clr_int_reg_28_int_state_ext_read_data |
| 2451 | }), |
| 2452 | .clr_int_reg_28_int_state_ext_wr_data (clr_int_reg_28_int_state_ext_wr_data), |
| 2453 | .clr_int_reg_29_ext_select (clr_int_reg_29_ext_select), |
| 2454 | .clr_int_reg_29_select (default_grp_clr_int_reg_29_select), |
| 2455 | .clr_int_reg_29_ext_read_data |
| 2456 | ( |
| 2457 | { |
| 2458 | 62'b0, |
| 2459 | clr_int_reg_29_int_state_ext_read_data |
| 2460 | }), |
| 2461 | .clr_int_reg_29_int_state_ext_wr_data (clr_int_reg_29_int_state_ext_wr_data), |
| 2462 | .clr_int_reg_30_ext_select (clr_int_reg_30_ext_select), |
| 2463 | .clr_int_reg_30_select (default_grp_clr_int_reg_30_select), |
| 2464 | .clr_int_reg_30_ext_read_data |
| 2465 | ( |
| 2466 | { |
| 2467 | 62'b0, |
| 2468 | clr_int_reg_30_int_state_ext_read_data |
| 2469 | }), |
| 2470 | .clr_int_reg_30_int_state_ext_wr_data (clr_int_reg_30_int_state_ext_wr_data), |
| 2471 | .clr_int_reg_31_ext_select (clr_int_reg_31_ext_select), |
| 2472 | .clr_int_reg_31_select (default_grp_clr_int_reg_31_select), |
| 2473 | .clr_int_reg_31_ext_read_data |
| 2474 | ( |
| 2475 | { |
| 2476 | 62'b0, |
| 2477 | clr_int_reg_31_int_state_ext_read_data |
| 2478 | }), |
| 2479 | .clr_int_reg_31_int_state_ext_wr_data (clr_int_reg_31_int_state_ext_wr_data), |
| 2480 | .clr_int_reg_32_ext_select (clr_int_reg_32_ext_select), |
| 2481 | .clr_int_reg_32_select (default_grp_clr_int_reg_32_select), |
| 2482 | .clr_int_reg_32_ext_read_data |
| 2483 | ( |
| 2484 | { |
| 2485 | 62'b0, |
| 2486 | clr_int_reg_32_int_state_ext_read_data |
| 2487 | }), |
| 2488 | .clr_int_reg_32_int_state_ext_wr_data (clr_int_reg_32_int_state_ext_wr_data), |
| 2489 | .clr_int_reg_33_ext_select (clr_int_reg_33_ext_select), |
| 2490 | .clr_int_reg_33_select (default_grp_clr_int_reg_33_select), |
| 2491 | .clr_int_reg_33_ext_read_data |
| 2492 | ( |
| 2493 | { |
| 2494 | 62'b0, |
| 2495 | clr_int_reg_33_int_state_ext_read_data |
| 2496 | }), |
| 2497 | .clr_int_reg_33_int_state_ext_wr_data (clr_int_reg_33_int_state_ext_wr_data), |
| 2498 | .clr_int_reg_34_ext_select (clr_int_reg_34_ext_select), |
| 2499 | .clr_int_reg_34_select (default_grp_clr_int_reg_34_select), |
| 2500 | .clr_int_reg_34_ext_read_data |
| 2501 | ( |
| 2502 | { |
| 2503 | 62'b0, |
| 2504 | clr_int_reg_34_int_state_ext_read_data |
| 2505 | }), |
| 2506 | .clr_int_reg_34_int_state_ext_wr_data (clr_int_reg_34_int_state_ext_wr_data), |
| 2507 | .clr_int_reg_35_ext_select (clr_int_reg_35_ext_select), |
| 2508 | .clr_int_reg_35_select (default_grp_clr_int_reg_35_select), |
| 2509 | .clr_int_reg_35_ext_read_data |
| 2510 | ( |
| 2511 | { |
| 2512 | 62'b0, |
| 2513 | clr_int_reg_35_int_state_ext_read_data |
| 2514 | }), |
| 2515 | .clr_int_reg_35_int_state_ext_wr_data (clr_int_reg_35_int_state_ext_wr_data), |
| 2516 | .clr_int_reg_36_ext_select (clr_int_reg_36_ext_select), |
| 2517 | .clr_int_reg_36_select (default_grp_clr_int_reg_36_select), |
| 2518 | .clr_int_reg_36_ext_read_data |
| 2519 | ( |
| 2520 | { |
| 2521 | 62'b0, |
| 2522 | clr_int_reg_36_int_state_ext_read_data |
| 2523 | }), |
| 2524 | .clr_int_reg_36_int_state_ext_wr_data (clr_int_reg_36_int_state_ext_wr_data), |
| 2525 | .clr_int_reg_37_ext_select (clr_int_reg_37_ext_select), |
| 2526 | .clr_int_reg_37_select (default_grp_clr_int_reg_37_select), |
| 2527 | .clr_int_reg_37_ext_read_data |
| 2528 | ( |
| 2529 | { |
| 2530 | 62'b0, |
| 2531 | clr_int_reg_37_int_state_ext_read_data |
| 2532 | }), |
| 2533 | .clr_int_reg_37_int_state_ext_wr_data (clr_int_reg_37_int_state_ext_wr_data), |
| 2534 | .clr_int_reg_38_ext_select (clr_int_reg_38_ext_select), |
| 2535 | .clr_int_reg_38_select (default_grp_clr_int_reg_38_select), |
| 2536 | .clr_int_reg_38_ext_read_data |
| 2537 | ( |
| 2538 | { |
| 2539 | 62'b0, |
| 2540 | clr_int_reg_38_int_state_ext_read_data |
| 2541 | }), |
| 2542 | .clr_int_reg_38_int_state_ext_wr_data (clr_int_reg_38_int_state_ext_wr_data), |
| 2543 | .clr_int_reg_39_ext_select (clr_int_reg_39_ext_select), |
| 2544 | .clr_int_reg_39_select (default_grp_clr_int_reg_39_select), |
| 2545 | .clr_int_reg_39_ext_read_data |
| 2546 | ( |
| 2547 | { |
| 2548 | 62'b0, |
| 2549 | clr_int_reg_39_int_state_ext_read_data |
| 2550 | }), |
| 2551 | .clr_int_reg_39_int_state_ext_wr_data (clr_int_reg_39_int_state_ext_wr_data), |
| 2552 | .clr_int_reg_40_ext_select (clr_int_reg_40_ext_select), |
| 2553 | .clr_int_reg_40_select (default_grp_clr_int_reg_40_select), |
| 2554 | .clr_int_reg_40_ext_read_data |
| 2555 | ( |
| 2556 | { |
| 2557 | 62'b0, |
| 2558 | clr_int_reg_40_int_state_ext_read_data |
| 2559 | }), |
| 2560 | .clr_int_reg_40_int_state_ext_wr_data (clr_int_reg_40_int_state_ext_wr_data), |
| 2561 | .clr_int_reg_41_ext_select (clr_int_reg_41_ext_select), |
| 2562 | .clr_int_reg_41_select (default_grp_clr_int_reg_41_select), |
| 2563 | .clr_int_reg_41_ext_read_data |
| 2564 | ( |
| 2565 | { |
| 2566 | 62'b0, |
| 2567 | clr_int_reg_41_int_state_ext_read_data |
| 2568 | }), |
| 2569 | .clr_int_reg_41_int_state_ext_wr_data (clr_int_reg_41_int_state_ext_wr_data), |
| 2570 | .clr_int_reg_42_ext_select (clr_int_reg_42_ext_select), |
| 2571 | .clr_int_reg_42_select (default_grp_clr_int_reg_42_select), |
| 2572 | .clr_int_reg_42_ext_read_data |
| 2573 | ( |
| 2574 | { |
| 2575 | 62'b0, |
| 2576 | clr_int_reg_42_int_state_ext_read_data |
| 2577 | }), |
| 2578 | .clr_int_reg_42_int_state_ext_wr_data (clr_int_reg_42_int_state_ext_wr_data), |
| 2579 | .clr_int_reg_43_ext_select (clr_int_reg_43_ext_select), |
| 2580 | .clr_int_reg_43_select (default_grp_clr_int_reg_43_select), |
| 2581 | .clr_int_reg_43_ext_read_data |
| 2582 | ( |
| 2583 | { |
| 2584 | 62'b0, |
| 2585 | clr_int_reg_43_int_state_ext_read_data |
| 2586 | }), |
| 2587 | .clr_int_reg_43_int_state_ext_wr_data (clr_int_reg_43_int_state_ext_wr_data), |
| 2588 | .clr_int_reg_44_ext_select (clr_int_reg_44_ext_select), |
| 2589 | .clr_int_reg_44_select (default_grp_clr_int_reg_44_select), |
| 2590 | .clr_int_reg_44_ext_read_data |
| 2591 | ( |
| 2592 | { |
| 2593 | 62'b0, |
| 2594 | clr_int_reg_44_int_state_ext_read_data |
| 2595 | }), |
| 2596 | .clr_int_reg_44_int_state_ext_wr_data (clr_int_reg_44_int_state_ext_wr_data), |
| 2597 | .clr_int_reg_45_ext_select (clr_int_reg_45_ext_select), |
| 2598 | .clr_int_reg_45_select (default_grp_clr_int_reg_45_select), |
| 2599 | .clr_int_reg_45_ext_read_data |
| 2600 | ( |
| 2601 | { |
| 2602 | 62'b0, |
| 2603 | clr_int_reg_45_int_state_ext_read_data |
| 2604 | }), |
| 2605 | .clr_int_reg_45_int_state_ext_wr_data (clr_int_reg_45_int_state_ext_wr_data), |
| 2606 | .clr_int_reg_46_ext_select (clr_int_reg_46_ext_select), |
| 2607 | .clr_int_reg_46_select (default_grp_clr_int_reg_46_select), |
| 2608 | .clr_int_reg_46_ext_read_data |
| 2609 | ( |
| 2610 | { |
| 2611 | 62'b0, |
| 2612 | clr_int_reg_46_int_state_ext_read_data |
| 2613 | }), |
| 2614 | .clr_int_reg_46_int_state_ext_wr_data (clr_int_reg_46_int_state_ext_wr_data), |
| 2615 | .clr_int_reg_47_ext_select (clr_int_reg_47_ext_select), |
| 2616 | .clr_int_reg_47_select (default_grp_clr_int_reg_47_select), |
| 2617 | .clr_int_reg_47_ext_read_data |
| 2618 | ( |
| 2619 | { |
| 2620 | 62'b0, |
| 2621 | clr_int_reg_47_int_state_ext_read_data |
| 2622 | }), |
| 2623 | .clr_int_reg_47_int_state_ext_wr_data (clr_int_reg_47_int_state_ext_wr_data), |
| 2624 | .clr_int_reg_48_ext_select (clr_int_reg_48_ext_select), |
| 2625 | .clr_int_reg_48_select (default_grp_clr_int_reg_48_select), |
| 2626 | .clr_int_reg_48_ext_read_data |
| 2627 | ( |
| 2628 | { |
| 2629 | 62'b0, |
| 2630 | clr_int_reg_48_int_state_ext_read_data |
| 2631 | }), |
| 2632 | .clr_int_reg_48_int_state_ext_wr_data (clr_int_reg_48_int_state_ext_wr_data), |
| 2633 | .clr_int_reg_49_ext_select (clr_int_reg_49_ext_select), |
| 2634 | .clr_int_reg_49_select (default_grp_clr_int_reg_49_select), |
| 2635 | .clr_int_reg_49_ext_read_data |
| 2636 | ( |
| 2637 | { |
| 2638 | 62'b0, |
| 2639 | clr_int_reg_49_int_state_ext_read_data |
| 2640 | }), |
| 2641 | .clr_int_reg_49_int_state_ext_wr_data (clr_int_reg_49_int_state_ext_wr_data), |
| 2642 | .clr_int_reg_50_ext_select (clr_int_reg_50_ext_select), |
| 2643 | .clr_int_reg_50_select (default_grp_clr_int_reg_50_select), |
| 2644 | .clr_int_reg_50_ext_read_data |
| 2645 | ( |
| 2646 | { |
| 2647 | 62'b0, |
| 2648 | clr_int_reg_50_int_state_ext_read_data |
| 2649 | }), |
| 2650 | .clr_int_reg_50_int_state_ext_wr_data (clr_int_reg_50_int_state_ext_wr_data), |
| 2651 | .clr_int_reg_51_ext_select (clr_int_reg_51_ext_select), |
| 2652 | .clr_int_reg_51_select (default_grp_clr_int_reg_51_select), |
| 2653 | .clr_int_reg_51_ext_read_data |
| 2654 | ( |
| 2655 | { |
| 2656 | 62'b0, |
| 2657 | clr_int_reg_51_int_state_ext_read_data |
| 2658 | }), |
| 2659 | .clr_int_reg_51_int_state_ext_wr_data (clr_int_reg_51_int_state_ext_wr_data), |
| 2660 | .clr_int_reg_52_ext_select (clr_int_reg_52_ext_select), |
| 2661 | .clr_int_reg_52_select (default_grp_clr_int_reg_52_select), |
| 2662 | .clr_int_reg_52_ext_read_data |
| 2663 | ( |
| 2664 | { |
| 2665 | 62'b0, |
| 2666 | clr_int_reg_52_int_state_ext_read_data |
| 2667 | }), |
| 2668 | .clr_int_reg_52_int_state_ext_wr_data (clr_int_reg_52_int_state_ext_wr_data), |
| 2669 | .clr_int_reg_53_ext_select (clr_int_reg_53_ext_select), |
| 2670 | .clr_int_reg_53_select (default_grp_clr_int_reg_53_select), |
| 2671 | .clr_int_reg_53_ext_read_data |
| 2672 | ( |
| 2673 | { |
| 2674 | 62'b0, |
| 2675 | clr_int_reg_53_int_state_ext_read_data |
| 2676 | }), |
| 2677 | .clr_int_reg_53_int_state_ext_wr_data (clr_int_reg_53_int_state_ext_wr_data), |
| 2678 | .clr_int_reg_54_ext_select (clr_int_reg_54_ext_select), |
| 2679 | .clr_int_reg_54_select (default_grp_clr_int_reg_54_select), |
| 2680 | .clr_int_reg_54_ext_read_data |
| 2681 | ( |
| 2682 | { |
| 2683 | 62'b0, |
| 2684 | clr_int_reg_54_int_state_ext_read_data |
| 2685 | }), |
| 2686 | .clr_int_reg_54_int_state_ext_wr_data (clr_int_reg_54_int_state_ext_wr_data), |
| 2687 | .clr_int_reg_55_ext_select (clr_int_reg_55_ext_select), |
| 2688 | .clr_int_reg_55_select (default_grp_clr_int_reg_55_select), |
| 2689 | .clr_int_reg_55_ext_read_data |
| 2690 | ( |
| 2691 | { |
| 2692 | 62'b0, |
| 2693 | clr_int_reg_55_int_state_ext_read_data |
| 2694 | }), |
| 2695 | .clr_int_reg_55_int_state_ext_wr_data (clr_int_reg_55_int_state_ext_wr_data), |
| 2696 | .clr_int_reg_56_ext_select (clr_int_reg_56_ext_select), |
| 2697 | .clr_int_reg_56_select (default_grp_clr_int_reg_56_select), |
| 2698 | .clr_int_reg_56_ext_read_data |
| 2699 | ( |
| 2700 | { |
| 2701 | 62'b0, |
| 2702 | clr_int_reg_56_int_state_ext_read_data |
| 2703 | }), |
| 2704 | .clr_int_reg_56_int_state_ext_wr_data (clr_int_reg_56_int_state_ext_wr_data), |
| 2705 | .clr_int_reg_57_ext_select (clr_int_reg_57_ext_select), |
| 2706 | .clr_int_reg_57_select (default_grp_clr_int_reg_57_select), |
| 2707 | .clr_int_reg_57_ext_read_data |
| 2708 | ( |
| 2709 | { |
| 2710 | 62'b0, |
| 2711 | clr_int_reg_57_int_state_ext_read_data |
| 2712 | }), |
| 2713 | .clr_int_reg_57_int_state_ext_wr_data (clr_int_reg_57_int_state_ext_wr_data), |
| 2714 | .clr_int_reg_58_ext_select (clr_int_reg_58_ext_select), |
| 2715 | .clr_int_reg_58_select (default_grp_clr_int_reg_58_select), |
| 2716 | .clr_int_reg_58_ext_read_data |
| 2717 | ( |
| 2718 | { |
| 2719 | 62'b0, |
| 2720 | clr_int_reg_58_int_state_ext_read_data |
| 2721 | }), |
| 2722 | .clr_int_reg_58_int_state_ext_wr_data (clr_int_reg_58_int_state_ext_wr_data), |
| 2723 | .clr_int_reg_59_ext_select (clr_int_reg_59_ext_select), |
| 2724 | .clr_int_reg_59_select (default_grp_clr_int_reg_59_select), |
| 2725 | .clr_int_reg_59_ext_read_data |
| 2726 | ( |
| 2727 | { |
| 2728 | 62'b0, |
| 2729 | clr_int_reg_59_int_state_ext_read_data |
| 2730 | }), |
| 2731 | .clr_int_reg_59_int_state_ext_wr_data (clr_int_reg_59_int_state_ext_wr_data), |
| 2732 | .clr_int_reg_62_ext_select (clr_int_reg_62_ext_select), |
| 2733 | .clr_int_reg_62_select (default_grp_clr_int_reg_62_select), |
| 2734 | .clr_int_reg_62_ext_read_data |
| 2735 | ( |
| 2736 | { |
| 2737 | 62'b0, |
| 2738 | clr_int_reg_62_int_state_ext_read_data |
| 2739 | }), |
| 2740 | .clr_int_reg_62_int_state_ext_wr_data (clr_int_reg_62_int_state_ext_wr_data), |
| 2741 | .clr_int_reg_63_ext_select (clr_int_reg_63_ext_select), |
| 2742 | .clr_int_reg_63_select (default_grp_clr_int_reg_63_select), |
| 2743 | .clr_int_reg_63_ext_read_data |
| 2744 | ( |
| 2745 | { |
| 2746 | 62'b0, |
| 2747 | clr_int_reg_63_int_state_ext_read_data |
| 2748 | }), |
| 2749 | .clr_int_reg_63_int_state_ext_wr_data (clr_int_reg_63_int_state_ext_wr_data), |
| 2750 | .interrupt_retry_timer_limit_hw_read (interrupt_retry_timer_limit_hw_read), |
| 2751 | .interrupt_retry_timer_select_pulse (default_grp_interrupt_retry_timer_select_pulse), |
| 2752 | .interrupt_state_status_1_select (default_grp_interrupt_state_status_1_select), |
| 2753 | .interrupt_state_status_1_ext_read_data |
| 2754 | ( |
| 2755 | { |
| 2756 | interrupt_state_status_1_state_ext_read_data, |
| 2757 | 40'b0 |
| 2758 | }), |
| 2759 | .interrupt_state_status_2_select (default_grp_interrupt_state_status_2_select), |
| 2760 | .interrupt_state_status_2_ext_read_data |
| 2761 | ( |
| 2762 | { |
| 2763 | interrupt_state_status_2_state_ext_read_data |
| 2764 | }), |
| 2765 | .rst_l (stage_mux_only_rst_l), |
| 2766 | .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr), |
| 2767 | .daemon_csrbus_wr_out (ext_wr), |
| 2768 | .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data), |
| 2769 | .read_data_0_out (default_grp_read_data_0_out) |
| 2770 | ); |
| 2771 | |
| 2772 | //----- Stage: 2 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only) |
| 2773 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out; |
| 2774 | |
| 2775 | dmu_imu_iss_stage_mux_only dmu_imu_iss_stage_mux_only |
| 2776 | ( |
| 2777 | .clk (clk), |
| 2778 | .read_data_0 (default_grp_read_data_0_out), |
| 2779 | .interrupt_mapping_20_select_pulse (interrupt_mapping_20_select_pulse), |
| 2780 | .interrupt_mapping_20_select_pulse_out (default_grp_interrupt_mapping_20_select_pulse), |
| 2781 | .interrupt_mapping_21_select_pulse (interrupt_mapping_21_select_pulse), |
| 2782 | .interrupt_mapping_21_select_pulse_out (default_grp_interrupt_mapping_21_select_pulse), |
| 2783 | .interrupt_mapping_22_select_pulse (interrupt_mapping_22_select_pulse), |
| 2784 | .interrupt_mapping_22_select_pulse_out (default_grp_interrupt_mapping_22_select_pulse), |
| 2785 | .interrupt_mapping_23_select_pulse (interrupt_mapping_23_select_pulse), |
| 2786 | .interrupt_mapping_23_select_pulse_out (default_grp_interrupt_mapping_23_select_pulse), |
| 2787 | .interrupt_mapping_24_select_pulse (interrupt_mapping_24_select_pulse), |
| 2788 | .interrupt_mapping_24_select_pulse_out (default_grp_interrupt_mapping_24_select_pulse), |
| 2789 | .interrupt_mapping_25_select_pulse (interrupt_mapping_25_select_pulse), |
| 2790 | .interrupt_mapping_25_select_pulse_out (default_grp_interrupt_mapping_25_select_pulse), |
| 2791 | .interrupt_mapping_26_select_pulse (interrupt_mapping_26_select_pulse), |
| 2792 | .interrupt_mapping_26_select_pulse_out (default_grp_interrupt_mapping_26_select_pulse), |
| 2793 | .interrupt_mapping_27_select_pulse (interrupt_mapping_27_select_pulse), |
| 2794 | .interrupt_mapping_27_select_pulse_out (default_grp_interrupt_mapping_27_select_pulse), |
| 2795 | .interrupt_mapping_28_select_pulse (interrupt_mapping_28_select_pulse), |
| 2796 | .interrupt_mapping_28_select_pulse_out (default_grp_interrupt_mapping_28_select_pulse), |
| 2797 | .interrupt_mapping_29_select_pulse (interrupt_mapping_29_select_pulse), |
| 2798 | .interrupt_mapping_29_select_pulse_out (default_grp_interrupt_mapping_29_select_pulse), |
| 2799 | .interrupt_mapping_30_select_pulse (interrupt_mapping_30_select_pulse), |
| 2800 | .interrupt_mapping_30_select_pulse_out (default_grp_interrupt_mapping_30_select_pulse), |
| 2801 | .interrupt_mapping_31_select_pulse (interrupt_mapping_31_select_pulse), |
| 2802 | .interrupt_mapping_31_select_pulse_out (default_grp_interrupt_mapping_31_select_pulse), |
| 2803 | .interrupt_mapping_32_select_pulse (interrupt_mapping_32_select_pulse), |
| 2804 | .interrupt_mapping_32_select_pulse_out (default_grp_interrupt_mapping_32_select_pulse), |
| 2805 | .interrupt_mapping_33_select_pulse (interrupt_mapping_33_select_pulse), |
| 2806 | .interrupt_mapping_33_select_pulse_out (default_grp_interrupt_mapping_33_select_pulse), |
| 2807 | .interrupt_mapping_34_select_pulse (interrupt_mapping_34_select_pulse), |
| 2808 | .interrupt_mapping_34_select_pulse_out (default_grp_interrupt_mapping_34_select_pulse), |
| 2809 | .interrupt_mapping_35_select_pulse (interrupt_mapping_35_select_pulse), |
| 2810 | .interrupt_mapping_35_select_pulse_out (default_grp_interrupt_mapping_35_select_pulse), |
| 2811 | .interrupt_mapping_36_select_pulse (interrupt_mapping_36_select_pulse), |
| 2812 | .interrupt_mapping_36_select_pulse_out (default_grp_interrupt_mapping_36_select_pulse), |
| 2813 | .interrupt_mapping_37_select_pulse (interrupt_mapping_37_select_pulse), |
| 2814 | .interrupt_mapping_37_select_pulse_out (default_grp_interrupt_mapping_37_select_pulse), |
| 2815 | .interrupt_mapping_38_select_pulse (interrupt_mapping_38_select_pulse), |
| 2816 | .interrupt_mapping_38_select_pulse_out (default_grp_interrupt_mapping_38_select_pulse), |
| 2817 | .interrupt_mapping_39_select_pulse (interrupt_mapping_39_select_pulse), |
| 2818 | .interrupt_mapping_39_select_pulse_out (default_grp_interrupt_mapping_39_select_pulse), |
| 2819 | .interrupt_mapping_40_select_pulse (interrupt_mapping_40_select_pulse), |
| 2820 | .interrupt_mapping_40_select_pulse_out (default_grp_interrupt_mapping_40_select_pulse), |
| 2821 | .interrupt_mapping_41_select_pulse (interrupt_mapping_41_select_pulse), |
| 2822 | .interrupt_mapping_41_select_pulse_out (default_grp_interrupt_mapping_41_select_pulse), |
| 2823 | .interrupt_mapping_42_select_pulse (interrupt_mapping_42_select_pulse), |
| 2824 | .interrupt_mapping_42_select_pulse_out (default_grp_interrupt_mapping_42_select_pulse), |
| 2825 | .interrupt_mapping_43_select_pulse (interrupt_mapping_43_select_pulse), |
| 2826 | .interrupt_mapping_43_select_pulse_out (default_grp_interrupt_mapping_43_select_pulse), |
| 2827 | .interrupt_mapping_44_select_pulse (interrupt_mapping_44_select_pulse), |
| 2828 | .interrupt_mapping_44_select_pulse_out (default_grp_interrupt_mapping_44_select_pulse), |
| 2829 | .interrupt_mapping_45_select_pulse (interrupt_mapping_45_select_pulse), |
| 2830 | .interrupt_mapping_45_select_pulse_out (default_grp_interrupt_mapping_45_select_pulse), |
| 2831 | .interrupt_mapping_46_select_pulse (interrupt_mapping_46_select_pulse), |
| 2832 | .interrupt_mapping_46_select_pulse_out (default_grp_interrupt_mapping_46_select_pulse), |
| 2833 | .interrupt_mapping_47_select_pulse (interrupt_mapping_47_select_pulse), |
| 2834 | .interrupt_mapping_47_select_pulse_out (default_grp_interrupt_mapping_47_select_pulse), |
| 2835 | .interrupt_mapping_48_select_pulse (interrupt_mapping_48_select_pulse), |
| 2836 | .interrupt_mapping_48_select_pulse_out (default_grp_interrupt_mapping_48_select_pulse), |
| 2837 | .interrupt_mapping_49_select_pulse (interrupt_mapping_49_select_pulse), |
| 2838 | .interrupt_mapping_49_select_pulse_out (default_grp_interrupt_mapping_49_select_pulse), |
| 2839 | .interrupt_mapping_50_select_pulse (interrupt_mapping_50_select_pulse), |
| 2840 | .interrupt_mapping_50_select_pulse_out (default_grp_interrupt_mapping_50_select_pulse), |
| 2841 | .interrupt_mapping_51_select_pulse (interrupt_mapping_51_select_pulse), |
| 2842 | .interrupt_mapping_51_select_pulse_out (default_grp_interrupt_mapping_51_select_pulse), |
| 2843 | .interrupt_mapping_52_select_pulse (interrupt_mapping_52_select_pulse), |
| 2844 | .interrupt_mapping_52_select_pulse_out (default_grp_interrupt_mapping_52_select_pulse), |
| 2845 | .interrupt_mapping_53_select_pulse (interrupt_mapping_53_select_pulse), |
| 2846 | .interrupt_mapping_53_select_pulse_out (default_grp_interrupt_mapping_53_select_pulse), |
| 2847 | .interrupt_mapping_54_select_pulse (interrupt_mapping_54_select_pulse), |
| 2848 | .interrupt_mapping_54_select_pulse_out (default_grp_interrupt_mapping_54_select_pulse), |
| 2849 | .interrupt_mapping_55_select_pulse (interrupt_mapping_55_select_pulse), |
| 2850 | .interrupt_mapping_55_select_pulse_out (default_grp_interrupt_mapping_55_select_pulse), |
| 2851 | .interrupt_mapping_56_select_pulse (interrupt_mapping_56_select_pulse), |
| 2852 | .interrupt_mapping_56_select_pulse_out (default_grp_interrupt_mapping_56_select_pulse), |
| 2853 | .interrupt_mapping_57_select_pulse (interrupt_mapping_57_select_pulse), |
| 2854 | .interrupt_mapping_57_select_pulse_out (default_grp_interrupt_mapping_57_select_pulse), |
| 2855 | .interrupt_mapping_58_select_pulse (interrupt_mapping_58_select_pulse), |
| 2856 | .interrupt_mapping_58_select_pulse_out (default_grp_interrupt_mapping_58_select_pulse), |
| 2857 | .interrupt_mapping_59_select_pulse (interrupt_mapping_59_select_pulse), |
| 2858 | .interrupt_mapping_59_select_pulse_out (default_grp_interrupt_mapping_59_select_pulse), |
| 2859 | .interrupt_mapping_62_select_pulse (interrupt_mapping_62_select_pulse), |
| 2860 | .interrupt_mapping_62_select_pulse_out (default_grp_interrupt_mapping_62_select_pulse), |
| 2861 | .interrupt_mapping_63_select_pulse (interrupt_mapping_63_select_pulse), |
| 2862 | .interrupt_mapping_63_select_pulse_out (default_grp_interrupt_mapping_63_select_pulse), |
| 2863 | .clr_int_reg_20_select (clr_int_reg_20_select), |
| 2864 | .clr_int_reg_20_select_out (default_grp_clr_int_reg_20_select), |
| 2865 | .clr_int_reg_21_select (clr_int_reg_21_select), |
| 2866 | .clr_int_reg_21_select_out (default_grp_clr_int_reg_21_select), |
| 2867 | .clr_int_reg_22_select (clr_int_reg_22_select), |
| 2868 | .clr_int_reg_22_select_out (default_grp_clr_int_reg_22_select), |
| 2869 | .clr_int_reg_23_select (clr_int_reg_23_select), |
| 2870 | .clr_int_reg_23_select_out (default_grp_clr_int_reg_23_select), |
| 2871 | .clr_int_reg_24_select (clr_int_reg_24_select), |
| 2872 | .clr_int_reg_24_select_out (default_grp_clr_int_reg_24_select), |
| 2873 | .clr_int_reg_25_select (clr_int_reg_25_select), |
| 2874 | .clr_int_reg_25_select_out (default_grp_clr_int_reg_25_select), |
| 2875 | .clr_int_reg_26_select (clr_int_reg_26_select), |
| 2876 | .clr_int_reg_26_select_out (default_grp_clr_int_reg_26_select), |
| 2877 | .clr_int_reg_27_select (clr_int_reg_27_select), |
| 2878 | .clr_int_reg_27_select_out (default_grp_clr_int_reg_27_select), |
| 2879 | .clr_int_reg_28_select (clr_int_reg_28_select), |
| 2880 | .clr_int_reg_28_select_out (default_grp_clr_int_reg_28_select), |
| 2881 | .clr_int_reg_29_select (clr_int_reg_29_select), |
| 2882 | .clr_int_reg_29_select_out (default_grp_clr_int_reg_29_select), |
| 2883 | .clr_int_reg_30_select (clr_int_reg_30_select), |
| 2884 | .clr_int_reg_30_select_out (default_grp_clr_int_reg_30_select), |
| 2885 | .clr_int_reg_31_select (clr_int_reg_31_select), |
| 2886 | .clr_int_reg_31_select_out (default_grp_clr_int_reg_31_select), |
| 2887 | .clr_int_reg_32_select (clr_int_reg_32_select), |
| 2888 | .clr_int_reg_32_select_out (default_grp_clr_int_reg_32_select), |
| 2889 | .clr_int_reg_33_select (clr_int_reg_33_select), |
| 2890 | .clr_int_reg_33_select_out (default_grp_clr_int_reg_33_select), |
| 2891 | .clr_int_reg_34_select (clr_int_reg_34_select), |
| 2892 | .clr_int_reg_34_select_out (default_grp_clr_int_reg_34_select), |
| 2893 | .clr_int_reg_35_select (clr_int_reg_35_select), |
| 2894 | .clr_int_reg_35_select_out (default_grp_clr_int_reg_35_select), |
| 2895 | .clr_int_reg_36_select (clr_int_reg_36_select), |
| 2896 | .clr_int_reg_36_select_out (default_grp_clr_int_reg_36_select), |
| 2897 | .clr_int_reg_37_select (clr_int_reg_37_select), |
| 2898 | .clr_int_reg_37_select_out (default_grp_clr_int_reg_37_select), |
| 2899 | .clr_int_reg_38_select (clr_int_reg_38_select), |
| 2900 | .clr_int_reg_38_select_out (default_grp_clr_int_reg_38_select), |
| 2901 | .clr_int_reg_39_select (clr_int_reg_39_select), |
| 2902 | .clr_int_reg_39_select_out (default_grp_clr_int_reg_39_select), |
| 2903 | .clr_int_reg_40_select (clr_int_reg_40_select), |
| 2904 | .clr_int_reg_40_select_out (default_grp_clr_int_reg_40_select), |
| 2905 | .clr_int_reg_41_select (clr_int_reg_41_select), |
| 2906 | .clr_int_reg_41_select_out (default_grp_clr_int_reg_41_select), |
| 2907 | .clr_int_reg_42_select (clr_int_reg_42_select), |
| 2908 | .clr_int_reg_42_select_out (default_grp_clr_int_reg_42_select), |
| 2909 | .clr_int_reg_43_select (clr_int_reg_43_select), |
| 2910 | .clr_int_reg_43_select_out (default_grp_clr_int_reg_43_select), |
| 2911 | .clr_int_reg_44_select (clr_int_reg_44_select), |
| 2912 | .clr_int_reg_44_select_out (default_grp_clr_int_reg_44_select), |
| 2913 | .clr_int_reg_45_select (clr_int_reg_45_select), |
| 2914 | .clr_int_reg_45_select_out (default_grp_clr_int_reg_45_select), |
| 2915 | .clr_int_reg_46_select (clr_int_reg_46_select), |
| 2916 | .clr_int_reg_46_select_out (default_grp_clr_int_reg_46_select), |
| 2917 | .clr_int_reg_47_select (clr_int_reg_47_select), |
| 2918 | .clr_int_reg_47_select_out (default_grp_clr_int_reg_47_select), |
| 2919 | .clr_int_reg_48_select (clr_int_reg_48_select), |
| 2920 | .clr_int_reg_48_select_out (default_grp_clr_int_reg_48_select), |
| 2921 | .clr_int_reg_49_select (clr_int_reg_49_select), |
| 2922 | .clr_int_reg_49_select_out (default_grp_clr_int_reg_49_select), |
| 2923 | .clr_int_reg_50_select (clr_int_reg_50_select), |
| 2924 | .clr_int_reg_50_select_out (default_grp_clr_int_reg_50_select), |
| 2925 | .clr_int_reg_51_select (clr_int_reg_51_select), |
| 2926 | .clr_int_reg_51_select_out (default_grp_clr_int_reg_51_select), |
| 2927 | .clr_int_reg_52_select (clr_int_reg_52_select), |
| 2928 | .clr_int_reg_52_select_out (default_grp_clr_int_reg_52_select), |
| 2929 | .clr_int_reg_53_select (clr_int_reg_53_select), |
| 2930 | .clr_int_reg_53_select_out (default_grp_clr_int_reg_53_select), |
| 2931 | .clr_int_reg_54_select (clr_int_reg_54_select), |
| 2932 | .clr_int_reg_54_select_out (default_grp_clr_int_reg_54_select), |
| 2933 | .clr_int_reg_55_select (clr_int_reg_55_select), |
| 2934 | .clr_int_reg_55_select_out (default_grp_clr_int_reg_55_select), |
| 2935 | .clr_int_reg_56_select (clr_int_reg_56_select), |
| 2936 | .clr_int_reg_56_select_out (default_grp_clr_int_reg_56_select), |
| 2937 | .clr_int_reg_57_select (clr_int_reg_57_select), |
| 2938 | .clr_int_reg_57_select_out (default_grp_clr_int_reg_57_select), |
| 2939 | .clr_int_reg_58_select (clr_int_reg_58_select), |
| 2940 | .clr_int_reg_58_select_out (default_grp_clr_int_reg_58_select), |
| 2941 | .clr_int_reg_59_select (clr_int_reg_59_select), |
| 2942 | .clr_int_reg_59_select_out (default_grp_clr_int_reg_59_select), |
| 2943 | .clr_int_reg_62_select (clr_int_reg_62_select), |
| 2944 | .clr_int_reg_62_select_out (default_grp_clr_int_reg_62_select), |
| 2945 | .clr_int_reg_63_select (clr_int_reg_63_select), |
| 2946 | .clr_int_reg_63_select_out (default_grp_clr_int_reg_63_select), |
| 2947 | .interrupt_retry_timer_select_pulse (interrupt_retry_timer_select_pulse), |
| 2948 | .interrupt_retry_timer_select_pulse_out (default_grp_interrupt_retry_timer_select_pulse), |
| 2949 | .interrupt_state_status_1_select (interrupt_state_status_1_select), |
| 2950 | .interrupt_state_status_1_select_out (default_grp_interrupt_state_status_1_select), |
| 2951 | .interrupt_state_status_2_select (interrupt_state_status_2_select), |
| 2952 | .interrupt_state_status_2_select_out (default_grp_interrupt_state_status_2_select), |
| 2953 | .daemon_csrbus_wr_in (daemon_csrbus_wr), |
| 2954 | .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr), |
| 2955 | .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data), |
| 2956 | .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data), |
| 2957 | .read_data_0_out (stage_mux_only_read_data_0_out), |
| 2958 | .rst_l (rst_l), |
| 2959 | .rst_l_out (stage_mux_only_rst_l) |
| 2960 | ); |
| 2961 | |
| 2962 | //----- OUTPUT: csrbus_read_data |
| 2963 | assign csrbus_read_data = stage_mux_only_read_data_0_out; |
| 2964 | |
| 2965 | endmodule // dmu_imu_iss_csr |