| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_rds_intx_csr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_rds_intx_csr |
| 36 | ( |
| 37 | clk, |
| 38 | csrbus_addr, |
| 39 | csrbus_wr_data, |
| 40 | csrbus_wr, |
| 41 | csrbus_valid, |
| 42 | csrbus_mapped, |
| 43 | csrbus_done, |
| 44 | csrbus_read_data, |
| 45 | rst_l, |
| 46 | csrbus_src_bus, |
| 47 | csrbus_acc_vio, |
| 48 | instance_id, |
| 49 | intx_status_reg_int_a_ext_read_data, |
| 50 | intx_status_reg_int_b_ext_read_data, |
| 51 | intx_status_reg_int_c_ext_read_data, |
| 52 | intx_status_reg_int_d_ext_read_data, |
| 53 | int_a_int_clr_reg_clr_hw_ld, |
| 54 | int_a_int_clr_reg_clr_hw_write, |
| 55 | int_a_int_clr_reg_clr_hw_read, |
| 56 | int_b_int_clr_reg_clr_hw_ld, |
| 57 | int_b_int_clr_reg_clr_hw_write, |
| 58 | int_b_int_clr_reg_clr_hw_read, |
| 59 | int_c_int_clr_reg_clr_hw_ld, |
| 60 | int_c_int_clr_reg_clr_hw_write, |
| 61 | int_c_int_clr_reg_clr_hw_read, |
| 62 | int_d_int_clr_reg_clr_hw_ld, |
| 63 | int_d_int_clr_reg_clr_hw_write, |
| 64 | int_d_int_clr_reg_clr_hw_read |
| 65 | ); |
| 66 | |
| 67 | //==================================================== |
| 68 | // Polarity declarations |
| 69 | //==================================================== |
| 70 | input clk; // Clock signal |
| 71 | input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus |
| 72 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 73 | input csrbus_wr; // Read/Write signal |
| 74 | input csrbus_valid; // Valid address |
| 75 | output csrbus_mapped; // Address is mapped |
| 76 | output csrbus_done; // Operation is done |
| 77 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus |
| 78 | input rst_l; // Reset signal |
| 79 | input [1:0] csrbus_src_bus; // Source bus |
| 80 | output csrbus_acc_vio; // Violation signal |
| 81 | input instance_id; // Instance ID |
| 82 | input [0:0] intx_status_reg_int_a_ext_read_data; // Ext read data (decode) |
| 83 | input [0:0] intx_status_reg_int_b_ext_read_data; // Ext read data (decode) |
| 84 | input [0:0] intx_status_reg_int_c_ext_read_data; // Ext read data (decode) |
| 85 | input [0:0] intx_status_reg_int_d_ext_read_data; // Ext read data (decode) |
| 86 | input int_a_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 87 | // int_a_int_clr_reg_clr. When set, <hw |
| 88 | // write signal> will be loaded into |
| 89 | // int_a_int_clr_reg. |
| 90 | input int_a_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 91 | // int_a_int_clr_reg_clr. |
| 92 | output int_a_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 93 | // of int_a_int_clr_reg_clr. |
| 94 | input int_b_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 95 | // int_b_int_clr_reg_clr. When set, <hw |
| 96 | // write signal> will be loaded into |
| 97 | // int_b_int_clr_reg. |
| 98 | input int_b_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 99 | // int_b_int_clr_reg_clr. |
| 100 | output int_b_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 101 | // of int_b_int_clr_reg_clr. |
| 102 | input int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 103 | // int_c_int_clr_reg_clr. When set, <hw |
| 104 | // write signal> will be loaded into |
| 105 | // int_c_int_clr_reg. |
| 106 | input int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 107 | // int_c_int_clr_reg_clr. |
| 108 | output int_c_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 109 | // of int_c_int_clr_reg_clr. |
| 110 | input int_d_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 111 | // int_d_int_clr_reg_clr. When set, <hw |
| 112 | // write signal> will be loaded into |
| 113 | // int_d_int_clr_reg. |
| 114 | input int_d_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 115 | // int_d_int_clr_reg_clr. |
| 116 | output int_d_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 117 | // of int_d_int_clr_reg_clr. |
| 118 | |
| 119 | //==================================================== |
| 120 | // Type declarations |
| 121 | //==================================================== |
| 122 | wire clk; // Clock signal |
| 123 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus |
| 124 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 125 | wire csrbus_wr; // Read/Write signal |
| 126 | wire csrbus_valid; // Valid address |
| 127 | wire csrbus_mapped; // Address is mapped |
| 128 | wire csrbus_done; // Operation is done |
| 129 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus |
| 130 | wire rst_l; // Reset signal |
| 131 | wire [1:0] csrbus_src_bus; // Source bus |
| 132 | wire csrbus_acc_vio; // Violation signal |
| 133 | wire instance_id; // Instance ID |
| 134 | wire [0:0] intx_status_reg_int_a_ext_read_data; // Ext read data (decode) |
| 135 | wire [0:0] intx_status_reg_int_b_ext_read_data; // Ext read data (decode) |
| 136 | wire [0:0] intx_status_reg_int_c_ext_read_data; // Ext read data (decode) |
| 137 | wire [0:0] intx_status_reg_int_d_ext_read_data; // Ext read data (decode) |
| 138 | wire int_a_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 139 | // int_a_int_clr_reg_clr. When set, <hw write |
| 140 | // signal> will be loaded into |
| 141 | // int_a_int_clr_reg. |
| 142 | wire int_a_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 143 | // int_a_int_clr_reg_clr. |
| 144 | wire int_a_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 145 | // of int_a_int_clr_reg_clr. |
| 146 | wire int_b_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 147 | // int_b_int_clr_reg_clr. When set, <hw write |
| 148 | // signal> will be loaded into |
| 149 | // int_b_int_clr_reg. |
| 150 | wire int_b_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 151 | // int_b_int_clr_reg_clr. |
| 152 | wire int_b_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 153 | // of int_b_int_clr_reg_clr. |
| 154 | wire int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 155 | // int_c_int_clr_reg_clr. When set, <hw write |
| 156 | // signal> will be loaded into |
| 157 | // int_c_int_clr_reg. |
| 158 | wire int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 159 | // int_c_int_clr_reg_clr. |
| 160 | wire int_c_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 161 | // of int_c_int_clr_reg_clr. |
| 162 | wire int_d_int_clr_reg_clr_hw_ld; // Hardware load enable for |
| 163 | // int_d_int_clr_reg_clr. When set, <hw write |
| 164 | // signal> will be loaded into |
| 165 | // int_d_int_clr_reg. |
| 166 | wire int_d_int_clr_reg_clr_hw_write; // data bus for hw loading of |
| 167 | // int_d_int_clr_reg_clr. |
| 168 | wire int_d_int_clr_reg_clr_hw_read; // This signal provides the current value |
| 169 | // of int_d_int_clr_reg_clr. |
| 170 | |
| 171 | //==================================================== |
| 172 | // Logic |
| 173 | //==================================================== |
| 174 | wire daemon_transaction_in_progress; |
| 175 | wire daemon_csrbus_mapped; |
| 176 | wire daemon_csrbus_valid; |
| 177 | // vlint flag_dangling_net_within_module off |
| 178 | // vlint flag_net_has_no_load off |
| 179 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp; |
| 180 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; |
| 181 | // vlint flag_dangling_net_within_module on |
| 182 | // vlint flag_net_has_no_load on |
| 183 | wire daemon_csrbus_done; |
| 184 | wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr; |
| 185 | wire daemon_csrbus_wr_tmp; |
| 186 | wire daemon_csrbus_wr; |
| 187 | |
| 188 | //summit modcovoff -bepgnv |
| 189 | pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon ( |
| 190 | .daemon_csrbus_valid (daemon_csrbus_valid), |
| 191 | .daemon_csrbus_mapped (daemon_csrbus_mapped), |
| 192 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp), |
| 193 | .daemon_csrbus_done (daemon_csrbus_done), |
| 194 | .daemon_csrbus_addr (daemon_csrbus_addr), |
| 195 | .daemon_csrbus_wr (daemon_csrbus_wr_tmp), |
| 196 | .daemon_transaction_in_progress (daemon_transaction_in_progress), |
| 197 | // synopsys translate_off |
| 198 | .clk(clk), |
| 199 | .csrbus_read_data (csrbus_read_data), |
| 200 | .rst_l (rst_l), |
| 201 | // synopsys translate_on |
| 202 | .csrbus_valid (csrbus_valid), |
| 203 | .csrbus_mapped (csrbus_mapped), |
| 204 | .csrbus_wr_data (csrbus_wr_data), |
| 205 | .csrbus_done (csrbus_done), |
| 206 | .csrbus_addr (csrbus_addr), |
| 207 | .csrbus_wr (csrbus_wr) |
| 208 | ); |
| 209 | //summit modcovon -bepgnv |
| 210 | |
| 211 | //==================================================================== |
| 212 | // Address decode |
| 213 | //==================================================================== |
| 214 | wire intx_status_reg_select; |
| 215 | wire int_a_int_clr_reg_select_pulse; |
| 216 | wire int_b_int_clr_reg_select_pulse; |
| 217 | wire int_c_int_clr_reg_select_pulse; |
| 218 | wire int_d_int_clr_reg_select_pulse; |
| 219 | |
| 220 | dmu_imu_rds_intx_addr_decode dmu_imu_rds_intx_addr_decode |
| 221 | ( |
| 222 | .clk (clk), |
| 223 | .rst_l (rst_l), |
| 224 | .daemon_csrbus_valid (daemon_csrbus_valid), |
| 225 | .daemon_csrbus_addr (daemon_csrbus_addr), |
| 226 | .csrbus_src_bus (csrbus_src_bus), |
| 227 | .daemon_csrbus_wr (daemon_csrbus_wr_tmp), |
| 228 | .daemon_csrbus_wr_out (daemon_csrbus_wr), |
| 229 | .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp), |
| 230 | .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data), |
| 231 | .daemon_csrbus_mapped (daemon_csrbus_mapped), |
| 232 | .csrbus_acc_vio (csrbus_acc_vio), |
| 233 | .daemon_transaction_in_progress (daemon_transaction_in_progress), |
| 234 | .instance_id (instance_id), |
| 235 | .daemon_csrbus_done (daemon_csrbus_done), |
| 236 | .intx_status_reg_select (intx_status_reg_select), |
| 237 | .int_a_int_clr_reg_select_pulse (int_a_int_clr_reg_select_pulse), |
| 238 | .int_b_int_clr_reg_select_pulse (int_b_int_clr_reg_select_pulse), |
| 239 | .int_c_int_clr_reg_select_pulse (int_c_int_clr_reg_select_pulse), |
| 240 | .int_d_int_clr_reg_select_pulse (int_d_int_clr_reg_select_pulse) |
| 241 | ); |
| 242 | |
| 243 | //==================================================================== |
| 244 | // OUTPUT: csrbus_read_data (pipelining) |
| 245 | //==================================================================== |
| 246 | //----- connecting wires |
| 247 | wire stage_mux_only_rst_l; |
| 248 | wire stage_mux_only_daemon_csrbus_wr; |
| 249 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data; |
| 250 | |
| 251 | //----- Stage: 1 / Grp: default_grp (5 inputs / 1 outputs) |
| 252 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out; |
| 253 | wire default_grp_intx_status_reg_select; |
| 254 | wire default_grp_int_a_int_clr_reg_select_pulse; |
| 255 | wire default_grp_int_b_int_clr_reg_select_pulse; |
| 256 | wire default_grp_int_c_int_clr_reg_select_pulse; |
| 257 | wire default_grp_int_d_int_clr_reg_select_pulse; |
| 258 | |
| 259 | dmu_imu_rds_intx_default_grp dmu_imu_rds_intx_default_grp |
| 260 | ( |
| 261 | .clk (clk), |
| 262 | .intx_status_reg_select (default_grp_intx_status_reg_select), |
| 263 | .intx_status_reg_ext_read_data |
| 264 | ( |
| 265 | { |
| 266 | 60'b0, |
| 267 | intx_status_reg_int_a_ext_read_data, |
| 268 | intx_status_reg_int_b_ext_read_data, |
| 269 | intx_status_reg_int_c_ext_read_data, |
| 270 | intx_status_reg_int_d_ext_read_data |
| 271 | }), |
| 272 | .int_a_int_clr_reg_clr_hw_ld (int_a_int_clr_reg_clr_hw_ld), |
| 273 | .int_a_int_clr_reg_clr_hw_write (int_a_int_clr_reg_clr_hw_write), |
| 274 | .int_a_int_clr_reg_clr_hw_read (int_a_int_clr_reg_clr_hw_read), |
| 275 | .int_a_int_clr_reg_select_pulse (default_grp_int_a_int_clr_reg_select_pulse), |
| 276 | .int_b_int_clr_reg_clr_hw_ld (int_b_int_clr_reg_clr_hw_ld), |
| 277 | .int_b_int_clr_reg_clr_hw_write (int_b_int_clr_reg_clr_hw_write), |
| 278 | .int_b_int_clr_reg_clr_hw_read (int_b_int_clr_reg_clr_hw_read), |
| 279 | .int_b_int_clr_reg_select_pulse (default_grp_int_b_int_clr_reg_select_pulse), |
| 280 | .int_c_int_clr_reg_clr_hw_ld (int_c_int_clr_reg_clr_hw_ld), |
| 281 | .int_c_int_clr_reg_clr_hw_write (int_c_int_clr_reg_clr_hw_write), |
| 282 | .int_c_int_clr_reg_clr_hw_read (int_c_int_clr_reg_clr_hw_read), |
| 283 | .int_c_int_clr_reg_select_pulse (default_grp_int_c_int_clr_reg_select_pulse), |
| 284 | .int_d_int_clr_reg_clr_hw_ld (int_d_int_clr_reg_clr_hw_ld), |
| 285 | .int_d_int_clr_reg_clr_hw_write (int_d_int_clr_reg_clr_hw_write), |
| 286 | .int_d_int_clr_reg_clr_hw_read (int_d_int_clr_reg_clr_hw_read), |
| 287 | .int_d_int_clr_reg_select_pulse (default_grp_int_d_int_clr_reg_select_pulse), |
| 288 | .rst_l (stage_mux_only_rst_l), |
| 289 | .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr), |
| 290 | .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data), |
| 291 | .read_data_0_out (default_grp_read_data_0_out) |
| 292 | ); |
| 293 | |
| 294 | //----- Stage: 2 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only) |
| 295 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out; |
| 296 | |
| 297 | dmu_imu_rds_intx_stage_mux_only dmu_imu_rds_intx_stage_mux_only |
| 298 | ( |
| 299 | .clk (clk), |
| 300 | .read_data_0 (default_grp_read_data_0_out), |
| 301 | .intx_status_reg_select (intx_status_reg_select), |
| 302 | .intx_status_reg_select_out (default_grp_intx_status_reg_select), |
| 303 | .int_a_int_clr_reg_select_pulse (int_a_int_clr_reg_select_pulse), |
| 304 | .int_a_int_clr_reg_select_pulse_out (default_grp_int_a_int_clr_reg_select_pulse), |
| 305 | .int_b_int_clr_reg_select_pulse (int_b_int_clr_reg_select_pulse), |
| 306 | .int_b_int_clr_reg_select_pulse_out (default_grp_int_b_int_clr_reg_select_pulse), |
| 307 | .int_c_int_clr_reg_select_pulse (int_c_int_clr_reg_select_pulse), |
| 308 | .int_c_int_clr_reg_select_pulse_out (default_grp_int_c_int_clr_reg_select_pulse), |
| 309 | .int_d_int_clr_reg_select_pulse (int_d_int_clr_reg_select_pulse), |
| 310 | .int_d_int_clr_reg_select_pulse_out (default_grp_int_d_int_clr_reg_select_pulse), |
| 311 | .daemon_csrbus_wr_in (daemon_csrbus_wr), |
| 312 | .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr), |
| 313 | .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data), |
| 314 | .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data), |
| 315 | .read_data_0_out (stage_mux_only_read_data_0_out), |
| 316 | .rst_l (rst_l), |
| 317 | .rst_l_out (stage_mux_only_rst_l) |
| 318 | ); |
| 319 | |
| 320 | //----- OUTPUT: csrbus_read_data |
| 321 | assign csrbus_read_data = stage_mux_only_read_data_0_out; |
| 322 | |
| 323 | endmodule // dmu_imu_rds_intx_csr |