| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_rds_intx_stage_mux_only.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_rds_intx_stage_mux_only |
| 36 | ( |
| 37 | clk, |
| 38 | read_data_0, |
| 39 | intx_status_reg_select, |
| 40 | intx_status_reg_select_out, |
| 41 | int_a_int_clr_reg_select_pulse, |
| 42 | int_a_int_clr_reg_select_pulse_out, |
| 43 | int_b_int_clr_reg_select_pulse, |
| 44 | int_b_int_clr_reg_select_pulse_out, |
| 45 | int_c_int_clr_reg_select_pulse, |
| 46 | int_c_int_clr_reg_select_pulse_out, |
| 47 | int_d_int_clr_reg_select_pulse, |
| 48 | int_d_int_clr_reg_select_pulse_out, |
| 49 | daemon_csrbus_wr_in, |
| 50 | daemon_csrbus_wr_out, |
| 51 | daemon_csrbus_wr_data_in, |
| 52 | daemon_csrbus_wr_data_out, |
| 53 | read_data_0_out, |
| 54 | rst_l, |
| 55 | rst_l_out |
| 56 | ); |
| 57 | |
| 58 | //==================================================== |
| 59 | // Polarity declarations |
| 60 | //==================================================== |
| 61 | input clk; // Clock signal |
| 62 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data |
| 63 | input intx_status_reg_select; // select |
| 64 | output intx_status_reg_select_out; // select |
| 65 | input int_a_int_clr_reg_select_pulse; // select |
| 66 | output int_a_int_clr_reg_select_pulse_out; // select |
| 67 | input int_b_int_clr_reg_select_pulse; // select |
| 68 | output int_b_int_clr_reg_select_pulse_out; // select |
| 69 | input int_c_int_clr_reg_select_pulse; // select |
| 70 | output int_c_int_clr_reg_select_pulse_out; // select |
| 71 | input int_d_int_clr_reg_select_pulse; // select |
| 72 | output int_d_int_clr_reg_select_pulse_out; // select |
| 73 | input daemon_csrbus_wr_in; // csrbus_wr |
| 74 | output daemon_csrbus_wr_out; // csrbus_wr |
| 75 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 76 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write |
| 77 | // data |
| 78 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 79 | input rst_l; // HW reset |
| 80 | output rst_l_out; // HW reset |
| 81 | |
| 82 | //==================================================== |
| 83 | // Type declarations |
| 84 | //==================================================== |
| 85 | wire clk; // Clock signal |
| 86 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data |
| 87 | wire intx_status_reg_select; // select |
| 88 | wire intx_status_reg_select_out; // select |
| 89 | wire int_a_int_clr_reg_select_pulse; // select |
| 90 | wire int_a_int_clr_reg_select_pulse_out; // select |
| 91 | wire int_b_int_clr_reg_select_pulse; // select |
| 92 | wire int_b_int_clr_reg_select_pulse_out; // select |
| 93 | wire int_c_int_clr_reg_select_pulse; // select |
| 94 | wire int_c_int_clr_reg_select_pulse_out; // select |
| 95 | wire int_d_int_clr_reg_select_pulse; // select |
| 96 | wire int_d_int_clr_reg_select_pulse_out; // select |
| 97 | wire daemon_csrbus_wr_in; // csrbus_wr |
| 98 | wire daemon_csrbus_wr_out; // csrbus_wr |
| 99 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 100 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data |
| 101 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 102 | wire rst_l; // HW reset |
| 103 | wire rst_l_out; // HW reset |
| 104 | |
| 105 | |
| 106 | //==================================================== |
| 107 | // Assignments only |
| 108 | //==================================================== |
| 109 | assign intx_status_reg_select_out = intx_status_reg_select; |
| 110 | assign int_a_int_clr_reg_select_pulse_out = int_a_int_clr_reg_select_pulse; |
| 111 | assign int_b_int_clr_reg_select_pulse_out = int_b_int_clr_reg_select_pulse; |
| 112 | assign int_c_int_clr_reg_select_pulse_out = int_c_int_clr_reg_select_pulse; |
| 113 | assign int_d_int_clr_reg_select_pulse_out = int_d_int_clr_reg_select_pulse; |
| 114 | assign rst_l_out = rst_l; |
| 115 | assign daemon_csrbus_wr_out = daemon_csrbus_wr_in; |
| 116 | assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in; |
| 117 | |
| 118 | |
| 119 | //===================================================== |
| 120 | // OUTPUT: read_data_out |
| 121 | //===================================================== |
| 122 | dmu_imu_rds_intx_csrpipe_1 dmu_imu_rds_intx_csrpipe_1_inst_1 |
| 123 | ( |
| 124 | .clk (clk), |
| 125 | .rst_l (rst_l), |
| 126 | .reg_in (1'b0), |
| 127 | .reg_out (1'b0), |
| 128 | .data0 (read_data_0), |
| 129 | .sel0 (1'b1), |
| 130 | .out (read_data_0_out) |
| 131 | ); |
| 132 | |
| 133 | endmodule // dmu_imu_rds_intx_stage_mux_only |