| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_rds_msi_csr_int_mondo_data_0_reg_entry.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_rds_msi_csr_int_mondo_data_0_reg_entry |
| 36 | ( |
| 37 | // synopsys translate_off |
| 38 | omni_ld, |
| 39 | omni_data, |
| 40 | // synopsys translate_on |
| 41 | clk, |
| 42 | rst_l, |
| 43 | w_ld, |
| 44 | csrbus_wr_data, |
| 45 | int_mondo_data_0_reg_csrbus_read_data |
| 46 | ); |
| 47 | |
| 48 | //==================================================================== |
| 49 | // Polarity declarations |
| 50 | //==================================================================== |
| 51 | // synopsys translate_off |
| 52 | input omni_ld; // Omni load |
| 53 | // vlint flag_input_port_not_connected off |
| 54 | input [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WIDTH - 1:0] omni_data; |
| 55 | // Omni write data |
| 56 | // synopsys translate_on |
| 57 | // vlint flag_input_port_not_connected on |
| 58 | input clk; // Clock signal |
| 59 | input rst_l; // Reset signal |
| 60 | input w_ld; // SW load |
| 61 | // vlint flag_input_port_not_connected off |
| 62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 63 | // vlint flag_input_port_not_connected on |
| 64 | output [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WIDTH-1:0] int_mondo_data_0_reg_csrbus_read_data; |
| 65 | // SW read data |
| 66 | |
| 67 | //==================================================================== |
| 68 | // Type declarations |
| 69 | //==================================================================== |
| 70 | // synopsys translate_off |
| 71 | wire omni_ld; // Omni load |
| 72 | // vlint flag_dangling_net_within_module off |
| 73 | // vlint flag_net_has_no_load off |
| 74 | wire [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WIDTH - 1:0] omni_data; |
| 75 | // Omni write data |
| 76 | // synopsys translate_on |
| 77 | // vlint flag_dangling_net_within_module on |
| 78 | // vlint flag_net_has_no_load on |
| 79 | wire clk; // Clock signal |
| 80 | wire rst_l; // Reset signal |
| 81 | wire w_ld; // SW load |
| 82 | // vlint flag_dangling_net_within_module off |
| 83 | // vlint flag_net_has_no_load off |
| 84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 85 | // vlint flag_dangling_net_within_module on |
| 86 | // vlint flag_net_has_no_load on |
| 87 | wire [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WIDTH-1:0] int_mondo_data_0_reg_csrbus_read_data; |
| 88 | // SW read data |
| 89 | |
| 90 | //==================================================================== |
| 91 | // Logic |
| 92 | //==================================================================== |
| 93 | |
| 94 | //----- Reset values |
| 95 | // verilint 531 off |
| 96 | wire [57:0] reset_data = 58'h0; |
| 97 | // verilint 531 on |
| 98 | |
| 99 | //----- Active high reset wires |
| 100 | wire rst_l_active_high = ~rst_l; |
| 101 | |
| 102 | //==================================================== |
| 103 | // Instantiation of flops |
| 104 | //==================================================== |
| 105 | |
| 106 | assign int_mondo_data_0_reg_csrbus_read_data[0] = 1'b0; // bit 0 |
| 107 | assign int_mondo_data_0_reg_csrbus_read_data[1] = 1'b0; // bit 1 |
| 108 | assign int_mondo_data_0_reg_csrbus_read_data[2] = 1'b0; // bit 2 |
| 109 | assign int_mondo_data_0_reg_csrbus_read_data[3] = 1'b0; // bit 3 |
| 110 | assign int_mondo_data_0_reg_csrbus_read_data[4] = 1'b0; // bit 4 |
| 111 | assign int_mondo_data_0_reg_csrbus_read_data[5] = 1'b0; // bit 5 |
| 112 | // bit 6 |
| 113 | csr_sw csr_sw_6 |
| 114 | ( |
| 115 | // synopsys translate_off |
| 116 | .omni_ld (omni_ld), |
| 117 | .omni_data (omni_data[6]), |
| 118 | .omni_rw_alias (1'b1), |
| 119 | .omni_rw1c_alias (1'b0), |
| 120 | .omni_rw1s_alias (1'b0), |
| 121 | // synopsys translate_on |
| 122 | .rst (rst_l_active_high), |
| 123 | .rst_val (reset_data[0]), |
| 124 | .csr_ld (w_ld), |
| 125 | .csr_data (csrbus_wr_data[6]), |
| 126 | .rw_alias (1'b1), |
| 127 | .rw1c_alias (1'b0), |
| 128 | .rw1s_alias (1'b0), |
| 129 | .hw_ld (1'b0), |
| 130 | .hw_data (1'b0), |
| 131 | .cp (clk), |
| 132 | .q (int_mondo_data_0_reg_csrbus_read_data[6]) |
| 133 | ); |
| 134 | |
| 135 | // bit 7 |
| 136 | csr_sw csr_sw_7 |
| 137 | ( |
| 138 | // synopsys translate_off |
| 139 | .omni_ld (omni_ld), |
| 140 | .omni_data (omni_data[7]), |
| 141 | .omni_rw_alias (1'b1), |
| 142 | .omni_rw1c_alias (1'b0), |
| 143 | .omni_rw1s_alias (1'b0), |
| 144 | // synopsys translate_on |
| 145 | .rst (rst_l_active_high), |
| 146 | .rst_val (reset_data[1]), |
| 147 | .csr_ld (w_ld), |
| 148 | .csr_data (csrbus_wr_data[7]), |
| 149 | .rw_alias (1'b1), |
| 150 | .rw1c_alias (1'b0), |
| 151 | .rw1s_alias (1'b0), |
| 152 | .hw_ld (1'b0), |
| 153 | .hw_data (1'b0), |
| 154 | .cp (clk), |
| 155 | .q (int_mondo_data_0_reg_csrbus_read_data[7]) |
| 156 | ); |
| 157 | |
| 158 | // bit 8 |
| 159 | csr_sw csr_sw_8 |
| 160 | ( |
| 161 | // synopsys translate_off |
| 162 | .omni_ld (omni_ld), |
| 163 | .omni_data (omni_data[8]), |
| 164 | .omni_rw_alias (1'b1), |
| 165 | .omni_rw1c_alias (1'b0), |
| 166 | .omni_rw1s_alias (1'b0), |
| 167 | // synopsys translate_on |
| 168 | .rst (rst_l_active_high), |
| 169 | .rst_val (reset_data[2]), |
| 170 | .csr_ld (w_ld), |
| 171 | .csr_data (csrbus_wr_data[8]), |
| 172 | .rw_alias (1'b1), |
| 173 | .rw1c_alias (1'b0), |
| 174 | .rw1s_alias (1'b0), |
| 175 | .hw_ld (1'b0), |
| 176 | .hw_data (1'b0), |
| 177 | .cp (clk), |
| 178 | .q (int_mondo_data_0_reg_csrbus_read_data[8]) |
| 179 | ); |
| 180 | |
| 181 | // bit 9 |
| 182 | csr_sw csr_sw_9 |
| 183 | ( |
| 184 | // synopsys translate_off |
| 185 | .omni_ld (omni_ld), |
| 186 | .omni_data (omni_data[9]), |
| 187 | .omni_rw_alias (1'b1), |
| 188 | .omni_rw1c_alias (1'b0), |
| 189 | .omni_rw1s_alias (1'b0), |
| 190 | // synopsys translate_on |
| 191 | .rst (rst_l_active_high), |
| 192 | .rst_val (reset_data[3]), |
| 193 | .csr_ld (w_ld), |
| 194 | .csr_data (csrbus_wr_data[9]), |
| 195 | .rw_alias (1'b1), |
| 196 | .rw1c_alias (1'b0), |
| 197 | .rw1s_alias (1'b0), |
| 198 | .hw_ld (1'b0), |
| 199 | .hw_data (1'b0), |
| 200 | .cp (clk), |
| 201 | .q (int_mondo_data_0_reg_csrbus_read_data[9]) |
| 202 | ); |
| 203 | |
| 204 | // bit 10 |
| 205 | csr_sw csr_sw_10 |
| 206 | ( |
| 207 | // synopsys translate_off |
| 208 | .omni_ld (omni_ld), |
| 209 | .omni_data (omni_data[10]), |
| 210 | .omni_rw_alias (1'b1), |
| 211 | .omni_rw1c_alias (1'b0), |
| 212 | .omni_rw1s_alias (1'b0), |
| 213 | // synopsys translate_on |
| 214 | .rst (rst_l_active_high), |
| 215 | .rst_val (reset_data[4]), |
| 216 | .csr_ld (w_ld), |
| 217 | .csr_data (csrbus_wr_data[10]), |
| 218 | .rw_alias (1'b1), |
| 219 | .rw1c_alias (1'b0), |
| 220 | .rw1s_alias (1'b0), |
| 221 | .hw_ld (1'b0), |
| 222 | .hw_data (1'b0), |
| 223 | .cp (clk), |
| 224 | .q (int_mondo_data_0_reg_csrbus_read_data[10]) |
| 225 | ); |
| 226 | |
| 227 | // bit 11 |
| 228 | csr_sw csr_sw_11 |
| 229 | ( |
| 230 | // synopsys translate_off |
| 231 | .omni_ld (omni_ld), |
| 232 | .omni_data (omni_data[11]), |
| 233 | .omni_rw_alias (1'b1), |
| 234 | .omni_rw1c_alias (1'b0), |
| 235 | .omni_rw1s_alias (1'b0), |
| 236 | // synopsys translate_on |
| 237 | .rst (rst_l_active_high), |
| 238 | .rst_val (reset_data[5]), |
| 239 | .csr_ld (w_ld), |
| 240 | .csr_data (csrbus_wr_data[11]), |
| 241 | .rw_alias (1'b1), |
| 242 | .rw1c_alias (1'b0), |
| 243 | .rw1s_alias (1'b0), |
| 244 | .hw_ld (1'b0), |
| 245 | .hw_data (1'b0), |
| 246 | .cp (clk), |
| 247 | .q (int_mondo_data_0_reg_csrbus_read_data[11]) |
| 248 | ); |
| 249 | |
| 250 | // bit 12 |
| 251 | csr_sw csr_sw_12 |
| 252 | ( |
| 253 | // synopsys translate_off |
| 254 | .omni_ld (omni_ld), |
| 255 | .omni_data (omni_data[12]), |
| 256 | .omni_rw_alias (1'b1), |
| 257 | .omni_rw1c_alias (1'b0), |
| 258 | .omni_rw1s_alias (1'b0), |
| 259 | // synopsys translate_on |
| 260 | .rst (rst_l_active_high), |
| 261 | .rst_val (reset_data[6]), |
| 262 | .csr_ld (w_ld), |
| 263 | .csr_data (csrbus_wr_data[12]), |
| 264 | .rw_alias (1'b1), |
| 265 | .rw1c_alias (1'b0), |
| 266 | .rw1s_alias (1'b0), |
| 267 | .hw_ld (1'b0), |
| 268 | .hw_data (1'b0), |
| 269 | .cp (clk), |
| 270 | .q (int_mondo_data_0_reg_csrbus_read_data[12]) |
| 271 | ); |
| 272 | |
| 273 | // bit 13 |
| 274 | csr_sw csr_sw_13 |
| 275 | ( |
| 276 | // synopsys translate_off |
| 277 | .omni_ld (omni_ld), |
| 278 | .omni_data (omni_data[13]), |
| 279 | .omni_rw_alias (1'b1), |
| 280 | .omni_rw1c_alias (1'b0), |
| 281 | .omni_rw1s_alias (1'b0), |
| 282 | // synopsys translate_on |
| 283 | .rst (rst_l_active_high), |
| 284 | .rst_val (reset_data[7]), |
| 285 | .csr_ld (w_ld), |
| 286 | .csr_data (csrbus_wr_data[13]), |
| 287 | .rw_alias (1'b1), |
| 288 | .rw1c_alias (1'b0), |
| 289 | .rw1s_alias (1'b0), |
| 290 | .hw_ld (1'b0), |
| 291 | .hw_data (1'b0), |
| 292 | .cp (clk), |
| 293 | .q (int_mondo_data_0_reg_csrbus_read_data[13]) |
| 294 | ); |
| 295 | |
| 296 | // bit 14 |
| 297 | csr_sw csr_sw_14 |
| 298 | ( |
| 299 | // synopsys translate_off |
| 300 | .omni_ld (omni_ld), |
| 301 | .omni_data (omni_data[14]), |
| 302 | .omni_rw_alias (1'b1), |
| 303 | .omni_rw1c_alias (1'b0), |
| 304 | .omni_rw1s_alias (1'b0), |
| 305 | // synopsys translate_on |
| 306 | .rst (rst_l_active_high), |
| 307 | .rst_val (reset_data[8]), |
| 308 | .csr_ld (w_ld), |
| 309 | .csr_data (csrbus_wr_data[14]), |
| 310 | .rw_alias (1'b1), |
| 311 | .rw1c_alias (1'b0), |
| 312 | .rw1s_alias (1'b0), |
| 313 | .hw_ld (1'b0), |
| 314 | .hw_data (1'b0), |
| 315 | .cp (clk), |
| 316 | .q (int_mondo_data_0_reg_csrbus_read_data[14]) |
| 317 | ); |
| 318 | |
| 319 | // bit 15 |
| 320 | csr_sw csr_sw_15 |
| 321 | ( |
| 322 | // synopsys translate_off |
| 323 | .omni_ld (omni_ld), |
| 324 | .omni_data (omni_data[15]), |
| 325 | .omni_rw_alias (1'b1), |
| 326 | .omni_rw1c_alias (1'b0), |
| 327 | .omni_rw1s_alias (1'b0), |
| 328 | // synopsys translate_on |
| 329 | .rst (rst_l_active_high), |
| 330 | .rst_val (reset_data[9]), |
| 331 | .csr_ld (w_ld), |
| 332 | .csr_data (csrbus_wr_data[15]), |
| 333 | .rw_alias (1'b1), |
| 334 | .rw1c_alias (1'b0), |
| 335 | .rw1s_alias (1'b0), |
| 336 | .hw_ld (1'b0), |
| 337 | .hw_data (1'b0), |
| 338 | .cp (clk), |
| 339 | .q (int_mondo_data_0_reg_csrbus_read_data[15]) |
| 340 | ); |
| 341 | |
| 342 | // bit 16 |
| 343 | csr_sw csr_sw_16 |
| 344 | ( |
| 345 | // synopsys translate_off |
| 346 | .omni_ld (omni_ld), |
| 347 | .omni_data (omni_data[16]), |
| 348 | .omni_rw_alias (1'b1), |
| 349 | .omni_rw1c_alias (1'b0), |
| 350 | .omni_rw1s_alias (1'b0), |
| 351 | // synopsys translate_on |
| 352 | .rst (rst_l_active_high), |
| 353 | .rst_val (reset_data[10]), |
| 354 | .csr_ld (w_ld), |
| 355 | .csr_data (csrbus_wr_data[16]), |
| 356 | .rw_alias (1'b1), |
| 357 | .rw1c_alias (1'b0), |
| 358 | .rw1s_alias (1'b0), |
| 359 | .hw_ld (1'b0), |
| 360 | .hw_data (1'b0), |
| 361 | .cp (clk), |
| 362 | .q (int_mondo_data_0_reg_csrbus_read_data[16]) |
| 363 | ); |
| 364 | |
| 365 | // bit 17 |
| 366 | csr_sw csr_sw_17 |
| 367 | ( |
| 368 | // synopsys translate_off |
| 369 | .omni_ld (omni_ld), |
| 370 | .omni_data (omni_data[17]), |
| 371 | .omni_rw_alias (1'b1), |
| 372 | .omni_rw1c_alias (1'b0), |
| 373 | .omni_rw1s_alias (1'b0), |
| 374 | // synopsys translate_on |
| 375 | .rst (rst_l_active_high), |
| 376 | .rst_val (reset_data[11]), |
| 377 | .csr_ld (w_ld), |
| 378 | .csr_data (csrbus_wr_data[17]), |
| 379 | .rw_alias (1'b1), |
| 380 | .rw1c_alias (1'b0), |
| 381 | .rw1s_alias (1'b0), |
| 382 | .hw_ld (1'b0), |
| 383 | .hw_data (1'b0), |
| 384 | .cp (clk), |
| 385 | .q (int_mondo_data_0_reg_csrbus_read_data[17]) |
| 386 | ); |
| 387 | |
| 388 | // bit 18 |
| 389 | csr_sw csr_sw_18 |
| 390 | ( |
| 391 | // synopsys translate_off |
| 392 | .omni_ld (omni_ld), |
| 393 | .omni_data (omni_data[18]), |
| 394 | .omni_rw_alias (1'b1), |
| 395 | .omni_rw1c_alias (1'b0), |
| 396 | .omni_rw1s_alias (1'b0), |
| 397 | // synopsys translate_on |
| 398 | .rst (rst_l_active_high), |
| 399 | .rst_val (reset_data[12]), |
| 400 | .csr_ld (w_ld), |
| 401 | .csr_data (csrbus_wr_data[18]), |
| 402 | .rw_alias (1'b1), |
| 403 | .rw1c_alias (1'b0), |
| 404 | .rw1s_alias (1'b0), |
| 405 | .hw_ld (1'b0), |
| 406 | .hw_data (1'b0), |
| 407 | .cp (clk), |
| 408 | .q (int_mondo_data_0_reg_csrbus_read_data[18]) |
| 409 | ); |
| 410 | |
| 411 | // bit 19 |
| 412 | csr_sw csr_sw_19 |
| 413 | ( |
| 414 | // synopsys translate_off |
| 415 | .omni_ld (omni_ld), |
| 416 | .omni_data (omni_data[19]), |
| 417 | .omni_rw_alias (1'b1), |
| 418 | .omni_rw1c_alias (1'b0), |
| 419 | .omni_rw1s_alias (1'b0), |
| 420 | // synopsys translate_on |
| 421 | .rst (rst_l_active_high), |
| 422 | .rst_val (reset_data[13]), |
| 423 | .csr_ld (w_ld), |
| 424 | .csr_data (csrbus_wr_data[19]), |
| 425 | .rw_alias (1'b1), |
| 426 | .rw1c_alias (1'b0), |
| 427 | .rw1s_alias (1'b0), |
| 428 | .hw_ld (1'b0), |
| 429 | .hw_data (1'b0), |
| 430 | .cp (clk), |
| 431 | .q (int_mondo_data_0_reg_csrbus_read_data[19]) |
| 432 | ); |
| 433 | |
| 434 | // bit 20 |
| 435 | csr_sw csr_sw_20 |
| 436 | ( |
| 437 | // synopsys translate_off |
| 438 | .omni_ld (omni_ld), |
| 439 | .omni_data (omni_data[20]), |
| 440 | .omni_rw_alias (1'b1), |
| 441 | .omni_rw1c_alias (1'b0), |
| 442 | .omni_rw1s_alias (1'b0), |
| 443 | // synopsys translate_on |
| 444 | .rst (rst_l_active_high), |
| 445 | .rst_val (reset_data[14]), |
| 446 | .csr_ld (w_ld), |
| 447 | .csr_data (csrbus_wr_data[20]), |
| 448 | .rw_alias (1'b1), |
| 449 | .rw1c_alias (1'b0), |
| 450 | .rw1s_alias (1'b0), |
| 451 | .hw_ld (1'b0), |
| 452 | .hw_data (1'b0), |
| 453 | .cp (clk), |
| 454 | .q (int_mondo_data_0_reg_csrbus_read_data[20]) |
| 455 | ); |
| 456 | |
| 457 | // bit 21 |
| 458 | csr_sw csr_sw_21 |
| 459 | ( |
| 460 | // synopsys translate_off |
| 461 | .omni_ld (omni_ld), |
| 462 | .omni_data (omni_data[21]), |
| 463 | .omni_rw_alias (1'b1), |
| 464 | .omni_rw1c_alias (1'b0), |
| 465 | .omni_rw1s_alias (1'b0), |
| 466 | // synopsys translate_on |
| 467 | .rst (rst_l_active_high), |
| 468 | .rst_val (reset_data[15]), |
| 469 | .csr_ld (w_ld), |
| 470 | .csr_data (csrbus_wr_data[21]), |
| 471 | .rw_alias (1'b1), |
| 472 | .rw1c_alias (1'b0), |
| 473 | .rw1s_alias (1'b0), |
| 474 | .hw_ld (1'b0), |
| 475 | .hw_data (1'b0), |
| 476 | .cp (clk), |
| 477 | .q (int_mondo_data_0_reg_csrbus_read_data[21]) |
| 478 | ); |
| 479 | |
| 480 | // bit 22 |
| 481 | csr_sw csr_sw_22 |
| 482 | ( |
| 483 | // synopsys translate_off |
| 484 | .omni_ld (omni_ld), |
| 485 | .omni_data (omni_data[22]), |
| 486 | .omni_rw_alias (1'b1), |
| 487 | .omni_rw1c_alias (1'b0), |
| 488 | .omni_rw1s_alias (1'b0), |
| 489 | // synopsys translate_on |
| 490 | .rst (rst_l_active_high), |
| 491 | .rst_val (reset_data[16]), |
| 492 | .csr_ld (w_ld), |
| 493 | .csr_data (csrbus_wr_data[22]), |
| 494 | .rw_alias (1'b1), |
| 495 | .rw1c_alias (1'b0), |
| 496 | .rw1s_alias (1'b0), |
| 497 | .hw_ld (1'b0), |
| 498 | .hw_data (1'b0), |
| 499 | .cp (clk), |
| 500 | .q (int_mondo_data_0_reg_csrbus_read_data[22]) |
| 501 | ); |
| 502 | |
| 503 | // bit 23 |
| 504 | csr_sw csr_sw_23 |
| 505 | ( |
| 506 | // synopsys translate_off |
| 507 | .omni_ld (omni_ld), |
| 508 | .omni_data (omni_data[23]), |
| 509 | .omni_rw_alias (1'b1), |
| 510 | .omni_rw1c_alias (1'b0), |
| 511 | .omni_rw1s_alias (1'b0), |
| 512 | // synopsys translate_on |
| 513 | .rst (rst_l_active_high), |
| 514 | .rst_val (reset_data[17]), |
| 515 | .csr_ld (w_ld), |
| 516 | .csr_data (csrbus_wr_data[23]), |
| 517 | .rw_alias (1'b1), |
| 518 | .rw1c_alias (1'b0), |
| 519 | .rw1s_alias (1'b0), |
| 520 | .hw_ld (1'b0), |
| 521 | .hw_data (1'b0), |
| 522 | .cp (clk), |
| 523 | .q (int_mondo_data_0_reg_csrbus_read_data[23]) |
| 524 | ); |
| 525 | |
| 526 | // bit 24 |
| 527 | csr_sw csr_sw_24 |
| 528 | ( |
| 529 | // synopsys translate_off |
| 530 | .omni_ld (omni_ld), |
| 531 | .omni_data (omni_data[24]), |
| 532 | .omni_rw_alias (1'b1), |
| 533 | .omni_rw1c_alias (1'b0), |
| 534 | .omni_rw1s_alias (1'b0), |
| 535 | // synopsys translate_on |
| 536 | .rst (rst_l_active_high), |
| 537 | .rst_val (reset_data[18]), |
| 538 | .csr_ld (w_ld), |
| 539 | .csr_data (csrbus_wr_data[24]), |
| 540 | .rw_alias (1'b1), |
| 541 | .rw1c_alias (1'b0), |
| 542 | .rw1s_alias (1'b0), |
| 543 | .hw_ld (1'b0), |
| 544 | .hw_data (1'b0), |
| 545 | .cp (clk), |
| 546 | .q (int_mondo_data_0_reg_csrbus_read_data[24]) |
| 547 | ); |
| 548 | |
| 549 | // bit 25 |
| 550 | csr_sw csr_sw_25 |
| 551 | ( |
| 552 | // synopsys translate_off |
| 553 | .omni_ld (omni_ld), |
| 554 | .omni_data (omni_data[25]), |
| 555 | .omni_rw_alias (1'b1), |
| 556 | .omni_rw1c_alias (1'b0), |
| 557 | .omni_rw1s_alias (1'b0), |
| 558 | // synopsys translate_on |
| 559 | .rst (rst_l_active_high), |
| 560 | .rst_val (reset_data[19]), |
| 561 | .csr_ld (w_ld), |
| 562 | .csr_data (csrbus_wr_data[25]), |
| 563 | .rw_alias (1'b1), |
| 564 | .rw1c_alias (1'b0), |
| 565 | .rw1s_alias (1'b0), |
| 566 | .hw_ld (1'b0), |
| 567 | .hw_data (1'b0), |
| 568 | .cp (clk), |
| 569 | .q (int_mondo_data_0_reg_csrbus_read_data[25]) |
| 570 | ); |
| 571 | |
| 572 | // bit 26 |
| 573 | csr_sw csr_sw_26 |
| 574 | ( |
| 575 | // synopsys translate_off |
| 576 | .omni_ld (omni_ld), |
| 577 | .omni_data (omni_data[26]), |
| 578 | .omni_rw_alias (1'b1), |
| 579 | .omni_rw1c_alias (1'b0), |
| 580 | .omni_rw1s_alias (1'b0), |
| 581 | // synopsys translate_on |
| 582 | .rst (rst_l_active_high), |
| 583 | .rst_val (reset_data[20]), |
| 584 | .csr_ld (w_ld), |
| 585 | .csr_data (csrbus_wr_data[26]), |
| 586 | .rw_alias (1'b1), |
| 587 | .rw1c_alias (1'b0), |
| 588 | .rw1s_alias (1'b0), |
| 589 | .hw_ld (1'b0), |
| 590 | .hw_data (1'b0), |
| 591 | .cp (clk), |
| 592 | .q (int_mondo_data_0_reg_csrbus_read_data[26]) |
| 593 | ); |
| 594 | |
| 595 | // bit 27 |
| 596 | csr_sw csr_sw_27 |
| 597 | ( |
| 598 | // synopsys translate_off |
| 599 | .omni_ld (omni_ld), |
| 600 | .omni_data (omni_data[27]), |
| 601 | .omni_rw_alias (1'b1), |
| 602 | .omni_rw1c_alias (1'b0), |
| 603 | .omni_rw1s_alias (1'b0), |
| 604 | // synopsys translate_on |
| 605 | .rst (rst_l_active_high), |
| 606 | .rst_val (reset_data[21]), |
| 607 | .csr_ld (w_ld), |
| 608 | .csr_data (csrbus_wr_data[27]), |
| 609 | .rw_alias (1'b1), |
| 610 | .rw1c_alias (1'b0), |
| 611 | .rw1s_alias (1'b0), |
| 612 | .hw_ld (1'b0), |
| 613 | .hw_data (1'b0), |
| 614 | .cp (clk), |
| 615 | .q (int_mondo_data_0_reg_csrbus_read_data[27]) |
| 616 | ); |
| 617 | |
| 618 | // bit 28 |
| 619 | csr_sw csr_sw_28 |
| 620 | ( |
| 621 | // synopsys translate_off |
| 622 | .omni_ld (omni_ld), |
| 623 | .omni_data (omni_data[28]), |
| 624 | .omni_rw_alias (1'b1), |
| 625 | .omni_rw1c_alias (1'b0), |
| 626 | .omni_rw1s_alias (1'b0), |
| 627 | // synopsys translate_on |
| 628 | .rst (rst_l_active_high), |
| 629 | .rst_val (reset_data[22]), |
| 630 | .csr_ld (w_ld), |
| 631 | .csr_data (csrbus_wr_data[28]), |
| 632 | .rw_alias (1'b1), |
| 633 | .rw1c_alias (1'b0), |
| 634 | .rw1s_alias (1'b0), |
| 635 | .hw_ld (1'b0), |
| 636 | .hw_data (1'b0), |
| 637 | .cp (clk), |
| 638 | .q (int_mondo_data_0_reg_csrbus_read_data[28]) |
| 639 | ); |
| 640 | |
| 641 | // bit 29 |
| 642 | csr_sw csr_sw_29 |
| 643 | ( |
| 644 | // synopsys translate_off |
| 645 | .omni_ld (omni_ld), |
| 646 | .omni_data (omni_data[29]), |
| 647 | .omni_rw_alias (1'b1), |
| 648 | .omni_rw1c_alias (1'b0), |
| 649 | .omni_rw1s_alias (1'b0), |
| 650 | // synopsys translate_on |
| 651 | .rst (rst_l_active_high), |
| 652 | .rst_val (reset_data[23]), |
| 653 | .csr_ld (w_ld), |
| 654 | .csr_data (csrbus_wr_data[29]), |
| 655 | .rw_alias (1'b1), |
| 656 | .rw1c_alias (1'b0), |
| 657 | .rw1s_alias (1'b0), |
| 658 | .hw_ld (1'b0), |
| 659 | .hw_data (1'b0), |
| 660 | .cp (clk), |
| 661 | .q (int_mondo_data_0_reg_csrbus_read_data[29]) |
| 662 | ); |
| 663 | |
| 664 | // bit 30 |
| 665 | csr_sw csr_sw_30 |
| 666 | ( |
| 667 | // synopsys translate_off |
| 668 | .omni_ld (omni_ld), |
| 669 | .omni_data (omni_data[30]), |
| 670 | .omni_rw_alias (1'b1), |
| 671 | .omni_rw1c_alias (1'b0), |
| 672 | .omni_rw1s_alias (1'b0), |
| 673 | // synopsys translate_on |
| 674 | .rst (rst_l_active_high), |
| 675 | .rst_val (reset_data[24]), |
| 676 | .csr_ld (w_ld), |
| 677 | .csr_data (csrbus_wr_data[30]), |
| 678 | .rw_alias (1'b1), |
| 679 | .rw1c_alias (1'b0), |
| 680 | .rw1s_alias (1'b0), |
| 681 | .hw_ld (1'b0), |
| 682 | .hw_data (1'b0), |
| 683 | .cp (clk), |
| 684 | .q (int_mondo_data_0_reg_csrbus_read_data[30]) |
| 685 | ); |
| 686 | |
| 687 | // bit 31 |
| 688 | csr_sw csr_sw_31 |
| 689 | ( |
| 690 | // synopsys translate_off |
| 691 | .omni_ld (omni_ld), |
| 692 | .omni_data (omni_data[31]), |
| 693 | .omni_rw_alias (1'b1), |
| 694 | .omni_rw1c_alias (1'b0), |
| 695 | .omni_rw1s_alias (1'b0), |
| 696 | // synopsys translate_on |
| 697 | .rst (rst_l_active_high), |
| 698 | .rst_val (reset_data[25]), |
| 699 | .csr_ld (w_ld), |
| 700 | .csr_data (csrbus_wr_data[31]), |
| 701 | .rw_alias (1'b1), |
| 702 | .rw1c_alias (1'b0), |
| 703 | .rw1s_alias (1'b0), |
| 704 | .hw_ld (1'b0), |
| 705 | .hw_data (1'b0), |
| 706 | .cp (clk), |
| 707 | .q (int_mondo_data_0_reg_csrbus_read_data[31]) |
| 708 | ); |
| 709 | |
| 710 | // bit 32 |
| 711 | csr_sw csr_sw_32 |
| 712 | ( |
| 713 | // synopsys translate_off |
| 714 | .omni_ld (omni_ld), |
| 715 | .omni_data (omni_data[32]), |
| 716 | .omni_rw_alias (1'b1), |
| 717 | .omni_rw1c_alias (1'b0), |
| 718 | .omni_rw1s_alias (1'b0), |
| 719 | // synopsys translate_on |
| 720 | .rst (rst_l_active_high), |
| 721 | .rst_val (reset_data[26]), |
| 722 | .csr_ld (w_ld), |
| 723 | .csr_data (csrbus_wr_data[32]), |
| 724 | .rw_alias (1'b1), |
| 725 | .rw1c_alias (1'b0), |
| 726 | .rw1s_alias (1'b0), |
| 727 | .hw_ld (1'b0), |
| 728 | .hw_data (1'b0), |
| 729 | .cp (clk), |
| 730 | .q (int_mondo_data_0_reg_csrbus_read_data[32]) |
| 731 | ); |
| 732 | |
| 733 | // bit 33 |
| 734 | csr_sw csr_sw_33 |
| 735 | ( |
| 736 | // synopsys translate_off |
| 737 | .omni_ld (omni_ld), |
| 738 | .omni_data (omni_data[33]), |
| 739 | .omni_rw_alias (1'b1), |
| 740 | .omni_rw1c_alias (1'b0), |
| 741 | .omni_rw1s_alias (1'b0), |
| 742 | // synopsys translate_on |
| 743 | .rst (rst_l_active_high), |
| 744 | .rst_val (reset_data[27]), |
| 745 | .csr_ld (w_ld), |
| 746 | .csr_data (csrbus_wr_data[33]), |
| 747 | .rw_alias (1'b1), |
| 748 | .rw1c_alias (1'b0), |
| 749 | .rw1s_alias (1'b0), |
| 750 | .hw_ld (1'b0), |
| 751 | .hw_data (1'b0), |
| 752 | .cp (clk), |
| 753 | .q (int_mondo_data_0_reg_csrbus_read_data[33]) |
| 754 | ); |
| 755 | |
| 756 | // bit 34 |
| 757 | csr_sw csr_sw_34 |
| 758 | ( |
| 759 | // synopsys translate_off |
| 760 | .omni_ld (omni_ld), |
| 761 | .omni_data (omni_data[34]), |
| 762 | .omni_rw_alias (1'b1), |
| 763 | .omni_rw1c_alias (1'b0), |
| 764 | .omni_rw1s_alias (1'b0), |
| 765 | // synopsys translate_on |
| 766 | .rst (rst_l_active_high), |
| 767 | .rst_val (reset_data[28]), |
| 768 | .csr_ld (w_ld), |
| 769 | .csr_data (csrbus_wr_data[34]), |
| 770 | .rw_alias (1'b1), |
| 771 | .rw1c_alias (1'b0), |
| 772 | .rw1s_alias (1'b0), |
| 773 | .hw_ld (1'b0), |
| 774 | .hw_data (1'b0), |
| 775 | .cp (clk), |
| 776 | .q (int_mondo_data_0_reg_csrbus_read_data[34]) |
| 777 | ); |
| 778 | |
| 779 | // bit 35 |
| 780 | csr_sw csr_sw_35 |
| 781 | ( |
| 782 | // synopsys translate_off |
| 783 | .omni_ld (omni_ld), |
| 784 | .omni_data (omni_data[35]), |
| 785 | .omni_rw_alias (1'b1), |
| 786 | .omni_rw1c_alias (1'b0), |
| 787 | .omni_rw1s_alias (1'b0), |
| 788 | // synopsys translate_on |
| 789 | .rst (rst_l_active_high), |
| 790 | .rst_val (reset_data[29]), |
| 791 | .csr_ld (w_ld), |
| 792 | .csr_data (csrbus_wr_data[35]), |
| 793 | .rw_alias (1'b1), |
| 794 | .rw1c_alias (1'b0), |
| 795 | .rw1s_alias (1'b0), |
| 796 | .hw_ld (1'b0), |
| 797 | .hw_data (1'b0), |
| 798 | .cp (clk), |
| 799 | .q (int_mondo_data_0_reg_csrbus_read_data[35]) |
| 800 | ); |
| 801 | |
| 802 | // bit 36 |
| 803 | csr_sw csr_sw_36 |
| 804 | ( |
| 805 | // synopsys translate_off |
| 806 | .omni_ld (omni_ld), |
| 807 | .omni_data (omni_data[36]), |
| 808 | .omni_rw_alias (1'b1), |
| 809 | .omni_rw1c_alias (1'b0), |
| 810 | .omni_rw1s_alias (1'b0), |
| 811 | // synopsys translate_on |
| 812 | .rst (rst_l_active_high), |
| 813 | .rst_val (reset_data[30]), |
| 814 | .csr_ld (w_ld), |
| 815 | .csr_data (csrbus_wr_data[36]), |
| 816 | .rw_alias (1'b1), |
| 817 | .rw1c_alias (1'b0), |
| 818 | .rw1s_alias (1'b0), |
| 819 | .hw_ld (1'b0), |
| 820 | .hw_data (1'b0), |
| 821 | .cp (clk), |
| 822 | .q (int_mondo_data_0_reg_csrbus_read_data[36]) |
| 823 | ); |
| 824 | |
| 825 | // bit 37 |
| 826 | csr_sw csr_sw_37 |
| 827 | ( |
| 828 | // synopsys translate_off |
| 829 | .omni_ld (omni_ld), |
| 830 | .omni_data (omni_data[37]), |
| 831 | .omni_rw_alias (1'b1), |
| 832 | .omni_rw1c_alias (1'b0), |
| 833 | .omni_rw1s_alias (1'b0), |
| 834 | // synopsys translate_on |
| 835 | .rst (rst_l_active_high), |
| 836 | .rst_val (reset_data[31]), |
| 837 | .csr_ld (w_ld), |
| 838 | .csr_data (csrbus_wr_data[37]), |
| 839 | .rw_alias (1'b1), |
| 840 | .rw1c_alias (1'b0), |
| 841 | .rw1s_alias (1'b0), |
| 842 | .hw_ld (1'b0), |
| 843 | .hw_data (1'b0), |
| 844 | .cp (clk), |
| 845 | .q (int_mondo_data_0_reg_csrbus_read_data[37]) |
| 846 | ); |
| 847 | |
| 848 | // bit 38 |
| 849 | csr_sw csr_sw_38 |
| 850 | ( |
| 851 | // synopsys translate_off |
| 852 | .omni_ld (omni_ld), |
| 853 | .omni_data (omni_data[38]), |
| 854 | .omni_rw_alias (1'b1), |
| 855 | .omni_rw1c_alias (1'b0), |
| 856 | .omni_rw1s_alias (1'b0), |
| 857 | // synopsys translate_on |
| 858 | .rst (rst_l_active_high), |
| 859 | .rst_val (reset_data[32]), |
| 860 | .csr_ld (w_ld), |
| 861 | .csr_data (csrbus_wr_data[38]), |
| 862 | .rw_alias (1'b1), |
| 863 | .rw1c_alias (1'b0), |
| 864 | .rw1s_alias (1'b0), |
| 865 | .hw_ld (1'b0), |
| 866 | .hw_data (1'b0), |
| 867 | .cp (clk), |
| 868 | .q (int_mondo_data_0_reg_csrbus_read_data[38]) |
| 869 | ); |
| 870 | |
| 871 | // bit 39 |
| 872 | csr_sw csr_sw_39 |
| 873 | ( |
| 874 | // synopsys translate_off |
| 875 | .omni_ld (omni_ld), |
| 876 | .omni_data (omni_data[39]), |
| 877 | .omni_rw_alias (1'b1), |
| 878 | .omni_rw1c_alias (1'b0), |
| 879 | .omni_rw1s_alias (1'b0), |
| 880 | // synopsys translate_on |
| 881 | .rst (rst_l_active_high), |
| 882 | .rst_val (reset_data[33]), |
| 883 | .csr_ld (w_ld), |
| 884 | .csr_data (csrbus_wr_data[39]), |
| 885 | .rw_alias (1'b1), |
| 886 | .rw1c_alias (1'b0), |
| 887 | .rw1s_alias (1'b0), |
| 888 | .hw_ld (1'b0), |
| 889 | .hw_data (1'b0), |
| 890 | .cp (clk), |
| 891 | .q (int_mondo_data_0_reg_csrbus_read_data[39]) |
| 892 | ); |
| 893 | |
| 894 | // bit 40 |
| 895 | csr_sw csr_sw_40 |
| 896 | ( |
| 897 | // synopsys translate_off |
| 898 | .omni_ld (omni_ld), |
| 899 | .omni_data (omni_data[40]), |
| 900 | .omni_rw_alias (1'b1), |
| 901 | .omni_rw1c_alias (1'b0), |
| 902 | .omni_rw1s_alias (1'b0), |
| 903 | // synopsys translate_on |
| 904 | .rst (rst_l_active_high), |
| 905 | .rst_val (reset_data[34]), |
| 906 | .csr_ld (w_ld), |
| 907 | .csr_data (csrbus_wr_data[40]), |
| 908 | .rw_alias (1'b1), |
| 909 | .rw1c_alias (1'b0), |
| 910 | .rw1s_alias (1'b0), |
| 911 | .hw_ld (1'b0), |
| 912 | .hw_data (1'b0), |
| 913 | .cp (clk), |
| 914 | .q (int_mondo_data_0_reg_csrbus_read_data[40]) |
| 915 | ); |
| 916 | |
| 917 | // bit 41 |
| 918 | csr_sw csr_sw_41 |
| 919 | ( |
| 920 | // synopsys translate_off |
| 921 | .omni_ld (omni_ld), |
| 922 | .omni_data (omni_data[41]), |
| 923 | .omni_rw_alias (1'b1), |
| 924 | .omni_rw1c_alias (1'b0), |
| 925 | .omni_rw1s_alias (1'b0), |
| 926 | // synopsys translate_on |
| 927 | .rst (rst_l_active_high), |
| 928 | .rst_val (reset_data[35]), |
| 929 | .csr_ld (w_ld), |
| 930 | .csr_data (csrbus_wr_data[41]), |
| 931 | .rw_alias (1'b1), |
| 932 | .rw1c_alias (1'b0), |
| 933 | .rw1s_alias (1'b0), |
| 934 | .hw_ld (1'b0), |
| 935 | .hw_data (1'b0), |
| 936 | .cp (clk), |
| 937 | .q (int_mondo_data_0_reg_csrbus_read_data[41]) |
| 938 | ); |
| 939 | |
| 940 | // bit 42 |
| 941 | csr_sw csr_sw_42 |
| 942 | ( |
| 943 | // synopsys translate_off |
| 944 | .omni_ld (omni_ld), |
| 945 | .omni_data (omni_data[42]), |
| 946 | .omni_rw_alias (1'b1), |
| 947 | .omni_rw1c_alias (1'b0), |
| 948 | .omni_rw1s_alias (1'b0), |
| 949 | // synopsys translate_on |
| 950 | .rst (rst_l_active_high), |
| 951 | .rst_val (reset_data[36]), |
| 952 | .csr_ld (w_ld), |
| 953 | .csr_data (csrbus_wr_data[42]), |
| 954 | .rw_alias (1'b1), |
| 955 | .rw1c_alias (1'b0), |
| 956 | .rw1s_alias (1'b0), |
| 957 | .hw_ld (1'b0), |
| 958 | .hw_data (1'b0), |
| 959 | .cp (clk), |
| 960 | .q (int_mondo_data_0_reg_csrbus_read_data[42]) |
| 961 | ); |
| 962 | |
| 963 | // bit 43 |
| 964 | csr_sw csr_sw_43 |
| 965 | ( |
| 966 | // synopsys translate_off |
| 967 | .omni_ld (omni_ld), |
| 968 | .omni_data (omni_data[43]), |
| 969 | .omni_rw_alias (1'b1), |
| 970 | .omni_rw1c_alias (1'b0), |
| 971 | .omni_rw1s_alias (1'b0), |
| 972 | // synopsys translate_on |
| 973 | .rst (rst_l_active_high), |
| 974 | .rst_val (reset_data[37]), |
| 975 | .csr_ld (w_ld), |
| 976 | .csr_data (csrbus_wr_data[43]), |
| 977 | .rw_alias (1'b1), |
| 978 | .rw1c_alias (1'b0), |
| 979 | .rw1s_alias (1'b0), |
| 980 | .hw_ld (1'b0), |
| 981 | .hw_data (1'b0), |
| 982 | .cp (clk), |
| 983 | .q (int_mondo_data_0_reg_csrbus_read_data[43]) |
| 984 | ); |
| 985 | |
| 986 | // bit 44 |
| 987 | csr_sw csr_sw_44 |
| 988 | ( |
| 989 | // synopsys translate_off |
| 990 | .omni_ld (omni_ld), |
| 991 | .omni_data (omni_data[44]), |
| 992 | .omni_rw_alias (1'b1), |
| 993 | .omni_rw1c_alias (1'b0), |
| 994 | .omni_rw1s_alias (1'b0), |
| 995 | // synopsys translate_on |
| 996 | .rst (rst_l_active_high), |
| 997 | .rst_val (reset_data[38]), |
| 998 | .csr_ld (w_ld), |
| 999 | .csr_data (csrbus_wr_data[44]), |
| 1000 | .rw_alias (1'b1), |
| 1001 | .rw1c_alias (1'b0), |
| 1002 | .rw1s_alias (1'b0), |
| 1003 | .hw_ld (1'b0), |
| 1004 | .hw_data (1'b0), |
| 1005 | .cp (clk), |
| 1006 | .q (int_mondo_data_0_reg_csrbus_read_data[44]) |
| 1007 | ); |
| 1008 | |
| 1009 | // bit 45 |
| 1010 | csr_sw csr_sw_45 |
| 1011 | ( |
| 1012 | // synopsys translate_off |
| 1013 | .omni_ld (omni_ld), |
| 1014 | .omni_data (omni_data[45]), |
| 1015 | .omni_rw_alias (1'b1), |
| 1016 | .omni_rw1c_alias (1'b0), |
| 1017 | .omni_rw1s_alias (1'b0), |
| 1018 | // synopsys translate_on |
| 1019 | .rst (rst_l_active_high), |
| 1020 | .rst_val (reset_data[39]), |
| 1021 | .csr_ld (w_ld), |
| 1022 | .csr_data (csrbus_wr_data[45]), |
| 1023 | .rw_alias (1'b1), |
| 1024 | .rw1c_alias (1'b0), |
| 1025 | .rw1s_alias (1'b0), |
| 1026 | .hw_ld (1'b0), |
| 1027 | .hw_data (1'b0), |
| 1028 | .cp (clk), |
| 1029 | .q (int_mondo_data_0_reg_csrbus_read_data[45]) |
| 1030 | ); |
| 1031 | |
| 1032 | // bit 46 |
| 1033 | csr_sw csr_sw_46 |
| 1034 | ( |
| 1035 | // synopsys translate_off |
| 1036 | .omni_ld (omni_ld), |
| 1037 | .omni_data (omni_data[46]), |
| 1038 | .omni_rw_alias (1'b1), |
| 1039 | .omni_rw1c_alias (1'b0), |
| 1040 | .omni_rw1s_alias (1'b0), |
| 1041 | // synopsys translate_on |
| 1042 | .rst (rst_l_active_high), |
| 1043 | .rst_val (reset_data[40]), |
| 1044 | .csr_ld (w_ld), |
| 1045 | .csr_data (csrbus_wr_data[46]), |
| 1046 | .rw_alias (1'b1), |
| 1047 | .rw1c_alias (1'b0), |
| 1048 | .rw1s_alias (1'b0), |
| 1049 | .hw_ld (1'b0), |
| 1050 | .hw_data (1'b0), |
| 1051 | .cp (clk), |
| 1052 | .q (int_mondo_data_0_reg_csrbus_read_data[46]) |
| 1053 | ); |
| 1054 | |
| 1055 | // bit 47 |
| 1056 | csr_sw csr_sw_47 |
| 1057 | ( |
| 1058 | // synopsys translate_off |
| 1059 | .omni_ld (omni_ld), |
| 1060 | .omni_data (omni_data[47]), |
| 1061 | .omni_rw_alias (1'b1), |
| 1062 | .omni_rw1c_alias (1'b0), |
| 1063 | .omni_rw1s_alias (1'b0), |
| 1064 | // synopsys translate_on |
| 1065 | .rst (rst_l_active_high), |
| 1066 | .rst_val (reset_data[41]), |
| 1067 | .csr_ld (w_ld), |
| 1068 | .csr_data (csrbus_wr_data[47]), |
| 1069 | .rw_alias (1'b1), |
| 1070 | .rw1c_alias (1'b0), |
| 1071 | .rw1s_alias (1'b0), |
| 1072 | .hw_ld (1'b0), |
| 1073 | .hw_data (1'b0), |
| 1074 | .cp (clk), |
| 1075 | .q (int_mondo_data_0_reg_csrbus_read_data[47]) |
| 1076 | ); |
| 1077 | |
| 1078 | // bit 48 |
| 1079 | csr_sw csr_sw_48 |
| 1080 | ( |
| 1081 | // synopsys translate_off |
| 1082 | .omni_ld (omni_ld), |
| 1083 | .omni_data (omni_data[48]), |
| 1084 | .omni_rw_alias (1'b1), |
| 1085 | .omni_rw1c_alias (1'b0), |
| 1086 | .omni_rw1s_alias (1'b0), |
| 1087 | // synopsys translate_on |
| 1088 | .rst (rst_l_active_high), |
| 1089 | .rst_val (reset_data[42]), |
| 1090 | .csr_ld (w_ld), |
| 1091 | .csr_data (csrbus_wr_data[48]), |
| 1092 | .rw_alias (1'b1), |
| 1093 | .rw1c_alias (1'b0), |
| 1094 | .rw1s_alias (1'b0), |
| 1095 | .hw_ld (1'b0), |
| 1096 | .hw_data (1'b0), |
| 1097 | .cp (clk), |
| 1098 | .q (int_mondo_data_0_reg_csrbus_read_data[48]) |
| 1099 | ); |
| 1100 | |
| 1101 | // bit 49 |
| 1102 | csr_sw csr_sw_49 |
| 1103 | ( |
| 1104 | // synopsys translate_off |
| 1105 | .omni_ld (omni_ld), |
| 1106 | .omni_data (omni_data[49]), |
| 1107 | .omni_rw_alias (1'b1), |
| 1108 | .omni_rw1c_alias (1'b0), |
| 1109 | .omni_rw1s_alias (1'b0), |
| 1110 | // synopsys translate_on |
| 1111 | .rst (rst_l_active_high), |
| 1112 | .rst_val (reset_data[43]), |
| 1113 | .csr_ld (w_ld), |
| 1114 | .csr_data (csrbus_wr_data[49]), |
| 1115 | .rw_alias (1'b1), |
| 1116 | .rw1c_alias (1'b0), |
| 1117 | .rw1s_alias (1'b0), |
| 1118 | .hw_ld (1'b0), |
| 1119 | .hw_data (1'b0), |
| 1120 | .cp (clk), |
| 1121 | .q (int_mondo_data_0_reg_csrbus_read_data[49]) |
| 1122 | ); |
| 1123 | |
| 1124 | // bit 50 |
| 1125 | csr_sw csr_sw_50 |
| 1126 | ( |
| 1127 | // synopsys translate_off |
| 1128 | .omni_ld (omni_ld), |
| 1129 | .omni_data (omni_data[50]), |
| 1130 | .omni_rw_alias (1'b1), |
| 1131 | .omni_rw1c_alias (1'b0), |
| 1132 | .omni_rw1s_alias (1'b0), |
| 1133 | // synopsys translate_on |
| 1134 | .rst (rst_l_active_high), |
| 1135 | .rst_val (reset_data[44]), |
| 1136 | .csr_ld (w_ld), |
| 1137 | .csr_data (csrbus_wr_data[50]), |
| 1138 | .rw_alias (1'b1), |
| 1139 | .rw1c_alias (1'b0), |
| 1140 | .rw1s_alias (1'b0), |
| 1141 | .hw_ld (1'b0), |
| 1142 | .hw_data (1'b0), |
| 1143 | .cp (clk), |
| 1144 | .q (int_mondo_data_0_reg_csrbus_read_data[50]) |
| 1145 | ); |
| 1146 | |
| 1147 | // bit 51 |
| 1148 | csr_sw csr_sw_51 |
| 1149 | ( |
| 1150 | // synopsys translate_off |
| 1151 | .omni_ld (omni_ld), |
| 1152 | .omni_data (omni_data[51]), |
| 1153 | .omni_rw_alias (1'b1), |
| 1154 | .omni_rw1c_alias (1'b0), |
| 1155 | .omni_rw1s_alias (1'b0), |
| 1156 | // synopsys translate_on |
| 1157 | .rst (rst_l_active_high), |
| 1158 | .rst_val (reset_data[45]), |
| 1159 | .csr_ld (w_ld), |
| 1160 | .csr_data (csrbus_wr_data[51]), |
| 1161 | .rw_alias (1'b1), |
| 1162 | .rw1c_alias (1'b0), |
| 1163 | .rw1s_alias (1'b0), |
| 1164 | .hw_ld (1'b0), |
| 1165 | .hw_data (1'b0), |
| 1166 | .cp (clk), |
| 1167 | .q (int_mondo_data_0_reg_csrbus_read_data[51]) |
| 1168 | ); |
| 1169 | |
| 1170 | // bit 52 |
| 1171 | csr_sw csr_sw_52 |
| 1172 | ( |
| 1173 | // synopsys translate_off |
| 1174 | .omni_ld (omni_ld), |
| 1175 | .omni_data (omni_data[52]), |
| 1176 | .omni_rw_alias (1'b1), |
| 1177 | .omni_rw1c_alias (1'b0), |
| 1178 | .omni_rw1s_alias (1'b0), |
| 1179 | // synopsys translate_on |
| 1180 | .rst (rst_l_active_high), |
| 1181 | .rst_val (reset_data[46]), |
| 1182 | .csr_ld (w_ld), |
| 1183 | .csr_data (csrbus_wr_data[52]), |
| 1184 | .rw_alias (1'b1), |
| 1185 | .rw1c_alias (1'b0), |
| 1186 | .rw1s_alias (1'b0), |
| 1187 | .hw_ld (1'b0), |
| 1188 | .hw_data (1'b0), |
| 1189 | .cp (clk), |
| 1190 | .q (int_mondo_data_0_reg_csrbus_read_data[52]) |
| 1191 | ); |
| 1192 | |
| 1193 | // bit 53 |
| 1194 | csr_sw csr_sw_53 |
| 1195 | ( |
| 1196 | // synopsys translate_off |
| 1197 | .omni_ld (omni_ld), |
| 1198 | .omni_data (omni_data[53]), |
| 1199 | .omni_rw_alias (1'b1), |
| 1200 | .omni_rw1c_alias (1'b0), |
| 1201 | .omni_rw1s_alias (1'b0), |
| 1202 | // synopsys translate_on |
| 1203 | .rst (rst_l_active_high), |
| 1204 | .rst_val (reset_data[47]), |
| 1205 | .csr_ld (w_ld), |
| 1206 | .csr_data (csrbus_wr_data[53]), |
| 1207 | .rw_alias (1'b1), |
| 1208 | .rw1c_alias (1'b0), |
| 1209 | .rw1s_alias (1'b0), |
| 1210 | .hw_ld (1'b0), |
| 1211 | .hw_data (1'b0), |
| 1212 | .cp (clk), |
| 1213 | .q (int_mondo_data_0_reg_csrbus_read_data[53]) |
| 1214 | ); |
| 1215 | |
| 1216 | // bit 54 |
| 1217 | csr_sw csr_sw_54 |
| 1218 | ( |
| 1219 | // synopsys translate_off |
| 1220 | .omni_ld (omni_ld), |
| 1221 | .omni_data (omni_data[54]), |
| 1222 | .omni_rw_alias (1'b1), |
| 1223 | .omni_rw1c_alias (1'b0), |
| 1224 | .omni_rw1s_alias (1'b0), |
| 1225 | // synopsys translate_on |
| 1226 | .rst (rst_l_active_high), |
| 1227 | .rst_val (reset_data[48]), |
| 1228 | .csr_ld (w_ld), |
| 1229 | .csr_data (csrbus_wr_data[54]), |
| 1230 | .rw_alias (1'b1), |
| 1231 | .rw1c_alias (1'b0), |
| 1232 | .rw1s_alias (1'b0), |
| 1233 | .hw_ld (1'b0), |
| 1234 | .hw_data (1'b0), |
| 1235 | .cp (clk), |
| 1236 | .q (int_mondo_data_0_reg_csrbus_read_data[54]) |
| 1237 | ); |
| 1238 | |
| 1239 | // bit 55 |
| 1240 | csr_sw csr_sw_55 |
| 1241 | ( |
| 1242 | // synopsys translate_off |
| 1243 | .omni_ld (omni_ld), |
| 1244 | .omni_data (omni_data[55]), |
| 1245 | .omni_rw_alias (1'b1), |
| 1246 | .omni_rw1c_alias (1'b0), |
| 1247 | .omni_rw1s_alias (1'b0), |
| 1248 | // synopsys translate_on |
| 1249 | .rst (rst_l_active_high), |
| 1250 | .rst_val (reset_data[49]), |
| 1251 | .csr_ld (w_ld), |
| 1252 | .csr_data (csrbus_wr_data[55]), |
| 1253 | .rw_alias (1'b1), |
| 1254 | .rw1c_alias (1'b0), |
| 1255 | .rw1s_alias (1'b0), |
| 1256 | .hw_ld (1'b0), |
| 1257 | .hw_data (1'b0), |
| 1258 | .cp (clk), |
| 1259 | .q (int_mondo_data_0_reg_csrbus_read_data[55]) |
| 1260 | ); |
| 1261 | |
| 1262 | // bit 56 |
| 1263 | csr_sw csr_sw_56 |
| 1264 | ( |
| 1265 | // synopsys translate_off |
| 1266 | .omni_ld (omni_ld), |
| 1267 | .omni_data (omni_data[56]), |
| 1268 | .omni_rw_alias (1'b1), |
| 1269 | .omni_rw1c_alias (1'b0), |
| 1270 | .omni_rw1s_alias (1'b0), |
| 1271 | // synopsys translate_on |
| 1272 | .rst (rst_l_active_high), |
| 1273 | .rst_val (reset_data[50]), |
| 1274 | .csr_ld (w_ld), |
| 1275 | .csr_data (csrbus_wr_data[56]), |
| 1276 | .rw_alias (1'b1), |
| 1277 | .rw1c_alias (1'b0), |
| 1278 | .rw1s_alias (1'b0), |
| 1279 | .hw_ld (1'b0), |
| 1280 | .hw_data (1'b0), |
| 1281 | .cp (clk), |
| 1282 | .q (int_mondo_data_0_reg_csrbus_read_data[56]) |
| 1283 | ); |
| 1284 | |
| 1285 | // bit 57 |
| 1286 | csr_sw csr_sw_57 |
| 1287 | ( |
| 1288 | // synopsys translate_off |
| 1289 | .omni_ld (omni_ld), |
| 1290 | .omni_data (omni_data[57]), |
| 1291 | .omni_rw_alias (1'b1), |
| 1292 | .omni_rw1c_alias (1'b0), |
| 1293 | .omni_rw1s_alias (1'b0), |
| 1294 | // synopsys translate_on |
| 1295 | .rst (rst_l_active_high), |
| 1296 | .rst_val (reset_data[51]), |
| 1297 | .csr_ld (w_ld), |
| 1298 | .csr_data (csrbus_wr_data[57]), |
| 1299 | .rw_alias (1'b1), |
| 1300 | .rw1c_alias (1'b0), |
| 1301 | .rw1s_alias (1'b0), |
| 1302 | .hw_ld (1'b0), |
| 1303 | .hw_data (1'b0), |
| 1304 | .cp (clk), |
| 1305 | .q (int_mondo_data_0_reg_csrbus_read_data[57]) |
| 1306 | ); |
| 1307 | |
| 1308 | // bit 58 |
| 1309 | csr_sw csr_sw_58 |
| 1310 | ( |
| 1311 | // synopsys translate_off |
| 1312 | .omni_ld (omni_ld), |
| 1313 | .omni_data (omni_data[58]), |
| 1314 | .omni_rw_alias (1'b1), |
| 1315 | .omni_rw1c_alias (1'b0), |
| 1316 | .omni_rw1s_alias (1'b0), |
| 1317 | // synopsys translate_on |
| 1318 | .rst (rst_l_active_high), |
| 1319 | .rst_val (reset_data[52]), |
| 1320 | .csr_ld (w_ld), |
| 1321 | .csr_data (csrbus_wr_data[58]), |
| 1322 | .rw_alias (1'b1), |
| 1323 | .rw1c_alias (1'b0), |
| 1324 | .rw1s_alias (1'b0), |
| 1325 | .hw_ld (1'b0), |
| 1326 | .hw_data (1'b0), |
| 1327 | .cp (clk), |
| 1328 | .q (int_mondo_data_0_reg_csrbus_read_data[58]) |
| 1329 | ); |
| 1330 | |
| 1331 | // bit 59 |
| 1332 | csr_sw csr_sw_59 |
| 1333 | ( |
| 1334 | // synopsys translate_off |
| 1335 | .omni_ld (omni_ld), |
| 1336 | .omni_data (omni_data[59]), |
| 1337 | .omni_rw_alias (1'b1), |
| 1338 | .omni_rw1c_alias (1'b0), |
| 1339 | .omni_rw1s_alias (1'b0), |
| 1340 | // synopsys translate_on |
| 1341 | .rst (rst_l_active_high), |
| 1342 | .rst_val (reset_data[53]), |
| 1343 | .csr_ld (w_ld), |
| 1344 | .csr_data (csrbus_wr_data[59]), |
| 1345 | .rw_alias (1'b1), |
| 1346 | .rw1c_alias (1'b0), |
| 1347 | .rw1s_alias (1'b0), |
| 1348 | .hw_ld (1'b0), |
| 1349 | .hw_data (1'b0), |
| 1350 | .cp (clk), |
| 1351 | .q (int_mondo_data_0_reg_csrbus_read_data[59]) |
| 1352 | ); |
| 1353 | |
| 1354 | // bit 60 |
| 1355 | csr_sw csr_sw_60 |
| 1356 | ( |
| 1357 | // synopsys translate_off |
| 1358 | .omni_ld (omni_ld), |
| 1359 | .omni_data (omni_data[60]), |
| 1360 | .omni_rw_alias (1'b1), |
| 1361 | .omni_rw1c_alias (1'b0), |
| 1362 | .omni_rw1s_alias (1'b0), |
| 1363 | // synopsys translate_on |
| 1364 | .rst (rst_l_active_high), |
| 1365 | .rst_val (reset_data[54]), |
| 1366 | .csr_ld (w_ld), |
| 1367 | .csr_data (csrbus_wr_data[60]), |
| 1368 | .rw_alias (1'b1), |
| 1369 | .rw1c_alias (1'b0), |
| 1370 | .rw1s_alias (1'b0), |
| 1371 | .hw_ld (1'b0), |
| 1372 | .hw_data (1'b0), |
| 1373 | .cp (clk), |
| 1374 | .q (int_mondo_data_0_reg_csrbus_read_data[60]) |
| 1375 | ); |
| 1376 | |
| 1377 | // bit 61 |
| 1378 | csr_sw csr_sw_61 |
| 1379 | ( |
| 1380 | // synopsys translate_off |
| 1381 | .omni_ld (omni_ld), |
| 1382 | .omni_data (omni_data[61]), |
| 1383 | .omni_rw_alias (1'b1), |
| 1384 | .omni_rw1c_alias (1'b0), |
| 1385 | .omni_rw1s_alias (1'b0), |
| 1386 | // synopsys translate_on |
| 1387 | .rst (rst_l_active_high), |
| 1388 | .rst_val (reset_data[55]), |
| 1389 | .csr_ld (w_ld), |
| 1390 | .csr_data (csrbus_wr_data[61]), |
| 1391 | .rw_alias (1'b1), |
| 1392 | .rw1c_alias (1'b0), |
| 1393 | .rw1s_alias (1'b0), |
| 1394 | .hw_ld (1'b0), |
| 1395 | .hw_data (1'b0), |
| 1396 | .cp (clk), |
| 1397 | .q (int_mondo_data_0_reg_csrbus_read_data[61]) |
| 1398 | ); |
| 1399 | |
| 1400 | // bit 62 |
| 1401 | csr_sw csr_sw_62 |
| 1402 | ( |
| 1403 | // synopsys translate_off |
| 1404 | .omni_ld (omni_ld), |
| 1405 | .omni_data (omni_data[62]), |
| 1406 | .omni_rw_alias (1'b1), |
| 1407 | .omni_rw1c_alias (1'b0), |
| 1408 | .omni_rw1s_alias (1'b0), |
| 1409 | // synopsys translate_on |
| 1410 | .rst (rst_l_active_high), |
| 1411 | .rst_val (reset_data[56]), |
| 1412 | .csr_ld (w_ld), |
| 1413 | .csr_data (csrbus_wr_data[62]), |
| 1414 | .rw_alias (1'b1), |
| 1415 | .rw1c_alias (1'b0), |
| 1416 | .rw1s_alias (1'b0), |
| 1417 | .hw_ld (1'b0), |
| 1418 | .hw_data (1'b0), |
| 1419 | .cp (clk), |
| 1420 | .q (int_mondo_data_0_reg_csrbus_read_data[62]) |
| 1421 | ); |
| 1422 | |
| 1423 | // bit 63 |
| 1424 | csr_sw csr_sw_63 |
| 1425 | ( |
| 1426 | // synopsys translate_off |
| 1427 | .omni_ld (omni_ld), |
| 1428 | .omni_data (omni_data[63]), |
| 1429 | .omni_rw_alias (1'b1), |
| 1430 | .omni_rw1c_alias (1'b0), |
| 1431 | .omni_rw1s_alias (1'b0), |
| 1432 | // synopsys translate_on |
| 1433 | .rst (rst_l_active_high), |
| 1434 | .rst_val (reset_data[57]), |
| 1435 | .csr_ld (w_ld), |
| 1436 | .csr_data (csrbus_wr_data[63]), |
| 1437 | .rw_alias (1'b1), |
| 1438 | .rw1c_alias (1'b0), |
| 1439 | .rw1s_alias (1'b0), |
| 1440 | .hw_ld (1'b0), |
| 1441 | .hw_data (1'b0), |
| 1442 | .cp (clk), |
| 1443 | .q (int_mondo_data_0_reg_csrbus_read_data[63]) |
| 1444 | ); |
| 1445 | |
| 1446 | |
| 1447 | endmodule // dmu_imu_rds_msi_csr_int_mondo_data_0_reg_entry |