| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_rds_msi_csrpipe_3.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_rds_msi_csrpipe_3 |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | reg_in, |
| 40 | reg_out, |
| 41 | data0, |
| 42 | data1, |
| 43 | data2, |
| 44 | sel0, |
| 45 | sel1, |
| 46 | sel2, |
| 47 | out |
| 48 | ); |
| 49 | |
| 50 | //==================================================================== |
| 51 | // Polarity declarations |
| 52 | //==================================================================== |
| 53 | input clk; // Clock signal |
| 54 | input rst_l; // Reset signal |
| 55 | input reg_in; // Set to constant. 0: sel* non-reg 1: sel* reg |
| 56 | input reg_out; // Set to constant. 0: out non-reg 1: out registered |
| 57 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data0; // Read data |
| 58 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data1; // Read data |
| 59 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data2; // Read data |
| 60 | input sel0; // Set to 1 if reg_in==0 |
| 61 | input sel1; // Set to 1 if reg_in==0 |
| 62 | input sel2; // Set to 1 if reg_in==0 |
| 63 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] out; // Read data out |
| 64 | |
| 65 | //==================================================================== |
| 66 | // Type declarations |
| 67 | //==================================================================== |
| 68 | wire clk; // Clock signal |
| 69 | wire rst_l; // Reset signal |
| 70 | wire reg_in; // Set to constant. 0: sel* non-reg 1: sel* reg |
| 71 | wire reg_out; // Set to constant. 0: out non-reg 1: out registered |
| 72 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data0; // Read data |
| 73 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data1; // Read data |
| 74 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data2; // Read data |
| 75 | wire sel0; // Set to 1 if reg_in==0 |
| 76 | wire sel1; // Set to 1 if reg_in==0 |
| 77 | wire sel2; // Set to 1 if reg_in==0 |
| 78 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] out; // Read data out |
| 79 | |
| 80 | //==================================================================== |
| 81 | // Local variables |
| 82 | //==================================================================== |
| 83 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] out_p1; |
| 84 | reg sel0_p1; |
| 85 | reg sel1_p1; |
| 86 | reg sel2_p1; |
| 87 | |
| 88 | //==================================================================== |
| 89 | // Logic |
| 90 | //==================================================================== |
| 91 | //select required ? |
| 92 | wire sel0_int=reg_in?sel0_p1:sel0; |
| 93 | wire sel1_int=reg_in?sel1_p1:sel1; |
| 94 | wire sel2_int=reg_in?sel2_p1:sel2; |
| 95 | |
| 96 | //generate AND/OR |
| 97 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] out_d = |
| 98 | {`FIRE_CSRBUS_DATA_WIDTH { sel0_int } } & data0 | |
| 99 | {`FIRE_CSRBUS_DATA_WIDTH { sel1_int } } & data1 | |
| 100 | {`FIRE_CSRBUS_DATA_WIDTH { sel2_int } } & data2; |
| 101 | |
| 102 | //reg out or combo |
| 103 | assign out=reg_out?out_p1:out_d; |
| 104 | |
| 105 | //pipe control/data |
| 106 | always @(posedge clk) |
| 107 | begin |
| 108 | if(~rst_l) |
| 109 | begin |
| 110 | sel0_p1<=1'b0; |
| 111 | sel1_p1<=1'b0; |
| 112 | sel2_p1<=1'b0; |
| 113 | out_p1<=`FIRE_CSRBUS_DATA_WIDTH'b0; |
| 114 | end |
| 115 | else |
| 116 | begin |
| 117 | sel0_p1<=sel0; |
| 118 | sel1_p1<=sel1; |
| 119 | sel2_p1<=sel2; |
| 120 | out_p1<=out_d; |
| 121 | end |
| 122 | end |
| 123 | |
| 124 | endmodule // dmu_imu_rds_msi_csrpipe_3 |