| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_scs.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_scs ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | |
| 43 | // Inputs from RDS sub-block |
| 44 | |
| 45 | rds2scs_rcd, |
| 46 | rds2scs_rcd_sel, |
| 47 | rds2scs_eq, |
| 48 | |
| 49 | // Inputs from the EQS sub-block |
| 50 | |
| 51 | eqs2scs_eq_ok, |
| 52 | eqs2scs_eq_not_en, |
| 53 | |
| 54 | // Outputs to ORS state Sub-block |
| 55 | |
| 56 | scs2ors_rcd, |
| 57 | scs2ors_rcd_sel, |
| 58 | |
| 59 | |
| 60 | // Error Int Output |
| 61 | scs2ics_eq_not_en_error, |
| 62 | scs2ics_error_data, |
| 63 | |
| 64 | |
| 65 | // Debug Ports |
| 66 | |
| 67 | dbg2scs_dbg_sel_a, |
| 68 | dbg2scs_dbg_sel_b, |
| 69 | scs2dbg_dbg_a, |
| 70 | scs2dbg_dbg_b |
| 71 | |
| 72 | |
| 73 | ); |
| 74 | |
| 75 | |
| 76 | //############################################################################ |
| 77 | // PORT DECLARATIONS |
| 78 | //############################################################################ |
| 79 | |
| 80 | //------------------------------------------------------------------------ |
| 81 | // Clock and Reset Signals |
| 82 | //------------------------------------------------------------------------ |
| 83 | input clk; |
| 84 | input rst_l; |
| 85 | |
| 86 | |
| 87 | //------------------------------------------------------------------------ |
| 88 | // Input from RDS |
| 89 | //------------------------------------------------------------------------ |
| 90 | input [`FIRE_DLC_IIN_REC_WDTH-1:0] rds2scs_rcd; |
| 91 | input rds2scs_rcd_sel; |
| 92 | input [5:0] rds2scs_eq; |
| 93 | |
| 94 | |
| 95 | //------------------------------------------------------------------------ |
| 96 | // Input from Decoder sub-block |
| 97 | //------------------------------------------------------------------------ |
| 98 | input eqs2scs_eq_ok; |
| 99 | input eqs2scs_eq_not_en; |
| 100 | |
| 101 | //------------------------------------------------------------------------ |
| 102 | // Output to Out Record Sub-block |
| 103 | //------------------------------------------------------------------------ |
| 104 | output [`FIRE_DLC_IIN_REC_WDTH-1:0] scs2ors_rcd; |
| 105 | output scs2ors_rcd_sel; |
| 106 | |
| 107 | output scs2ics_eq_not_en_error; |
| 108 | output [63:0] scs2ics_error_data; |
| 109 | |
| 110 | //------------------------------------------------------------------------ |
| 111 | // Debug Ports |
| 112 | //------------------------------------------------------------------------ |
| 113 | |
| 114 | input [2:0] dbg2scs_dbg_sel_a; |
| 115 | input [2:0] dbg2scs_dbg_sel_b; |
| 116 | output [`FIRE_DEBUG_WDTH-1:0] scs2dbg_dbg_a; |
| 117 | output [`FIRE_DEBUG_WDTH-1:0] scs2dbg_dbg_b; |
| 118 | |
| 119 | //############################################################################ |
| 120 | // PARAMETERS |
| 121 | //############################################################################ |
| 122 | |
| 123 | |
| 124 | //############################################################################ |
| 125 | // SIGNAL DECLARATIONS |
| 126 | //############################################################################ |
| 127 | |
| 128 | |
| 129 | //************************************************** |
| 130 | // Wires |
| 131 | //************************************************** |
| 132 | |
| 133 | //------------------------------------- |
| 134 | // Live In Record Fields |
| 135 | //------------------------------------- |
| 136 | wire [`FIRE_DLC_IIN_TYPE_WDTH -1:0] in_type; |
| 137 | |
| 138 | //------------------------------------- |
| 139 | // Packet Type Decode Wires |
| 140 | //------------------------------------- |
| 141 | wire pkt_is_msi; |
| 142 | wire pkt_is_mes; |
| 143 | |
| 144 | //------------------------------------- |
| 145 | // Signal to look at EQ lookup results |
| 146 | //------------------------------------- |
| 147 | wire check_results; |
| 148 | |
| 149 | //------------------------------------- |
| 150 | // Signal for out record type |
| 151 | //------------------------------------- |
| 152 | wire [`FIRE_DLC_IIN_TYPE_WDTH -1:0] out_type; |
| 153 | |
| 154 | //************************************************** |
| 155 | // Registers that Are Not Flops |
| 156 | //************************************************** |
| 157 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_a; |
| 158 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_b; |
| 159 | |
| 160 | //************************************************** |
| 161 | // Registers that Are Flops |
| 162 | //************************************************** |
| 163 | |
| 164 | //------------------------------------- |
| 165 | // Out Record Flops |
| 166 | //------------------------------------- |
| 167 | reg [`FIRE_DLC_IIN_REC_WDTH-1:0] scs2ors_rcd; |
| 168 | reg scs2ors_rcd_sel; |
| 169 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_a; |
| 170 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_b; |
| 171 | //############################################################################ |
| 172 | // ZERO IN CHECKERS |
| 173 | //############################################################################ |
| 174 | |
| 175 | |
| 176 | //############################################################################ |
| 177 | // COMBINATIONAL LOGIC |
| 178 | //############################################################################ |
| 179 | |
| 180 | //-------------------------------- |
| 181 | // Grab the Incomming Packet Type |
| 182 | //-------------------------------- |
| 183 | |
| 184 | assign in_type = rds2scs_rcd[`FIRE_DLC_IIN_TYPE_MSB:`FIRE_DLC_IIN_TYPE_LSB]; |
| 185 | |
| 186 | //-------------------------------- |
| 187 | // Decode Incomming Packet Type |
| 188 | // |
| 189 | // See if the packet is either |
| 190 | // - MSI |
| 191 | // - Message |
| 192 | //-------------------------------- |
| 193 | |
| 194 | assign pkt_is_msi = in_type[`FIRE_DLC_IMU_OTYPE_DECODE_2] & |
| 195 | !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_1] & |
| 196 | !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_0]; |
| 197 | |
| 198 | assign pkt_is_mes = !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_2]; |
| 199 | |
| 200 | //-------------------------------- |
| 201 | // Form check results Signal |
| 202 | // |
| 203 | // If it is either |
| 204 | // - MSI |
| 205 | // - Message |
| 206 | //-------------------------------- |
| 207 | |
| 208 | assign check_results = pkt_is_msi | pkt_is_mes; |
| 209 | |
| 210 | //-------------------------------------- |
| 211 | // Calculate Proper Output Type |
| 212 | // |
| 213 | // If need to check results |
| 214 | // |
| 215 | // -Check to see if results are good |
| 216 | // - if good keep type |
| 217 | // - if bad put in null |
| 218 | // |
| 219 | // If dont need to check results |
| 220 | // |
| 221 | /// - Keep current type |
| 222 | //-------------------------------------- |
| 223 | |
| 224 | assign out_type = check_results ? ( eqs2scs_eq_ok ? in_type : `FIRE_DLC_IMU_TYPE_NULL) : in_type; |
| 225 | |
| 226 | |
| 227 | //-------------------------------- |
| 228 | // Error Checking for Interrupt |
| 229 | // - get an EQ wite (mess or msi) |
| 230 | // - EQ is in IDLE state |
| 231 | // |
| 232 | //-------------------------------- |
| 233 | |
| 234 | assign scs2ics_eq_not_en_error = rds2scs_rcd_sel & check_results & eqs2scs_eq_not_en; |
| 235 | |
| 236 | |
| 237 | assign scs2ics_error_data = { rds2scs_rcd[`FIRE_DLC_IIN_TYPE_MSB-1 : `FIRE_DLC_IIN_TYPE_LSB], |
| 238 | rds2scs_rcd[`FIRE_DLC_IIN_LEN_MSB : `FIRE_DLC_IIN_LEN_LSB], |
| 239 | rds2scs_rcd[`FIRE_DLC_IIN_REQID_MSB : `FIRE_DLC_IIN_REQID_LSB], |
| 240 | rds2scs_rcd[`FIRE_DLC_IIN_TLPTAG_MSB : `FIRE_DLC_IIN_TLPTAG_LSB], |
| 241 | rds2scs_rcd[`FIRE_DLC_IIN_DATA_MSB : `FIRE_DLC_IIN_DATA_LSB], |
| 242 | 10'h0, rds2scs_eq}; |
| 243 | |
| 244 | //----------------------------------------------------- |
| 245 | // Debug Ports |
| 246 | //----------------------------------------------------- |
| 247 | |
| 248 | always @ (dbg2scs_dbg_sel_a or rds2scs_rcd_sel or in_type or pkt_is_msi or pkt_is_mes or |
| 249 | check_results or eqs2scs_eq_ok or eqs2scs_eq_not_en or scs2ics_eq_not_en_error) |
| 250 | begin |
| 251 | case (dbg2scs_dbg_sel_a) // synopsys infer_mux |
| 252 | 3'b000: n_dbg_a = {rds2scs_rcd_sel, in_type[6:0]}; |
| 253 | 3'b001: n_dbg_a = {3'h0, pkt_is_msi, pkt_is_mes, check_results, eqs2scs_eq_ok, eqs2scs_eq_not_en}; |
| 254 | 3'b010: n_dbg_a = {7'h0, scs2ics_eq_not_en_error}; |
| 255 | 3'b011: n_dbg_a = 8'h00; |
| 256 | 3'b100: n_dbg_a = 8'h00; |
| 257 | 3'b101: n_dbg_a = 8'h00; |
| 258 | 3'b110: n_dbg_a = 8'h00; |
| 259 | 3'b111: n_dbg_a = 8'h00; |
| 260 | endcase |
| 261 | end |
| 262 | |
| 263 | always @ (dbg2scs_dbg_sel_b or rds2scs_rcd_sel or in_type or pkt_is_msi or pkt_is_mes or |
| 264 | check_results or eqs2scs_eq_ok or eqs2scs_eq_not_en or scs2ics_eq_not_en_error) |
| 265 | begin |
| 266 | case (dbg2scs_dbg_sel_b) // synopsys infer_mux |
| 267 | 3'b000: n_dbg_b = {rds2scs_rcd_sel, in_type[6:0]}; |
| 268 | 3'b001: n_dbg_b = {3'h0, pkt_is_msi, pkt_is_mes, check_results, eqs2scs_eq_ok, eqs2scs_eq_not_en}; |
| 269 | 3'b010: n_dbg_b = {7'h0, scs2ics_eq_not_en_error}; |
| 270 | 3'b011: n_dbg_b = 8'h00; |
| 271 | 3'b100: n_dbg_b = 8'h00; |
| 272 | 3'b101: n_dbg_b = 8'h00; |
| 273 | 3'b110: n_dbg_b = 8'h00; |
| 274 | 3'b111: n_dbg_b = 8'h00; |
| 275 | endcase |
| 276 | end |
| 277 | |
| 278 | |
| 279 | always @ (posedge clk) |
| 280 | begin |
| 281 | if (!rst_l) begin |
| 282 | dbg_a <= 8'b0; |
| 283 | dbg_b <= 8'b0; |
| 284 | end |
| 285 | else begin |
| 286 | dbg_a <= n_dbg_a; |
| 287 | dbg_b <= n_dbg_b; |
| 288 | end |
| 289 | end |
| 290 | |
| 291 | |
| 292 | assign scs2dbg_dbg_a = dbg_a; |
| 293 | assign scs2dbg_dbg_b = dbg_b; |
| 294 | |
| 295 | |
| 296 | |
| 297 | |
| 298 | //############################################################################ |
| 299 | // SEQUENTIAL LOGIC |
| 300 | //############################################################################ |
| 301 | |
| 302 | //----------------------------------------------------------------------------- |
| 303 | // Delay all of the In Record information to keep in step with the pipeline. |
| 304 | //----------------------------------------------------------------------------- |
| 305 | always @ (posedge clk) |
| 306 | if (!rst_l) |
| 307 | begin |
| 308 | scs2ors_rcd <= {`FIRE_DLC_IIN_REC_WDTH{1'h0}}; |
| 309 | scs2ors_rcd_sel <= 1'h0; |
| 310 | end |
| 311 | else |
| 312 | begin |
| 313 | scs2ors_rcd <= {out_type,rds2scs_rcd[`FIRE_DLC_IIN_TC_MSB:0]}; |
| 314 | scs2ors_rcd_sel <= rds2scs_rcd_sel; |
| 315 | end |
| 316 | |
| 317 | |
| 318 | endmodule |