| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_csr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_csr |
| 36 | ( |
| 37 | clk, // clock |
| 38 | por_l, // power-on reset |
| 39 | rst_l, // reset |
| 40 | j2d_instance_id, // jbc instance id |
| 41 | cr2mm_csrbus_addr, // cru csr addr |
| 42 | cr2mm_csrbus_src_bus, // cru scr source bus |
| 43 | cr2mm_csrbus_valid, // cru csr valid |
| 44 | cr2mm_csrbus_wr, // cru csr write |
| 45 | cr2mm_csrbus_wr_data, // cru csr write data |
| 46 | cr2mm_dbg_sel_a, // cru debug select a |
| 47 | cr2mm_dbg_sel_b, // cru debug select b |
| 48 | crb2csr_dbg_a, // crb debug data a |
| 49 | crb2csr_dbg_b, // crb debug data b |
| 50 | crb2csr_rd, // crb read data |
| 51 | ptb2csr_rd, // ptb read data |
| 52 | qcb2csr_dbg_a, // qcb debug data a |
| 53 | qcb2csr_dbg_b, // qcb debug data b |
| 54 | qcb2csr_paq, // csr physical address queue not empty |
| 55 | qcb2csr_vaq, // csr virtual address queue not empty |
| 56 | tcb2csr_dbg_a, // tcb debug data a |
| 57 | tcb2csr_dbg_b, // tcb debug data b |
| 58 | tcb2csr_err, // tcb error |
| 59 | tcb2csr_prf, // tcb performance events |
| 60 | tcb2csr_tcm, // csr tablewalk cache mode |
| 61 | tcb2csr_tip, // csr tablewalk in progress |
| 62 | tcb2csr_tpl, // csr translation pipeline not empty |
| 63 | tdb2csr_rd, // tdb read data |
| 64 | tlb2csr_addr, // tlb address |
| 65 | tlb2csr_dbra, // tlb data buffer read address |
| 66 | tlb2csr_rqid, // tlb requester ID |
| 67 | tlb2csr_type, // tlb type |
| 68 | vtb2csr_prf, // vtb performance event |
| 69 | vtb2csr_rd, // vtb read data |
| 70 | mm2cr_csrbus_acc_vio, // cru csr access violation |
| 71 | mm2cr_csrbus_done, // cru csr done |
| 72 | mm2cr_csrbus_mapped, // cru csr mapped |
| 73 | mm2cr_csrbus_read_data, // cru csr read data |
| 74 | mm2cr_dbg_a, // cru debug data a |
| 75 | mm2cr_dbg_b, // cru debug data b |
| 76 | mm2im_int, // imu interrupt |
| 77 | csr2crb_ds_a, // crb debug select a |
| 78 | csr2crb_ds_b, // crb debug select b |
| 79 | csr2crb_ra, // crb read address |
| 80 | csr2crb_wa, // crb write address |
| 81 | csr2crb_wd, // crb write data |
| 82 | csr2crb_we, // crb write enable |
| 83 | csr2pab_ps, // pab page size |
| 84 | csr2ptb_inv, // crb tag invalidate |
| 85 | csr2ptb_ra, // ptb read address |
| 86 | csr2ptb_wa, // ptb write address |
| 87 | csr2ptb_wd, // ptb write data |
| 88 | csr2ptb_we, // ptb write enable |
| 89 | csr2qcb_ds_a, // qcb debug select a |
| 90 | csr2qcb_ds_b, // qcb debug select b |
| 91 | csr2rcb_se, // rcb snoop enable |
| 92 | // csr2rcb_tb, // rcb tsb base address |
| 93 | // csr2rcb_ts, // rcb tsb size |
| 94 | csr2tcb_av, // tcb access violation |
| 95 | csr2tcb_be, // tcb bypass enable |
| 96 | csr2tcb_cm, // tcb cache mode |
| 97 | csr2tcb_ds_a, // tcb debug select a |
| 98 | csr2tcb_ds_b, // tcb debug select b |
| 99 | csr2tcb_pd, // tcb processing disable |
| 100 | csr2tcb_te, // tcb translation enable |
| 101 | csr2tdb_ra, // tdb read address |
| 102 | csr2tdb_wa, // tdb write address |
| 103 | csr2tdb_wd, // tdb write data |
| 104 | csr2tdb_we, // tdb write enable |
| 105 | csr2tlb_ps, // tlb page size |
| 106 | csr2tlb_tb, // tlb table base address |
| 107 | csr2tlb_ts, // tlb table size |
| 108 | csr2vab_ps, // vab page size |
| 109 | csr2vab_ts, // vab table size |
| 110 | csr2vtb_ra, // vtb read address |
| 111 | csr2vtb_wa, // vtb write address |
| 112 | csr2vtb_wd, // vtb write data |
| 113 | csr2vtb_we, // vtb write enable |
| 114 | csr2dev_iotsb_wd, |
| 115 | dev_iotsb2csr_rd, |
| 116 | csr2dev2iotsb_we, |
| 117 | csr2dev2iotsb_re, |
| 118 | csr2IotsbDesc_we, |
| 119 | csr2IotsbDesc_re, |
| 120 | csr2dev_iotsb_rwa, |
| 121 | dev_iotsb_ext_done, |
| 122 | ctl_busid_sel_hw_read, |
| 123 | ctl_sun4v_en_hw_read |
| 124 | ); |
| 125 | |
| 126 | // ---------------------------------------------------------------------------- |
| 127 | // Ports |
| 128 | // ---------------------------------------------------------------------------- |
| 129 | input clk; |
| 130 | input por_l; |
| 131 | input rst_l; |
| 132 | |
| 133 | input [`FIRE_J2D_INSTANCE_ID_BITS] j2d_instance_id; |
| 134 | input [`FIRE_CSR_ADDR_BITS] cr2mm_csrbus_addr; |
| 135 | input [`FIRE_CSR_SRCB_BITS] cr2mm_csrbus_src_bus; |
| 136 | input cr2mm_csrbus_valid; |
| 137 | input cr2mm_csrbus_wr; |
| 138 | input [`FIRE_CSR_DATA_BITS] cr2mm_csrbus_wr_data; |
| 139 | input [`FIRE_DLC_DBG_SEL_BITS] cr2mm_dbg_sel_a; |
| 140 | input [`FIRE_DLC_DBG_SEL_BITS] cr2mm_dbg_sel_b; |
| 141 | input [`FIRE_DBG_DATA_BITS] crb2csr_dbg_a; |
| 142 | input [`FIRE_DBG_DATA_BITS] crb2csr_dbg_b; |
| 143 | input [`FIRE_DLC_MMU_VTC_BITS] crb2csr_rd; |
| 144 | input [`FIRE_CSR_DATA_BITS] ptb2csr_rd; |
| 145 | input [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a; |
| 146 | input [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_b; |
| 147 | input qcb2csr_paq; |
| 148 | input qcb2csr_vaq; |
| 149 | input [`FIRE_DBG_DATA_BITS] tcb2csr_dbg_a; |
| 150 | input [`FIRE_DBG_DATA_BITS] tcb2csr_dbg_b; |
| 151 | input [`FIRE_DLC_MMU_CSR_ERR_BITS] tcb2csr_err; |
| 152 | input [`FIRE_DLC_MMU_TCB_PRF_BITS] tcb2csr_prf; |
| 153 | input [`FIRE_DLC_MMU_CSR_CM_BITS] tcb2csr_tcm; |
| 154 | input tcb2csr_tip; |
| 155 | input tcb2csr_tpl; |
| 156 | input [`FIRE_DLC_MMU_TDR_BITS] tdb2csr_rd; |
| 157 | input [`FIRE_DLC_MMU_VA_ADDR_BITS] tlb2csr_addr; |
| 158 | input [`FIRE_DLC_MMU_TDB_PTR_BITS] tlb2csr_dbra; |
| 159 | input [`FIRE_DLC_MMU_VA_RQID_BITS] tlb2csr_rqid; |
| 160 | input [`FIRE_DLC_MMU_VA_TYPE_BITS] tlb2csr_type; |
| 161 | input vtb2csr_prf; |
| 162 | input [`FIRE_DLC_MMU_VTR_BITS] vtb2csr_rd; |
| 163 | input [`FIRE_CSR_DATA_BITS] dev_iotsb2csr_rd; |
| 164 | input dev_iotsb_ext_done; |
| 165 | |
| 166 | |
| 167 | output mm2cr_csrbus_acc_vio; |
| 168 | output mm2cr_csrbus_done; |
| 169 | output mm2cr_csrbus_mapped; |
| 170 | output [`FIRE_CSR_DATA_BITS] mm2cr_csrbus_read_data; |
| 171 | output [`FIRE_DBG_DATA_BITS] mm2cr_dbg_a; |
| 172 | output [`FIRE_DBG_DATA_BITS] mm2cr_dbg_b; |
| 173 | output mm2im_int; |
| 174 | output [`FIRE_DLC_MMU_CSR_DS_BITS] csr2crb_ds_a; |
| 175 | output [`FIRE_DLC_MMU_CSR_DS_BITS] csr2crb_ds_b; |
| 176 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2crb_ra; |
| 177 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2crb_wa; |
| 178 | output [`FIRE_DLC_MMU_VTC_BITS] csr2crb_wd; |
| 179 | output csr2crb_we; |
| 180 | output csr2pab_ps; |
| 181 | output csr2ptb_inv; |
| 182 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2ptb_ra; |
| 183 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2ptb_wa; |
| 184 | output [`FIRE_CSR_DATA_BITS] csr2ptb_wd; |
| 185 | output csr2ptb_we; |
| 186 | output [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_a; |
| 187 | output [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_b; |
| 188 | output csr2rcb_se; |
| 189 | // output [`FIRE_DLC_MMU_CSR_TB_BITS] csr2rcb_tb; |
| 190 | // output [`FIRE_DLC_MMU_CSR_TS_BITS] csr2rcb_ts; |
| 191 | output csr2tcb_av; |
| 192 | output csr2tcb_be; |
| 193 | output [`FIRE_DLC_MMU_CSR_CM_BITS] csr2tcb_cm; |
| 194 | output [`FIRE_DLC_MMU_CSR_DS_BITS] csr2tcb_ds_a; |
| 195 | output [`FIRE_DLC_MMU_CSR_DS_BITS] csr2tcb_ds_b; |
| 196 | output csr2tcb_pd; |
| 197 | output csr2tcb_te; |
| 198 | output [`FIRE_DLC_MMU_TDB_PTR_BITS] csr2tdb_ra; |
| 199 | output [`FIRE_DLC_MMU_TDB_PTR_BITS] csr2tdb_wa; |
| 200 | output [`FIRE_DLC_MMU_TDR_BITS] csr2tdb_wd; |
| 201 | output csr2tdb_we; |
| 202 | output csr2tlb_ps; |
| 203 | output [`FIRE_DLC_MMU_CSR_TB_BITS] csr2tlb_tb; |
| 204 | output [`FIRE_DLC_MMU_CSR_TS_BITS] csr2tlb_ts; |
| 205 | output csr2vab_ps; |
| 206 | output [`FIRE_DLC_MMU_CSR_TS_BITS] csr2vab_ts; |
| 207 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2vtb_ra; |
| 208 | output [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2vtb_wa; |
| 209 | output [`FIRE_DLC_MMU_VTR_BITS] csr2vtb_wd; |
| 210 | output csr2vtb_we; |
| 211 | output [`FIRE_CSR_DATA_BITS] csr2dev_iotsb_wd; |
| 212 | output csr2dev2iotsb_we; |
| 213 | output csr2dev2iotsb_re; |
| 214 | output csr2IotsbDesc_we; |
| 215 | output csr2IotsbDesc_re; |
| 216 | output [4:0] csr2dev_iotsb_rwa; |
| 217 | output ctl_busid_sel_hw_read; |
| 218 | output ctl_sun4v_en_hw_read; |
| 219 | |
| 220 | |
| 221 | |
| 222 | // ---------------------------------------------------------------------------- |
| 223 | // Variables |
| 224 | // ---------------------------------------------------------------------------- |
| 225 | wire mm2cr_csrbus_acc_vio; |
| 226 | wire mm2cr_csrbus_done; |
| 227 | wire mm2cr_csrbus_mapped; |
| 228 | wire [`FIRE_CSR_DATA_BITS] mm2cr_csrbus_read_data; |
| 229 | wire [`FIRE_DBG_DATA_BITS] mm2cr_dbg_a; |
| 230 | wire [`FIRE_DBG_DATA_BITS] mm2cr_dbg_b; |
| 231 | wire mm2im_int; |
| 232 | wire [`FIRE_DLC_MMU_CSR_DS_BITS] csr2crb_ds_a; |
| 233 | wire [`FIRE_DLC_MMU_CSR_DS_BITS] csr2crb_ds_b; |
| 234 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2crb_ra; |
| 235 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2crb_wa; |
| 236 | wire [`FIRE_DLC_MMU_VTC_BITS] csr2crb_wd; |
| 237 | wire csr2crb_we; |
| 238 | wire csr2pab_ps; |
| 239 | wire csr2ptb_inv; |
| 240 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2ptb_ra; |
| 241 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2ptb_wa; |
| 242 | wire [`FIRE_CSR_DATA_BITS] csr2ptb_wd; |
| 243 | wire csr2ptb_we; |
| 244 | wire csr2rcb_se; |
| 245 | // wire [`FIRE_DLC_MMU_CSR_TB_BITS] csr2rcb_tb; |
| 246 | // wire [`FIRE_DLC_MMU_CSR_TS_BITS] csr2rcb_ts; |
| 247 | wire csr2tcb_be; |
| 248 | wire [`FIRE_DLC_MMU_CSR_CM_BITS] csr2tcb_cm; |
| 249 | wire [`FIRE_DLC_MMU_CSR_DS_BITS] csr2tcb_ds_a; |
| 250 | wire [`FIRE_DLC_MMU_CSR_DS_BITS] csr2tcb_ds_b; |
| 251 | wire csr2tcb_pd; |
| 252 | wire csr2tcb_te; |
| 253 | wire [`FIRE_DLC_MMU_TDB_PTR_BITS] csr2tdb_ra; |
| 254 | wire [`FIRE_DLC_MMU_TDB_PTR_BITS] csr2tdb_wa; |
| 255 | wire [`FIRE_DLC_MMU_TDR_BITS] csr2tdb_wd; |
| 256 | wire csr2tdb_we; |
| 257 | wire csr2tlb_ps; |
| 258 | wire [`FIRE_DLC_MMU_CSR_TB_BITS] csr2tlb_tb; |
| 259 | wire [`FIRE_DLC_MMU_CSR_TS_BITS] csr2tlb_ts; |
| 260 | wire csr2vab_ps; |
| 261 | wire [`FIRE_DLC_MMU_CSR_TS_BITS] csr2vab_ts; |
| 262 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2vtb_ra; |
| 263 | wire [`FIRE_DLC_MMU_TAG_PTR_BITS] csr2vtb_wa; |
| 264 | wire [`FIRE_DLC_MMU_VTR_BITS] csr2vtb_wd; |
| 265 | wire csr2vtb_we; |
| 266 | |
| 267 | wire [`FIRE_DLC_MMU_TDB_PTR_BITS] ext_addr; |
| 268 | wire ext_wr; |
| 269 | wire [`FIRE_CSR_DATA_BITS] ext_wr_data; |
| 270 | wire [3:0] ctl_spares_hw_write; |
| 271 | wire ctl_paq_hw_write; |
| 272 | wire ctl_vaq_hw_write; |
| 273 | wire ctl_tpl_hw_write; |
| 274 | wire ctl_tip_hw_write; |
| 275 | wire [`FIRE_DLC_MMU_CSR_CM_BITS] ctl_tcm_hw_write; |
| 276 | wire [3:0] ctl_sparec_hw_read; |
| 277 | wire ctl_pd_hw_read; |
| 278 | wire ctl_se_hw_read; |
| 279 | wire [`FIRE_DLC_MMU_CSR_CM_BITS] ctl_cm_hw_read; |
| 280 | wire ctl_be_hw_read; |
| 281 | wire ctl_te_hw_read; |
| 282 | wire [`FIRE_DLC_MMU_CSR_TB_BITS] tsb_tb_hw_read; |
| 283 | wire tsb_ps_hw_read; |
| 284 | wire [`FIRE_DLC_MMU_CSR_TS_BITS] tsb_ts_hw_read; |
| 285 | wire inv_ext_select; |
| 286 | wire [`FIRE_DLC_MMU_CSR_ERR_BITS] log_en_hw_read; |
| 287 | wire [`FIRE_CSR_DATA_BITS] int_en_hw_read; |
| 288 | wire [`FIRE_CSR_DATA_BITS] err_hw_read; |
| 289 | wire [`FIRE_PRF_ADDR_BITS] prfc_sel1_hw_read, prfc_sel0_hw_read; |
| 290 | wire [`FIRE_PRF_DATA_BITS] prf0_cnt_hw_read, prf1_cnt_hw_read; |
| 291 | wire vtb_ext_select; |
| 292 | wire ptb_ext_select; |
| 293 | wire tdb_ext_select; |
| 294 | wire vtb_hw_acc_jtag_rd; |
| 295 | wire vtb_hw_acc_jtag_wr; |
| 296 | wire vtb_hw_acc_pio_slow_rd; |
| 297 | wire vtb_hw_acc_pio_slow_wr; |
| 298 | wire vtb_hw_acc_pio_med_rd; |
| 299 | wire vtb_hw_acc_pio_med_wr; |
| 300 | wire vtb_hw_acc_pio_fast_rd; |
| 301 | wire vtb_hw_acc_pio_fast_wr; |
| 302 | wire ptb_hw_acc_jtag_rd; |
| 303 | wire ptb_hw_acc_jtag_wr; |
| 304 | wire ptb_hw_acc_pio_slow_rd; |
| 305 | wire ptb_hw_acc_pio_slow_wr; |
| 306 | wire ptb_hw_acc_pio_med_rd; |
| 307 | wire ptb_hw_acc_pio_med_wr; |
| 308 | wire ptb_hw_acc_pio_fast_rd; |
| 309 | wire ptb_hw_acc_pio_fast_wr; |
| 310 | wire tdb_hw_acc_jtag_rd; |
| 311 | wire tdb_hw_acc_jtag_wr; |
| 312 | wire tdb_hw_acc_pio_slow_rd; |
| 313 | wire tdb_hw_acc_pio_slow_wr; |
| 314 | wire tdb_hw_acc_pio_med_rd; |
| 315 | wire tdb_hw_acc_pio_med_wr; |
| 316 | wire tdb_hw_acc_pio_fast_rd; |
| 317 | wire tdb_hw_acc_pio_fast_wr; |
| 318 | wire [`FIRE_DLC_MMU_CSR_ERR_BITS] en_err_err_s_ext_read_data; |
| 319 | wire [`FIRE_DLC_MMU_CSR_ERR_BITS] en_err_err_p_ext_read_data; |
| 320 | wire [`FIRE_CSR_DATA_BITS] err_hw_set; |
| 321 | wire flta_va_hw_ld; |
| 322 | wire [`FIRE_DLC_MMU_VA_ADDR_BITS] flta_va_hw_write; |
| 323 | wire flts_entry_hw_ld; |
| 324 | wire [`FIRE_DLC_MMU_TDB_PTR_BITS] flts_entry_hw_write; |
| 325 | wire flts_type_hw_ld; |
| 326 | wire [`FIRE_DLC_MMU_VA_TYPE_BITS] flts_type_hw_write; |
| 327 | wire flts_id_hw_ld; |
| 328 | wire [`FIRE_DLC_MMU_VA_RQID_BITS] flts_id_hw_write; |
| 329 | wire [`FIRE_PRF_DATA_BITS] prf0_cnt_hw_write, prf1_cnt_hw_write; |
| 330 | wire [`FIRE_CSR_DATA_BITS] vtb_ext_read_data; |
| 331 | wire [`FIRE_CSR_DATA_BITS] ptb_ext_read_data; |
| 332 | wire [`FIRE_CSR_DATA_BITS] tdb_ext_read_data; |
| 333 | wire ctl_busid_sel_hw_read,ctl_sun4v_en_hw_read; |
| 334 | wire [`FIRE_CSR_DATA_BITS] dev_iotsb_ext_read_data; |
| 335 | wire IotsbDesc_ext_select; |
| 336 | wire IotsbDesc_hw_acc_jtag_rd; |
| 337 | wire IotsbDesc_hw_acc_jtag_wr; |
| 338 | wire IotsbDesc_hw_acc_pio_slow_rd; |
| 339 | wire IotsbDesc_hw_acc_pio_slow_wr; |
| 340 | wire IotsbDesc_hw_acc_pio_med_rd; |
| 341 | wire IotsbDesc_hw_acc_pio_med_wr; |
| 342 | wire IotsbDesc_hw_acc_pio_fast_rd; |
| 343 | wire IotsbDesc_hw_acc_pio_fast_wr; |
| 344 | wire dev2iotsb_hw_acc_jtag_rd; |
| 345 | wire dev2iotsb_hw_acc_jtag_wr; |
| 346 | wire dev2iotsb_hw_acc_pio_slow_rd; |
| 347 | wire dev2iotsb_hw_acc_pio_slow_wr; |
| 348 | wire dev2iotsb_hw_acc_pio_med_rd; |
| 349 | wire dev2iotsb_hw_acc_pio_med_wr; |
| 350 | wire dev2iotsb_hw_acc_pio_fast_rd; |
| 351 | wire dev2iotsb_hw_acc_pio_fast_wr; |
| 352 | wire dev2iotsb_ext_select; |
| 353 | |
| 354 | // ---------------------------------------------------------------------------- |
| 355 | // Instantiaions |
| 356 | // ---------------------------------------------------------------------------- |
| 357 | |
| 358 | dmu_mmu_csr_csr csr |
| 359 | ( |
| 360 | .clk (clk), |
| 361 | .csrbus_valid (cr2mm_csrbus_valid), |
| 362 | .csrbus_done (mm2cr_csrbus_done), |
| 363 | .csrbus_mapped (mm2cr_csrbus_mapped), |
| 364 | .csrbus_wr_data (cr2mm_csrbus_wr_data), |
| 365 | .csrbus_wr (cr2mm_csrbus_wr), |
| 366 | .csrbus_read_data (mm2cr_csrbus_read_data), |
| 367 | .csrbus_addr (cr2mm_csrbus_addr), |
| 368 | .rst_l (rst_l), |
| 369 | .por_l (por_l), |
| 370 | .csrbus_src_bus (cr2mm_csrbus_src_bus), |
| 371 | .csrbus_acc_vio (mm2cr_csrbus_acc_vio), |
| 372 | .instance_id (j2d_instance_id), |
| 373 | .ext_addr (ext_addr), |
| 374 | .ext_wr (ext_wr), |
| 375 | .ext_wr_data (ext_wr_data), |
| 376 | .ctl_spares_hw_write (ctl_spares_hw_write), |
| 377 | .ctl_paq_hw_write (ctl_paq_hw_write), |
| 378 | .ctl_vaq_hw_write (ctl_vaq_hw_write), |
| 379 | .ctl_tpl_hw_write (ctl_tpl_hw_write), |
| 380 | .ctl_tip_hw_write (ctl_tip_hw_write), |
| 381 | .ctl_tcm_hw_write (ctl_tcm_hw_write), |
| 382 | .ctl_sparec_hw_read (ctl_sparec_hw_read), |
| 383 | .ctl_pd_hw_read (ctl_pd_hw_read), |
| 384 | .ctl_se_hw_read (ctl_se_hw_read), |
| 385 | .ctl_cm_hw_read (ctl_cm_hw_read), |
| 386 | .ctl_busid_sel_hw_read (ctl_busid_sel_hw_read), |
| 387 | .ctl_sun4v_en_hw_read (ctl_sun4v_en_hw_read), |
| 388 | .ctl_be_hw_read (ctl_be_hw_read), |
| 389 | .ctl_te_hw_read (ctl_te_hw_read), |
| 390 | .tsb_tb_hw_read (tsb_tb_hw_read), |
| 391 | .tsb_ps_hw_read (tsb_ps_hw_read), |
| 392 | .tsb_ts_hw_read (tsb_ts_hw_read), |
| 393 | .inv_ext_select (inv_ext_select), |
| 394 | .log_en_hw_read (log_en_hw_read), |
| 395 | .int_en_hw_read (int_en_hw_read), |
| 396 | .en_err_err_s_ext_read_data (en_err_err_s_ext_read_data), |
| 397 | .en_err_err_p_ext_read_data (en_err_err_p_ext_read_data), |
| 398 | .err_hw_set (err_hw_set), |
| 399 | .err_hw_read (err_hw_read), |
| 400 | .flta_va_hw_ld (flta_va_hw_ld), |
| 401 | .flta_va_hw_write (flta_va_hw_write), |
| 402 | .flts_entry_hw_ld (flts_entry_hw_ld), |
| 403 | .flts_entry_hw_write (flts_entry_hw_write), |
| 404 | .flts_type_hw_ld (flts_type_hw_ld), |
| 405 | .flts_type_hw_write (flts_type_hw_write), |
| 406 | .flts_id_hw_ld (flts_id_hw_ld), |
| 407 | .flts_id_hw_write (flts_id_hw_write), |
| 408 | .prfc_sel1_hw_read (prfc_sel1_hw_read), |
| 409 | .prfc_sel0_hw_read (prfc_sel0_hw_read), |
| 410 | .prf0_cnt_hw_write (prf0_cnt_hw_write), |
| 411 | .prf0_cnt_hw_read (prf0_cnt_hw_read), |
| 412 | .prf1_cnt_hw_write (prf1_cnt_hw_write), |
| 413 | .prf1_cnt_hw_read (prf1_cnt_hw_read), |
| 414 | .vtb_hw_acc_jtag_rd (vtb_hw_acc_jtag_rd), |
| 415 | .vtb_hw_acc_jtag_wr (vtb_hw_acc_jtag_wr), |
| 416 | .vtb_hw_acc_pio_slow_rd (vtb_hw_acc_pio_slow_rd), |
| 417 | .vtb_hw_acc_pio_slow_wr (vtb_hw_acc_pio_slow_wr), |
| 418 | .vtb_hw_acc_pio_med_rd (vtb_hw_acc_pio_med_rd), |
| 419 | .vtb_hw_acc_pio_med_wr (vtb_hw_acc_pio_med_wr), |
| 420 | .vtb_hw_acc_pio_fast_rd (vtb_hw_acc_pio_fast_rd), |
| 421 | .vtb_hw_acc_pio_fast_wr (vtb_hw_acc_pio_fast_wr), |
| 422 | .vtb_ext_select (vtb_ext_select), |
| 423 | .vtb_ext_read_data (vtb_ext_read_data), |
| 424 | .ptb_hw_acc_jtag_rd (ptb_hw_acc_jtag_rd), |
| 425 | .ptb_hw_acc_jtag_wr (ptb_hw_acc_jtag_wr), |
| 426 | .ptb_hw_acc_pio_slow_rd (ptb_hw_acc_pio_slow_rd), |
| 427 | .ptb_hw_acc_pio_slow_wr (ptb_hw_acc_pio_slow_wr), |
| 428 | .ptb_hw_acc_pio_med_rd (ptb_hw_acc_pio_med_rd), |
| 429 | .ptb_hw_acc_pio_med_wr (ptb_hw_acc_pio_med_wr), |
| 430 | .ptb_hw_acc_pio_fast_rd (ptb_hw_acc_pio_fast_rd), |
| 431 | .ptb_hw_acc_pio_fast_wr (ptb_hw_acc_pio_fast_wr), |
| 432 | .ptb_ext_select (ptb_ext_select), |
| 433 | .ptb_ext_read_data (ptb_ext_read_data), |
| 434 | .tdb_hw_acc_jtag_rd (tdb_hw_acc_jtag_rd), |
| 435 | .tdb_hw_acc_jtag_wr (tdb_hw_acc_jtag_wr), |
| 436 | .tdb_hw_acc_pio_slow_rd (tdb_hw_acc_pio_slow_rd), |
| 437 | .tdb_hw_acc_pio_slow_wr (tdb_hw_acc_pio_slow_wr), |
| 438 | .tdb_hw_acc_pio_med_rd (tdb_hw_acc_pio_med_rd), |
| 439 | .tdb_hw_acc_pio_med_wr (tdb_hw_acc_pio_med_wr), |
| 440 | .tdb_hw_acc_pio_fast_rd (tdb_hw_acc_pio_fast_rd), |
| 441 | .tdb_hw_acc_pio_fast_wr (tdb_hw_acc_pio_fast_wr), |
| 442 | .tdb_ext_select (tdb_ext_select), |
| 443 | .tdb_ext_read_data (tdb_ext_read_data), |
| 444 | .dev2iotsb_hw_acc_jtag_rd (dev2iotsb_hw_acc_jtag_rd), |
| 445 | .dev2iotsb_hw_acc_jtag_wr (dev2iotsb_hw_acc_jtag_wr), |
| 446 | .dev2iotsb_hw_acc_pio_slow_rd (dev2iotsb_hw_acc_pio_slow_rd), |
| 447 | .dev2iotsb_hw_acc_pio_slow_wr (dev2iotsb_hw_acc_pio_slow_wr), |
| 448 | .dev2iotsb_hw_acc_pio_med_rd (dev2iotsb_hw_acc_pio_med_rd), |
| 449 | .dev2iotsb_hw_acc_pio_med_wr (dev2iotsb_hw_acc_pio_med_wr), |
| 450 | .dev2iotsb_hw_acc_pio_fast_rd (dev2iotsb_hw_acc_pio_fast_rd), |
| 451 | .dev2iotsb_hw_acc_pio_fast_wr (dev2iotsb_hw_acc_pio_fast_wr), |
| 452 | .dev2iotsb_ext_select (dev2iotsb_ext_select), |
| 453 | .dev2iotsb_ext_read_data (dev_iotsb_ext_read_data), |
| 454 | .dev2iotsb_ext_done (dev_iotsb_ext_done), |
| 455 | .IotsbDesc_hw_acc_jtag_rd (IotsbDesc_hw_acc_jtag_rd), |
| 456 | .IotsbDesc_hw_acc_jtag_wr (IotsbDesc_hw_acc_jtag_wr), |
| 457 | .IotsbDesc_hw_acc_pio_slow_rd (IotsbDesc_hw_acc_pio_slow_rd), |
| 458 | .IotsbDesc_hw_acc_pio_slow_wr (IotsbDesc_hw_acc_pio_slow_wr), |
| 459 | .IotsbDesc_hw_acc_pio_med_rd (IotsbDesc_hw_acc_pio_med_rd), |
| 460 | .IotsbDesc_hw_acc_pio_med_wr (IotsbDesc_hw_acc_pio_med_wr), |
| 461 | .IotsbDesc_hw_acc_pio_fast_rd (IotsbDesc_hw_acc_pio_fast_rd), |
| 462 | .IotsbDesc_hw_acc_pio_fast_wr (IotsbDesc_hw_acc_pio_fast_wr), |
| 463 | .IotsbDesc_ext_select (IotsbDesc_ext_select), |
| 464 | .IotsbDesc_ext_read_data (dev_iotsb_ext_read_data), |
| 465 | .IotsbDesc_ext_done (dev_iotsb_ext_done) |
| 466 | ); |
| 467 | |
| 468 | dmu_mmu_csr_cim cim |
| 469 | ( |
| 470 | .clk (clk), |
| 471 | .rst_l (rst_l), |
| 472 | .cr2mm_dbg_sel_a (cr2mm_dbg_sel_a), |
| 473 | .cr2mm_dbg_sel_b (cr2mm_dbg_sel_b), |
| 474 | .crb2csr_dbg_a (crb2csr_dbg_a), |
| 475 | .crb2csr_dbg_b (crb2csr_dbg_b), |
| 476 | .crb2csr_rd (crb2csr_rd), |
| 477 | .ptb2csr_rd (ptb2csr_rd), |
| 478 | .qcb2csr_dbg_a (qcb2csr_dbg_a), |
| 479 | .qcb2csr_dbg_b (qcb2csr_dbg_b), |
| 480 | .qcb2csr_paq (qcb2csr_paq), |
| 481 | .qcb2csr_vaq (qcb2csr_vaq), |
| 482 | .tcb2csr_dbg_a (tcb2csr_dbg_a), |
| 483 | .tcb2csr_dbg_b (tcb2csr_dbg_b), |
| 484 | .tcb2csr_err (tcb2csr_err), |
| 485 | .tcb2csr_prf (tcb2csr_prf), |
| 486 | .tcb2csr_tcm (tcb2csr_tcm), |
| 487 | .tcb2csr_tip (tcb2csr_tip), |
| 488 | .tcb2csr_tpl (tcb2csr_tpl), |
| 489 | .tdb2csr_rd (tdb2csr_rd), |
| 490 | .tlb2csr_addr (tlb2csr_addr), |
| 491 | .tlb2csr_dbra (tlb2csr_dbra), |
| 492 | .tlb2csr_rqid (tlb2csr_rqid), |
| 493 | .tlb2csr_type (tlb2csr_type), |
| 494 | .vtb2csr_prf (vtb2csr_prf), |
| 495 | .vtb2csr_rd (vtb2csr_rd), |
| 496 | .csrbus_acc_vio (mm2cr_csrbus_acc_vio), |
| 497 | .ext_addr (ext_addr), |
| 498 | .ext_wr (ext_wr), |
| 499 | .ext_wr_data (ext_wr_data), |
| 500 | .ctl_sparec_hw_read (ctl_sparec_hw_read), |
| 501 | .ctl_pd_hw_read (ctl_pd_hw_read), |
| 502 | .ctl_se_hw_read (ctl_se_hw_read), |
| 503 | .ctl_cm_hw_read (ctl_cm_hw_read), |
| 504 | .ctl_be_hw_read (ctl_be_hw_read), |
| 505 | .ctl_te_hw_read (ctl_te_hw_read), |
| 506 | .tsb_tb_hw_read (tsb_tb_hw_read), |
| 507 | .tsb_ps_hw_read (tsb_ps_hw_read), |
| 508 | .tsb_ts_hw_read (tsb_ts_hw_read), |
| 509 | .int_en_hw_read (int_en_hw_read), |
| 510 | .log_en_hw_read (log_en_hw_read), |
| 511 | .err_hw_read (err_hw_read), |
| 512 | .prfc_sel1_hw_read (prfc_sel1_hw_read), |
| 513 | .prfc_sel0_hw_read (prfc_sel0_hw_read), |
| 514 | .prf0_cnt_hw_read (prf0_cnt_hw_read), |
| 515 | .prf1_cnt_hw_read (prf1_cnt_hw_read), |
| 516 | .inv_ext_select (inv_ext_select), |
| 517 | .vtb_ext_select (vtb_ext_select), |
| 518 | .ptb_ext_select (ptb_ext_select), |
| 519 | .tdb_ext_select (tdb_ext_select), |
| 520 | .mm2cr_dbg_a (mm2cr_dbg_a), |
| 521 | .mm2cr_dbg_b (mm2cr_dbg_b), |
| 522 | .mm2im_int (mm2im_int), |
| 523 | .csr2crb_ds_a (csr2crb_ds_a), |
| 524 | .csr2crb_ds_b (csr2crb_ds_b), |
| 525 | .csr2crb_ra (csr2crb_ra), |
| 526 | .csr2crb_wa (csr2crb_wa), |
| 527 | .csr2crb_wd (csr2crb_wd), |
| 528 | .csr2crb_we (csr2crb_we), |
| 529 | .csr2pab_ps (csr2pab_ps), |
| 530 | .csr2ptb_inv (csr2ptb_inv), |
| 531 | .csr2ptb_ra (csr2ptb_ra), |
| 532 | .csr2ptb_wa (csr2ptb_wa), |
| 533 | .csr2ptb_wd (csr2ptb_wd), |
| 534 | .csr2ptb_we (csr2ptb_we), |
| 535 | .csr2qcb_ds_a (csr2qcb_ds_a), |
| 536 | .csr2qcb_ds_b (csr2qcb_ds_b), |
| 537 | .csr2rcb_se (csr2rcb_se), |
| 538 | // .csr2rcb_tb (csr2rcb_tb), |
| 539 | // .csr2rcb_ts (csr2rcb_ts), |
| 540 | .csr2tcb_av (csr2tcb_av), |
| 541 | .csr2tcb_be (csr2tcb_be), |
| 542 | .csr2tcb_cm (csr2tcb_cm), |
| 543 | .csr2tcb_ds_a (csr2tcb_ds_a), |
| 544 | .csr2tcb_ds_b (csr2tcb_ds_b), |
| 545 | .csr2tcb_pd (csr2tcb_pd), |
| 546 | .csr2tcb_te (csr2tcb_te), |
| 547 | .csr2tdb_ra (csr2tdb_ra), |
| 548 | .csr2tdb_wa (csr2tdb_wa), |
| 549 | .csr2tdb_wd (csr2tdb_wd), |
| 550 | .csr2tdb_we (csr2tdb_we), |
| 551 | .csr2tlb_ps (csr2tlb_ps), |
| 552 | .csr2tlb_tb (csr2tlb_tb), |
| 553 | .csr2tlb_ts (csr2tlb_ts), |
| 554 | .csr2vab_ps (csr2vab_ps), |
| 555 | .csr2vab_ts (csr2vab_ts), |
| 556 | .csr2vtb_ra (csr2vtb_ra), |
| 557 | .csr2vtb_wa (csr2vtb_wa), |
| 558 | .csr2vtb_wd (csr2vtb_wd), |
| 559 | .csr2vtb_we (csr2vtb_we), |
| 560 | .ctl_spares_hw_write (ctl_spares_hw_write), |
| 561 | .ctl_paq_hw_write (ctl_paq_hw_write), |
| 562 | .ctl_vaq_hw_write (ctl_vaq_hw_write), |
| 563 | .ctl_tpl_hw_write (ctl_tpl_hw_write), |
| 564 | .ctl_tip_hw_write (ctl_tip_hw_write), |
| 565 | .ctl_tcm_hw_write (ctl_tcm_hw_write), |
| 566 | .en_err_err_s_ext_read_data (en_err_err_s_ext_read_data), |
| 567 | .en_err_err_p_ext_read_data (en_err_err_p_ext_read_data), |
| 568 | .err_hw_set (err_hw_set), |
| 569 | .flta_va_hw_ld (flta_va_hw_ld), |
| 570 | .flta_va_hw_write (flta_va_hw_write), |
| 571 | .flts_entry_hw_ld (flts_entry_hw_ld), |
| 572 | .flts_entry_hw_write (flts_entry_hw_write), |
| 573 | .flts_type_hw_ld (flts_type_hw_ld), |
| 574 | .flts_type_hw_write (flts_type_hw_write), |
| 575 | .flts_id_hw_ld (flts_id_hw_ld), |
| 576 | .flts_id_hw_write (flts_id_hw_write), |
| 577 | .prf0_cnt_hw_write (prf0_cnt_hw_write), |
| 578 | .prf1_cnt_hw_write (prf1_cnt_hw_write), |
| 579 | .vtb_hw_acc_jtag_rd (vtb_hw_acc_jtag_rd), |
| 580 | .vtb_hw_acc_jtag_wr (vtb_hw_acc_jtag_wr), |
| 581 | .vtb_hw_acc_pio_slow_rd (vtb_hw_acc_pio_slow_rd), |
| 582 | .vtb_hw_acc_pio_slow_wr (vtb_hw_acc_pio_slow_wr), |
| 583 | .vtb_hw_acc_pio_med_rd (vtb_hw_acc_pio_med_rd), |
| 584 | .vtb_hw_acc_pio_med_wr (vtb_hw_acc_pio_med_wr), |
| 585 | .vtb_hw_acc_pio_fast_rd (vtb_hw_acc_pio_fast_rd), |
| 586 | .vtb_hw_acc_pio_fast_wr (vtb_hw_acc_pio_fast_wr), |
| 587 | .vtb_ext_read_data (vtb_ext_read_data), |
| 588 | .ptb_hw_acc_jtag_rd (ptb_hw_acc_jtag_rd), |
| 589 | .ptb_hw_acc_jtag_wr (ptb_hw_acc_jtag_wr), |
| 590 | .ptb_hw_acc_pio_slow_rd (ptb_hw_acc_pio_slow_rd), |
| 591 | .ptb_hw_acc_pio_slow_wr (ptb_hw_acc_pio_slow_wr), |
| 592 | .ptb_hw_acc_pio_med_rd (ptb_hw_acc_pio_med_rd), |
| 593 | .ptb_hw_acc_pio_med_wr (ptb_hw_acc_pio_med_wr), |
| 594 | .ptb_hw_acc_pio_fast_rd (ptb_hw_acc_pio_fast_rd), |
| 595 | .ptb_hw_acc_pio_fast_wr (ptb_hw_acc_pio_fast_wr), |
| 596 | .ptb_ext_read_data (ptb_ext_read_data), |
| 597 | .tdb_hw_acc_jtag_rd (tdb_hw_acc_jtag_rd), |
| 598 | .tdb_hw_acc_jtag_wr (tdb_hw_acc_jtag_wr), |
| 599 | .tdb_hw_acc_pio_slow_rd (tdb_hw_acc_pio_slow_rd), |
| 600 | .tdb_hw_acc_pio_slow_wr (tdb_hw_acc_pio_slow_wr), |
| 601 | .tdb_hw_acc_pio_med_rd (tdb_hw_acc_pio_med_rd), |
| 602 | .tdb_hw_acc_pio_med_wr (tdb_hw_acc_pio_med_wr), |
| 603 | .tdb_hw_acc_pio_fast_rd (tdb_hw_acc_pio_fast_rd), |
| 604 | .tdb_hw_acc_pio_fast_wr (tdb_hw_acc_pio_fast_wr), |
| 605 | .tdb_ext_read_data (tdb_ext_read_data), |
| 606 | .dev2iotsb_hw_acc_jtag_rd (dev2iotsb_hw_acc_jtag_rd), |
| 607 | .dev2iotsb_hw_acc_jtag_wr (dev2iotsb_hw_acc_jtag_wr), |
| 608 | .dev2iotsb_hw_acc_pio_slow_rd (dev2iotsb_hw_acc_pio_slow_rd), |
| 609 | .dev2iotsb_hw_acc_pio_slow_wr (dev2iotsb_hw_acc_pio_slow_wr), |
| 610 | .dev2iotsb_hw_acc_pio_med_rd (dev2iotsb_hw_acc_pio_med_rd), |
| 611 | .dev2iotsb_hw_acc_pio_med_wr (dev2iotsb_hw_acc_pio_med_wr), |
| 612 | .dev2iotsb_hw_acc_pio_fast_rd (dev2iotsb_hw_acc_pio_fast_rd), |
| 613 | .dev2iotsb_hw_acc_pio_fast_wr (dev2iotsb_hw_acc_pio_fast_wr), |
| 614 | .dev2iotsb_ext_select (dev2iotsb_ext_select), |
| 615 | .dev_iotsb_ext_read_data (dev_iotsb_ext_read_data), |
| 616 | .dev_iotsb2csr_rd (dev_iotsb2csr_rd), // read data from DEV RAM |
| 617 | .csr2dev_iotsb_rwa (csr2dev_iotsb_rwa), |
| 618 | .csr2dev_iotsb_wd (csr2dev_iotsb_wd), |
| 619 | .csr2dev2iotsb_we (csr2dev2iotsb_we), |
| 620 | .csr2dev2iotsb_re (csr2dev2iotsb_re), |
| 621 | .IotsbDesc_hw_acc_jtag_rd (IotsbDesc_hw_acc_jtag_rd), |
| 622 | .IotsbDesc_hw_acc_jtag_wr (IotsbDesc_hw_acc_jtag_wr), |
| 623 | .IotsbDesc_hw_acc_pio_slow_rd (IotsbDesc_hw_acc_pio_slow_rd), |
| 624 | .IotsbDesc_hw_acc_pio_slow_wr (IotsbDesc_hw_acc_pio_slow_wr), |
| 625 | .IotsbDesc_hw_acc_pio_med_rd (IotsbDesc_hw_acc_pio_med_rd), |
| 626 | .IotsbDesc_hw_acc_pio_med_wr (IotsbDesc_hw_acc_pio_med_wr), |
| 627 | .IotsbDesc_hw_acc_pio_fast_rd (IotsbDesc_hw_acc_pio_fast_rd), |
| 628 | .IotsbDesc_hw_acc_pio_fast_wr (IotsbDesc_hw_acc_pio_fast_wr), |
| 629 | .IotsbDesc_ext_select (IotsbDesc_ext_select), |
| 630 | .csr2IotsbDesc_we (csr2IotsbDesc_we), |
| 631 | .csr2IotsbDesc_re (csr2IotsbDesc_re) |
| 632 | ); |
| 633 | |
| 634 | endmodule // dmu_mmu_csr |