| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_stage_2_default_grp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_csr_stage_2_default_grp |
| 36 | ( |
| 37 | clk, |
| 38 | read_data_0, |
| 39 | read_data_1, |
| 40 | ext_done_0, |
| 41 | ctl_select_pulse, |
| 42 | ctl_select_pulse_out, |
| 43 | tsb_select_pulse, |
| 44 | tsb_select_pulse_out, |
| 45 | fsh_select_pulse, |
| 46 | fsh_select_pulse_out, |
| 47 | inv_select, |
| 48 | inv_select_out, |
| 49 | log_select_pulse, |
| 50 | log_select_pulse_out, |
| 51 | int_en_select_pulse, |
| 52 | int_en_select_pulse_out, |
| 53 | en_err_select, |
| 54 | en_err_select_out, |
| 55 | err_select_pulse, |
| 56 | err_select_pulse_out, |
| 57 | flta_select_pulse, |
| 58 | flta_select_pulse_out, |
| 59 | flts_select_pulse, |
| 60 | flts_select_pulse_out, |
| 61 | prfc_select_pulse, |
| 62 | prfc_select_pulse_out, |
| 63 | prf0_select_pulse, |
| 64 | prf0_select_pulse_out, |
| 65 | prf1_select_pulse, |
| 66 | prf1_select_pulse_out, |
| 67 | vtb_select, |
| 68 | vtb_select_out, |
| 69 | ptb_select, |
| 70 | ptb_select_out, |
| 71 | tdb_select, |
| 72 | tdb_select_out, |
| 73 | dev2iotsb_select, |
| 74 | dev2iotsb_select_out, |
| 75 | IotsbDesc_select, |
| 76 | IotsbDesc_select_out, |
| 77 | err_rw1c_alias, |
| 78 | err_rw1c_alias_out, |
| 79 | err_rw1s_alias, |
| 80 | err_rw1s_alias_out, |
| 81 | rst_l, |
| 82 | rst_l_out, |
| 83 | por_l, |
| 84 | por_l_out, |
| 85 | daemon_csrbus_wr_in, |
| 86 | daemon_csrbus_wr_out, |
| 87 | daemon_csrbus_wr_data_in, |
| 88 | daemon_csrbus_wr_data_out, |
| 89 | ext_addr_in, |
| 90 | ext_addr_out, |
| 91 | read_data_0_out, |
| 92 | ext_done_0_out |
| 93 | ); |
| 94 | |
| 95 | //==================================================== |
| 96 | // Polarity declarations |
| 97 | //==================================================== |
| 98 | input clk; // Clock signal |
| 99 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data |
| 100 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data |
| 101 | input ext_done_0; // Ext Done |
| 102 | input ctl_select_pulse; // select |
| 103 | output ctl_select_pulse_out; // select |
| 104 | input tsb_select_pulse; // select |
| 105 | output tsb_select_pulse_out; // select |
| 106 | input fsh_select_pulse; // select |
| 107 | output fsh_select_pulse_out; // select |
| 108 | input inv_select; // select |
| 109 | output inv_select_out; // select |
| 110 | input log_select_pulse; // select |
| 111 | output log_select_pulse_out; // select |
| 112 | input int_en_select_pulse; // select |
| 113 | output int_en_select_pulse_out; // select |
| 114 | input en_err_select; // select |
| 115 | output en_err_select_out; // select |
| 116 | input err_select_pulse; // select |
| 117 | output err_select_pulse_out; // select |
| 118 | input flta_select_pulse; // select |
| 119 | output flta_select_pulse_out; // select |
| 120 | input flts_select_pulse; // select |
| 121 | output flts_select_pulse_out; // select |
| 122 | input prfc_select_pulse; // select |
| 123 | output prfc_select_pulse_out; // select |
| 124 | input prf0_select_pulse; // select |
| 125 | output prf0_select_pulse_out; // select |
| 126 | input prf1_select_pulse; // select |
| 127 | output prf1_select_pulse_out; // select |
| 128 | input vtb_select; // select |
| 129 | output vtb_select_out; // select |
| 130 | input ptb_select; // select |
| 131 | output ptb_select_out; // select |
| 132 | input tdb_select; // select |
| 133 | output tdb_select_out; // select |
| 134 | input dev2iotsb_select; // select |
| 135 | output dev2iotsb_select_out; // select |
| 136 | input IotsbDesc_select; // select |
| 137 | output IotsbDesc_select_out; // select |
| 138 | input err_rw1c_alias; // SW load |
| 139 | output err_rw1c_alias_out; // alias |
| 140 | input err_rw1s_alias; // SW load |
| 141 | output err_rw1s_alias_out; // alias |
| 142 | input rst_l; // HW reset |
| 143 | output rst_l_out; // HW reset |
| 144 | input por_l; // HW reset |
| 145 | output por_l_out; // HW reset |
| 146 | input daemon_csrbus_wr_in; // csrbus_wr |
| 147 | output daemon_csrbus_wr_out; // csrbus_wr |
| 148 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 149 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write |
| 150 | // data |
| 151 | input [8:0] ext_addr_in; // Ext addr |
| 152 | output [8:0] ext_addr_out; // Ext addr |
| 153 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 154 | output ext_done_0_out; // Ext Done |
| 155 | |
| 156 | //==================================================== |
| 157 | // Type declarations |
| 158 | //==================================================== |
| 159 | wire clk; // Clock signal |
| 160 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data |
| 161 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data |
| 162 | wire ext_done_0; // Ext Done |
| 163 | wire ctl_select_pulse; // select |
| 164 | reg ctl_select_pulse_out; // select |
| 165 | wire tsb_select_pulse; // select |
| 166 | reg tsb_select_pulse_out; // select |
| 167 | wire fsh_select_pulse; // select |
| 168 | reg fsh_select_pulse_out; // select |
| 169 | wire inv_select; // select |
| 170 | reg inv_select_out; // select |
| 171 | wire log_select_pulse; // select |
| 172 | reg log_select_pulse_out; // select |
| 173 | wire int_en_select_pulse; // select |
| 174 | reg int_en_select_pulse_out; // select |
| 175 | wire en_err_select; // select |
| 176 | reg en_err_select_out; // select |
| 177 | wire err_select_pulse; // select |
| 178 | reg err_select_pulse_out; // select |
| 179 | wire flta_select_pulse; // select |
| 180 | reg flta_select_pulse_out; // select |
| 181 | wire flts_select_pulse; // select |
| 182 | reg flts_select_pulse_out; // select |
| 183 | wire prfc_select_pulse; // select |
| 184 | reg prfc_select_pulse_out; // select |
| 185 | wire prf0_select_pulse; // select |
| 186 | reg prf0_select_pulse_out; // select |
| 187 | wire prf1_select_pulse; // select |
| 188 | reg prf1_select_pulse_out; // select |
| 189 | wire vtb_select; // select |
| 190 | reg vtb_select_out; // select |
| 191 | wire ptb_select; // select |
| 192 | reg ptb_select_out; // select |
| 193 | wire tdb_select; // select |
| 194 | reg tdb_select_out; // select |
| 195 | wire dev2iotsb_select; // select |
| 196 | reg dev2iotsb_select_out; // select |
| 197 | wire IotsbDesc_select; // select |
| 198 | reg IotsbDesc_select_out; // select |
| 199 | wire err_rw1c_alias; // SW load |
| 200 | wire err_rw1c_alias_out; // alias |
| 201 | wire err_rw1s_alias; // SW load |
| 202 | wire err_rw1s_alias_out; // alias |
| 203 | wire rst_l; // HW reset |
| 204 | wire rst_l_out; // HW reset |
| 205 | wire por_l; // HW reset |
| 206 | wire por_l_out; // HW reset |
| 207 | wire daemon_csrbus_wr_in; // csrbus_wr |
| 208 | wire daemon_csrbus_wr_out; // csrbus_wr |
| 209 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 210 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data |
| 211 | wire [8:0] ext_addr_in; // Ext addr |
| 212 | wire [8:0] ext_addr_out; // Ext addr |
| 213 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 214 | reg ext_done_0_out; // Ext Done |
| 215 | |
| 216 | |
| 217 | //==================================================== |
| 218 | // Pipelining |
| 219 | //==================================================== |
| 220 | always @(posedge clk) |
| 221 | begin |
| 222 | ext_done_0_out <= |
| 223 | ext_done_0; |
| 224 | |
| 225 | ctl_select_pulse_out <= ctl_select_pulse; |
| 226 | tsb_select_pulse_out <= tsb_select_pulse; |
| 227 | fsh_select_pulse_out <= fsh_select_pulse; |
| 228 | inv_select_out <= inv_select; |
| 229 | log_select_pulse_out <= log_select_pulse; |
| 230 | int_en_select_pulse_out <= int_en_select_pulse; |
| 231 | en_err_select_out <= en_err_select; |
| 232 | err_select_pulse_out <= err_select_pulse; |
| 233 | flta_select_pulse_out <= flta_select_pulse; |
| 234 | flts_select_pulse_out <= flts_select_pulse; |
| 235 | prfc_select_pulse_out <= prfc_select_pulse; |
| 236 | prf0_select_pulse_out <= prf0_select_pulse; |
| 237 | prf1_select_pulse_out <= prf1_select_pulse; |
| 238 | vtb_select_out <= vtb_select; |
| 239 | ptb_select_out <= ptb_select; |
| 240 | tdb_select_out <= tdb_select; |
| 241 | dev2iotsb_select_out <= dev2iotsb_select; |
| 242 | IotsbDesc_select_out <= IotsbDesc_select; |
| 243 | end |
| 244 | |
| 245 | |
| 246 | //==================================================== |
| 247 | // Assignments only |
| 248 | //==================================================== |
| 249 | assign daemon_csrbus_wr_out = daemon_csrbus_wr_in; |
| 250 | assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in; |
| 251 | assign ext_addr_out = ext_addr_in; |
| 252 | assign err_rw1c_alias_out = err_rw1c_alias; |
| 253 | assign err_rw1s_alias_out = err_rw1s_alias; |
| 254 | assign rst_l_out = rst_l; |
| 255 | assign por_l_out = por_l; |
| 256 | |
| 257 | //===================================================== |
| 258 | // OUTPUT: read_data_out |
| 259 | //===================================================== |
| 260 | dmu_mmu_csr_csrpipe_15 dmu_mmu_csr_csrpipe_15_inst_1 |
| 261 | ( |
| 262 | .clk (clk), |
| 263 | .rst_l (rst_l), |
| 264 | .reg_in (1'b0), |
| 265 | .reg_out (1'b1), |
| 266 | .data0 (read_data_0), |
| 267 | .sel0 (1'b1), |
| 268 | .data1 (read_data_1), |
| 269 | .sel1 (1'b1), |
| 270 | .data2 (64'b0), |
| 271 | .sel2 (1'b1), |
| 272 | .data3 (64'b0), |
| 273 | .sel3 (1'b1), |
| 274 | .data4 (64'b0), |
| 275 | .sel4 (1'b1), |
| 276 | .data5 (64'b0), |
| 277 | .sel5 (1'b1), |
| 278 | .data6 (64'b0), |
| 279 | .sel6 (1'b1), |
| 280 | .data7 (64'b0), |
| 281 | .sel7 (1'b1), |
| 282 | .data8 (64'b0), |
| 283 | .sel8 (1'b1), |
| 284 | .data9 (64'b0), |
| 285 | .sel9 (1'b1), |
| 286 | .data10 (64'b0), |
| 287 | .sel10 (1'b1), |
| 288 | .data11 (64'b0), |
| 289 | .sel11 (1'b1), |
| 290 | .data12 (64'b0), |
| 291 | .sel12 (1'b1), |
| 292 | .data13 (64'b0), |
| 293 | .sel13 (1'b1), |
| 294 | .data14 (64'b0), |
| 295 | .sel14 (1'b1), |
| 296 | .out (read_data_0_out) |
| 297 | ); |
| 298 | |
| 299 | endmodule // dmu_mmu_csr_stage_2_default_grp |