| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_tsb_entry.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_csr_tsb_entry |
| 36 | ( |
| 37 | // synopsys translate_off |
| 38 | omni_ld, |
| 39 | omni_data, |
| 40 | // synopsys translate_on |
| 41 | clk, |
| 42 | rst_l, |
| 43 | w_ld, |
| 44 | csrbus_wr_data, |
| 45 | tsb_csrbus_read_data |
| 46 | ); |
| 47 | |
| 48 | //==================================================================== |
| 49 | // Polarity declarations |
| 50 | //==================================================================== |
| 51 | // synopsys translate_off |
| 52 | input omni_ld; // Omni load |
| 53 | // vlint flag_input_port_not_connected off |
| 54 | input [`FIRE_DLC_MMU_CSR_TSB_WIDTH - 1:0] omni_data; // Omni write data |
| 55 | // synopsys translate_on |
| 56 | // vlint flag_input_port_not_connected on |
| 57 | input clk; // Clock signal |
| 58 | input rst_l; // Reset signal |
| 59 | input w_ld; // SW load |
| 60 | // vlint flag_input_port_not_connected off |
| 61 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 62 | // vlint flag_input_port_not_connected on |
| 63 | output [`FIRE_DLC_MMU_CSR_TSB_WIDTH-1:0] tsb_csrbus_read_data; // SW read data |
| 64 | |
| 65 | //==================================================================== |
| 66 | // Type declarations |
| 67 | //==================================================================== |
| 68 | // synopsys translate_off |
| 69 | wire omni_ld; // Omni load |
| 70 | // vlint flag_dangling_net_within_module off |
| 71 | // vlint flag_net_has_no_load off |
| 72 | wire [`FIRE_DLC_MMU_CSR_TSB_WIDTH - 1:0] omni_data; // Omni write data |
| 73 | // synopsys translate_on |
| 74 | // vlint flag_dangling_net_within_module on |
| 75 | // vlint flag_net_has_no_load on |
| 76 | wire clk; // Clock signal |
| 77 | wire rst_l; // Reset signal |
| 78 | wire w_ld; // SW load |
| 79 | // vlint flag_dangling_net_within_module off |
| 80 | // vlint flag_net_has_no_load off |
| 81 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 82 | // vlint flag_dangling_net_within_module on |
| 83 | // vlint flag_net_has_no_load on |
| 84 | wire [`FIRE_DLC_MMU_CSR_TSB_WIDTH-1:0] tsb_csrbus_read_data; // SW read data |
| 85 | |
| 86 | //==================================================================== |
| 87 | // Logic |
| 88 | //==================================================================== |
| 89 | |
| 90 | //----- Reset values |
| 91 | // verilint 531 off |
| 92 | wire [25:0] reset_tb = 26'h0; |
| 93 | wire [0:0] reset_ps = 1'h0; |
| 94 | wire [3:0] reset_ts = 4'h0; |
| 95 | // verilint 531 on |
| 96 | |
| 97 | //----- Active high reset wires |
| 98 | wire rst_l_active_high = ~rst_l; |
| 99 | |
| 100 | //==================================================== |
| 101 | // Instantiation of flops |
| 102 | //==================================================== |
| 103 | |
| 104 | // bit 0 |
| 105 | csr_sw csr_sw_0 |
| 106 | ( |
| 107 | // synopsys translate_off |
| 108 | .omni_ld (omni_ld), |
| 109 | .omni_data (omni_data[0]), |
| 110 | .omni_rw_alias (1'b1), |
| 111 | .omni_rw1c_alias (1'b0), |
| 112 | .omni_rw1s_alias (1'b0), |
| 113 | // synopsys translate_on |
| 114 | .rst (rst_l_active_high), |
| 115 | .rst_val (reset_ts[0]), |
| 116 | .csr_ld (w_ld), |
| 117 | .csr_data (csrbus_wr_data[0]), |
| 118 | .rw_alias (1'b1), |
| 119 | .rw1c_alias (1'b0), |
| 120 | .rw1s_alias (1'b0), |
| 121 | .hw_ld (1'b0), |
| 122 | .hw_data (1'b0), |
| 123 | .cp (clk), |
| 124 | .q (tsb_csrbus_read_data[0]) |
| 125 | ); |
| 126 | |
| 127 | // bit 1 |
| 128 | csr_sw csr_sw_1 |
| 129 | ( |
| 130 | // synopsys translate_off |
| 131 | .omni_ld (omni_ld), |
| 132 | .omni_data (omni_data[1]), |
| 133 | .omni_rw_alias (1'b1), |
| 134 | .omni_rw1c_alias (1'b0), |
| 135 | .omni_rw1s_alias (1'b0), |
| 136 | // synopsys translate_on |
| 137 | .rst (rst_l_active_high), |
| 138 | .rst_val (reset_ts[1]), |
| 139 | .csr_ld (w_ld), |
| 140 | .csr_data (csrbus_wr_data[1]), |
| 141 | .rw_alias (1'b1), |
| 142 | .rw1c_alias (1'b0), |
| 143 | .rw1s_alias (1'b0), |
| 144 | .hw_ld (1'b0), |
| 145 | .hw_data (1'b0), |
| 146 | .cp (clk), |
| 147 | .q (tsb_csrbus_read_data[1]) |
| 148 | ); |
| 149 | |
| 150 | // bit 2 |
| 151 | csr_sw csr_sw_2 |
| 152 | ( |
| 153 | // synopsys translate_off |
| 154 | .omni_ld (omni_ld), |
| 155 | .omni_data (omni_data[2]), |
| 156 | .omni_rw_alias (1'b1), |
| 157 | .omni_rw1c_alias (1'b0), |
| 158 | .omni_rw1s_alias (1'b0), |
| 159 | // synopsys translate_on |
| 160 | .rst (rst_l_active_high), |
| 161 | .rst_val (reset_ts[2]), |
| 162 | .csr_ld (w_ld), |
| 163 | .csr_data (csrbus_wr_data[2]), |
| 164 | .rw_alias (1'b1), |
| 165 | .rw1c_alias (1'b0), |
| 166 | .rw1s_alias (1'b0), |
| 167 | .hw_ld (1'b0), |
| 168 | .hw_data (1'b0), |
| 169 | .cp (clk), |
| 170 | .q (tsb_csrbus_read_data[2]) |
| 171 | ); |
| 172 | |
| 173 | // bit 3 |
| 174 | csr_sw csr_sw_3 |
| 175 | ( |
| 176 | // synopsys translate_off |
| 177 | .omni_ld (omni_ld), |
| 178 | .omni_data (omni_data[3]), |
| 179 | .omni_rw_alias (1'b1), |
| 180 | .omni_rw1c_alias (1'b0), |
| 181 | .omni_rw1s_alias (1'b0), |
| 182 | // synopsys translate_on |
| 183 | .rst (rst_l_active_high), |
| 184 | .rst_val (reset_ts[3]), |
| 185 | .csr_ld (w_ld), |
| 186 | .csr_data (csrbus_wr_data[3]), |
| 187 | .rw_alias (1'b1), |
| 188 | .rw1c_alias (1'b0), |
| 189 | .rw1s_alias (1'b0), |
| 190 | .hw_ld (1'b0), |
| 191 | .hw_data (1'b0), |
| 192 | .cp (clk), |
| 193 | .q (tsb_csrbus_read_data[3]) |
| 194 | ); |
| 195 | |
| 196 | assign tsb_csrbus_read_data[4] = 1'b0; // bit 4 |
| 197 | assign tsb_csrbus_read_data[5] = 1'b0; // bit 5 |
| 198 | assign tsb_csrbus_read_data[6] = 1'b0; // bit 6 |
| 199 | assign tsb_csrbus_read_data[7] = 1'b0; // bit 7 |
| 200 | // bit 8 |
| 201 | csr_sw csr_sw_8 |
| 202 | ( |
| 203 | // synopsys translate_off |
| 204 | .omni_ld (omni_ld), |
| 205 | .omni_data (omni_data[8]), |
| 206 | .omni_rw_alias (1'b1), |
| 207 | .omni_rw1c_alias (1'b0), |
| 208 | .omni_rw1s_alias (1'b0), |
| 209 | // synopsys translate_on |
| 210 | .rst (rst_l_active_high), |
| 211 | .rst_val (reset_ps[0]), |
| 212 | .csr_ld (w_ld), |
| 213 | .csr_data (csrbus_wr_data[8]), |
| 214 | .rw_alias (1'b1), |
| 215 | .rw1c_alias (1'b0), |
| 216 | .rw1s_alias (1'b0), |
| 217 | .hw_ld (1'b0), |
| 218 | .hw_data (1'b0), |
| 219 | .cp (clk), |
| 220 | .q (tsb_csrbus_read_data[8]) |
| 221 | ); |
| 222 | |
| 223 | assign tsb_csrbus_read_data[9] = 1'b0; // bit 9 |
| 224 | assign tsb_csrbus_read_data[10] = 1'b0; // bit 10 |
| 225 | assign tsb_csrbus_read_data[11] = 1'b0; // bit 11 |
| 226 | assign tsb_csrbus_read_data[12] = 1'b0; // bit 12 |
| 227 | // bit 13 |
| 228 | csr_sw csr_sw_13 |
| 229 | ( |
| 230 | // synopsys translate_off |
| 231 | .omni_ld (omni_ld), |
| 232 | .omni_data (omni_data[13]), |
| 233 | .omni_rw_alias (1'b1), |
| 234 | .omni_rw1c_alias (1'b0), |
| 235 | .omni_rw1s_alias (1'b0), |
| 236 | // synopsys translate_on |
| 237 | .rst (rst_l_active_high), |
| 238 | .rst_val (reset_tb[0]), |
| 239 | .csr_ld (w_ld), |
| 240 | .csr_data (csrbus_wr_data[13]), |
| 241 | .rw_alias (1'b1), |
| 242 | .rw1c_alias (1'b0), |
| 243 | .rw1s_alias (1'b0), |
| 244 | .hw_ld (1'b0), |
| 245 | .hw_data (1'b0), |
| 246 | .cp (clk), |
| 247 | .q (tsb_csrbus_read_data[13]) |
| 248 | ); |
| 249 | |
| 250 | // bit 14 |
| 251 | csr_sw csr_sw_14 |
| 252 | ( |
| 253 | // synopsys translate_off |
| 254 | .omni_ld (omni_ld), |
| 255 | .omni_data (omni_data[14]), |
| 256 | .omni_rw_alias (1'b1), |
| 257 | .omni_rw1c_alias (1'b0), |
| 258 | .omni_rw1s_alias (1'b0), |
| 259 | // synopsys translate_on |
| 260 | .rst (rst_l_active_high), |
| 261 | .rst_val (reset_tb[1]), |
| 262 | .csr_ld (w_ld), |
| 263 | .csr_data (csrbus_wr_data[14]), |
| 264 | .rw_alias (1'b1), |
| 265 | .rw1c_alias (1'b0), |
| 266 | .rw1s_alias (1'b0), |
| 267 | .hw_ld (1'b0), |
| 268 | .hw_data (1'b0), |
| 269 | .cp (clk), |
| 270 | .q (tsb_csrbus_read_data[14]) |
| 271 | ); |
| 272 | |
| 273 | // bit 15 |
| 274 | csr_sw csr_sw_15 |
| 275 | ( |
| 276 | // synopsys translate_off |
| 277 | .omni_ld (omni_ld), |
| 278 | .omni_data (omni_data[15]), |
| 279 | .omni_rw_alias (1'b1), |
| 280 | .omni_rw1c_alias (1'b0), |
| 281 | .omni_rw1s_alias (1'b0), |
| 282 | // synopsys translate_on |
| 283 | .rst (rst_l_active_high), |
| 284 | .rst_val (reset_tb[2]), |
| 285 | .csr_ld (w_ld), |
| 286 | .csr_data (csrbus_wr_data[15]), |
| 287 | .rw_alias (1'b1), |
| 288 | .rw1c_alias (1'b0), |
| 289 | .rw1s_alias (1'b0), |
| 290 | .hw_ld (1'b0), |
| 291 | .hw_data (1'b0), |
| 292 | .cp (clk), |
| 293 | .q (tsb_csrbus_read_data[15]) |
| 294 | ); |
| 295 | |
| 296 | // bit 16 |
| 297 | csr_sw csr_sw_16 |
| 298 | ( |
| 299 | // synopsys translate_off |
| 300 | .omni_ld (omni_ld), |
| 301 | .omni_data (omni_data[16]), |
| 302 | .omni_rw_alias (1'b1), |
| 303 | .omni_rw1c_alias (1'b0), |
| 304 | .omni_rw1s_alias (1'b0), |
| 305 | // synopsys translate_on |
| 306 | .rst (rst_l_active_high), |
| 307 | .rst_val (reset_tb[3]), |
| 308 | .csr_ld (w_ld), |
| 309 | .csr_data (csrbus_wr_data[16]), |
| 310 | .rw_alias (1'b1), |
| 311 | .rw1c_alias (1'b0), |
| 312 | .rw1s_alias (1'b0), |
| 313 | .hw_ld (1'b0), |
| 314 | .hw_data (1'b0), |
| 315 | .cp (clk), |
| 316 | .q (tsb_csrbus_read_data[16]) |
| 317 | ); |
| 318 | |
| 319 | // bit 17 |
| 320 | csr_sw csr_sw_17 |
| 321 | ( |
| 322 | // synopsys translate_off |
| 323 | .omni_ld (omni_ld), |
| 324 | .omni_data (omni_data[17]), |
| 325 | .omni_rw_alias (1'b1), |
| 326 | .omni_rw1c_alias (1'b0), |
| 327 | .omni_rw1s_alias (1'b0), |
| 328 | // synopsys translate_on |
| 329 | .rst (rst_l_active_high), |
| 330 | .rst_val (reset_tb[4]), |
| 331 | .csr_ld (w_ld), |
| 332 | .csr_data (csrbus_wr_data[17]), |
| 333 | .rw_alias (1'b1), |
| 334 | .rw1c_alias (1'b0), |
| 335 | .rw1s_alias (1'b0), |
| 336 | .hw_ld (1'b0), |
| 337 | .hw_data (1'b0), |
| 338 | .cp (clk), |
| 339 | .q (tsb_csrbus_read_data[17]) |
| 340 | ); |
| 341 | |
| 342 | // bit 18 |
| 343 | csr_sw csr_sw_18 |
| 344 | ( |
| 345 | // synopsys translate_off |
| 346 | .omni_ld (omni_ld), |
| 347 | .omni_data (omni_data[18]), |
| 348 | .omni_rw_alias (1'b1), |
| 349 | .omni_rw1c_alias (1'b0), |
| 350 | .omni_rw1s_alias (1'b0), |
| 351 | // synopsys translate_on |
| 352 | .rst (rst_l_active_high), |
| 353 | .rst_val (reset_tb[5]), |
| 354 | .csr_ld (w_ld), |
| 355 | .csr_data (csrbus_wr_data[18]), |
| 356 | .rw_alias (1'b1), |
| 357 | .rw1c_alias (1'b0), |
| 358 | .rw1s_alias (1'b0), |
| 359 | .hw_ld (1'b0), |
| 360 | .hw_data (1'b0), |
| 361 | .cp (clk), |
| 362 | .q (tsb_csrbus_read_data[18]) |
| 363 | ); |
| 364 | |
| 365 | // bit 19 |
| 366 | csr_sw csr_sw_19 |
| 367 | ( |
| 368 | // synopsys translate_off |
| 369 | .omni_ld (omni_ld), |
| 370 | .omni_data (omni_data[19]), |
| 371 | .omni_rw_alias (1'b1), |
| 372 | .omni_rw1c_alias (1'b0), |
| 373 | .omni_rw1s_alias (1'b0), |
| 374 | // synopsys translate_on |
| 375 | .rst (rst_l_active_high), |
| 376 | .rst_val (reset_tb[6]), |
| 377 | .csr_ld (w_ld), |
| 378 | .csr_data (csrbus_wr_data[19]), |
| 379 | .rw_alias (1'b1), |
| 380 | .rw1c_alias (1'b0), |
| 381 | .rw1s_alias (1'b0), |
| 382 | .hw_ld (1'b0), |
| 383 | .hw_data (1'b0), |
| 384 | .cp (clk), |
| 385 | .q (tsb_csrbus_read_data[19]) |
| 386 | ); |
| 387 | |
| 388 | // bit 20 |
| 389 | csr_sw csr_sw_20 |
| 390 | ( |
| 391 | // synopsys translate_off |
| 392 | .omni_ld (omni_ld), |
| 393 | .omni_data (omni_data[20]), |
| 394 | .omni_rw_alias (1'b1), |
| 395 | .omni_rw1c_alias (1'b0), |
| 396 | .omni_rw1s_alias (1'b0), |
| 397 | // synopsys translate_on |
| 398 | .rst (rst_l_active_high), |
| 399 | .rst_val (reset_tb[7]), |
| 400 | .csr_ld (w_ld), |
| 401 | .csr_data (csrbus_wr_data[20]), |
| 402 | .rw_alias (1'b1), |
| 403 | .rw1c_alias (1'b0), |
| 404 | .rw1s_alias (1'b0), |
| 405 | .hw_ld (1'b0), |
| 406 | .hw_data (1'b0), |
| 407 | .cp (clk), |
| 408 | .q (tsb_csrbus_read_data[20]) |
| 409 | ); |
| 410 | |
| 411 | // bit 21 |
| 412 | csr_sw csr_sw_21 |
| 413 | ( |
| 414 | // synopsys translate_off |
| 415 | .omni_ld (omni_ld), |
| 416 | .omni_data (omni_data[21]), |
| 417 | .omni_rw_alias (1'b1), |
| 418 | .omni_rw1c_alias (1'b0), |
| 419 | .omni_rw1s_alias (1'b0), |
| 420 | // synopsys translate_on |
| 421 | .rst (rst_l_active_high), |
| 422 | .rst_val (reset_tb[8]), |
| 423 | .csr_ld (w_ld), |
| 424 | .csr_data (csrbus_wr_data[21]), |
| 425 | .rw_alias (1'b1), |
| 426 | .rw1c_alias (1'b0), |
| 427 | .rw1s_alias (1'b0), |
| 428 | .hw_ld (1'b0), |
| 429 | .hw_data (1'b0), |
| 430 | .cp (clk), |
| 431 | .q (tsb_csrbus_read_data[21]) |
| 432 | ); |
| 433 | |
| 434 | // bit 22 |
| 435 | csr_sw csr_sw_22 |
| 436 | ( |
| 437 | // synopsys translate_off |
| 438 | .omni_ld (omni_ld), |
| 439 | .omni_data (omni_data[22]), |
| 440 | .omni_rw_alias (1'b1), |
| 441 | .omni_rw1c_alias (1'b0), |
| 442 | .omni_rw1s_alias (1'b0), |
| 443 | // synopsys translate_on |
| 444 | .rst (rst_l_active_high), |
| 445 | .rst_val (reset_tb[9]), |
| 446 | .csr_ld (w_ld), |
| 447 | .csr_data (csrbus_wr_data[22]), |
| 448 | .rw_alias (1'b1), |
| 449 | .rw1c_alias (1'b0), |
| 450 | .rw1s_alias (1'b0), |
| 451 | .hw_ld (1'b0), |
| 452 | .hw_data (1'b0), |
| 453 | .cp (clk), |
| 454 | .q (tsb_csrbus_read_data[22]) |
| 455 | ); |
| 456 | |
| 457 | // bit 23 |
| 458 | csr_sw csr_sw_23 |
| 459 | ( |
| 460 | // synopsys translate_off |
| 461 | .omni_ld (omni_ld), |
| 462 | .omni_data (omni_data[23]), |
| 463 | .omni_rw_alias (1'b1), |
| 464 | .omni_rw1c_alias (1'b0), |
| 465 | .omni_rw1s_alias (1'b0), |
| 466 | // synopsys translate_on |
| 467 | .rst (rst_l_active_high), |
| 468 | .rst_val (reset_tb[10]), |
| 469 | .csr_ld (w_ld), |
| 470 | .csr_data (csrbus_wr_data[23]), |
| 471 | .rw_alias (1'b1), |
| 472 | .rw1c_alias (1'b0), |
| 473 | .rw1s_alias (1'b0), |
| 474 | .hw_ld (1'b0), |
| 475 | .hw_data (1'b0), |
| 476 | .cp (clk), |
| 477 | .q (tsb_csrbus_read_data[23]) |
| 478 | ); |
| 479 | |
| 480 | // bit 24 |
| 481 | csr_sw csr_sw_24 |
| 482 | ( |
| 483 | // synopsys translate_off |
| 484 | .omni_ld (omni_ld), |
| 485 | .omni_data (omni_data[24]), |
| 486 | .omni_rw_alias (1'b1), |
| 487 | .omni_rw1c_alias (1'b0), |
| 488 | .omni_rw1s_alias (1'b0), |
| 489 | // synopsys translate_on |
| 490 | .rst (rst_l_active_high), |
| 491 | .rst_val (reset_tb[11]), |
| 492 | .csr_ld (w_ld), |
| 493 | .csr_data (csrbus_wr_data[24]), |
| 494 | .rw_alias (1'b1), |
| 495 | .rw1c_alias (1'b0), |
| 496 | .rw1s_alias (1'b0), |
| 497 | .hw_ld (1'b0), |
| 498 | .hw_data (1'b0), |
| 499 | .cp (clk), |
| 500 | .q (tsb_csrbus_read_data[24]) |
| 501 | ); |
| 502 | |
| 503 | // bit 25 |
| 504 | csr_sw csr_sw_25 |
| 505 | ( |
| 506 | // synopsys translate_off |
| 507 | .omni_ld (omni_ld), |
| 508 | .omni_data (omni_data[25]), |
| 509 | .omni_rw_alias (1'b1), |
| 510 | .omni_rw1c_alias (1'b0), |
| 511 | .omni_rw1s_alias (1'b0), |
| 512 | // synopsys translate_on |
| 513 | .rst (rst_l_active_high), |
| 514 | .rst_val (reset_tb[12]), |
| 515 | .csr_ld (w_ld), |
| 516 | .csr_data (csrbus_wr_data[25]), |
| 517 | .rw_alias (1'b1), |
| 518 | .rw1c_alias (1'b0), |
| 519 | .rw1s_alias (1'b0), |
| 520 | .hw_ld (1'b0), |
| 521 | .hw_data (1'b0), |
| 522 | .cp (clk), |
| 523 | .q (tsb_csrbus_read_data[25]) |
| 524 | ); |
| 525 | |
| 526 | // bit 26 |
| 527 | csr_sw csr_sw_26 |
| 528 | ( |
| 529 | // synopsys translate_off |
| 530 | .omni_ld (omni_ld), |
| 531 | .omni_data (omni_data[26]), |
| 532 | .omni_rw_alias (1'b1), |
| 533 | .omni_rw1c_alias (1'b0), |
| 534 | .omni_rw1s_alias (1'b0), |
| 535 | // synopsys translate_on |
| 536 | .rst (rst_l_active_high), |
| 537 | .rst_val (reset_tb[13]), |
| 538 | .csr_ld (w_ld), |
| 539 | .csr_data (csrbus_wr_data[26]), |
| 540 | .rw_alias (1'b1), |
| 541 | .rw1c_alias (1'b0), |
| 542 | .rw1s_alias (1'b0), |
| 543 | .hw_ld (1'b0), |
| 544 | .hw_data (1'b0), |
| 545 | .cp (clk), |
| 546 | .q (tsb_csrbus_read_data[26]) |
| 547 | ); |
| 548 | |
| 549 | // bit 27 |
| 550 | csr_sw csr_sw_27 |
| 551 | ( |
| 552 | // synopsys translate_off |
| 553 | .omni_ld (omni_ld), |
| 554 | .omni_data (omni_data[27]), |
| 555 | .omni_rw_alias (1'b1), |
| 556 | .omni_rw1c_alias (1'b0), |
| 557 | .omni_rw1s_alias (1'b0), |
| 558 | // synopsys translate_on |
| 559 | .rst (rst_l_active_high), |
| 560 | .rst_val (reset_tb[14]), |
| 561 | .csr_ld (w_ld), |
| 562 | .csr_data (csrbus_wr_data[27]), |
| 563 | .rw_alias (1'b1), |
| 564 | .rw1c_alias (1'b0), |
| 565 | .rw1s_alias (1'b0), |
| 566 | .hw_ld (1'b0), |
| 567 | .hw_data (1'b0), |
| 568 | .cp (clk), |
| 569 | .q (tsb_csrbus_read_data[27]) |
| 570 | ); |
| 571 | |
| 572 | // bit 28 |
| 573 | csr_sw csr_sw_28 |
| 574 | ( |
| 575 | // synopsys translate_off |
| 576 | .omni_ld (omni_ld), |
| 577 | .omni_data (omni_data[28]), |
| 578 | .omni_rw_alias (1'b1), |
| 579 | .omni_rw1c_alias (1'b0), |
| 580 | .omni_rw1s_alias (1'b0), |
| 581 | // synopsys translate_on |
| 582 | .rst (rst_l_active_high), |
| 583 | .rst_val (reset_tb[15]), |
| 584 | .csr_ld (w_ld), |
| 585 | .csr_data (csrbus_wr_data[28]), |
| 586 | .rw_alias (1'b1), |
| 587 | .rw1c_alias (1'b0), |
| 588 | .rw1s_alias (1'b0), |
| 589 | .hw_ld (1'b0), |
| 590 | .hw_data (1'b0), |
| 591 | .cp (clk), |
| 592 | .q (tsb_csrbus_read_data[28]) |
| 593 | ); |
| 594 | |
| 595 | // bit 29 |
| 596 | csr_sw csr_sw_29 |
| 597 | ( |
| 598 | // synopsys translate_off |
| 599 | .omni_ld (omni_ld), |
| 600 | .omni_data (omni_data[29]), |
| 601 | .omni_rw_alias (1'b1), |
| 602 | .omni_rw1c_alias (1'b0), |
| 603 | .omni_rw1s_alias (1'b0), |
| 604 | // synopsys translate_on |
| 605 | .rst (rst_l_active_high), |
| 606 | .rst_val (reset_tb[16]), |
| 607 | .csr_ld (w_ld), |
| 608 | .csr_data (csrbus_wr_data[29]), |
| 609 | .rw_alias (1'b1), |
| 610 | .rw1c_alias (1'b0), |
| 611 | .rw1s_alias (1'b0), |
| 612 | .hw_ld (1'b0), |
| 613 | .hw_data (1'b0), |
| 614 | .cp (clk), |
| 615 | .q (tsb_csrbus_read_data[29]) |
| 616 | ); |
| 617 | |
| 618 | // bit 30 |
| 619 | csr_sw csr_sw_30 |
| 620 | ( |
| 621 | // synopsys translate_off |
| 622 | .omni_ld (omni_ld), |
| 623 | .omni_data (omni_data[30]), |
| 624 | .omni_rw_alias (1'b1), |
| 625 | .omni_rw1c_alias (1'b0), |
| 626 | .omni_rw1s_alias (1'b0), |
| 627 | // synopsys translate_on |
| 628 | .rst (rst_l_active_high), |
| 629 | .rst_val (reset_tb[17]), |
| 630 | .csr_ld (w_ld), |
| 631 | .csr_data (csrbus_wr_data[30]), |
| 632 | .rw_alias (1'b1), |
| 633 | .rw1c_alias (1'b0), |
| 634 | .rw1s_alias (1'b0), |
| 635 | .hw_ld (1'b0), |
| 636 | .hw_data (1'b0), |
| 637 | .cp (clk), |
| 638 | .q (tsb_csrbus_read_data[30]) |
| 639 | ); |
| 640 | |
| 641 | // bit 31 |
| 642 | csr_sw csr_sw_31 |
| 643 | ( |
| 644 | // synopsys translate_off |
| 645 | .omni_ld (omni_ld), |
| 646 | .omni_data (omni_data[31]), |
| 647 | .omni_rw_alias (1'b1), |
| 648 | .omni_rw1c_alias (1'b0), |
| 649 | .omni_rw1s_alias (1'b0), |
| 650 | // synopsys translate_on |
| 651 | .rst (rst_l_active_high), |
| 652 | .rst_val (reset_tb[18]), |
| 653 | .csr_ld (w_ld), |
| 654 | .csr_data (csrbus_wr_data[31]), |
| 655 | .rw_alias (1'b1), |
| 656 | .rw1c_alias (1'b0), |
| 657 | .rw1s_alias (1'b0), |
| 658 | .hw_ld (1'b0), |
| 659 | .hw_data (1'b0), |
| 660 | .cp (clk), |
| 661 | .q (tsb_csrbus_read_data[31]) |
| 662 | ); |
| 663 | |
| 664 | // bit 32 |
| 665 | csr_sw csr_sw_32 |
| 666 | ( |
| 667 | // synopsys translate_off |
| 668 | .omni_ld (omni_ld), |
| 669 | .omni_data (omni_data[32]), |
| 670 | .omni_rw_alias (1'b1), |
| 671 | .omni_rw1c_alias (1'b0), |
| 672 | .omni_rw1s_alias (1'b0), |
| 673 | // synopsys translate_on |
| 674 | .rst (rst_l_active_high), |
| 675 | .rst_val (reset_tb[19]), |
| 676 | .csr_ld (w_ld), |
| 677 | .csr_data (csrbus_wr_data[32]), |
| 678 | .rw_alias (1'b1), |
| 679 | .rw1c_alias (1'b0), |
| 680 | .rw1s_alias (1'b0), |
| 681 | .hw_ld (1'b0), |
| 682 | .hw_data (1'b0), |
| 683 | .cp (clk), |
| 684 | .q (tsb_csrbus_read_data[32]) |
| 685 | ); |
| 686 | |
| 687 | // bit 33 |
| 688 | csr_sw csr_sw_33 |
| 689 | ( |
| 690 | // synopsys translate_off |
| 691 | .omni_ld (omni_ld), |
| 692 | .omni_data (omni_data[33]), |
| 693 | .omni_rw_alias (1'b1), |
| 694 | .omni_rw1c_alias (1'b0), |
| 695 | .omni_rw1s_alias (1'b0), |
| 696 | // synopsys translate_on |
| 697 | .rst (rst_l_active_high), |
| 698 | .rst_val (reset_tb[20]), |
| 699 | .csr_ld (w_ld), |
| 700 | .csr_data (csrbus_wr_data[33]), |
| 701 | .rw_alias (1'b1), |
| 702 | .rw1c_alias (1'b0), |
| 703 | .rw1s_alias (1'b0), |
| 704 | .hw_ld (1'b0), |
| 705 | .hw_data (1'b0), |
| 706 | .cp (clk), |
| 707 | .q (tsb_csrbus_read_data[33]) |
| 708 | ); |
| 709 | |
| 710 | // bit 34 |
| 711 | csr_sw csr_sw_34 |
| 712 | ( |
| 713 | // synopsys translate_off |
| 714 | .omni_ld (omni_ld), |
| 715 | .omni_data (omni_data[34]), |
| 716 | .omni_rw_alias (1'b1), |
| 717 | .omni_rw1c_alias (1'b0), |
| 718 | .omni_rw1s_alias (1'b0), |
| 719 | // synopsys translate_on |
| 720 | .rst (rst_l_active_high), |
| 721 | .rst_val (reset_tb[21]), |
| 722 | .csr_ld (w_ld), |
| 723 | .csr_data (csrbus_wr_data[34]), |
| 724 | .rw_alias (1'b1), |
| 725 | .rw1c_alias (1'b0), |
| 726 | .rw1s_alias (1'b0), |
| 727 | .hw_ld (1'b0), |
| 728 | .hw_data (1'b0), |
| 729 | .cp (clk), |
| 730 | .q (tsb_csrbus_read_data[34]) |
| 731 | ); |
| 732 | |
| 733 | // bit 35 |
| 734 | csr_sw csr_sw_35 |
| 735 | ( |
| 736 | // synopsys translate_off |
| 737 | .omni_ld (omni_ld), |
| 738 | .omni_data (omni_data[35]), |
| 739 | .omni_rw_alias (1'b1), |
| 740 | .omni_rw1c_alias (1'b0), |
| 741 | .omni_rw1s_alias (1'b0), |
| 742 | // synopsys translate_on |
| 743 | .rst (rst_l_active_high), |
| 744 | .rst_val (reset_tb[22]), |
| 745 | .csr_ld (w_ld), |
| 746 | .csr_data (csrbus_wr_data[35]), |
| 747 | .rw_alias (1'b1), |
| 748 | .rw1c_alias (1'b0), |
| 749 | .rw1s_alias (1'b0), |
| 750 | .hw_ld (1'b0), |
| 751 | .hw_data (1'b0), |
| 752 | .cp (clk), |
| 753 | .q (tsb_csrbus_read_data[35]) |
| 754 | ); |
| 755 | |
| 756 | // bit 36 |
| 757 | csr_sw csr_sw_36 |
| 758 | ( |
| 759 | // synopsys translate_off |
| 760 | .omni_ld (omni_ld), |
| 761 | .omni_data (omni_data[36]), |
| 762 | .omni_rw_alias (1'b1), |
| 763 | .omni_rw1c_alias (1'b0), |
| 764 | .omni_rw1s_alias (1'b0), |
| 765 | // synopsys translate_on |
| 766 | .rst (rst_l_active_high), |
| 767 | .rst_val (reset_tb[23]), |
| 768 | .csr_ld (w_ld), |
| 769 | .csr_data (csrbus_wr_data[36]), |
| 770 | .rw_alias (1'b1), |
| 771 | .rw1c_alias (1'b0), |
| 772 | .rw1s_alias (1'b0), |
| 773 | .hw_ld (1'b0), |
| 774 | .hw_data (1'b0), |
| 775 | .cp (clk), |
| 776 | .q (tsb_csrbus_read_data[36]) |
| 777 | ); |
| 778 | |
| 779 | // bit 37 |
| 780 | csr_sw csr_sw_37 |
| 781 | ( |
| 782 | // synopsys translate_off |
| 783 | .omni_ld (omni_ld), |
| 784 | .omni_data (omni_data[37]), |
| 785 | .omni_rw_alias (1'b1), |
| 786 | .omni_rw1c_alias (1'b0), |
| 787 | .omni_rw1s_alias (1'b0), |
| 788 | // synopsys translate_on |
| 789 | .rst (rst_l_active_high), |
| 790 | .rst_val (reset_tb[24]), |
| 791 | .csr_ld (w_ld), |
| 792 | .csr_data (csrbus_wr_data[37]), |
| 793 | .rw_alias (1'b1), |
| 794 | .rw1c_alias (1'b0), |
| 795 | .rw1s_alias (1'b0), |
| 796 | .hw_ld (1'b0), |
| 797 | .hw_data (1'b0), |
| 798 | .cp (clk), |
| 799 | .q (tsb_csrbus_read_data[37]) |
| 800 | ); |
| 801 | |
| 802 | // bit 38 |
| 803 | csr_sw csr_sw_38 |
| 804 | ( |
| 805 | // synopsys translate_off |
| 806 | .omni_ld (omni_ld), |
| 807 | .omni_data (omni_data[38]), |
| 808 | .omni_rw_alias (1'b1), |
| 809 | .omni_rw1c_alias (1'b0), |
| 810 | .omni_rw1s_alias (1'b0), |
| 811 | // synopsys translate_on |
| 812 | .rst (rst_l_active_high), |
| 813 | .rst_val (reset_tb[25]), |
| 814 | .csr_ld (w_ld), |
| 815 | .csr_data (csrbus_wr_data[38]), |
| 816 | .rw_alias (1'b1), |
| 817 | .rw1c_alias (1'b0), |
| 818 | .rw1s_alias (1'b0), |
| 819 | .hw_ld (1'b0), |
| 820 | .hw_data (1'b0), |
| 821 | .cp (clk), |
| 822 | .q (tsb_csrbus_read_data[38]) |
| 823 | ); |
| 824 | |
| 825 | assign tsb_csrbus_read_data[39] = 1'b0; // bit 39 |
| 826 | assign tsb_csrbus_read_data[40] = 1'b0; // bit 40 |
| 827 | assign tsb_csrbus_read_data[41] = 1'b0; // bit 41 |
| 828 | assign tsb_csrbus_read_data[42] = 1'b0; // bit 42 |
| 829 | assign tsb_csrbus_read_data[43] = 1'b0; // bit 43 |
| 830 | assign tsb_csrbus_read_data[44] = 1'b0; // bit 44 |
| 831 | assign tsb_csrbus_read_data[45] = 1'b0; // bit 45 |
| 832 | assign tsb_csrbus_read_data[46] = 1'b0; // bit 46 |
| 833 | assign tsb_csrbus_read_data[47] = 1'b0; // bit 47 |
| 834 | assign tsb_csrbus_read_data[48] = 1'b0; // bit 48 |
| 835 | assign tsb_csrbus_read_data[49] = 1'b0; // bit 49 |
| 836 | assign tsb_csrbus_read_data[50] = 1'b0; // bit 50 |
| 837 | assign tsb_csrbus_read_data[51] = 1'b0; // bit 51 |
| 838 | assign tsb_csrbus_read_data[52] = 1'b0; // bit 52 |
| 839 | assign tsb_csrbus_read_data[53] = 1'b0; // bit 53 |
| 840 | assign tsb_csrbus_read_data[54] = 1'b0; // bit 54 |
| 841 | assign tsb_csrbus_read_data[55] = 1'b0; // bit 55 |
| 842 | assign tsb_csrbus_read_data[56] = 1'b0; // bit 56 |
| 843 | assign tsb_csrbus_read_data[57] = 1'b0; // bit 57 |
| 844 | assign tsb_csrbus_read_data[58] = 1'b0; // bit 58 |
| 845 | assign tsb_csrbus_read_data[59] = 1'b0; // bit 59 |
| 846 | assign tsb_csrbus_read_data[60] = 1'b0; // bit 60 |
| 847 | assign tsb_csrbus_read_data[61] = 1'b0; // bit 61 |
| 848 | assign tsb_csrbus_read_data[62] = 1'b0; // bit 62 |
| 849 | assign tsb_csrbus_read_data[63] = 1'b0; // bit 63 |
| 850 | |
| 851 | endmodule // dmu_mmu_csr_tsb_entry |