| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_tcb_tdc.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_tcb_tdc |
| 36 | ( |
| 37 | clk, // clock |
| 38 | rst_l, // reset |
| 39 | rcb2tcb_err, // rcb error |
| 40 | rcb2tcb_tag, // rcb tag |
| 41 | rcb2tcb_vld, // rcb valid |
| 42 | tcc2tdc_cld, // tdc cache load |
| 43 | tcc2tdc_req, // tdc request |
| 44 | tcc2tdc_tag, // tdc replacement tag |
| 45 | tcb2tdb_wa, // tdb write address |
| 46 | tcb2tdb_we, // tdb write enable |
| 47 | tcb2tlb_dld, // tlb data load |
| 48 | tcb2tlb_ra, // tlb read address |
| 49 | tcb2tlb_ras, // tlb read address select |
| 50 | tdc2tcc_ack, // tcc acknowledge |
| 51 | tdc2tcc_err, // tcc error |
| 52 | tdc2tmc_dbg, // tmc debug |
| 53 | tdc2tmc_err // tmc errors |
| 54 | ); |
| 55 | |
| 56 | // ---------------------------------------------------------------------------- |
| 57 | // Parameters |
| 58 | // ---------------------------------------------------------------------------- |
| 59 | parameter CNT_TST0 = 3'b011, |
| 60 | CNT_TST1 = 3'b110; |
| 61 | |
| 62 | |
| 63 | parameter IDLE = 2'b00, // state machine states |
| 64 | WAIT = 2'b01, |
| 65 | DATA = 2'b10, |
| 66 | DONE = 2'b11; |
| 67 | |
| 68 | // ---------------------------------------------------------------------------- |
| 69 | // Ports |
| 70 | // ---------------------------------------------------------------------------- |
| 71 | |
| 72 | input clk; |
| 73 | input rst_l; |
| 74 | |
| 75 | input [`FIRE_DLC_MMU_RCB_ERR_BITS] rcb2tcb_err; |
| 76 | input [`FIRE_DLC_MMU_TAG_PTR_BITS] rcb2tcb_tag; |
| 77 | input rcb2tcb_vld; |
| 78 | input tcc2tdc_cld; |
| 79 | input tcc2tdc_req; |
| 80 | input [`FIRE_DLC_MMU_TAG_PTR_BITS] tcc2tdc_tag; |
| 81 | |
| 82 | output [`FIRE_DLC_MMU_TDB_PTR_BITS] tcb2tdb_wa; |
| 83 | output tcb2tdb_we; |
| 84 | output tcb2tlb_dld; |
| 85 | output [`FILE_DLC_MMU_TTE_CNT_BITS] tcb2tlb_ra; |
| 86 | output tcb2tlb_ras; |
| 87 | output tdc2tcc_ack; |
| 88 | output tdc2tcc_err; |
| 89 | output [`FIRE_DBG_DATA_BITS] tdc2tmc_dbg; |
| 90 | output [`FIRE_DLC_MMU_TDC_ERR_BITS] tdc2tmc_err; |
| 91 | |
| 92 | // ---------------------------------------------------------------------------- |
| 93 | // Variables |
| 94 | // ---------------------------------------------------------------------------- |
| 95 | wire [`FIRE_DLC_MMU_TDB_PTR_BITS] tcb2tdb_wa; |
| 96 | wire [`FIRE_DBG_DATA_BITS] tdc2tmc_dbg; |
| 97 | wire [`FIRE_DLC_MMU_RCB_ERR_BITS] tdr_err; |
| 98 | |
| 99 | reg tcb2tdb_we; |
| 100 | reg [`FILE_DLC_MMU_TTE_CNT_BITS] tcb2tlb_ra; |
| 101 | reg tcb2tlb_ras; |
| 102 | reg tdc2tcc_ack; |
| 103 | reg [`FIRE_DLC_MMU_TDC_ERR_BITS] tdc2tmc_err; |
| 104 | reg [1:0] state, nxt_state; |
| 105 | reg [`FILE_DLC_MMU_TTE_CNT_BITS] cnt, nxt_cnt; |
| 106 | reg [`FIRE_DLC_MMU_TDC_ERR_BITS] err, nxt_err; |
| 107 | |
| 108 | // ---------------------------------------------------------------------------- |
| 109 | // Zero In Checkers |
| 110 | // ---------------------------------------------------------------------------- |
| 111 | |
| 112 | // 0in state_transition -var state -val IDLE -next WAIT |
| 113 | // 0in state_transition -var state -val WAIT -next DATA DONE |
| 114 | // 0in state_transition -var state -val DATA -next DONE IDLE |
| 115 | // 0in state_transition -var state -val DONE -next IDLE |
| 116 | |
| 117 | // ---------------------------------------------------------------------------- |
| 118 | // Combinational |
| 119 | // ---------------------------------------------------------------------------- |
| 120 | |
| 121 | // tlb data load |
| 122 | wire tcb2tlb_dld = rcb2tcb_vld; |
| 123 | |
| 124 | // tdb write address |
| 125 | assign tcb2tdb_wa = { tcc2tdc_tag, cnt }; |
| 126 | |
| 127 | // tcc error |
| 128 | wire tdc2tcc_err = |(err | tdr_err) & tdc2tcc_ack; |
| 129 | |
| 130 | // tag and tdr errors |
| 131 | wire tag_err = rcb2tcb_vld & (tcc2tdc_tag != rcb2tcb_tag); |
| 132 | assign tdr_err = rcb2tcb_vld ? rcb2tcb_err : 0; |
| 133 | |
| 134 | // next state |
| 135 | always @ (state or rcb2tcb_vld or tdr_err or tcc2tdc_cld or tcc2tdc_req or |
| 136 | cnt) begin |
| 137 | case (state) // synopsys parallel_case |
| 138 | IDLE : begin |
| 139 | case (tcc2tdc_req) // synopsys parallel_case |
| 140 | 1'b0 : nxt_state = IDLE; // idle |
| 141 | 1'b1 : nxt_state = WAIT; // request |
| 142 | endcase |
| 143 | end |
| 144 | WAIT : begin |
| 145 | case ({rcb2tcb_vld, tdr_err[0]}) // synopsys parallel_case |
| 146 | 2'b00 : nxt_state = WAIT; // wait for rcb vld |
| 147 | 2'b01 : nxt_state = IDLE; // cannot happen |
| 148 | 2'b10 : nxt_state = DATA; // rcb vld |
| 149 | 2'b11 : nxt_state = DONE; // error |
| 150 | endcase |
| 151 | end |
| 152 | DATA : begin |
| 153 | case (cnt) // synopsys parallel_case |
| 154 | 3'b000 : nxt_state = rcb2tcb_vld ? DATA : DONE; |
| 155 | 3'b001 : nxt_state = rcb2tcb_vld ? DATA : DONE; |
| 156 | 3'b010 : nxt_state = rcb2tcb_vld ? DATA : DONE; |
| 157 | 3'b011 : nxt_state = tcc2tdc_cld ? DATA : DONE; |
| 158 | 3'b100 : nxt_state = DATA; |
| 159 | 3'b101 : nxt_state = DATA; |
| 160 | 3'b110 : nxt_state = DATA; |
| 161 | 3'b111 : nxt_state = IDLE; |
| 162 | endcase |
| 163 | end |
| 164 | DONE : begin |
| 165 | nxt_state = IDLE; |
| 166 | end |
| 167 | endcase |
| 168 | end |
| 169 | |
| 170 | // state machine outputs |
| 171 | always @ (state or tdr_err or tcc2tdc_cld or cnt or err or tag_err) begin |
| 172 | case (state) // synopsys parallel_case |
| 173 | IDLE : begin |
| 174 | tcb2tlb_ras = 0; |
| 175 | tcb2tdb_we = 0; |
| 176 | tdc2tcc_ack = 0; |
| 177 | tdc2tmc_err = err; |
| 178 | nxt_cnt = 0; |
| 179 | nxt_err = 0; |
| 180 | end |
| 181 | WAIT : begin |
| 182 | tcb2tlb_ras = 0; |
| 183 | tcb2tdb_we = 0; |
| 184 | tdc2tcc_ack = tdr_err[0]; |
| 185 | tdc2tmc_err = 0; |
| 186 | nxt_cnt = 0; |
| 187 | nxt_err[0] = err[0] | tag_err; |
| 188 | nxt_err[1] = err[1] | (|tdr_err[1:0]); |
| 189 | nxt_err[2] = err[2] | tdr_err[2]; |
| 190 | end |
| 191 | DATA : begin |
| 192 | tcb2tlb_ras = tcc2tdc_cld; |
| 193 | tcb2tdb_we = tcc2tdc_cld; |
| 194 | tdc2tcc_ack = tcc2tdc_cld ? (cnt == CNT_TST1) : (cnt == CNT_TST0); |
| 195 | tdc2tmc_err = 0; |
| 196 | nxt_cnt = cnt + 1; |
| 197 | nxt_err = err | tdr_err; |
| 198 | end |
| 199 | DONE : begin |
| 200 | tcb2tlb_ras = 0; |
| 201 | tcb2tdb_we = 0; |
| 202 | tdc2tcc_ack = 0; |
| 203 | tdc2tmc_err = 0; |
| 204 | nxt_cnt = 0; |
| 205 | nxt_err = err; |
| 206 | end |
| 207 | endcase |
| 208 | end |
| 209 | |
| 210 | // tlb read address |
| 211 | always @ (cnt) begin |
| 212 | case (cnt) // synopsys parallel_case |
| 213 | 3'b000 : tcb2tlb_ra = 3'b110; |
| 214 | 3'b001 : tcb2tlb_ra = 3'b101; |
| 215 | 3'b010 : tcb2tlb_ra = 3'b100; |
| 216 | 3'b011 : tcb2tlb_ra = 3'b011; |
| 217 | 3'b100 : tcb2tlb_ra = 3'b100; |
| 218 | 3'b101 : tcb2tlb_ra = 3'b101; |
| 219 | 3'b110 : tcb2tlb_ra = 3'b110; |
| 220 | 3'b111 : tcb2tlb_ra = 3'b111; |
| 221 | endcase |
| 222 | end |
| 223 | |
| 224 | // ---------------------------------------------------------------------------- |
| 225 | // Debug |
| 226 | // ---------------------------------------------------------------------------- |
| 227 | assign tdc2tmc_dbg = {state, cnt, err}; |
| 228 | |
| 229 | // ---------------------------------------------------------------------------- |
| 230 | // Sequential |
| 231 | // ---------------------------------------------------------------------------- |
| 232 | always @ (posedge clk) begin |
| 233 | if (!rst_l) begin |
| 234 | cnt <= 0; |
| 235 | err <= 0; |
| 236 | state <= IDLE; |
| 237 | end |
| 238 | else begin |
| 239 | cnt <= nxt_cnt; |
| 240 | err <= nxt_err; |
| 241 | state <= nxt_state; |
| 242 | end |
| 243 | end |
| 244 | |
| 245 | endmodule // dmu_mmu_tcb_tdc |
| 246 | |