| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_tdb.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_tdb |
| 36 | ( |
| 37 | l2clk, // clock for rams |
| 38 | clk, // clock |
| 39 | scan_in, |
| 40 | tcu_array_bypass, |
| 41 | tcu_scan_en, |
| 42 | tcu_se_scancollar_in, |
| 43 | tcu_array_wr_inhibit, |
| 44 | tcu_pce_ov, |
| 45 | tcu_aclk, |
| 46 | tcu_bclk, |
| 47 | scan_out, |
| 48 | |
| 49 | csr2tdb_ra, // csr read address |
| 50 | csr2tdb_wa, // csr write address |
| 51 | csr2tdb_wd, // csr write data |
| 52 | csr2tdb_we, // csr write enable |
| 53 | tcb2tdb_sel, // tcb select |
| 54 | tcb2tdb_wa, // tcb write address |
| 55 | tcb2tdb_we, // tcb write enable |
| 56 | tlb2tdb_data, // tlb data |
| 57 | tlb2tdb_rqid, // rqid in ps2 to compare against rqid in ram |
| 58 | vtb2tdb_dbra, // vtb data buffer read address |
| 59 | tdb2csr_rd, // csr read data |
| 60 | tdb2pab_par, // pab parity |
| 61 | tdb2pab_ppn, // pab physical page number |
| 62 | tdb2pab_vld, // pab valid |
| 63 | tdb2pab_keyvld, // pab key valid |
| 64 | tdb2pab_fnm, // pab function number |
| 65 | tdb2pab_key, // pab key |
| 66 | tdb2pab_wrt, // pab write |
| 67 | tdb2tmc_kerr, // key error, do not translate |
| 68 | dsn_dmc_iei, // NCU can force parity into tdb ram by setting this |
| 69 | |
| 70 | tdb_dout_8msb, |
| 71 | dmu_mb0_run, |
| 72 | dmu_mb0_addr, |
| 73 | dmu_mb0_wdata, |
| 74 | dmu_mb0_tdb_wr_en, |
| 75 | dmu_mb0_tdb_rd_en |
| 76 | |
| 77 | ); |
| 78 | |
| 79 | // ---------------------------------------------------------------------------- |
| 80 | // Ports |
| 81 | // ---------------------------------------------------------------------------- |
| 82 | input l2clk; |
| 83 | input clk; |
| 84 | input scan_in; |
| 85 | input tcu_array_bypass; |
| 86 | input tcu_scan_en; |
| 87 | input tcu_se_scancollar_in; |
| 88 | input tcu_array_wr_inhibit; |
| 89 | input tcu_pce_ov; |
| 90 | input tcu_aclk; |
| 91 | input tcu_bclk; |
| 92 | output scan_out; |
| 93 | |
| 94 | input [`FIRE_DLC_MMU_TDB_PTR_BITS] csr2tdb_ra; |
| 95 | input [`FIRE_DLC_MMU_TDB_PTR_BITS] csr2tdb_wa; |
| 96 | input [`FIRE_DLC_MMU_TDR_BITS] csr2tdb_wd; |
| 97 | input csr2tdb_we; |
| 98 | input tcb2tdb_sel; |
| 99 | input [`FIRE_DLC_MMU_TDB_PTR_BITS] tcb2tdb_wa; |
| 100 | input tcb2tdb_we; |
| 101 | input [`FIRE_DLC_MMU_TDR_MINUS_PAR_BITS] tlb2tdb_data; |
| 102 | input [`FIRE_DLC_MMU_VA_RQID_BITS] tlb2tdb_rqid; |
| 103 | input [`FIRE_DLC_MMU_TDB_PTR_BITS] vtb2tdb_dbra; |
| 104 | |
| 105 | output [`FIRE_DLC_MMU_TDR_BITS] tdb2csr_rd; |
| 106 | output [`FIRE_DLC_MMU_TDD_PAR_BITS] tdb2pab_par; |
| 107 | output [`FIRE_DLC_MMU_TDD_PPN_BITS] tdb2pab_ppn; |
| 108 | output [`FIRE_DLC_MMU_TDD_KEY_BITS] tdb2pab_key; |
| 109 | output [`FIRE_DLC_MMU_TDD_FNM_BITS] tdb2pab_fnm; |
| 110 | output tdb2pab_vld; |
| 111 | output tdb2pab_keyvld; |
| 112 | output tdb2pab_wrt; |
| 113 | output tdb2tmc_kerr; |
| 114 | input dsn_dmc_iei; |
| 115 | |
| 116 | input dmu_mb0_run; |
| 117 | |
| 118 | input [8:0] dmu_mb0_addr; |
| 119 | input [7:0] dmu_mb0_wdata; |
| 120 | input dmu_mb0_tdb_wr_en; |
| 121 | input dmu_mb0_tdb_rd_en; |
| 122 | output [7:0] tdb_dout_8msb; |
| 123 | |
| 124 | // ---------------------------------------------------------------------------- |
| 125 | // Variables |
| 126 | // ---------------------------------------------------------------------------- |
| 127 | wire [`FIRE_DLC_MMU_TDR_BITS] tdb2csr_rd; |
| 128 | wire [`FIRE_DLC_MMU_TDD_PAR_BITS] tdb2pab_par; |
| 129 | wire [`FIRE_DLC_MMU_TDD_PPN_BITS] tdb2pab_ppn; |
| 130 | wire [`FIRE_DLC_MMU_TDD_KEY_BITS] tdb2pab_key; |
| 131 | wire [`FIRE_DLC_MMU_TDD_FNM_BITS] tdb2pab_fnm; |
| 132 | |
| 133 | wire [`FIRE_DLC_MMU_TDR_BITS] dib, doa; |
| 134 | wire [`FIRE_DLC_MMU_TDB_PTR_BITS] aadr, badr; |
| 135 | wire [3:0] par; |
| 136 | wire tdb2tmc_kerr; |
| 137 | |
| 138 | // ---------------------------------------------------------------------------- |
| 139 | // Zero In Checkers |
| 140 | // ---------------------------------------------------------------------------- |
| 141 | |
| 142 | // ---------------------------------------------------------------------------- |
| 143 | // Combinational |
| 144 | // ---------------------------------------------------------------------------- |
| 145 | |
| 146 | // addresses |
| 147 | assign aadr = tcb2tdb_sel ? vtb2tdb_dbra : csr2tdb_ra; |
| 148 | assign badr = tcb2tdb_sel ? tcb2tdb_wa : csr2tdb_wa; |
| 149 | |
| 150 | // data in |
| 151 | assign dib[`FIRE_DLC_MMU_TDR_MINUS_PAR_BITS] = tcb2tdb_sel ? |
| 152 | tlb2tdb_data[`FIRE_DLC_MMU_TDR_MINUS_PAR_BITS] : csr2tdb_wd[`FIRE_DLC_MMU_TDR_MINUS_PAR_BITS]; |
| 153 | // assign dib[`FIRE_DLC_MMU_TDR_PAR_BITS] = 4'b0; |
| 154 | assign par[3] = ^{dib[`FIRE_DLC_MMU_TDR_KEY_MSB:`FIRE_DLC_MMU_TDR_KEY_LSB+4]}; |
| 155 | assign par[2] = ^{dib[`FIRE_DLC_MMU_TDR_KEY_LSB+3:`FIRE_DLC_MMU_TDR_KEY_LSB],dib[`FIRE_DLC_MMU_TDR_PPN_MSB:`FIRE_DLC_MMU_TDR_PPN_MSB-7]}; |
| 156 | assign par[1] = ^dib[`FIRE_DLC_MMU_TDR_PPN_MSB-8:`FIRE_DLC_MMU_TDR_PPN_LSB+6]; |
| 157 | assign par[0] = ^{dib[`FIRE_DLC_MMU_TDR_PPN_LSB+5:`FIRE_DLC_MMU_TDR_PPN_LSB],dib[5:1], |
| 158 | (dib[0] ^ dsn_dmc_iei)}; |
| 159 | |
| 160 | assign dib[`FIRE_DLC_MMU_TDR_PAR_MSB] = par[3] ? 1'b0 : 1'b1; |
| 161 | assign dib[`FIRE_DLC_MMU_TDR_PAR_MSB-1] = par[2] ? 1'b0 : 1'b1; |
| 162 | assign dib[`FIRE_DLC_MMU_TDR_PAR_MSB-2] = par[1] ? 1'b0 : 1'b1; |
| 163 | assign dib[`FIRE_DLC_MMU_TDR_PAR_MSB-3] = par[0] ? 1'b0 : 1'b1; |
| 164 | |
| 165 | |
| 166 | // data out |
| 167 | assign tdb2csr_rd = doa; |
| 168 | |
| 169 | assign tdb2pab_par = doa[`FIRE_DLC_MMU_TDR_PAR_BITS]; |
| 170 | assign tdb2pab_key = doa[`FIRE_DLC_MMU_TDR_KEY_BITS]; |
| 171 | assign tdb2pab_ppn = doa[`FIRE_DLC_MMU_TDR_PPN_BITS]; |
| 172 | assign tdb2pab_fnm = doa[`FIRE_DLC_MMU_TDR_FNM_BITS]; |
| 173 | wire tdb2pab_keyvld = doa[`FIRE_DLC_MMU_TDR_KEYVLD_BITS]; |
| 174 | wire tdb2pab_wrt = doa[`FIRE_DLC_MMU_TDR_WRT_BITS]; |
| 175 | wire tdb2pab_vld = doa[`FIRE_DLC_MMU_TDR_VLD_BITS]; |
| 176 | |
| 177 | assign tdb2tmc_kerr = doa[`FIRE_DLC_MMU_TDR_KEYVLD_BITS] && |
| 178 | ~((tlb2tdb_rqid & {{13{1'b1}},doa[`FIRE_DLC_MMU_TDR_FNM_BITS]}) == |
| 179 | (doa[`FIRE_DLC_MMU_TDR_KEY_BITS] & {{13{1'b1}},doa[`FIRE_DLC_MMU_TDR_FNM_BITS]})); |
| 180 | |
| 181 | // write enables |
| 182 | wire web = tcb2tdb_sel ? tcb2tdb_we : csr2tdb_we; |
| 183 | |
| 184 | // ---------------------------------------------------------------------------- |
| 185 | // Instantiations |
| 186 | // ---------------------------------------------------------------------------- |
| 187 | /* |
| 188 | fire_dlc_ram512x36_211hd4 ram |
| 189 | ( |
| 190 | // address ports |
| 191 | .aadr (aadr), |
| 192 | .badr (badr), |
| 193 | |
| 194 | // clock ports |
| 195 | .clka (l2clk), |
| 196 | .clkb (l2clk), |
| 197 | |
| 198 | // data input ports |
| 199 | .dib (dib), |
| 200 | |
| 201 | // data output ports |
| 202 | .doa (doa), |
| 203 | |
| 204 | // port enables |
| 205 | .ena (1'b1), |
| 206 | .enb (1'b1), |
| 207 | |
| 208 | // write enables |
| 209 | .web (web) |
| 210 | ); |
| 211 | */ |
| 212 | wire [7:0] spare; |
| 213 | |
| 214 | //BP n2 6-11-04 new ram model |
| 215 | //BP n2 9-23-04 scan bypass |
| 216 | // note, tlb2tdb_data comes from flops in the tlb block, since tlb2tdb_data is short |
| 217 | // by the parity bits, I duplicate 4 of them to finish it |
| 218 | wire [`FIRE_DLC_MMU_TDR_BITS] tdb_ram_out; |
| 219 | assign doa = tcu_array_bypass ? {tlb2tdb_data[3:0],tlb2tdb_data} : tdb_ram_out; |
| 220 | |
| 221 | //SV 02/24/05 added BIST logic |
| 222 | wire [59:0] din_ram ; |
| 223 | wire [8:0] rd_addr_ram, wr_addr_ram ; |
| 224 | wire wr_en_ram, rd_en_ram ; |
| 225 | |
| 226 | assign tdb_dout_8msb = spare[7:0] ; |
| 227 | assign din_ram = dmu_mb0_run ? ({dmu_mb0_wdata[3:0],{7{dmu_mb0_wdata}}}) : ({{8{1'b0}},dib}) ; |
| 228 | assign rd_addr_ram = dmu_mb0_run ? dmu_mb0_addr : aadr ; |
| 229 | assign wr_addr_ram = dmu_mb0_run ? dmu_mb0_addr : badr ; |
| 230 | assign wr_en_ram = dmu_mb0_run ? dmu_mb0_tdb_wr_en : web ; |
| 231 | assign rd_en_ram = dmu_mb0_run ? dmu_mb0_tdb_rd_en : 1'b1 ; |
| 232 | |
| 233 | /* 0in memory_access -read_addr aadr -read (aadr != badr) |
| 234 | -write_addr badr -write web |
| 235 | -latency 1 |
| 236 | -write_data {{8{1'b0}},dib} -read_data {spare,tdb_ram_out} |
| 237 | -active (~dmu_mb0_run) |
| 238 | -group mbist_mode |
| 239 | */ |
| 240 | |
| 241 | |
| 242 | n2_dmu_dp_512x60s_cust tdb_ram512x60 |
| 243 | ( |
| 244 | // address ports |
| 245 | .rd_addr (rd_addr_ram), |
| 246 | .wr_addr (wr_addr_ram), |
| 247 | |
| 248 | // clock ports |
| 249 | .clk (l2clk), |
| 250 | |
| 251 | // data input ports |
| 252 | .din (din_ram), |
| 253 | |
| 254 | // data output ports |
| 255 | .dout ({spare,tdb_ram_out}), |
| 256 | |
| 257 | // port enables |
| 258 | .rd_en (rd_en_ram), |
| 259 | .wr_en (wr_en_ram), |
| 260 | |
| 261 | // scan ports |
| 262 | .scan_in (scan_in), |
| 263 | .tcu_scan_en (tcu_scan_en), |
| 264 | .tcu_se_scancollar_in (tcu_se_scancollar_in), |
| 265 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), |
| 266 | .tcu_pce_ov (tcu_pce_ov), |
| 267 | .pce (1'b1), |
| 268 | .tcu_aclk (tcu_aclk), |
| 269 | .tcu_bclk (tcu_bclk), |
| 270 | .scan_out (scan_out) |
| 271 | ); |
| 272 | |
| 273 | endmodule // dmu_mmu_tdb |