| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_psb_dbg.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_psb_dbg |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | |
| 40 | // PSB |
| 41 | cr2ps_dbg_sel_a, // PSB debug select a |
| 42 | cr2ps_dbg_sel_b, // PSB debug select b |
| 43 | |
| 44 | ps2cr_dbg_a, // PSB debug output a |
| 45 | ps2cr_dbg_b, // PSB debug output b |
| 46 | |
| 47 | // PTG |
| 48 | dbg2ptg_dbg_sel_a, // PTG debug select a |
| 49 | dbg2ptg_dbg_sel_b, // PTG debug select b |
| 50 | |
| 51 | ptg2dbg_dbg_a, // PTG debug output a |
| 52 | ptg2dbg_dbg_b, // PTG debug output b |
| 53 | |
| 54 | // PDL |
| 55 | dbg2pdl_dbg_sel_a, // PDL debug select a |
| 56 | dbg2pdl_dbg_sel_b, // PDL debug select b |
| 57 | |
| 58 | pdl2dbg_dbg_a, // PDL debug output a |
| 59 | pdl2dbg_dbg_b, // PDL debug output b |
| 60 | |
| 61 | // PIC |
| 62 | dbg2pic_dbg_sel_a, // PIC debug select a |
| 63 | dbg2pic_dbg_sel_b, // PIC debug select b |
| 64 | |
| 65 | pic2dbg_dbg_a, // PIC debug output a |
| 66 | pic2dbg_dbg_b, // PIC debug output b |
| 67 | |
| 68 | // PCE |
| 69 | dbg2pce_dbg_sel_a, // PCE debug select a |
| 70 | dbg2pce_dbg_sel_b, // PCE debug select b |
| 71 | |
| 72 | pce2dbg_dbg_a, // PCE debug output a |
| 73 | pce2dbg_dbg_b // PCE debug output b |
| 74 | ); |
| 75 | |
| 76 | // synopsys sync_set_reset "rst_l" |
| 77 | |
| 78 | //************************************************ |
| 79 | // PORTS |
| 80 | //************************************************ |
| 81 | |
| 82 | input clk; |
| 83 | input rst_l; |
| 84 | |
| 85 | // PSB Debug |
| 86 | input [5:0] cr2ps_dbg_sel_a; |
| 87 | input [5:0] cr2ps_dbg_sel_b; |
| 88 | output [`FIRE_DBG_DATA_BITS] ps2cr_dbg_a; |
| 89 | output [`FIRE_DBG_DATA_BITS] ps2cr_dbg_b; |
| 90 | |
| 91 | // PTG debug |
| 92 | input [`FIRE_DBG_DATA_BITS] ptg2dbg_dbg_a; |
| 93 | input [`FIRE_DBG_DATA_BITS] ptg2dbg_dbg_b; |
| 94 | output [2:0] dbg2ptg_dbg_sel_a; |
| 95 | output [2:0] dbg2ptg_dbg_sel_b; |
| 96 | |
| 97 | // PDL debug |
| 98 | input [`FIRE_DBG_DATA_BITS] pdl2dbg_dbg_a; |
| 99 | input [`FIRE_DBG_DATA_BITS] pdl2dbg_dbg_b; |
| 100 | output [2:0] dbg2pdl_dbg_sel_a; |
| 101 | output [2:0] dbg2pdl_dbg_sel_b; |
| 102 | |
| 103 | // PIC debug |
| 104 | input [`FIRE_DBG_DATA_BITS] pic2dbg_dbg_a; |
| 105 | input [`FIRE_DBG_DATA_BITS] pic2dbg_dbg_b; |
| 106 | output [2:0] dbg2pic_dbg_sel_a; |
| 107 | output [2:0] dbg2pic_dbg_sel_b; |
| 108 | |
| 109 | // PCE debug |
| 110 | input [`FIRE_DBG_DATA_BITS] pce2dbg_dbg_a; |
| 111 | input [`FIRE_DBG_DATA_BITS] pce2dbg_dbg_b; |
| 112 | output [2:0] dbg2pce_dbg_sel_a; |
| 113 | output [2:0] dbg2pce_dbg_sel_b; |
| 114 | |
| 115 | |
| 116 | //************************************************ |
| 117 | // SIGNALS |
| 118 | //************************************************ |
| 119 | |
| 120 | // Debug Port Interface |
| 121 | |
| 122 | // PSB |
| 123 | wire [5:0] cr2ps_dbg_sel_a; // PSB debug select a |
| 124 | wire [5:0] cr2ps_dbg_sel_b; // PSB debug select b |
| 125 | |
| 126 | wire [`FIRE_DBG_DATA_BITS] ps2cr_dbg_a; // PSB debug output a |
| 127 | wire [`FIRE_DBG_DATA_BITS] ps2cr_dbg_b; // PSB debug output b |
| 128 | |
| 129 | // PTG |
| 130 | wire [2:0] dbg2ptg_dbg_sel_a; // PTG debug select a |
| 131 | wire [2:0] dbg2ptg_dbg_sel_b; // PTG debug select b |
| 132 | |
| 133 | wire [`FIRE_DBG_DATA_BITS] ptg2dbg_dbg_a; // PTG debug output a |
| 134 | wire [`FIRE_DBG_DATA_BITS] ptg2dbg_dbg_b; // PTG debug output b |
| 135 | |
| 136 | // PDL |
| 137 | wire [2:0] dbg2pdl_dbg_sel_a; // PDL debug select a |
| 138 | wire [2:0] dbg2pdl_dbg_sel_b; // PDL debug select b |
| 139 | |
| 140 | wire [`FIRE_DBG_DATA_BITS] pdl2dbg_dbg_a; // PDL debug output a |
| 141 | wire [`FIRE_DBG_DATA_BITS] pdl2dbg_dbg_b; // PDL debug output b |
| 142 | |
| 143 | // PIC |
| 144 | wire [2:0] dbg2pic_dbg_sel_a; // PIC debug select a |
| 145 | wire [2:0] dbg2pic_dbg_sel_b; // PIC debug select b |
| 146 | |
| 147 | wire [`FIRE_DBG_DATA_BITS] pic2dbg_dbg_a; // PIC debug output a |
| 148 | wire [`FIRE_DBG_DATA_BITS] pic2dbg_dbg_b; // PIC debug output b |
| 149 | |
| 150 | // PCE |
| 151 | wire [2:0] dbg2pce_dbg_sel_a; // PCE debug select a |
| 152 | wire [2:0] dbg2pce_dbg_sel_b; // PCE debug select b |
| 153 | |
| 154 | wire [`FIRE_DBG_DATA_BITS] pce2dbg_dbg_a; // PCE debug output a |
| 155 | wire [`FIRE_DBG_DATA_BITS] pce2dbg_dbg_b; // PCE debug output b |
| 156 | |
| 157 | // *************** Local Declarations ************************************* |
| 158 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; |
| 159 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1]; |
| 160 | |
| 161 | integer i; |
| 162 | |
| 163 | //************************************************ |
| 164 | // Zero In checkers |
| 165 | //************************************************ |
| 166 | |
| 167 | |
| 168 | // *************** Procedures ************************************* |
| 169 | |
| 170 | // ********************** signal registers *************************/ |
| 171 | |
| 172 | always @ (cr2ps_dbg_sel_a or ptg2dbg_dbg_a or pdl2dbg_dbg_a |
| 173 | or pic2dbg_dbg_a or pce2dbg_dbg_a) |
| 174 | begin |
| 175 | case (cr2ps_dbg_sel_a[5:3]) // synopsys infer_mux |
| 176 | 3'b000: nxt_dbg_bus[0] = ptg2dbg_dbg_a; |
| 177 | 3'b001: nxt_dbg_bus[0] = pdl2dbg_dbg_a; |
| 178 | 3'b010: nxt_dbg_bus[0] = pic2dbg_dbg_a; |
| 179 | 3'b011: nxt_dbg_bus[0] = pce2dbg_dbg_a; |
| 180 | 3'b100: nxt_dbg_bus[0] = 8'h00; |
| 181 | 3'b101: nxt_dbg_bus[0] = 8'h00; |
| 182 | 3'b110: nxt_dbg_bus[0] = 8'h00; |
| 183 | 3'b111: nxt_dbg_bus[0] = 8'h00; |
| 184 | endcase // case(cr2ps_dbg_sel_a[5:3]) |
| 185 | end // always @ (cr2ps_dbg_sel_a or ptg2dbg_dbg_a or pdl2dbg_dbg_a... |
| 186 | |
| 187 | always @ (cr2ps_dbg_sel_b or ptg2dbg_dbg_b or pdl2dbg_dbg_b |
| 188 | or pic2dbg_dbg_b or pce2dbg_dbg_b ) |
| 189 | begin |
| 190 | case (cr2ps_dbg_sel_b[5:3]) // synopsys infer_mux |
| 191 | 3'b000: nxt_dbg_bus[1] = ptg2dbg_dbg_b; |
| 192 | 3'b001: nxt_dbg_bus[1] = pdl2dbg_dbg_b; |
| 193 | 3'b010: nxt_dbg_bus[1] = pic2dbg_dbg_b; |
| 194 | 3'b011: nxt_dbg_bus[1] = pce2dbg_dbg_b; |
| 195 | 3'b100: nxt_dbg_bus[1] = 8'h00; |
| 196 | 3'b101: nxt_dbg_bus[1] = 8'h00; |
| 197 | 3'b110: nxt_dbg_bus[1] = 8'h00; |
| 198 | 3'b111: nxt_dbg_bus[1] = 8'h00; |
| 199 | endcase // case(cr2ps_dbg_sel_b[5:3]) |
| 200 | end // always @ (cr2ps_dbg_sel_b or ptg2dbg_dbg_b or pdl2dbg_dbg_b... |
| 201 | |
| 202 | // ********************** Output Procedures ***********************/ |
| 203 | |
| 204 | always @ (posedge clk) |
| 205 | begin |
| 206 | if(~rst_l) |
| 207 | for (i = 0; i < 2; i = i + 1) |
| 208 | dbg_bus[i] <= 8'h00; |
| 209 | else |
| 210 | for (i = 0; i < 2; i = i + 1) |
| 211 | dbg_bus[i] <= nxt_dbg_bus[i]; |
| 212 | end // always @ (posedge clk) |
| 213 | |
| 214 | |
| 215 | // ***********************Assignments *****************************/ |
| 216 | |
| 217 | // debug select ab data port distribution |
| 218 | assign dbg2ptg_dbg_sel_a = cr2ps_dbg_sel_a [2:0]; |
| 219 | assign dbg2ptg_dbg_sel_b = cr2ps_dbg_sel_b [2:0]; |
| 220 | assign dbg2pdl_dbg_sel_a = cr2ps_dbg_sel_a [2:0]; |
| 221 | assign dbg2pdl_dbg_sel_b = cr2ps_dbg_sel_b [2:0]; |
| 222 | assign dbg2pic_dbg_sel_a = cr2ps_dbg_sel_a [2:0]; |
| 223 | assign dbg2pic_dbg_sel_b = cr2ps_dbg_sel_b [2:0]; |
| 224 | assign dbg2pce_dbg_sel_a = cr2ps_dbg_sel_a [2:0]; |
| 225 | assign dbg2pce_dbg_sel_b = cr2ps_dbg_sel_b [2:0]; |
| 226 | |
| 227 | // Output |
| 228 | assign ps2cr_dbg_a = dbg_bus[0]; |
| 229 | assign ps2cr_dbg_b = dbg_bus[1]; |
| 230 | |
| 231 | endmodule // dmu_psb_dbg |
| 232 | |