| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_rmu_lrm_ictl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_rmu_lrm_ictl ( |
| 36 | |
| 37 | clk, |
| 38 | rst_l, |
| 39 | |
| 40 | // TMU Interface (DIM) - DIM Record |
| 41 | tm2rm_rcd, |
| 42 | tm2rm_rcd_enq, |
| 43 | rm2tm_rcd_full, |
| 44 | |
| 45 | // Inputs from IMU - Mondo Request Record |
| 46 | im2rm_mdo, |
| 47 | im2rm_mdo_enq, |
| 48 | |
| 49 | // Outputs to IMU - Interrupt In Record (RRM to IMU) |
| 50 | rm2im_rcd, |
| 51 | rm2im_rcd_enq, |
| 52 | |
| 53 | // LRM Sub-block Interface to Ingress TSB FSM - STD rcd |
| 54 | std_rcd, |
| 55 | std_rcd_enq, |
| 56 | std_rcd_deq, |
| 57 | |
| 58 | // Input from IMU - used to flow control IIN rcds |
| 59 | iot_rcd_deq, |
| 60 | |
| 61 | // Output to RMU - PIO WR Release |
| 62 | lrm2rrm_cpl, |
| 63 | lrm2rrm_cpl_enq, |
| 64 | |
| 65 | // Output (local) for Debug Visibility |
| 66 | fork_type, |
| 67 | sr_dim_deq, |
| 68 | sr_dim_empty, |
| 69 | iot_credit_ok, |
| 70 | ld_iin_mdo_reg, |
| 71 | mdo_fifo_empty, |
| 72 | std_credit_ok |
| 73 | |
| 74 | ); |
| 75 | |
| 76 | // synopsys sync_set_reset "rst_l" |
| 77 | |
| 78 | //############################################################################ |
| 79 | // PORT DECLARATIONS |
| 80 | //############################################################################ |
| 81 | |
| 82 | //------------------------------------------------------------------------ |
| 83 | // Clock and Reset Signals |
| 84 | //------------------------------------------------------------------------ |
| 85 | input clk; |
| 86 | input rst_l; |
| 87 | |
| 88 | |
| 89 | //------------------------------------------------------------------------ |
| 90 | // TMU Interface |
| 91 | //------------------------------------------------------------------------ |
| 92 | |
| 93 | // Ingress pipeline interface - 123 bit DIM RECORD (DIM to LRM) |
| 94 | input [`FIRE_DLC_DIM_REC_WDTH-1:0] tm2rm_rcd; |
| 95 | input tm2rm_rcd_enq; |
| 96 | output rm2tm_rcd_full; |
| 97 | |
| 98 | //------------------------------------------------------------------------ |
| 99 | // IMU Interface |
| 100 | //------------------------------------------------------------------------ |
| 101 | |
| 102 | // Mondo Requests from IMU - 15 bit Mondo ReQuest Record (IMU to LRM) |
| 103 | input [`FIRE_DLC_MQR_REC_WDTH-1:0] im2rm_mdo; |
| 104 | input im2rm_mdo_enq; |
| 105 | |
| 106 | // Interrupt In Record - 131 bit IIN Record (LRM to IMU) |
| 107 | output [`FIRE_DLC_IIN_REC_WDTH-1:0] rm2im_rcd; |
| 108 | output rm2im_rcd_enq; |
| 109 | |
| 110 | |
| 111 | //------------------------------------------------------------------------ |
| 112 | // Internal LRM Interface to LRM Output Ingress TSB FSM Module |
| 113 | //------------------------------------------------------------------------ |
| 114 | |
| 115 | // Standard Records that are being sent up Ingress Pipeline - includes lrmtag |
| 116 | output [`FIRE_DLC_RMU_LRM_WDTH-1:0] std_rcd; // 131 bit Std Rcd |
| 117 | output std_rcd_enq; // Std Rcd FIFO Enqueue |
| 118 | input std_rcd_deq; // SR STD rcd Dequeue |
| 119 | |
| 120 | input iot_rcd_deq; // Dequeue Intr Out Rcd input |
| 121 | |
| 122 | //------------------------------------------------------------------------ |
| 123 | // Sub-Block Interface to RRM |
| 124 | //------------------------------------------------------------------------ |
| 125 | |
| 126 | // PIO Transaction Credit Recorda - 4 bits |
| 127 | |
| 128 | output [`FIRE_DLC_RMU_LRM_REL_WDTH-1:0] lrm2rrm_cpl; |
| 129 | output lrm2rrm_cpl_enq; |
| 130 | |
| 131 | |
| 132 | //------------------------------------------------------------------------ |
| 133 | // Outputs for Debug Port Visibility |
| 134 | //------------------------------------------------------------------------ |
| 135 | |
| 136 | output [1:0] fork_type; // Ingress Trans Type Decoder |
| 137 | output sr_dim_deq; // Dequeue DIM record from SR FIFO |
| 138 | output sr_dim_empty; // Output from DIM SR FIFO |
| 139 | output iot_credit_ok; // LRM has credit for IOT Rcds |
| 140 | output ld_iin_mdo_reg; // Load IIN rcd from Mondo FIFO |
| 141 | output mdo_fifo_empty; // Output from Mondo ReQuest FIFO |
| 142 | output std_credit_ok; // Std Rcd FIFO has room |
| 143 | |
| 144 | |
| 145 | |
| 146 | //############################################################################ |
| 147 | // PARAMETERS |
| 148 | //############################################################################ |
| 149 | |
| 150 | // Ingress Transaction Type Decoder - either continue up INGRESS or Fork to IMU |
| 151 | parameter |
| 152 | FORK_INGRESS = 2'b00, // DMA or (Posted) PIO header - continue up Ingress Pipeline |
| 153 | FORK_IMU = 2'b01, // MSG or MSI Type - fork to IMU for Servicing |
| 154 | FORK_RMU = 2'b10, // Non Posted PIO Wr Completion |
| 155 | UNKNOWN_TYPE = 2'b11; // For zero in |
| 156 | |
| 157 | // Ingress Command Type Decoder Parameter |
| 158 | |
| 159 | parameter |
| 160 | DMA_MRD32 = 7'b0000000, |
| 161 | DMA_MRD64 = 7'b0100000, |
| 162 | DMA_MRDLK32 = 7'b0000001, |
| 163 | DMA_MRDLK64 = 7'b0100001, |
| 164 | DMA_MWR32 = 7'b1000000, |
| 165 | DMA_MWR64 = 7'b1100000, |
| 166 | PIO_CPL = 7'b0001010, |
| 167 | PIO_CPLD = 7'b1001010, |
| 168 | DMA_UR = 7'b0001001, |
| 169 | MSG = 7'b0110zzz, |
| 170 | MSI_32 = 7'b1011000, // Need to find out more info wrt MSI's |
| 171 | MSI_64 = 7'b1111000, |
| 172 | MONDO = 7'b1111010; // Identifies MONDO type out from LRM sub-block |
| 173 | |
| 174 | |
| 175 | // Ingress LRM SR FIFO (DIM Records) DEPTH and WIDTH Parameters |
| 176 | |
| 177 | parameter |
| 178 | DIM_SR_DEPTH = 6, // 6 Entry FIFO per MAS 2.0 spec |
| 179 | DIM_SR_WIDTH = `FIRE_DLC_DIM_REC_WDTH; // DIM record currently 123 bits wide |
| 180 | |
| 181 | //------------------------------------------------------------------------------------------- |
| 182 | // Parameters to be passed into Common Simple FIFO |
| 183 | // MDO_WDTH = `FIRE_DLC_MQR_REC_WDTH = 14 bit Mondo Request from IMU |
| 184 | // MDO_DPTH = 3'd4 = Max sized to 4 Mondo's |
| 185 | // MDO_PTR_WDTH = 2 = |
| 186 | // MDO_DPTH_MINUSONE = 2'd3 = Depth-1 |
| 187 | //------------------------------------------------------------------------------------------- |
| 188 | |
| 189 | parameter |
| 190 | MDO_WDTH = `FIRE_DLC_MQR_REC_WDTH, |
| 191 | MDO_DPTH = 3'd4, |
| 192 | MDO_PTR_WDTH = 2, |
| 193 | MDO_DPTH_MINUSONE = 2'd3; |
| 194 | |
| 195 | |
| 196 | //############################################################################ |
| 197 | // DECLARE Module Wires and Registers |
| 198 | //############################################################################ |
| 199 | |
| 200 | wire [`FIRE_DLC_RMU_LRM_WDTH-1:0] std_rcd; // DIM record + lrmtag Std SR FIFO |
| 201 | // 123+8 = 131 bit Record |
| 202 | |
| 203 | wire mdo_fifo_empty; // Output from Mondo ReQuest FIFO |
| 204 | wire sr_dim_empty; // Output from DIM SR FIFO |
| 205 | |
| 206 | //-------------------------------------------------- |
| 207 | // Internal Sub-Block Wires |
| 208 | //-------------------------------------------------- |
| 209 | |
| 210 | // Ingress DIM Record fields out of the SR fifo - 70 bit ERR record |
| 211 | |
| 212 | wire [`FIRE_DLC_DIM_REC_WDTH-1:0] sr_dim_dout; // Entire 123 bit DIM Record |
| 213 | wire [`FIRE_DLC_DIM_TYPE_WDTH-1:0] sr_dim_type; // 7 bit Type Field |
| 214 | wire sr_dim_piowr; // decoded bit that signifies NonPosted |
| 215 | // PIO Wr completion - to be forked to RMU |
| 216 | |
| 217 | wire [`FIRE_DLC_DIM_REC_WDTH-1:0] next_iin_reg; // Int In Rcd Generation - less lrm tag |
| 218 | |
| 219 | wire [`FIRE_DLC_MQR_REC_WDTH-1:0] mdo_fifo_dout; // 15 bit Mondo Req Rcd out of FIFO |
| 220 | |
| 221 | wire ld_iin_rcd; // Load Enable for IIN record |
| 222 | wire mdo_fifo_deq; // Dequeue signal to Mondo Simple FIFO |
| 223 | wire iot_credit_ok; // LRM has credit for IOT Rcds |
| 224 | wire std_credit_ok; // Std Rcd FIFO has room |
| 225 | |
| 226 | wire [`FIRE_DLC_IIN_LRMTAG_WDTH-1:0] next_lrmtag; // TTAG for merge logic in Pipeline |
| 227 | wire [`FIRE_DLC_IIN_LRMTAG_WDTH-1:0] lrmtag_plusone; // Incremented version of TTAG |
| 228 | |
| 229 | wire [`FIRE_DLC_RMU_LRM_REL_WDTH-1:0] sr_dim_piotag; // 4 bit pio_tag taken from sr_dim_dout TAG |
| 230 | |
| 231 | |
| 232 | //-------------------------------------------------- |
| 233 | // Registers that Are Not Flops |
| 234 | //-------------------------------------------------- |
| 235 | |
| 236 | // Output from Combinatorial Decode of sr_dim_dout - type field from DIM record |
| 237 | reg [1:0] fork_type; // LRM Transaction Type Decoder |
| 238 | |
| 239 | // Combinatorial Outputs from Ingress Control Logic block |
| 240 | reg ld_iin_mdo_reg; // Load IIN rcd from Mondo FIFO |
| 241 | reg ld_iin_dim_reg; // Load IIN rcd from DIM SR FIFO |
| 242 | reg ld_pio_cpl_reg; // Load 4 bit PIO Tag to be Released |
| 243 | reg incr_lrmtag; // Increment LRM transmit tag |
| 244 | reg sr_dim_deq; // Dequeue DIM record from SR FIFO |
| 245 | reg std_rcd_enq; // Enqueue signal to STD Rcd FIFO |
| 246 | |
| 247 | |
| 248 | //-------------------------------------------------- |
| 249 | // Registers that Are Flops |
| 250 | //-------------------------------------------------- |
| 251 | |
| 252 | reg [3:0] iot_credit_count, next_iot_credit_count; // IIN, IOT Rcd Credit Mechanism |
| 253 | reg [2:0] std_credit_count, next_std_credit_count; // STD Rcd Credit Mechanism |
| 254 | |
| 255 | reg [`FIRE_DLC_DIM_REC_WDTH-1:0] iin_reg; // Interrupt In Record Generation |
| 256 | reg rm2im_rcd_enq; // Enqueue signal to IMU for IIN Rcd |
| 257 | |
| 258 | reg [`FIRE_DLC_IIN_LRMTAG_WDTH-1:0] lrmtag; // DIM Transmit Tag for Pipeline Merging |
| 259 | reg [`FIRE_DLC_IIN_LRMTAG_WDTH-1:0] imu_lrmtag; // IMU Transmit Tag for Pipeline Merging |
| 260 | // mtag is a synchronized version of lrmtag |
| 261 | reg [`FIRE_DLC_RMU_LRM_REL_WDTH-1:0] lrm2rrm_cpl; // PIOWR Completion (NP WR ack) to RRM |
| 262 | reg lrm2rrm_cpl_enq; // PIOWR Cpl Enqueue to RRM |
| 263 | |
| 264 | |
| 265 | //############################################################################ |
| 266 | // ZERO IN CHECKERS |
| 267 | //############################################################################ |
| 268 | |
| 269 | // 0in maximum -var iot_credit_count -val 8 |
| 270 | |
| 271 | // 0in maximum -var std_credit_count -val 5 |
| 272 | |
| 273 | // 0in known_driven -var fork_type -active ~sr_dim_empty |
| 274 | |
| 275 | // 0in maximum -var fork_type -val 2 |
| 276 | |
| 277 | // Intentional Redundant checks on fork_type - but wanted to ask if there is a |
| 278 | // benefit of using one type over another |
| 279 | |
| 280 | // Note: The following check triggered... values in dim_type = 0x36, 0x35, 0x34, 0x30 - test is eq_full_with_msg_twice |
| 281 | /* zeroin val |
| 282 | -var sr_dim_type |
| 283 | -val DMA_MRD32 |
| 284 | DMA_MRD64 |
| 285 | DMA_MRDLK32 |
| 286 | DMA_MRDLK64 |
| 287 | DMA_MWR32 |
| 288 | DMA_MWR64 |
| 289 | PIO_CPL |
| 290 | PIO_CPLD |
| 291 | DMA_UR |
| 292 | MSI_32 |
| 293 | MSI_64 |
| 294 | MSG |
| 295 | -active ~sr_dim_empty |
| 296 | -message "Illegal Type Field written into DIM Queue - LRM ictl module" |
| 297 | */ |
| 298 | |
| 299 | //############################################################################ |
| 300 | // COMBINATORIAL LOGIC |
| 301 | //############################################################################ |
| 302 | |
| 303 | //-------------------------------------------------------------------- |
| 304 | // Outgoing IIN Record to IMU, or Outgoing DIM Record to Std Rcd Queue |
| 305 | //-------------------------------------------------------------------- |
| 306 | |
| 307 | assign rm2im_rcd = { iin_reg, |
| 308 | imu_lrmtag }; |
| 309 | |
| 310 | assign std_rcd = { sr_dim_dout, |
| 311 | lrmtag }; |
| 312 | |
| 313 | // Want to make sure that identical tags are never seen... checker will be in lrm_octl module |
| 314 | |
| 315 | |
| 316 | //---------------------------------------------------------------------- |
| 317 | // Signal that indicates that LRM has credit to hold IOT record from IMU |
| 318 | //---------------------------------------------------------------------- |
| 319 | |
| 320 | assign iot_credit_ok = |iot_credit_count; // If Credit is 1-8, then OK!! |
| 321 | // If Credit is 0 - NOT ok! IOT SR full |
| 322 | |
| 323 | assign std_credit_ok = |std_credit_count; // If Credit is 1-5, then OK!! |
| 324 | // If Credit is 0 - NOT ok! IOT SR full |
| 325 | |
| 326 | //------------------------------------------------------------------------------ |
| 327 | // DIM Record Type Field needed to determine whether IMU needs to service Record |
| 328 | //------------------------------------------------------------------------------ |
| 329 | |
| 330 | assign sr_dim_type = sr_dim_dout[`FIRE_DLC_DIM_TYPE_MSB:`FIRE_DLC_DIM_TYPE_LSB]; |
| 331 | |
| 332 | assign sr_dim_piotag = sr_dim_dout[`FIRE_DLC_DIM_TAG_LSB+3:`FIRE_DLC_DIM_TAG_LSB]; |
| 333 | assign sr_dim_piowr = sr_dim_dout[`FIRE_DLC_DIM_TAG_LSB+4]; // if 1 - PIOWR Cpl |
| 334 | |
| 335 | |
| 336 | //---------------------------------------------------------- |
| 337 | // Ingress DIM Record Type Decode Logic - fork to IMU or SRM |
| 338 | //---------------------------------------------------------- |
| 339 | |
| 340 | |
| 341 | always @ (sr_dim_type or sr_dim_piowr or sr_dim_empty) |
| 342 | begin |
| 343 | if (sr_dim_empty) |
| 344 | fork_type = FORK_INGRESS; |
| 345 | |
| 346 | else |
| 347 | casez (sr_dim_type) // 0in < case -parallel -default |
| 348 | DMA_MRD32 : fork_type = FORK_INGRESS; |
| 349 | DMA_MRD64 : fork_type = FORK_INGRESS; |
| 350 | DMA_MRDLK32 : fork_type = FORK_INGRESS; |
| 351 | DMA_MRDLK64 : fork_type = FORK_INGRESS; |
| 352 | DMA_MWR32 : fork_type = FORK_INGRESS; |
| 353 | DMA_MWR64 : fork_type = FORK_INGRESS; |
| 354 | PIO_CPL : fork_type = sr_dim_piowr ? FORK_RMU : FORK_INGRESS; |
| 355 | PIO_CPLD : fork_type = FORK_INGRESS; |
| 356 | DMA_UR : fork_type = FORK_INGRESS; |
| 357 | MSI_32 : fork_type = FORK_IMU; |
| 358 | MSI_64 : fork_type = FORK_IMU; |
| 359 | MSG : fork_type = FORK_IMU; // Using casez to match MSG type |
| 360 | |
| 361 | // Zero In Check for INVALID decode if FIFO is not empty |
| 362 | default : fork_type = UNKNOWN_TYPE; |
| 363 | |
| 364 | endcase |
| 365 | end |
| 366 | |
| 367 | |
| 368 | //----------------------------------------------------------------------------- |
| 369 | // LRM Ingress Control Logic - Controls both the Mondo FIFO and the DIM SR FIFO |
| 370 | //----------------------------------------------------------------------------- |
| 371 | |
| 372 | assign mdo_fifo_deq = ld_iin_mdo_reg; // explicit signal to Mondo simple_fifo |
| 373 | |
| 374 | |
| 375 | always @ (mdo_fifo_empty or sr_dim_empty or iot_credit_ok or fork_type or std_credit_ok) |
| 376 | |
| 377 | begin |
| 378 | ld_iin_mdo_reg = 1'b0; // Saves some typing - Defaults for |
| 379 | ld_iin_dim_reg = 1'b0; // when FIFO's are not empty |
| 380 | ld_pio_cpl_reg = 1'b0; |
| 381 | incr_lrmtag = 1'b0; |
| 382 | sr_dim_deq = 1'b0; |
| 383 | std_rcd_enq = 1'b0; |
| 384 | |
| 385 | if (~mdo_fifo_empty & iot_credit_ok) // Mondo FIFO has highest priority! |
| 386 | begin |
| 387 | ld_iin_mdo_reg = 1'b1; // Deq's Mondo FIFO, assert next_rm2im_rcd_enq |
| 388 | incr_lrmtag = 1'b1; // Increment lrmtag! |
| 389 | end |
| 390 | |
| 391 | else if (~sr_dim_empty) // SR FIFO has valid DIM record at output! |
| 392 | begin |
| 393 | case (fork_type) // 0in < case -full |
| 394 | |
| 395 | FORK_INGRESS : |
| 396 | begin |
| 397 | if (std_credit_ok) |
| 398 | begin |
| 399 | sr_dim_deq = 1'b1; // Deq SR FIFO |
| 400 | std_rcd_enq = 1'b1; // Enqueue DIM rcd to Std Rcd SR |
| 401 | incr_lrmtag = 1'b1; // Increment lrmtag! |
| 402 | end |
| 403 | else |
| 404 | begin |
| 405 | sr_dim_deq = 1'b0; // Std Rcd FIFO is full - hold up |
| 406 | std_rcd_enq = 1'b0; |
| 407 | incr_lrmtag = 1'b0; |
| 408 | end |
| 409 | end |
| 410 | |
| 411 | FORK_IMU : |
| 412 | begin |
| 413 | if (iot_credit_ok) |
| 414 | begin |
| 415 | sr_dim_deq = 1'b1; // Dequeue MSI or MSG from Rcd In FIFO |
| 416 | ld_iin_dim_reg = 1'b1; // Load IIN rcd from DIM, assert next_rm2im_rcd_enq |
| 417 | incr_lrmtag = 1'b1; // Increment lrmtag |
| 418 | end |
| 419 | else |
| 420 | begin |
| 421 | sr_dim_deq = 1'b0; // LRM IOT FIFO full - Wait for Credit |
| 422 | ld_iin_dim_reg = 1'b0; |
| 423 | incr_lrmtag = 1'b0; |
| 424 | end |
| 425 | end |
| 426 | |
| 427 | FORK_RMU : // Non Posted PIO Wr (Io/Config) |
| 428 | begin |
| 429 | sr_dim_deq = 1'b1; // Dequeue DIM rcd and |
| 430 | ld_pio_cpl_reg = 1'b1; // Ld CPL reg, Enq CPL rcd to RRM |
| 431 | end |
| 432 | |
| 433 | |
| 434 | endcase // ends fork_type case |
| 435 | end // ends sr_dim_empty begin |
| 436 | |
| 437 | else // Default values for when FIFO's are EMPTY |
| 438 | begin |
| 439 | ld_iin_mdo_reg = 1'b0; |
| 440 | ld_iin_dim_reg = 1'b0; |
| 441 | ld_pio_cpl_reg = 1'b0; |
| 442 | incr_lrmtag = 1'b0; |
| 443 | sr_dim_deq = 1'b0; |
| 444 | std_rcd_enq = 1'b0; |
| 445 | end |
| 446 | |
| 447 | end // Ends Always Block for Ingress Control Logic |
| 448 | |
| 449 | |
| 450 | |
| 451 | //############################################################################ |
| 452 | // SEQUENTIAL LOGIC |
| 453 | //############################################################################ |
| 454 | |
| 455 | //---------------------------------------------- |
| 456 | // LRM PIOWR Cpl (Release) Record generation |
| 457 | //---------------------------------------------- |
| 458 | |
| 459 | always @ (posedge clk) |
| 460 | if (~rst_l) |
| 461 | lrm2rrm_cpl <= {`FIRE_DLC_RMU_LRM_REL_WDTH{1'b0}}; |
| 462 | else if (ld_pio_cpl_reg) |
| 463 | lrm2rrm_cpl <= sr_dim_piotag; // 4 bit pio_tag to be released |
| 464 | else |
| 465 | lrm2rrm_cpl <= lrm2rrm_cpl; |
| 466 | |
| 467 | // LRM PIOWR Cpl (Release) Record generation |
| 468 | |
| 469 | always @ (posedge clk) |
| 470 | if (~rst_l) |
| 471 | lrm2rrm_cpl_enq <= 1'b0; |
| 472 | else |
| 473 | lrm2rrm_cpl_enq <= ld_pio_cpl_reg; // next_lrm2rrm_cpl_enq = ld_pio_cpl_reg |
| 474 | |
| 475 | |
| 476 | //----------------------------------------------------- |
| 477 | // Interrupt In Record Generation - LESS 8 bit LRM lrmtag |
| 478 | //----------------------------------------------------- |
| 479 | |
| 480 | always @ (posedge clk) |
| 481 | if (~rst_l) |
| 482 | iin_reg <= {`FIRE_DLC_DIM_REC_WDTH{1'b0}}; |
| 483 | else if (ld_iin_rcd) // IIN Load Enable = ld_iin_mdo | ld_in_dim |
| 484 | iin_reg <= next_iin_reg; |
| 485 | else |
| 486 | iin_reg <= iin_reg; |
| 487 | |
| 488 | // Interrupt In Record Enqueue Signal |
| 489 | |
| 490 | always @ (posedge clk) |
| 491 | if (~rst_l) |
| 492 | rm2im_rcd_enq <= 1'b0; |
| 493 | else |
| 494 | rm2im_rcd_enq <= ld_iin_rcd; // next_rm2im_rcd_enq = ld_iin_rcd |
| 495 | |
| 496 | |
| 497 | //----------------------------------------------------------- |
| 498 | // For Readability - will define next IIN record fields here! |
| 499 | //----------------------------------------------------------- |
| 500 | |
| 501 | // IIN register Load Enable Signal - spelled out for debug - Loading RRM from MDO or DIM record |
| 502 | assign ld_iin_rcd = ld_iin_mdo_reg | ld_iin_dim_reg; |
| 503 | |
| 504 | // IIN Record based on incoming MONDO from IMU - or MSI,MSG from TMU |
| 505 | assign next_iin_reg = ld_iin_mdo_reg ? |
| 506 | { MONDO, |
| 507 | `FIRE_DLC_IIN_TC_WDTH'b0, |
| 508 | `FIRE_DLC_IIN_ATR_WDTH'b0, |
| 509 | `FIRE_DLC_IIN_LEN_WDTH'b0, |
| 510 | 1'b0, mdo_fifo_dout, |
| 511 | `FIRE_DLC_IIN_TLPTAG_WDTH'b0, |
| 512 | `FIRE_DLC_IIN_DATA_WDTH'b0, |
| 513 | `FIRE_DLC_IIN_ADDR_WDTH'b0, |
| 514 | `FIRE_DLC_IIN_DPTR_WDTH'b0 } : sr_dim_dout; |
| 515 | |
| 516 | |
| 517 | //------------------------------------------------------------------------------------------ |
| 518 | // IOT rcd Credit Counter Logic - Determines whether the IIN rcd's can be Enqueued to IMU |
| 519 | //------------------------------------------------------------------------------------------ |
| 520 | |
| 521 | always @ (posedge clk) |
| 522 | if (~rst_l) |
| 523 | iot_credit_count <= 4'b1000; // Initially sized to IOT FIFO depth - 8 |
| 524 | else |
| 525 | iot_credit_count <= next_iot_credit_count; |
| 526 | |
| 527 | |
| 528 | always @ (ld_iin_rcd or iot_rcd_deq or iot_credit_count) |
| 529 | begin |
| 530 | next_iot_credit_count = 4'b0000; // Just for initialization |
| 531 | |
| 532 | case ({iot_rcd_deq, ld_iin_rcd}) // synopsys infer_mux |
| 533 | |
| 534 | (2'b01) : // Enqueueing IIN record |
| 535 | next_iot_credit_count = iot_credit_count - 1'b1; // Decrement LRM credit |
| 536 | (2'b10) : // Dequeueing Record from IOT SR |
| 537 | next_iot_credit_count = iot_credit_count + 1'b1; // Increment LRM credit |
| 538 | (2'b00), |
| 539 | (2'b11) : |
| 540 | next_iot_credit_count = iot_credit_count; // Credit Count Remains the Same |
| 541 | |
| 542 | endcase |
| 543 | end |
| 544 | |
| 545 | |
| 546 | //------------------------------------------------------------------------------------------ |
| 547 | // STD rcd Credit Counter Logic - Determines whether the STD rcd FIFO can be Enqueued |
| 548 | //------------------------------------------------------------------------------------------ |
| 549 | |
| 550 | always @ (posedge clk) |
| 551 | if (~rst_l) |
| 552 | std_credit_count <= 3'b100; // Initially sized to STD FIFO depth - 4 |
| 553 | else |
| 554 | std_credit_count <= next_std_credit_count; |
| 555 | |
| 556 | |
| 557 | always @ (std_rcd_enq or std_rcd_deq or std_credit_count) |
| 558 | begin |
| 559 | next_std_credit_count = 3'b000; |
| 560 | |
| 561 | case ({std_rcd_deq, std_rcd_enq}) // synopsys infer_mux |
| 562 | |
| 563 | (2'b01) : // Enqueueing STD record |
| 564 | next_std_credit_count = std_credit_count - 1'b1; // Decrement STD credit |
| 565 | (2'b10) : // Dequeueing Record from STD SR |
| 566 | next_std_credit_count = std_credit_count + 1'b1; // Increment STD credit |
| 567 | (2'b00), |
| 568 | (2'b11) : |
| 569 | next_std_credit_count = std_credit_count; // Credit Count Remains the Same |
| 570 | |
| 571 | endcase |
| 572 | end |
| 573 | |
| 574 | |
| 575 | //------------------------------ |
| 576 | // LRM Tag Manager Functionality |
| 577 | //------------------------------ |
| 578 | |
| 579 | always @ (posedge clk) |
| 580 | if (~rst_l) |
| 581 | begin |
| 582 | lrmtag <= `FIRE_DLC_IIN_LRMTAG_WDTH'b0; |
| 583 | imu_lrmtag <= `FIRE_DLC_IIN_LRMTAG_WDTH'b0; |
| 584 | end |
| 585 | |
| 586 | else |
| 587 | begin |
| 588 | lrmtag <= next_lrmtag; |
| 589 | imu_lrmtag <= lrmtag; // Synchronized lrmtag - ie: 1 clock delayed version to |
| 590 | end // IMU - this accounts for IIN registered output delay |
| 591 | |
| 592 | |
| 593 | // LRM Transmit Tag Logic is simply a counter |
| 594 | assign next_lrmtag = incr_lrmtag ? lrmtag_plusone : lrmtag; |
| 595 | assign lrmtag_plusone = lrmtag + 1'b1; |
| 596 | |
| 597 | |
| 598 | //############################################################################ |
| 599 | // MODULE INSTANTIATIONS |
| 600 | //############################################################################ |
| 601 | |
| 602 | |
| 603 | //------------------------------------------------------------------------- |
| 604 | // LRM Ingress DIM Record SR FIFO = (WIDTH) 123 * (DEPTH) 6 = 738 registers |
| 605 | //------------------------------------------------------------------------- |
| 606 | |
| 607 | fire_dmc_common_srfifo #(DIM_SR_WIDTH, DIM_SR_DEPTH) sr_dim_fifo ( |
| 608 | .clk (clk), |
| 609 | .rst_l (rst_l), |
| 610 | |
| 611 | .enq (tm2rm_rcd_enq), |
| 612 | .data_in (tm2rm_rcd), |
| 613 | |
| 614 | .deq (sr_dim_deq), |
| 615 | .data_out (sr_dim_dout), |
| 616 | |
| 617 | .full (rm2tm_rcd_full), |
| 618 | .empty (sr_dim_empty), |
| 619 | .overflow (), |
| 620 | .underflow () |
| 621 | ); |
| 622 | |
| 623 | //------------------------------------------------------------------------------------------- |
| 624 | // Parameters to be passed into Common Simple FIFO |
| 625 | // MDO_WDTH = `FIRE_DLC_MQR_REC_WDTH = 14 bit Mondo Request from IMU |
| 626 | // MDO_DPTH = 3'd4 = Max sized to 4 Mondo's |
| 627 | // MDO_PTR_WDTH = 2 = |
| 628 | // MDO_DPTH_MINUSONE = 2'd3 = Depth-1 |
| 629 | //------------------------------------------------------------------------------------------- |
| 630 | |
| 631 | |
| 632 | dmu_common_simple_fifo #(MDO_WDTH,MDO_DPTH,MDO_PTR_WDTH,MDO_DPTH_MINUSONE) mdo_request_fifo( |
| 633 | .clk (clk), |
| 634 | .rst_l (rst_l), |
| 635 | |
| 636 | .data_in (im2rm_mdo), |
| 637 | .write (im2rm_mdo_enq), |
| 638 | |
| 639 | .data_out (mdo_fifo_dout), |
| 640 | .read (mdo_fifo_deq), |
| 641 | |
| 642 | .fifo_full (), |
| 643 | .fifo_almost_full (), |
| 644 | .fifo_empty (mdo_fifo_empty) |
| 645 | |
| 646 | ); |
| 647 | |
| 648 | |
| 649 | endmodule |