| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_rmu_rrm_etsbfsm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_rmu_rrm_etsbfsm ( |
| 36 | |
| 37 | clk, |
| 38 | rst_l, |
| 39 | |
| 40 | // Outputs to TSB - Egress Pipeline |
| 41 | rm2ts_e_cmd_type, |
| 42 | rm2ts_e_req, |
| 43 | |
| 44 | // Inputs from TSB |
| 45 | ts2rm_e_gnt, |
| 46 | |
| 47 | // Outputs to EFSM module |
| 48 | tsb_fsm_idle, |
| 49 | ld_epe_rcd_tsb, |
| 50 | |
| 51 | // Inputs from EFSM module |
| 52 | gen_tsb_access, |
| 53 | sr_err_last_pkt, |
| 54 | |
| 55 | // Output (local) for debug visibility |
| 56 | e_tsb_state |
| 57 | ); |
| 58 | |
| 59 | // synopsys sync_set_reset "rst_l" |
| 60 | |
| 61 | //############################################################################ |
| 62 | // PORT DECLARATIONS |
| 63 | //############################################################################ |
| 64 | |
| 65 | //------------------------------------------------------------------------ |
| 66 | // Clock and Reset Signals |
| 67 | //------------------------------------------------------------------------ |
| 68 | input clk; |
| 69 | input rst_l; |
| 70 | |
| 71 | |
| 72 | //------------------------------------------------------------------------ |
| 73 | // TSB Interfacs |
| 74 | //------------------------------------------------------------------------ |
| 75 | |
| 76 | output [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_e_cmd_type; // 4 bit TSB Cmd |
| 77 | output rm2ts_e_req; |
| 78 | |
| 79 | input ts2rm_e_gnt; |
| 80 | |
| 81 | |
| 82 | //------------------------------------------------------------------------ |
| 83 | // Egress FSM Interface |
| 84 | //------------------------------------------------------------------------ |
| 85 | |
| 86 | output tsb_fsm_idle; // TSB fsm IDLE |
| 87 | output ld_epe_rcd_tsb; // TSB Read Data Valid |
| 88 | |
| 89 | input gen_tsb_access; // Kick off TSB FSM |
| 90 | input sr_err_last_pkt; // DMA Cpl LAST Packet bit set |
| 91 | |
| 92 | |
| 93 | //------------------------------------------------------------------------ |
| 94 | // Outputs (local) for Debug Port Visibility |
| 95 | //------------------------------------------------------------------------ |
| 96 | |
| 97 | output [3:0] e_tsb_state; // 1-hot Egress FSM |
| 98 | |
| 99 | |
| 100 | //############################################################################ |
| 101 | // PARAMETERS |
| 102 | //############################################################################ |
| 103 | |
| 104 | // TSB Command Decode |
| 105 | parameter |
| 106 | ETSB_CMD_NULL = 4'b0000, // Initial Value - NULL - can be removed |
| 107 | ETSB_CMD_RDCLR = 4'b0011, // Read/Clr - ie: last_pkt=1 |
| 108 | ETSB_CMD_RD = 4'b0001, // Read bcnt - ie: last_pkt=0 |
| 109 | ETSB_CMD_WR = 4'b0100; // Write back remaining bcnt |
| 110 | |
| 111 | |
| 112 | // Egress TSB Control Finite State Machine Parameters |
| 113 | |
| 114 | parameter |
| 115 | ETSB_IDLE = 0, // E_TSB FSM Idle |
| 116 | ETSB_RDCLR = 1, // Issue READ/CLEAR and retire TRN |
| 117 | ETSB_RD = 2, // Issue READ command to TSB |
| 118 | ETSB_WR = 3; // Issue WRITE command to TSB |
| 119 | |
| 120 | parameter |
| 121 | NUM_STATES = 4; |
| 122 | |
| 123 | |
| 124 | |
| 125 | //############################################################################ |
| 126 | // DECLARE Module Wires and Registers |
| 127 | //############################################################################ |
| 128 | |
| 129 | |
| 130 | wire ld_epe_rcd_tsb; // TSB Rd Data Valid -EFSM to LOAD RRM rcd |
| 131 | wire tsb_fsm_idle; // TSB IDLE - ready for action |
| 132 | |
| 133 | |
| 134 | //-------------------------------------------------- |
| 135 | // Registers that Are Flops |
| 136 | //-------------------------------------------------- |
| 137 | |
| 138 | // Egress TSB FSM 1-hot state machine |
| 139 | reg [NUM_STATES-1:0] e_tsb_state, next_e_tsb_state; // 1-hot Egress FSM |
| 140 | |
| 141 | |
| 142 | // Egress State Machine Registered Outputs |
| 143 | reg rm2ts_e_req, next_rm2ts_e_req; // Registered E TSB REQ |
| 144 | |
| 145 | reg [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_e_cmd_type, // Registerd E TSB Cmnd |
| 146 | next_rm2ts_e_cmd_type; |
| 147 | |
| 148 | |
| 149 | //############################################################################ |
| 150 | // ZERO IN CHECKERS |
| 151 | //############################################################################ |
| 152 | |
| 153 | //--------------------------------------------------------------------- |
| 154 | // Egress TSB State Machine Checkers |
| 155 | //--------------------------------------------------------------------- |
| 156 | /* |
| 157 | 0in state -var e_tsb_state |
| 158 | -val (4'b0001 << ETSB_IDLE) |
| 159 | -next (4'b0001 << ETSB_RDCLR) |
| 160 | (4'b0001 << ETSB_RD) |
| 161 | */ |
| 162 | |
| 163 | /* |
| 164 | 0in state -var e_tsb_state |
| 165 | -val (4'b0001 << ETSB_RDCLR) |
| 166 | -next (4'b0001 << ETSB_IDLE) |
| 167 | */ |
| 168 | |
| 169 | /* |
| 170 | 0in state -var e_tsb_state |
| 171 | -val (4'b0001 << ETSB_RD) |
| 172 | -next (4'b0001 << ETSB_WR) |
| 173 | */ |
| 174 | |
| 175 | /* |
| 176 | 0in state -var e_tsb_state |
| 177 | -val (4'b0001 << ETSB_WR) |
| 178 | -next (4'b0001 << ETSB_IDLE) |
| 179 | */ |
| 180 | |
| 181 | // 0in one_hot -var e_tsb_state |
| 182 | |
| 183 | |
| 184 | /* 0in kndr -var sr_err_last_pkt |
| 185 | -active gen_tsb_access |
| 186 | */ |
| 187 | |
| 188 | |
| 189 | //############################################################################ |
| 190 | // COMBINATORIAL LOGIC |
| 191 | //############################################################################ |
| 192 | |
| 193 | // Output signal that tells EFSM to |
| 194 | // 1) Load EPE record since TSB Rd data valid and |
| 195 | // 2) Tells EFSM to proceed processing ERR's from TCM |
| 196 | |
| 197 | assign ld_epe_rcd_tsb = ((e_tsb_state[ETSB_RD] | e_tsb_state[ETSB_RDCLR]) & |
| 198 | ts2rm_e_gnt); |
| 199 | |
| 200 | // Output that keeps Egress FSM in sync with Egress TSB FSM |
| 201 | assign tsb_fsm_idle = e_tsb_state[ETSB_IDLE]; |
| 202 | |
| 203 | |
| 204 | |
| 205 | //############################################################################ |
| 206 | // SEQUENTIAL LOGIC |
| 207 | //############################################################################ |
| 208 | |
| 209 | |
| 210 | //---------------------------------------------- |
| 211 | // Egress TSB State Machine Sequential Logic |
| 212 | //---------------------------------------------- |
| 213 | |
| 214 | always @ (posedge clk) |
| 215 | if (~rst_l) |
| 216 | begin |
| 217 | e_tsb_state[NUM_STATES-1:0] <= {NUM_STATES{1'b0}}; |
| 218 | e_tsb_state[ETSB_IDLE] <= 1'b1; |
| 219 | |
| 220 | rm2ts_e_req <= 1'b0; |
| 221 | rm2ts_e_cmd_type <= {`FIRE_DLC_TSR_CMD_TYPE_WDTH{1'b0}}; |
| 222 | end |
| 223 | else |
| 224 | begin |
| 225 | e_tsb_state <= next_e_tsb_state; |
| 226 | |
| 227 | rm2ts_e_req <= next_rm2ts_e_req; // State Machine Registered Outputs |
| 228 | rm2ts_e_cmd_type <= next_rm2ts_e_cmd_type; |
| 229 | end |
| 230 | |
| 231 | |
| 232 | //---------------------------------------------------------- |
| 233 | // Egress TSB State Machine Combinatorial (Next State) Logic |
| 234 | //---------------------------------------------------------- |
| 235 | |
| 236 | |
| 237 | always @ ( e_tsb_state or gen_tsb_access or sr_err_last_pkt or ts2rm_e_gnt ) |
| 238 | |
| 239 | begin |
| 240 | next_e_tsb_state = {NUM_STATES{1'b0}}; // Default Outputs |
| 241 | next_rm2ts_e_req = 1'b0; |
| 242 | next_rm2ts_e_cmd_type = `FIRE_DLC_TSR_CMD_TYPE_WDTH'b0; |
| 243 | |
| 244 | |
| 245 | |
| 246 | case(1'b1) // synopsys parallel_case |
| 247 | // 0in < case -full |
| 248 | |
| 249 | // ETSB_IDLE -Initial State |
| 250 | |
| 251 | e_tsb_state[ETSB_IDLE] : |
| 252 | |
| 253 | casez({gen_tsb_access,sr_err_last_pkt}) |
| 254 | |
| 255 | (2'b0z) : // Ignore ERR including x's` |
| 256 | begin // until we NEED to access tsb |
| 257 | next_e_tsb_state[ETSB_IDLE] = 1'b1; // wait for gen_tsb_access |
| 258 | next_rm2ts_e_cmd_type = ETSB_CMD_NULL; // keep default value |
| 259 | next_rm2ts_e_req = 1'b0; // Req deasserted |
| 260 | end |
| 261 | |
| 262 | (2'b10) : |
| 263 | begin |
| 264 | next_e_tsb_state[ETSB_RD] = 1'b1; // DMA Cpl - Not Last Pkt - RDWR |
| 265 | next_rm2ts_e_cmd_type = ETSB_CMD_RD; // Access TSB to build RRM rcd |
| 266 | next_rm2ts_e_req = 1'b1; // assert REQ |
| 267 | end |
| 268 | |
| 269 | (2'b11) : |
| 270 | begin |
| 271 | next_e_tsb_state[ETSB_RDCLR]= 1'b1; // DMA Cpl - Last Pkt - RD/CLR |
| 272 | next_rm2ts_e_cmd_type = ETSB_CMD_RDCLR; // Issue Read Clear command |
| 273 | next_rm2ts_e_req = 1'b1; // assert REQ |
| 274 | end |
| 275 | endcase // ends ETSB_IDLE state case |
| 276 | |
| 277 | |
| 278 | // ETSB_RD - Go get data associated with DMA Response to build RRM Record |
| 279 | |
| 280 | e_tsb_state[ETSB_RD] : |
| 281 | |
| 282 | begin |
| 283 | next_rm2ts_e_req = 1'b1; // keep REQ asserted |
| 284 | if (ts2rm_e_gnt) // RD completed - Start WR |
| 285 | begin |
| 286 | next_e_tsb_state[ETSB_WR] = 1'b1; // Go to ETSB_WR state |
| 287 | next_rm2ts_e_cmd_type = ETSB_CMD_WR; // Issue Write command |
| 288 | end |
| 289 | else |
| 290 | begin |
| 291 | next_e_tsb_state[ETSB_RD] = 1'b1; // ~gnt - keep RD asserted |
| 292 | next_rm2ts_e_cmd_type = ETSB_CMD_RD; |
| 293 | end |
| 294 | end |
| 295 | |
| 296 | |
| 297 | // ETSB_WR - RRM Rcd complete - write back new bcnt to TSB |
| 298 | |
| 299 | e_tsb_state[ETSB_WR] : |
| 300 | |
| 301 | if (ts2rm_e_gnt) // TSB WR completed |
| 302 | begin |
| 303 | next_rm2ts_e_req = 1'b0; // Deassert REQ |
| 304 | next_e_tsb_state[ETSB_IDLE] = 1'b1; // Back to IDLE |
| 305 | next_rm2ts_e_cmd_type = ETSB_CMD_NULL; // Command no longer Vld |
| 306 | end |
| 307 | else // GNT not yet asserted |
| 308 | begin |
| 309 | next_rm2ts_e_req = 1'b1; // Keep REQ asserted |
| 310 | next_e_tsb_state[ETSB_WR] = 1'b1; // Stay in WR state |
| 311 | next_rm2ts_e_cmd_type = ETSB_CMD_WR; // Hold WR Cmd |
| 312 | end |
| 313 | |
| 314 | |
| 315 | // ETSB_WR - RRM Rcd complete - write back new bcnt to TSB |
| 316 | |
| 317 | e_tsb_state[ETSB_RDCLR] : |
| 318 | |
| 319 | if (ts2rm_e_gnt) // RDCLR completed |
| 320 | begin |
| 321 | next_rm2ts_e_req = 1'b0; // Deassert REQ |
| 322 | next_e_tsb_state[ETSB_IDLE] = 1'b1; // Back to IDLE |
| 323 | next_rm2ts_e_cmd_type = ETSB_CMD_NULL; // Command no longer Vld |
| 324 | end |
| 325 | else // GNT not yet asserted |
| 326 | begin |
| 327 | next_rm2ts_e_req = 1'b1; // Keep REQ asserted |
| 328 | next_e_tsb_state[ETSB_RDCLR] = 1'b1; // Stay in WR state |
| 329 | next_rm2ts_e_cmd_type = ETSB_CMD_RDCLR; // Hold RD/CLR Cmd |
| 330 | end |
| 331 | |
| 332 | endcase // Ends ETSB 1-hot FSM Case Statement |
| 333 | |
| 334 | end // Ends combinatorial ETSB next state always block |
| 335 | |
| 336 | endmodule |