| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2b_ecc39_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2b_ecc39_dp ( |
| 36 | dout, |
| 37 | cflag, |
| 38 | pflag, |
| 39 | din, |
| 40 | parity); |
| 41 | wire c0_10; |
| 42 | wire c0_11; |
| 43 | wire c0_12; |
| 44 | wire c0_13; |
| 45 | wire c0_14; |
| 46 | wire c0_15; |
| 47 | wire c0_20; |
| 48 | wire c0_21; |
| 49 | wire c0_1; |
| 50 | wire c0_2; |
| 51 | wire c0_3; |
| 52 | wire c1_10; |
| 53 | wire c1_11; |
| 54 | wire c1_12; |
| 55 | wire c1_13; |
| 56 | wire c1_14; |
| 57 | wire c1_15; |
| 58 | wire c1_20; |
| 59 | wire c1_21; |
| 60 | wire c1_1; |
| 61 | wire c1_2; |
| 62 | wire c2_10; |
| 63 | wire c2_11; |
| 64 | wire c2_12; |
| 65 | wire c2_13; |
| 66 | wire c2_14; |
| 67 | wire c2_15; |
| 68 | wire c2_20; |
| 69 | wire c2_21; |
| 70 | wire c2_1; |
| 71 | wire c2_2; |
| 72 | wire c3_10; |
| 73 | wire c3_11; |
| 74 | wire c3_12; |
| 75 | wire c3_13; |
| 76 | wire c3_14; |
| 77 | wire c3_20; |
| 78 | wire c3_21; |
| 79 | wire c3_1; |
| 80 | wire c3_2; |
| 81 | wire c4_10; |
| 82 | wire c4_11; |
| 83 | wire c4_12; |
| 84 | wire c4_13; |
| 85 | wire c4_14; |
| 86 | wire c4_20; |
| 87 | wire c4_21; |
| 88 | wire c4_1; |
| 89 | wire c4_2; |
| 90 | wire c5_10; |
| 91 | wire c5_11; |
| 92 | wire c5; |
| 93 | wire pflag_10; |
| 94 | wire pflag_11; |
| 95 | wire pflag_12; |
| 96 | wire pflag_13; |
| 97 | wire pflag_14; |
| 98 | wire pflag_15; |
| 99 | wire pflag_20; |
| 100 | wire pflag_21; |
| 101 | wire pflag_30; |
| 102 | wire nc0_1; |
| 103 | wire nc0_2; |
| 104 | wire nc1_1; |
| 105 | wire nc1_2; |
| 106 | wire nc2_1; |
| 107 | wire nc2_2; |
| 108 | wire nc3_1; |
| 109 | wire nc3_2; |
| 110 | wire nc4_1; |
| 111 | wire nc4_2; |
| 112 | wire nc5_1; |
| 113 | wire nc5_2; |
| 114 | wire err_bit0_pos_10a; |
| 115 | wire err_bit0_pos_10b; |
| 116 | wire err_bit1_pos_10a; |
| 117 | wire err_bit1_pos_10b; |
| 118 | wire err_bit2_pos_10a; |
| 119 | wire err_bit2_pos_10b; |
| 120 | wire err_bit3_pos_10a; |
| 121 | wire err_bit3_pos_10b; |
| 122 | wire err_bit4_pos_10a; |
| 123 | wire err_bit4_pos_10b; |
| 124 | wire err_bit5_pos_10a; |
| 125 | wire err_bit5_pos_10b; |
| 126 | wire err_bit6_pos_10a; |
| 127 | wire err_bit6_pos_10b; |
| 128 | wire err_bit7_pos_10a; |
| 129 | wire err_bit7_pos_10b; |
| 130 | wire err_bit8_pos_10a; |
| 131 | wire err_bit8_pos_10b; |
| 132 | wire err_bit9_pos_10a; |
| 133 | wire err_bit9_pos_10b; |
| 134 | wire err_bit10_pos_10a; |
| 135 | wire err_bit10_pos_10b; |
| 136 | wire err_bit11_pos_10a; |
| 137 | wire err_bit11_pos_10b; |
| 138 | wire err_bit12_pos_10a; |
| 139 | wire err_bit12_pos_10b; |
| 140 | wire err_bit13_pos_10a; |
| 141 | wire err_bit13_pos_10b; |
| 142 | wire err_bit14_pos_10a; |
| 143 | wire err_bit14_pos_10b; |
| 144 | wire err_bit15_pos_10a; |
| 145 | wire err_bit15_pos_10b; |
| 146 | wire err_bit16_pos_10a; |
| 147 | wire err_bit16_pos_10b; |
| 148 | wire err_bit17_pos_10a; |
| 149 | wire err_bit17_pos_10b; |
| 150 | wire err_bit18_pos_10a; |
| 151 | wire err_bit18_pos_10b; |
| 152 | wire err_bit19_pos_10a; |
| 153 | wire err_bit19_pos_10b; |
| 154 | wire err_bit20_pos_10a; |
| 155 | wire err_bit20_pos_10b; |
| 156 | wire err_bit21_pos_10a; |
| 157 | wire err_bit21_pos_10b; |
| 158 | wire err_bit22_pos_10a; |
| 159 | wire err_bit22_pos_10b; |
| 160 | wire err_bit23_pos_10a; |
| 161 | wire err_bit23_pos_10b; |
| 162 | wire err_bit24_pos_10a; |
| 163 | wire err_bit24_pos_10b; |
| 164 | wire err_bit25_pos_10a; |
| 165 | wire err_bit25_pos_10b; |
| 166 | wire err_bit26_pos_10a; |
| 167 | wire err_bit26_pos_10b; |
| 168 | wire err_bit27_pos_10a; |
| 169 | wire err_bit27_pos_10b; |
| 170 | wire err_bit28_pos_10a; |
| 171 | wire err_bit28_pos_10b; |
| 172 | wire err_bit29_pos_10a; |
| 173 | wire err_bit29_pos_10b; |
| 174 | wire err_bit30_pos_10a; |
| 175 | wire err_bit30_pos_10b; |
| 176 | wire err_bit31_pos_10a; |
| 177 | wire err_bit31_pos_10b; |
| 178 | |
| 179 | |
| 180 | //Output: 32bit corrected data |
| 181 | output[31:0] dout; |
| 182 | output [5:0] cflag; |
| 183 | output pflag; |
| 184 | |
| 185 | //Input: 32bit data din |
| 186 | input [31:0] din; |
| 187 | input [6:0] parity; |
| 188 | |
| 189 | //wire c0,c1,c2,c3,c4,c5; |
| 190 | wire [31:0] err_bit_pos; |
| 191 | |
| 192 | //refer to the comments in parity_gen_32b.v for the position description |
| 193 | // |
| 194 | // assign c0= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8]) |
| 195 | // ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19]) |
| 196 | // ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]); |
| 197 | |
| 198 | |
| 199 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c0_slice_10 ( |
| 200 | .dout (c0_10), |
| 201 | .din0 (din[0]), |
| 202 | .din1 (din[1]), |
| 203 | .din2 (din[3]) |
| 204 | ); |
| 205 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c0_slice_11 ( |
| 206 | .dout (c0_11), |
| 207 | .din0 (din[4]), |
| 208 | .din1 (din[6]), |
| 209 | .din2 (din[8]) |
| 210 | ); |
| 211 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c0_slice_12 ( |
| 212 | .dout (c0_12), |
| 213 | .din0 (din[10]), |
| 214 | .din1 (din[11]), |
| 215 | .din2 (din[13]) |
| 216 | ); |
| 217 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c0_slice_13 ( |
| 218 | .dout (c0_13), |
| 219 | .din0 (din[15]), |
| 220 | .din1 (din[17]), |
| 221 | .din2 (din[19]) |
| 222 | ); |
| 223 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_14 ( |
| 224 | .dout (c0_14), |
| 225 | .din0 (din[21]), |
| 226 | .din1 (din[23]), |
| 227 | .din2 (din[25]) |
| 228 | ); |
| 229 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c0_slice_15 ( |
| 230 | .dout (c0_15), |
| 231 | .din0 (din[26]), |
| 232 | .din1 (din[28]), |
| 233 | .din2 (din[30]) |
| 234 | ); |
| 235 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c0_slice_20 ( |
| 236 | .dout (c0_20), |
| 237 | .din0 (c0_10), |
| 238 | .din1 (c0_11), |
| 239 | .din2 (c0_12) |
| 240 | ); |
| 241 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_21 ( |
| 242 | .dout (c0_21), |
| 243 | .din0 (c0_13), |
| 244 | .din1 (c0_14), |
| 245 | .din2 (c0_15) |
| 246 | ); |
| 247 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22a ( |
| 248 | .dout (c0_1), |
| 249 | .din0 (c0_20), |
| 250 | .din1 (c0_21), |
| 251 | .din2 (parity[0]) |
| 252 | ); |
| 253 | |
| 254 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22b ( |
| 255 | .dout (c0_2), |
| 256 | .din0 (c0_20), |
| 257 | .din1 (c0_21), |
| 258 | .din2 (parity[0]) |
| 259 | ); |
| 260 | |
| 261 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22c ( |
| 262 | .dout (c0_3), |
| 263 | .din0 (c0_20), |
| 264 | .din1 (c0_21), |
| 265 | .din2 (parity[0]) |
| 266 | ); |
| 267 | |
| 268 | |
| 269 | |
| 270 | // assign c1= parity[1]^(din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9]) |
| 271 | // ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20]) |
| 272 | // ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]); |
| 273 | |
| 274 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c1_slice_10 ( |
| 275 | .dout (c1_10), |
| 276 | .din0 (din[0]), |
| 277 | .din1 (din[2]), |
| 278 | .din2 (din[3]) |
| 279 | ); |
| 280 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c1_slice_11 ( |
| 281 | .dout (c1_11), |
| 282 | .din0 (din[5]), |
| 283 | .din1 (din[6]), |
| 284 | .din2 (din[9]) |
| 285 | ); |
| 286 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c1_slice_12 ( |
| 287 | .dout (c1_12), |
| 288 | .din0 (din[10]), |
| 289 | .din1 (din[12]), |
| 290 | .din2 (din[13]) |
| 291 | ); |
| 292 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c1_slice_13 ( |
| 293 | .dout (c1_13), |
| 294 | .din0 (din[16]), |
| 295 | .din1 (din[17]), |
| 296 | .din2 (din[20]) |
| 297 | ); |
| 298 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c1_slice_14 ( |
| 299 | .dout (c1_14), |
| 300 | .din0 (din[21]), |
| 301 | .din1 (din[24]), |
| 302 | .din2 (din[25]) |
| 303 | ); |
| 304 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c1_slice_15 ( |
| 305 | .dout (c1_15), |
| 306 | .din0 (din[27]), |
| 307 | .din1 (din[28]), |
| 308 | .din2 (din[31]) |
| 309 | ); |
| 310 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_20 ( |
| 311 | .dout (c1_20), |
| 312 | .din0 (c1_10), |
| 313 | .din1 (c1_11), |
| 314 | .din2 (c1_12) |
| 315 | ); |
| 316 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_21 ( |
| 317 | .dout (c1_21), |
| 318 | .din0 (c1_13), |
| 319 | .din1 (c1_14), |
| 320 | .din2 (c1_15) |
| 321 | ); |
| 322 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_22a ( |
| 323 | .dout (c1_1), |
| 324 | .din0 (c1_20), |
| 325 | .din1 (c1_21), |
| 326 | .din2 (parity[1]) |
| 327 | ); |
| 328 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_22b ( |
| 329 | .dout (c1_2), |
| 330 | .din0 (c1_20), |
| 331 | .din1 (c1_21), |
| 332 | .din2 (parity[1]) |
| 333 | ); |
| 334 | |
| 335 | |
| 336 | // assign c2= parity[2]^(din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9]) |
| 337 | // ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22]) |
| 338 | // ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]); |
| 339 | |
| 340 | |
| 341 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c2_slice_10 ( |
| 342 | .dout (c2_10), |
| 343 | .din0 (din[1]), |
| 344 | .din1 (din[2]), |
| 345 | .din2 (din[3]) |
| 346 | ); |
| 347 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c2_slice_11 ( |
| 348 | .dout (c2_11), |
| 349 | .din0 (din[7]), |
| 350 | .din1 (din[8]), |
| 351 | .din2 (din[9]) |
| 352 | ); |
| 353 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c2_slice_12 ( |
| 354 | .dout (c2_12), |
| 355 | .din0 (din[10]), |
| 356 | .din1 (din[14]), |
| 357 | .din2 (din[15]) |
| 358 | ); |
| 359 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c2_slice_13 ( |
| 360 | .dout (c2_13), |
| 361 | .din0 (din[16]), |
| 362 | .din1 (din[17]), |
| 363 | .din2 (din[22]) |
| 364 | ); |
| 365 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c2_slice_14 ( |
| 366 | .dout (c2_14), |
| 367 | .din0 (din[23]), |
| 368 | .din1 (din[24]), |
| 369 | .din2 (din[25]) |
| 370 | ); |
| 371 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c2_slice_15 ( |
| 372 | .dout (c2_15), |
| 373 | .din0 (din[29]), |
| 374 | .din1 (din[30]), |
| 375 | .din2 (din[31]) |
| 376 | ); |
| 377 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_20 ( |
| 378 | .dout (c2_20), |
| 379 | .din0 (c2_10), |
| 380 | .din1 (c2_11), |
| 381 | .din2 (c2_12) |
| 382 | ); |
| 383 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_21 ( |
| 384 | .dout (c2_21), |
| 385 | .din0 (c2_13), |
| 386 | .din1 (c2_14), |
| 387 | .din2 (c2_15) |
| 388 | ); |
| 389 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_22a ( |
| 390 | .dout (c2_1), |
| 391 | .din0 (c2_20), |
| 392 | .din1 (c2_21), |
| 393 | .din2 (parity[2]) |
| 394 | ); |
| 395 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_22b ( |
| 396 | .dout (c2_2), |
| 397 | .din0 (c2_20), |
| 398 | .din1 (c2_21), |
| 399 | .din2 (parity[2]) |
| 400 | ); |
| 401 | |
| 402 | |
| 403 | |
| 404 | |
| 405 | // assign c3= parity[3]^(din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9]) |
| 406 | // ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22]) |
| 407 | // ^(din[23]^din[24])^din[25]; |
| 408 | |
| 409 | |
| 410 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c3_slice_10 ( |
| 411 | .dout (c3_10), |
| 412 | .din0 (din[4]), |
| 413 | .din1 (din[5]), |
| 414 | .din2 (din[6]) |
| 415 | ); |
| 416 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c3_slice_11 ( |
| 417 | .dout (c3_11), |
| 418 | .din0 (din[7]), |
| 419 | .din1 (din[8]), |
| 420 | .din2 (din[9]) |
| 421 | ); |
| 422 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c3_slice_12 ( |
| 423 | .dout (c3_12), |
| 424 | .din0 (din[10]), |
| 425 | .din1 (din[18]), |
| 426 | .din2 (din[19]) |
| 427 | ); |
| 428 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c3_slice_13 ( |
| 429 | .dout (c3_13), |
| 430 | .din0 (din[20]), |
| 431 | .din1 (din[21]), |
| 432 | .din2 (din[22]) |
| 433 | ); |
| 434 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c3_slice_14 ( |
| 435 | .dout (c3_14), |
| 436 | .din0 (din[23]), |
| 437 | .din1 (din[24]), |
| 438 | .din2 (din[25]) |
| 439 | ); |
| 440 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_20 ( |
| 441 | .dout (c3_20), |
| 442 | .din0 (c3_10), |
| 443 | .din1 (c3_11), |
| 444 | .din2 (c3_12) |
| 445 | ); |
| 446 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_21 ( |
| 447 | .dout (c3_21), |
| 448 | .din0 (c3_13), |
| 449 | .din1 (c3_14), |
| 450 | .din2 (parity[3]) |
| 451 | ); |
| 452 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_2__width_1 c3_slice_22a ( |
| 453 | .dout (c3_1), |
| 454 | .din0 (c3_20), |
| 455 | .din1 (c3_21) |
| 456 | ); |
| 457 | |
| 458 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_2__width_1 c3_slice_22b ( |
| 459 | .dout (c3_2), |
| 460 | .din0 (c3_20), |
| 461 | .din1 (c3_21) |
| 462 | ); |
| 463 | |
| 464 | |
| 465 | // assign c4= parity[4]^(din[11]^din[12])^(din[13]^din[14])^ |
| 466 | // (din[15]^din[16])^(din[17]^din[18])^(din[19]^din[20])^ |
| 467 | // (din[21]^din[22])^(din[23]^din[24])^din[25]; |
| 468 | |
| 469 | |
| 470 | |
| 471 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c4_slice_10 ( |
| 472 | .dout (c4_10), |
| 473 | .din0 (din[11]), |
| 474 | .din1 (din[12]), |
| 475 | .din2 (din[13]) |
| 476 | ); |
| 477 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c4_slice_11 ( |
| 478 | .dout (c4_11), |
| 479 | .din0 (din[14]), |
| 480 | .din1 (din[15]), |
| 481 | .din2 (din[16]) |
| 482 | ); |
| 483 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c4_slice_12 ( |
| 484 | .dout (c4_12), |
| 485 | .din0 (din[17]), |
| 486 | .din1 (din[18]), |
| 487 | .din2 (din[19]) |
| 488 | ); |
| 489 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c4_slice_13 ( |
| 490 | .dout (c4_13), |
| 491 | .din0 (din[20]), |
| 492 | .din1 (din[21]), |
| 493 | .din2 (din[22]) |
| 494 | ); |
| 495 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c4_slice_14 ( |
| 496 | .dout (c4_14), |
| 497 | .din0 (din[23]), |
| 498 | .din1 (din[24]), |
| 499 | .din2 (din[25]) |
| 500 | ); |
| 501 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_20 ( |
| 502 | .dout (c4_20), |
| 503 | .din0 (c4_10), |
| 504 | .din1 (c4_11), |
| 505 | .din2 (c4_12) |
| 506 | ); |
| 507 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_21 ( |
| 508 | .dout (c4_21), |
| 509 | .din0 (c4_13), |
| 510 | .din1 (c4_14), |
| 511 | .din2 (parity[4]) |
| 512 | ); |
| 513 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_2__width_1 c4_slice_22a ( |
| 514 | .dout (c4_1), |
| 515 | .din0 (c4_20), |
| 516 | .din1 (c4_21) |
| 517 | ); |
| 518 | |
| 519 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_2__width_1 c4_slice_22b ( |
| 520 | .dout (c4_2), |
| 521 | .din0 (c4_20), |
| 522 | .din1 (c4_21) |
| 523 | ); |
| 524 | |
| 525 | |
| 526 | |
| 527 | // assign c5= parity[5]^(din[26]^din[27])^(din[28]^din[29])^ |
| 528 | // (din[30]^din[31]); |
| 529 | |
| 530 | |
| 531 | |
| 532 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c5_slice_10 ( |
| 533 | .dout (c5_10), |
| 534 | .din0 (din[26]), |
| 535 | .din1 (din[27]), |
| 536 | .din2 (din[28]) |
| 537 | ); |
| 538 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 c5_slice_11 ( |
| 539 | .dout (c5_11), |
| 540 | .din0 (din[29]), |
| 541 | .din1 (din[30]), |
| 542 | .din2 (din[31]) |
| 543 | ); |
| 544 | l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_20 ( |
| 545 | .dout (c5), |
| 546 | .din0 (c5_10), |
| 547 | .din1 (c5_11), |
| 548 | .din2 (parity[5]) |
| 549 | ); |
| 550 | |
| 551 | |
| 552 | // //generate total parity flag |
| 553 | // assign pflag= c0 ^ |
| 554 | // (( (((parity[1]^parity[2])^(parity[3]^parity[4])) ^ |
| 555 | // ((parity[5]^parity[6])^(din[2]^din[5]))) ^ |
| 556 | // (((din[7]^din[9])^(din[12]^din[14])) ^ |
| 557 | // ((din[16]^din[18])^(din[20]^din[22]))) ) ^ |
| 558 | // ((din[24]^din[27])^(din[29]^din[31])) ); |
| 559 | |
| 560 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_10 ( |
| 561 | .dout (pflag_10), |
| 562 | .din0 (parity[1]), |
| 563 | .din1 (parity[2]), |
| 564 | .din2 (parity[3]) |
| 565 | ); |
| 566 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_11 ( |
| 567 | .dout (pflag_11), |
| 568 | .din0 (parity[4]), |
| 569 | .din1 (parity[5]), |
| 570 | .din2 (parity[6]) |
| 571 | ); |
| 572 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_12 ( |
| 573 | .dout (pflag_12), |
| 574 | .din0 (din[2]), |
| 575 | .din1 (din[5]), |
| 576 | .din2 (din[7]) |
| 577 | ); |
| 578 | |
| 579 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_13 ( |
| 580 | .dout (pflag_13), |
| 581 | .din0 (din[9]), |
| 582 | .din1 (din[12]), |
| 583 | .din2 (din[14]) |
| 584 | ); |
| 585 | |
| 586 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_14 ( |
| 587 | .dout (pflag_14), |
| 588 | .din0 (din[16]), |
| 589 | .din1 (din[18]), |
| 590 | .din2 (din[20]) |
| 591 | ); |
| 592 | |
| 593 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_15 ( |
| 594 | .dout (pflag_15), |
| 595 | .din0 (din[22]), |
| 596 | .din1 (din[24]), |
| 597 | .din2 (din[27]) |
| 598 | ); |
| 599 | |
| 600 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_20 ( |
| 601 | .dout (pflag_20), |
| 602 | .din0 (din[29]), |
| 603 | .din1 (din[31]), |
| 604 | .din2 (pflag_10) |
| 605 | ); |
| 606 | |
| 607 | |
| 608 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_21 ( |
| 609 | .dout (pflag_21), |
| 610 | .din0 (pflag_11), |
| 611 | .din1 (pflag_12), |
| 612 | .din2 (pflag_13) |
| 613 | ); |
| 614 | |
| 615 | |
| 616 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_30 ( |
| 617 | .dout (pflag_30), |
| 618 | .din0 (pflag_14), |
| 619 | .din1 (pflag_15), |
| 620 | .din2 (pflag_20) |
| 621 | ); |
| 622 | |
| 623 | |
| 624 | l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 pflag_slice_31 ( |
| 625 | .dout (pflag), |
| 626 | .din0 (pflag_30), |
| 627 | .din1 (pflag_21), |
| 628 | .din2 (c0_1) |
| 629 | ); |
| 630 | |
| 631 | |
| 632 | assign cflag= {c5,c4_1,c3_1,c2_1,c1_1,c0_1}; |
| 633 | |
| 634 | |
| 635 | //6 to 32 decoder |
| 636 | |
| 637 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c0_inv_slice_1 |
| 638 | ( |
| 639 | .din (c0_1), |
| 640 | .dout (nc0_1) |
| 641 | ); |
| 642 | |
| 643 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c0_inv_slice_2 |
| 644 | ( |
| 645 | .din (c0_3), |
| 646 | .dout (nc0_2) |
| 647 | ); |
| 648 | |
| 649 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c1_inv_slice_1 |
| 650 | ( |
| 651 | .din (c1_1), |
| 652 | .dout (nc1_1) |
| 653 | ); |
| 654 | |
| 655 | |
| 656 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c1_inv_slice_2 |
| 657 | ( |
| 658 | .din (c1_2), |
| 659 | .dout (nc1_2) |
| 660 | ); |
| 661 | |
| 662 | |
| 663 | |
| 664 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c2_inv_slice_1 |
| 665 | ( |
| 666 | .din (c2_1), |
| 667 | .dout (nc2_1) |
| 668 | ); |
| 669 | |
| 670 | |
| 671 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c2_inv_slice_2 |
| 672 | ( |
| 673 | .din (c2_2), |
| 674 | .dout (nc2_2) |
| 675 | ); |
| 676 | |
| 677 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c3_inv_slice_1 |
| 678 | ( |
| 679 | .din (c3_1), |
| 680 | .dout (nc3_1) |
| 681 | ); |
| 682 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c3_inv_slice_2 |
| 683 | ( |
| 684 | .din (c3_1), |
| 685 | .dout (nc3_2) |
| 686 | ); |
| 687 | |
| 688 | |
| 689 | |
| 690 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c4_inv_slice_1 |
| 691 | ( |
| 692 | .din (c4_1), |
| 693 | .dout (nc4_1) |
| 694 | ); |
| 695 | |
| 696 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c4_inv_slice_2 |
| 697 | ( |
| 698 | .din (c4_2), |
| 699 | .dout (nc4_2) |
| 700 | ); |
| 701 | |
| 702 | |
| 703 | |
| 704 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c5_inv_slice_1 |
| 705 | ( |
| 706 | .din (c5), |
| 707 | .dout (nc5_1) |
| 708 | ); |
| 709 | |
| 710 | |
| 711 | l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 c5_inv_slice_2 |
| 712 | ( |
| 713 | .din (c5), |
| 714 | .dout (nc5_2) |
| 715 | ); |
| 716 | |
| 717 | |
| 718 | // bit 0 |
| 719 | |
| 720 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit0_pos_slice_10a ( |
| 721 | .dout (err_bit0_pos_10a), |
| 722 | .din0 (c0_2), |
| 723 | .din1 (c1_1), |
| 724 | .din2 (nc2_1) |
| 725 | ); |
| 726 | |
| 727 | |
| 728 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit0_pos_slice_10b ( |
| 729 | .dout (err_bit0_pos_10b), |
| 730 | .din0 (nc3_1), |
| 731 | .din1 (nc4_1), |
| 732 | .din2 (nc5_1) |
| 733 | ); |
| 734 | |
| 735 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit0_pos_slice_10c ( |
| 736 | .dout (err_bit_pos[0]), |
| 737 | .din0 (err_bit0_pos_10a), |
| 738 | .din1 (err_bit0_pos_10b) |
| 739 | ); |
| 740 | |
| 741 | // bit 1 |
| 742 | |
| 743 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit1_pos_slice_10a ( |
| 744 | .dout (err_bit1_pos_10a), |
| 745 | .din0 (c0_2), |
| 746 | .din1 (nc1_1), |
| 747 | .din2 (c2_1) |
| 748 | ); |
| 749 | |
| 750 | |
| 751 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit1_pos_slice_10b ( |
| 752 | .dout (err_bit1_pos_10b), |
| 753 | .din0 (nc3_1), |
| 754 | .din1 (nc4_1), |
| 755 | .din2 (nc5_1) |
| 756 | ); |
| 757 | |
| 758 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit1_pos_slice_10c ( |
| 759 | .dout (err_bit_pos[1]), |
| 760 | .din0 (err_bit1_pos_10a), |
| 761 | .din1 (err_bit1_pos_10b) |
| 762 | ); |
| 763 | |
| 764 | // bit 2 |
| 765 | |
| 766 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit2_pos_slice_10a ( |
| 767 | .dout (err_bit2_pos_10a), |
| 768 | .din0 (nc0_1), |
| 769 | .din1 (c1_1), |
| 770 | .din2 (c2_1) |
| 771 | ); |
| 772 | |
| 773 | |
| 774 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit2_pos_slice_10b ( |
| 775 | .dout (err_bit2_pos_10b), |
| 776 | .din0 (nc3_1), |
| 777 | .din1 (nc4_1), |
| 778 | .din2 (nc5_1) |
| 779 | ); |
| 780 | |
| 781 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit2_pos_slice_10c ( |
| 782 | .dout (err_bit_pos[2]), |
| 783 | .din0 (err_bit2_pos_10a), |
| 784 | .din1 (err_bit2_pos_10b) |
| 785 | ); |
| 786 | |
| 787 | |
| 788 | // bit 3 |
| 789 | |
| 790 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit3_pos_slice_10a ( |
| 791 | .dout (err_bit3_pos_10a), |
| 792 | .din0 (c0_2), |
| 793 | .din1 (c1_1), |
| 794 | .din2 (c2_1) |
| 795 | ); |
| 796 | |
| 797 | |
| 798 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit3_pos_slice_10b ( |
| 799 | .dout (err_bit3_pos_10b), |
| 800 | .din0 (nc3_1), |
| 801 | .din1 (nc4_1), |
| 802 | .din2 (nc5_1) |
| 803 | ); |
| 804 | |
| 805 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit3_pos_slice_10c ( |
| 806 | .dout (err_bit_pos[3]), |
| 807 | .din0 (err_bit3_pos_10a), |
| 808 | .din1 (err_bit3_pos_10b) |
| 809 | ); |
| 810 | |
| 811 | |
| 812 | // bit 4 |
| 813 | |
| 814 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit4_pos_slice_10a ( |
| 815 | .dout (err_bit4_pos_10a), |
| 816 | .din0 (c0_2), |
| 817 | .din1 (nc1_1), |
| 818 | .din2 (nc2_1) |
| 819 | ); |
| 820 | |
| 821 | |
| 822 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit4_pos_slice_10b ( |
| 823 | .dout (err_bit4_pos_10b), |
| 824 | .din0 (c3_1), |
| 825 | .din1 (nc4_1), |
| 826 | .din2 (nc5_1) |
| 827 | ); |
| 828 | |
| 829 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit4_pos_slice_10c ( |
| 830 | .dout (err_bit_pos[4]), |
| 831 | .din0 (err_bit4_pos_10a), |
| 832 | .din1 (err_bit4_pos_10b) |
| 833 | ); |
| 834 | |
| 835 | // bit 5 |
| 836 | |
| 837 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit5_pos_slice_10a ( |
| 838 | .dout (err_bit5_pos_10a), |
| 839 | .din0 (nc0_1), |
| 840 | .din1 (c1_1), |
| 841 | .din2 (nc2_1) |
| 842 | ); |
| 843 | |
| 844 | |
| 845 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit5_pos_slice_10b ( |
| 846 | .dout (err_bit5_pos_10b), |
| 847 | .din0 (c3_1), |
| 848 | .din1 (nc4_2), |
| 849 | .din2 (nc5_1) |
| 850 | ); |
| 851 | |
| 852 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit5_pos_slice_10c ( |
| 853 | .dout (err_bit_pos[5]), |
| 854 | .din0 (err_bit5_pos_10a), |
| 855 | .din1 (err_bit5_pos_10b) |
| 856 | ); |
| 857 | |
| 858 | // bit 6 |
| 859 | |
| 860 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit6_pos_slice_10a ( |
| 861 | .dout (err_bit6_pos_10a), |
| 862 | .din0 (c0_1), |
| 863 | .din1 (c1_1), |
| 864 | .din2 (nc2_1) |
| 865 | ); |
| 866 | |
| 867 | |
| 868 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit6_pos_slice_10b ( |
| 869 | .dout (err_bit6_pos_10b), |
| 870 | .din0 (c3_1), |
| 871 | .din1 (nc4_2), |
| 872 | .din2 (nc5_1) |
| 873 | ); |
| 874 | |
| 875 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit6_pos_slice_10c ( |
| 876 | .dout (err_bit_pos[6]), |
| 877 | .din0 (err_bit6_pos_10a), |
| 878 | .din1 (err_bit6_pos_10b) |
| 879 | ); |
| 880 | |
| 881 | // bit 7 |
| 882 | |
| 883 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit7_pos_slice_10a ( |
| 884 | .dout (err_bit7_pos_10a), |
| 885 | .din0 (nc0_1), |
| 886 | .din1 (nc1_1), |
| 887 | .din2 (c2_1) |
| 888 | ); |
| 889 | |
| 890 | |
| 891 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit7_pos_slice_10b ( |
| 892 | .dout (err_bit7_pos_10b), |
| 893 | .din0 (c3_1), |
| 894 | .din1 (nc4_2), |
| 895 | .din2 (nc5_1) |
| 896 | ); |
| 897 | |
| 898 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit7_pos_slice_10c ( |
| 899 | .dout (err_bit_pos[7]), |
| 900 | .din0 (err_bit7_pos_10a), |
| 901 | .din1 (err_bit7_pos_10b) |
| 902 | ); |
| 903 | |
| 904 | // bit 8 |
| 905 | |
| 906 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit8_pos_slice_10a ( |
| 907 | .dout (err_bit8_pos_10a), |
| 908 | .din0 (c0_2), |
| 909 | .din1 (nc1_1), |
| 910 | .din2 (c2_1) |
| 911 | ); |
| 912 | |
| 913 | |
| 914 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit8_pos_slice_10b ( |
| 915 | .dout (err_bit8_pos_10b), |
| 916 | .din0 (c3_1), |
| 917 | .din1 (nc4_2), |
| 918 | .din2 (nc5_2) |
| 919 | ); |
| 920 | |
| 921 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit8_pos_slice_10c ( |
| 922 | .dout (err_bit_pos[8]), |
| 923 | .din0 (err_bit8_pos_10a), |
| 924 | .din1 (err_bit8_pos_10b) |
| 925 | ); |
| 926 | |
| 927 | // bit 9 |
| 928 | |
| 929 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit9_pos_slice_10a ( |
| 930 | .dout (err_bit9_pos_10a), |
| 931 | .din0 (nc0_1), |
| 932 | .din1 (c1_1), |
| 933 | .din2 (c2_1) |
| 934 | ); |
| 935 | |
| 936 | |
| 937 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit9_pos_slice_10b ( |
| 938 | .dout (err_bit9_pos_10b), |
| 939 | .din0 (c3_1), |
| 940 | .din1 (nc4_2), |
| 941 | .din2 (nc5_2) |
| 942 | ); |
| 943 | |
| 944 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit9_pos_slice_10c ( |
| 945 | .dout (err_bit_pos[9]), |
| 946 | .din0 (err_bit9_pos_10a), |
| 947 | .din1 (err_bit9_pos_10b) |
| 948 | ); |
| 949 | |
| 950 | // bit 10 |
| 951 | |
| 952 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit10_pos_slice_10a ( |
| 953 | .dout (err_bit10_pos_10a), |
| 954 | .din0 (c0_1), |
| 955 | .din1 (c1_1), |
| 956 | .din2 (c2_2) |
| 957 | ); |
| 958 | |
| 959 | |
| 960 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit10_pos_slice_10b ( |
| 961 | .dout (err_bit10_pos_10b), |
| 962 | .din0 (c3_1), |
| 963 | .din1 (nc4_1), |
| 964 | .din2 (nc5_2) |
| 965 | ); |
| 966 | |
| 967 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit10_pos_slice_10c ( |
| 968 | .dout (err_bit_pos[10]), |
| 969 | .din0 (err_bit10_pos_10a), |
| 970 | .din1 (err_bit10_pos_10b) |
| 971 | ); |
| 972 | |
| 973 | // bit 11 |
| 974 | |
| 975 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit11_pos_slice_10a ( |
| 976 | .dout (err_bit11_pos_10a), |
| 977 | .din0 (c0_2), |
| 978 | .din1 (nc1_1), |
| 979 | .din2 (nc2_1) |
| 980 | ); |
| 981 | |
| 982 | |
| 983 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit11_pos_slice_10b ( |
| 984 | .dout (err_bit11_pos_10b), |
| 985 | .din0 (nc3_1), |
| 986 | .din1 (c4_1), |
| 987 | .din2 (nc5_2) |
| 988 | ); |
| 989 | |
| 990 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit11_pos_slice_10c ( |
| 991 | .dout (err_bit_pos[11]), |
| 992 | .din0 (err_bit11_pos_10a), |
| 993 | .din1 (err_bit11_pos_10b) |
| 994 | ); |
| 995 | |
| 996 | // bit 12 |
| 997 | |
| 998 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit12_pos_slice_10a ( |
| 999 | .dout (err_bit12_pos_10a), |
| 1000 | .din0 (nc0_1), |
| 1001 | .din1 (c1_1), |
| 1002 | .din2 (nc2_2) |
| 1003 | ); |
| 1004 | |
| 1005 | |
| 1006 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit12_pos_slice_10b ( |
| 1007 | .dout (err_bit12_pos_10b), |
| 1008 | .din0 (nc3_2), |
| 1009 | .din1 (c4_1), |
| 1010 | .din2 (nc5_2) |
| 1011 | ); |
| 1012 | |
| 1013 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit12_pos_slice_10c ( |
| 1014 | .dout (err_bit_pos[12]), |
| 1015 | .din0 (err_bit12_pos_10a), |
| 1016 | .din1 (err_bit12_pos_10b) |
| 1017 | ); |
| 1018 | |
| 1019 | // bit 13 |
| 1020 | |
| 1021 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit13_pos_slice_10a ( |
| 1022 | .dout (err_bit13_pos_10a), |
| 1023 | .din0 (c0_2), |
| 1024 | .din1 (c1_1), |
| 1025 | .din2 (nc2_2) |
| 1026 | ); |
| 1027 | |
| 1028 | |
| 1029 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit13_pos_slice_10b ( |
| 1030 | .dout (err_bit13_pos_10b), |
| 1031 | .din0 (nc3_2), |
| 1032 | .din1 (c4_1), |
| 1033 | .din2 (nc5_2) |
| 1034 | ); |
| 1035 | |
| 1036 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit13_pos_slice_10c ( |
| 1037 | .dout (err_bit_pos[13]), |
| 1038 | .din0 (err_bit13_pos_10a), |
| 1039 | .din1 (err_bit13_pos_10b) |
| 1040 | ); |
| 1041 | |
| 1042 | // bit 14 |
| 1043 | |
| 1044 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit14_pos_slice_10a ( |
| 1045 | .dout (err_bit14_pos_10a), |
| 1046 | .din0 (nc0_1), |
| 1047 | .din1 (nc1_2), |
| 1048 | .din2 (c2_2) |
| 1049 | ); |
| 1050 | |
| 1051 | |
| 1052 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit14_pos_slice_10b ( |
| 1053 | .dout (err_bit14_pos_10b), |
| 1054 | .din0 (nc3_2), |
| 1055 | .din1 (c4_1), |
| 1056 | .din2 (nc5_2) |
| 1057 | ); |
| 1058 | |
| 1059 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit14_pos_slice_10c ( |
| 1060 | .dout (err_bit_pos[14]), |
| 1061 | .din0 (err_bit14_pos_10a), |
| 1062 | .din1 (err_bit14_pos_10b) |
| 1063 | ); |
| 1064 | |
| 1065 | // bit 15 |
| 1066 | |
| 1067 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit15_pos_slice_10a ( |
| 1068 | .dout (err_bit15_pos_10a), |
| 1069 | .din0 (c0_2), |
| 1070 | .din1 (nc1_2), |
| 1071 | .din2 (c2_2) |
| 1072 | ); |
| 1073 | |
| 1074 | |
| 1075 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit15_pos_slice_10b ( |
| 1076 | .dout (err_bit15_pos_10b), |
| 1077 | .din0 (nc3_2), |
| 1078 | .din1 (c4_2), |
| 1079 | .din2 (nc5_2) |
| 1080 | ); |
| 1081 | |
| 1082 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit15_pos_slice_10c ( |
| 1083 | .dout (err_bit_pos[15]), |
| 1084 | .din0 (err_bit15_pos_10a), |
| 1085 | .din1 (err_bit15_pos_10b) |
| 1086 | ); |
| 1087 | |
| 1088 | // bit 16 |
| 1089 | |
| 1090 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit16_pos_slice_10a ( |
| 1091 | .dout (err_bit16_pos_10a), |
| 1092 | .din0 (nc0_2), |
| 1093 | .din1 (c1_2), |
| 1094 | .din2 (c2_2) |
| 1095 | ); |
| 1096 | |
| 1097 | |
| 1098 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit16_pos_slice_10b ( |
| 1099 | .dout (err_bit16_pos_10b), |
| 1100 | .din0 (nc3_2), |
| 1101 | .din1 (c4_2), |
| 1102 | .din2 (nc5_2) |
| 1103 | ); |
| 1104 | |
| 1105 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit16_pos_slice_10c ( |
| 1106 | .dout (err_bit_pos[16]), |
| 1107 | .din0 (err_bit16_pos_10a), |
| 1108 | .din1 (err_bit16_pos_10b) |
| 1109 | ); |
| 1110 | |
| 1111 | // bit 17 |
| 1112 | |
| 1113 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit17_pos_slice_10a ( |
| 1114 | .dout (err_bit17_pos_10a), |
| 1115 | .din0 (c0_3), |
| 1116 | .din1 (c1_2), |
| 1117 | .din2 (c2_2) |
| 1118 | ); |
| 1119 | |
| 1120 | |
| 1121 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit17_pos_slice_10b ( |
| 1122 | .dout (err_bit17_pos_10b), |
| 1123 | .din0 (nc3_2), |
| 1124 | .din1 (c4_2), |
| 1125 | .din2 (nc5_2) |
| 1126 | ); |
| 1127 | |
| 1128 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit17_pos_slice_10c ( |
| 1129 | .dout (err_bit_pos[17]), |
| 1130 | .din0 (err_bit17_pos_10a), |
| 1131 | .din1 (err_bit17_pos_10b) |
| 1132 | ); |
| 1133 | |
| 1134 | // bit 18 |
| 1135 | |
| 1136 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit18_pos_slice_10a ( |
| 1137 | .dout (err_bit18_pos_10a), |
| 1138 | .din0 (nc0_2), |
| 1139 | .din1 (nc1_2), |
| 1140 | .din2 (nc2_2) |
| 1141 | ); |
| 1142 | |
| 1143 | |
| 1144 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit18_pos_slice_10b ( |
| 1145 | .dout (err_bit18_pos_10b), |
| 1146 | .din0 (c3_2), |
| 1147 | .din1 (c4_2), |
| 1148 | .din2 (nc5_1) |
| 1149 | ); |
| 1150 | |
| 1151 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit18_pos_slice_10c ( |
| 1152 | .dout (err_bit_pos[18]), |
| 1153 | .din0 (err_bit18_pos_10a), |
| 1154 | .din1 (err_bit18_pos_10b) |
| 1155 | ); |
| 1156 | |
| 1157 | // bit 19 |
| 1158 | |
| 1159 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit19_pos_slice_10a ( |
| 1160 | .dout (err_bit19_pos_10a), |
| 1161 | .din0 (c0_3), |
| 1162 | .din1 (nc1_2), |
| 1163 | .din2 (nc2_2) |
| 1164 | ); |
| 1165 | |
| 1166 | |
| 1167 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit19_pos_slice_10b ( |
| 1168 | .dout (err_bit19_pos_10b), |
| 1169 | .din0 (c3_2), |
| 1170 | .din1 (c4_1), |
| 1171 | .din2 (nc5_1) |
| 1172 | ); |
| 1173 | |
| 1174 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit19_pos_slice_10c ( |
| 1175 | .dout (err_bit_pos[19]), |
| 1176 | .din0 (err_bit19_pos_10a), |
| 1177 | .din1 (err_bit19_pos_10b) |
| 1178 | ); |
| 1179 | |
| 1180 | // bit 20 |
| 1181 | |
| 1182 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit20_pos_slice_10a ( |
| 1183 | .dout (err_bit20_pos_10a), |
| 1184 | .din0 (nc0_2), |
| 1185 | .din1 (c1_2), |
| 1186 | .din2 (nc2_2) |
| 1187 | ); |
| 1188 | |
| 1189 | |
| 1190 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit20_pos_slice_10b ( |
| 1191 | .dout (err_bit20_pos_10b), |
| 1192 | .din0 (c3_2), |
| 1193 | .din1 (c4_2), |
| 1194 | .din2 (nc5_1) |
| 1195 | ); |
| 1196 | |
| 1197 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit20_pos_slice_10c ( |
| 1198 | .dout (err_bit_pos[20]), |
| 1199 | .din0 (err_bit20_pos_10a), |
| 1200 | .din1 (err_bit20_pos_10b) |
| 1201 | ); |
| 1202 | |
| 1203 | // bit 21 |
| 1204 | |
| 1205 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit21_pos_slice_10a ( |
| 1206 | .dout (err_bit21_pos_10a), |
| 1207 | .din0 (c0_3), |
| 1208 | .din1 (c1_2), |
| 1209 | .din2 (nc2_2) |
| 1210 | ); |
| 1211 | |
| 1212 | |
| 1213 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit21_pos_slice_10b ( |
| 1214 | .dout (err_bit21_pos_10b), |
| 1215 | .din0 (c3_2), |
| 1216 | .din1 (c4_1), |
| 1217 | .din2 (nc5_2) |
| 1218 | ); |
| 1219 | |
| 1220 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit21_pos_slice_10c ( |
| 1221 | .dout (err_bit_pos[21]), |
| 1222 | .din0 (err_bit21_pos_10a), |
| 1223 | .din1 (err_bit21_pos_10b) |
| 1224 | ); |
| 1225 | |
| 1226 | // bit 22 |
| 1227 | |
| 1228 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit22_pos_slice_10a ( |
| 1229 | .dout (err_bit22_pos_10a), |
| 1230 | .din0 (nc0_2), |
| 1231 | .din1 (nc1_2), |
| 1232 | .din2 (c2_2) |
| 1233 | ); |
| 1234 | |
| 1235 | |
| 1236 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit22_pos_slice_10b ( |
| 1237 | .dout (err_bit22_pos_10b), |
| 1238 | .din0 (c3_2), |
| 1239 | .din1 (c4_2), |
| 1240 | .din2 (nc5_2) |
| 1241 | ); |
| 1242 | |
| 1243 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit22_pos_slice_10c ( |
| 1244 | .dout (err_bit_pos[22]), |
| 1245 | .din0 (err_bit22_pos_10a), |
| 1246 | .din1 (err_bit22_pos_10b) |
| 1247 | ); |
| 1248 | |
| 1249 | // bit 23 |
| 1250 | |
| 1251 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit23_pos_slice_10a ( |
| 1252 | .dout (err_bit23_pos_10a), |
| 1253 | .din0 (c0_3), |
| 1254 | .din1 (nc1_2), |
| 1255 | .din2 (c2_2) |
| 1256 | ); |
| 1257 | |
| 1258 | |
| 1259 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit23_pos_slice_10b ( |
| 1260 | .dout (err_bit23_pos_10b), |
| 1261 | .din0 (c3_2), |
| 1262 | .din1 (c4_1), |
| 1263 | .din2 (nc5_2) |
| 1264 | ); |
| 1265 | |
| 1266 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit23_pos_slice_10c ( |
| 1267 | .dout (err_bit_pos[23]), |
| 1268 | .din0 (err_bit23_pos_10a), |
| 1269 | .din1 (err_bit23_pos_10b) |
| 1270 | ); |
| 1271 | |
| 1272 | // bit 24 |
| 1273 | |
| 1274 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit24_pos_slice_10a ( |
| 1275 | .dout (err_bit24_pos_10a), |
| 1276 | .din0 (nc0_2), |
| 1277 | .din1 (c1_2), |
| 1278 | .din2 (c2_2) |
| 1279 | ); |
| 1280 | |
| 1281 | |
| 1282 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit24_pos_slice_10b ( |
| 1283 | .dout (err_bit24_pos_10b), |
| 1284 | .din0 (c3_2), |
| 1285 | .din1 (c4_2), |
| 1286 | .din2 (nc5_2) |
| 1287 | ); |
| 1288 | |
| 1289 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit24_pos_slice_10c ( |
| 1290 | .dout (err_bit_pos[24]), |
| 1291 | .din0 (err_bit24_pos_10a), |
| 1292 | .din1 (err_bit24_pos_10b) |
| 1293 | ); |
| 1294 | |
| 1295 | // bit 25 |
| 1296 | |
| 1297 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit25_pos_slice_10a ( |
| 1298 | .dout (err_bit25_pos_10a), |
| 1299 | .din0 (c0_3), |
| 1300 | .din1 (c1_2), |
| 1301 | .din2 (c2_2) |
| 1302 | ); |
| 1303 | |
| 1304 | |
| 1305 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit25_pos_slice_10b ( |
| 1306 | .dout (err_bit25_pos_10b), |
| 1307 | .din0 (c3_2), |
| 1308 | .din1 (c4_2), |
| 1309 | .din2 (nc5_1) |
| 1310 | ); |
| 1311 | |
| 1312 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit25_pos_slice_10c ( |
| 1313 | .dout (err_bit_pos[25]), |
| 1314 | .din0 (err_bit25_pos_10a), |
| 1315 | .din1 (err_bit25_pos_10b) |
| 1316 | ); |
| 1317 | |
| 1318 | // bit 26 |
| 1319 | |
| 1320 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit26_pos_slice_10a ( |
| 1321 | .dout (err_bit26_pos_10a), |
| 1322 | .din0 (c0_3), |
| 1323 | .din1 (nc1_1), |
| 1324 | .din2 (nc2_1) |
| 1325 | ); |
| 1326 | |
| 1327 | |
| 1328 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit26_pos_slice_10b ( |
| 1329 | .dout (err_bit26_pos_10b), |
| 1330 | .din0 (nc3_2), |
| 1331 | .din1 (nc4_1), |
| 1332 | .din2 (c5) |
| 1333 | ); |
| 1334 | |
| 1335 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit26_pos_slice_10c ( |
| 1336 | .dout (err_bit_pos[26]), |
| 1337 | .din0 (err_bit26_pos_10a), |
| 1338 | .din1 (err_bit26_pos_10b) |
| 1339 | ); |
| 1340 | |
| 1341 | // bit 27 |
| 1342 | |
| 1343 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit27_pos_slice_10a ( |
| 1344 | .dout (err_bit27_pos_10a), |
| 1345 | .din0 (nc0_2), |
| 1346 | .din1 (c1_2), |
| 1347 | .din2 (nc2_1) |
| 1348 | ); |
| 1349 | |
| 1350 | |
| 1351 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit27_pos_slice_10b ( |
| 1352 | .dout (err_bit27_pos_10b), |
| 1353 | .din0 (nc3_2), |
| 1354 | .din1 (nc4_1), |
| 1355 | .din2 (c5) |
| 1356 | ); |
| 1357 | |
| 1358 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit27_pos_slice_10c ( |
| 1359 | .dout (err_bit_pos[27]), |
| 1360 | .din0 (err_bit27_pos_10a), |
| 1361 | .din1 (err_bit27_pos_10b) |
| 1362 | ); |
| 1363 | |
| 1364 | // bit 28 |
| 1365 | |
| 1366 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit28_pos_slice_10a ( |
| 1367 | .dout (err_bit28_pos_10a), |
| 1368 | .din0 (c0_3), |
| 1369 | .din1 (c1_2), |
| 1370 | .din2 (nc2_1) |
| 1371 | ); |
| 1372 | |
| 1373 | |
| 1374 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit28_pos_slice_10b ( |
| 1375 | .dout (err_bit28_pos_10b), |
| 1376 | .din0 (nc3_1), |
| 1377 | .din1 (nc4_1), |
| 1378 | .din2 (c5) |
| 1379 | ); |
| 1380 | |
| 1381 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit28_pos_slice_10c ( |
| 1382 | .dout (err_bit_pos[28]), |
| 1383 | .din0 (err_bit28_pos_10a), |
| 1384 | .din1 (err_bit28_pos_10b) |
| 1385 | ); |
| 1386 | |
| 1387 | // bit 29 |
| 1388 | |
| 1389 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit29_pos_slice_10a ( |
| 1390 | .dout (err_bit29_pos_10a), |
| 1391 | .din0 (nc0_2), |
| 1392 | .din1 (nc1_1), |
| 1393 | .din2 (c2_2) |
| 1394 | ); |
| 1395 | |
| 1396 | |
| 1397 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit29_pos_slice_10b ( |
| 1398 | .dout (err_bit29_pos_10b), |
| 1399 | .din0 (nc3_1), |
| 1400 | .din1 (nc4_1), |
| 1401 | .din2 (c5) |
| 1402 | ); |
| 1403 | |
| 1404 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit29_pos_slice_10c ( |
| 1405 | .dout (err_bit_pos[29]), |
| 1406 | .din0 (err_bit29_pos_10a), |
| 1407 | .din1 (err_bit29_pos_10b) |
| 1408 | ); |
| 1409 | |
| 1410 | // bit 30 |
| 1411 | |
| 1412 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit30_pos_slice_10a ( |
| 1413 | .dout (err_bit30_pos_10a), |
| 1414 | .din0 (c0_3), |
| 1415 | .din1 (nc1_1), |
| 1416 | .din2 (c2_1) |
| 1417 | ); |
| 1418 | |
| 1419 | |
| 1420 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit30_pos_slice_10b ( |
| 1421 | .dout (err_bit30_pos_10b), |
| 1422 | .din0 (nc3_1), |
| 1423 | .din1 (nc4_2), |
| 1424 | .din2 (c5) |
| 1425 | ); |
| 1426 | |
| 1427 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit30_pos_slice_10c ( |
| 1428 | .dout (err_bit_pos[30]), |
| 1429 | .din0 (err_bit30_pos_10a), |
| 1430 | .din1 (err_bit30_pos_10b) |
| 1431 | ); |
| 1432 | |
| 1433 | // bit 31 |
| 1434 | |
| 1435 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit31_pos_slice_10a ( |
| 1436 | .dout (err_bit31_pos_10a), |
| 1437 | .din0 (nc0_2), |
| 1438 | .din1 (c1_2), |
| 1439 | .din2 (c2_1) |
| 1440 | ); |
| 1441 | |
| 1442 | |
| 1443 | l2b_ecc39_dp_nand_macro__ports_3__width_1 err_bit31_pos_slice_10b ( |
| 1444 | .dout (err_bit31_pos_10b), |
| 1445 | .din0 (nc3_1), |
| 1446 | .din1 (nc4_2), |
| 1447 | .din2 (c5) |
| 1448 | ); |
| 1449 | |
| 1450 | l2b_ecc39_dp_nor_macro__ports_2__width_1 err_bit31_pos_slice_10c ( |
| 1451 | .dout (err_bit_pos[31]), |
| 1452 | .din0 (err_bit31_pos_10a), |
| 1453 | .din1 (err_bit31_pos_10b) |
| 1454 | ); |
| 1455 | |
| 1456 | |
| 1457 | // correct the error bit, it can only correct one error bit. |
| 1458 | // assign dout = din ^ err_bit_pos; |
| 1459 | |
| 1460 | l2b_ecc39_dp_xor_macro__stack_32r__width_32 dout_slice |
| 1461 | ( |
| 1462 | .dout (dout[31:0]), |
| 1463 | .din0 (din[31:0]), |
| 1464 | .din1 (err_bit_pos[31:0]) |
| 1465 | ); |
| 1466 | |
| 1467 | |
| 1468 | endmodule |
| 1469 | |
| 1470 | |
| 1471 | // |
| 1472 | // xor macro for ports = 2,3 |
| 1473 | // |
| 1474 | // |
| 1475 | |
| 1476 | |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | module l2b_ecc39_dp_xor_macro__dxor_8x__ports_3__width_1 ( |
| 1481 | din0, |
| 1482 | din1, |
| 1483 | din2, |
| 1484 | dout); |
| 1485 | input [0:0] din0; |
| 1486 | input [0:0] din1; |
| 1487 | input [0:0] din2; |
| 1488 | output [0:0] dout; |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | xor3 #(1) d0_0 ( |
| 1495 | .in0(din0[0:0]), |
| 1496 | .in1(din1[0:0]), |
| 1497 | .in2(din2[0:0]), |
| 1498 | .out(dout[0:0]) |
| 1499 | ); |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | endmodule |
| 1509 | |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | // |
| 1515 | // xor macro for ports = 2,3 |
| 1516 | // |
| 1517 | // |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | |
| 1523 | module l2b_ecc39_dp_xor_macro__dxor_16x__ports_3__width_1 ( |
| 1524 | din0, |
| 1525 | din1, |
| 1526 | din2, |
| 1527 | dout); |
| 1528 | input [0:0] din0; |
| 1529 | input [0:0] din1; |
| 1530 | input [0:0] din2; |
| 1531 | output [0:0] dout; |
| 1532 | |
| 1533 | |
| 1534 | |
| 1535 | |
| 1536 | |
| 1537 | xor3 #(1) d0_0 ( |
| 1538 | .in0(din0[0:0]), |
| 1539 | .in1(din1[0:0]), |
| 1540 | .in2(din2[0:0]), |
| 1541 | .out(dout[0:0]) |
| 1542 | ); |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | |
| 1548 | |
| 1549 | |
| 1550 | |
| 1551 | endmodule |
| 1552 | |
| 1553 | |
| 1554 | |
| 1555 | |
| 1556 | |
| 1557 | // |
| 1558 | // xor macro for ports = 2,3 |
| 1559 | // |
| 1560 | // |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | module l2b_ecc39_dp_xor_macro__dxor_16x__ports_2__width_1 ( |
| 1567 | din0, |
| 1568 | din1, |
| 1569 | dout); |
| 1570 | input [0:0] din0; |
| 1571 | input [0:0] din1; |
| 1572 | output [0:0] dout; |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | xor2 #(1) d0_0 ( |
| 1579 | .in0(din0[0:0]), |
| 1580 | .in1(din1[0:0]), |
| 1581 | .out(dout[0:0]) |
| 1582 | ); |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | |
| 1591 | endmodule |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | // |
| 1598 | // invert macro |
| 1599 | // |
| 1600 | // |
| 1601 | |
| 1602 | |
| 1603 | |
| 1604 | |
| 1605 | |
| 1606 | module l2b_ecc39_dp_inv_macro__dinv_32x__stack_1r__width_1 ( |
| 1607 | din, |
| 1608 | dout); |
| 1609 | input [0:0] din; |
| 1610 | output [0:0] dout; |
| 1611 | |
| 1612 | |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | |
| 1617 | inv #(1) d0_0 ( |
| 1618 | .in(din[0:0]), |
| 1619 | .out(dout[0:0]) |
| 1620 | ); |
| 1621 | |
| 1622 | |
| 1623 | |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | endmodule |
| 1631 | |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | |
| 1636 | // |
| 1637 | // nand macro for ports = 2,3,4 |
| 1638 | // |
| 1639 | // |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | module l2b_ecc39_dp_nand_macro__ports_3__width_1 ( |
| 1646 | din0, |
| 1647 | din1, |
| 1648 | din2, |
| 1649 | dout); |
| 1650 | input [0:0] din0; |
| 1651 | input [0:0] din1; |
| 1652 | input [0:0] din2; |
| 1653 | output [0:0] dout; |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | nand3 #(1) d0_0 ( |
| 1661 | .in0(din0[0:0]), |
| 1662 | .in1(din1[0:0]), |
| 1663 | .in2(din2[0:0]), |
| 1664 | .out(dout[0:0]) |
| 1665 | ); |
| 1666 | |
| 1667 | |
| 1668 | |
| 1669 | |
| 1670 | |
| 1671 | |
| 1672 | |
| 1673 | |
| 1674 | |
| 1675 | endmodule |
| 1676 | |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | |
| 1681 | // |
| 1682 | // nor macro for ports = 2,3 |
| 1683 | // |
| 1684 | // |
| 1685 | |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | |
| 1690 | module l2b_ecc39_dp_nor_macro__ports_2__width_1 ( |
| 1691 | din0, |
| 1692 | din1, |
| 1693 | dout); |
| 1694 | input [0:0] din0; |
| 1695 | input [0:0] din1; |
| 1696 | output [0:0] dout; |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | nor2 #(1) d0_0 ( |
| 1704 | .in0(din0[0:0]), |
| 1705 | .in1(din1[0:0]), |
| 1706 | .out(dout[0:0]) |
| 1707 | ); |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | |
| 1712 | |
| 1713 | |
| 1714 | |
| 1715 | endmodule |
| 1716 | |
| 1717 | |
| 1718 | |
| 1719 | |
| 1720 | |
| 1721 | // |
| 1722 | // xor macro for ports = 2,3 |
| 1723 | // |
| 1724 | // |
| 1725 | |
| 1726 | |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | module l2b_ecc39_dp_xor_macro__stack_32r__width_32 ( |
| 1731 | din0, |
| 1732 | din1, |
| 1733 | dout); |
| 1734 | input [31:0] din0; |
| 1735 | input [31:0] din1; |
| 1736 | output [31:0] dout; |
| 1737 | |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | |
| 1742 | xor2 #(32) d0_0 ( |
| 1743 | .in0(din0[31:0]), |
| 1744 | .in1(din1[31:0]), |
| 1745 | .out(dout[31:0]) |
| 1746 | ); |
| 1747 | |
| 1748 | |
| 1749 | |
| 1750 | |
| 1751 | |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | endmodule |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |