| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2b_mb0_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2b_mb0_ctl ( |
| 36 | mbist_run, |
| 37 | mbist_addr, |
| 38 | mbist_wb_array_wr_en, |
| 39 | mbist_wb_array_rd_en, |
| 40 | mbist_rdma_array_wr_en, |
| 41 | mbist_rdma_array_rd_en, |
| 42 | mbist_fb_array_rd_en, |
| 43 | mbist_fb_array_wr_en, |
| 44 | mbist_sel_wb_arrays, |
| 45 | mbist_cmpsel, |
| 46 | mbist_compare_read_sel, |
| 47 | fb_mux_sel, |
| 48 | scan_out, |
| 49 | mbist_done, |
| 50 | mbist_fail, |
| 51 | wb_or_rdma_rw_fail, |
| 52 | fb_rw_fail, |
| 53 | rdma_mbist_enable, |
| 54 | rdma_mbist_data_in, |
| 55 | fb_mbist_enable, |
| 56 | fb_mbist_data_in, |
| 57 | wb_mbist_enable, |
| 58 | wb_mbist_data_in, |
| 59 | l2clk, |
| 60 | scan_in, |
| 61 | tcu_pce_ov, |
| 62 | tcu_clk_stop, |
| 63 | tcu_aclk, |
| 64 | tcu_bclk, |
| 65 | tcu_scan_en, |
| 66 | mbist_start, |
| 67 | mbist_user_mode, |
| 68 | mbist_bisi_mode); |
| 69 | wire pce_ov; |
| 70 | wire stop; |
| 71 | wire siclk; |
| 72 | wire soclk; |
| 73 | wire se; |
| 74 | wire l1clk; |
| 75 | wire clock_enable; |
| 76 | wire start_in; |
| 77 | wire l1clk_pm1; |
| 78 | wire array_usr_reg_scanin; |
| 79 | wire array_usr_reg_scanout; |
| 80 | wire [3:0] user_array_sel_in; |
| 81 | wire [3:0] user_array_sel; |
| 82 | wire user_addr_mode_reg_scanin; |
| 83 | wire user_addr_mode_reg_scanout; |
| 84 | wire user_addr_mode_in; |
| 85 | wire user_addr_mode; |
| 86 | wire user_start_addr_reg_scanin; |
| 87 | wire user_start_addr_reg_scanout; |
| 88 | wire [2:0] user_start_addr_in; |
| 89 | wire [2:0] user_start_addr; |
| 90 | wire user_stop_addr_reg_scanin; |
| 91 | wire user_stop_addr_reg_scanout; |
| 92 | wire [2:0] user_stop_addr_in; |
| 93 | wire [2:0] user_stop_addr; |
| 94 | wire user_incr_addr_reg_scanin; |
| 95 | wire user_incr_addr_reg_scanout; |
| 96 | wire [2:0] user_incr_addr_in; |
| 97 | wire [2:0] user_incr_addr; |
| 98 | wire user_data_mode_reg_scanin; |
| 99 | wire user_data_mode_reg_scanout; |
| 100 | wire user_data_mode_in; |
| 101 | wire user_data_mode; |
| 102 | wire user_data_reg_scanin; |
| 103 | wire user_data_reg_scanout; |
| 104 | wire [7:0] user_data_in; |
| 105 | wire [7:0] user_data; |
| 106 | wire user_cmpsel_hold_reg_scanin; |
| 107 | wire user_cmpsel_hold_reg_scanout; |
| 108 | wire user_cmpsel_hold_in; |
| 109 | wire user_cmpsel_hold; |
| 110 | wire user_cmpsel_reg_scanin; |
| 111 | wire user_cmpsel_reg_scanout; |
| 112 | wire [3:0] user_cmpsel_in; |
| 113 | wire [3:0] user_cmpsel; |
| 114 | wire user_loop_mode_reg_scanin; |
| 115 | wire user_loop_mode_reg_scanout; |
| 116 | wire user_loop_mode_in; |
| 117 | wire user_loop_mode; |
| 118 | wire ten_n_mode_reg_scanin; |
| 119 | wire ten_n_mode_reg_scanout; |
| 120 | wire ten_n_mode_in; |
| 121 | wire ten_n_mode; |
| 122 | wire input_signals_reg_scanin; |
| 123 | wire input_signals_reg_scanout; |
| 124 | wire start; |
| 125 | wire bisi_mode; |
| 126 | wire user_mode; |
| 127 | wire config_reg_scanin; |
| 128 | wire config_reg_scanout; |
| 129 | wire [1:0] config_in; |
| 130 | wire [1:0] config_out; |
| 131 | wire start_transition; |
| 132 | wire end_transition; |
| 133 | wire reset_engine; |
| 134 | wire loop_again; |
| 135 | wire run; |
| 136 | wire loop_again_reg_scanin; |
| 137 | wire loop_again_reg_scanout; |
| 138 | wire stop_engine_l; |
| 139 | wire stop_engine_l_q; |
| 140 | wire mb_user_loop_mode; |
| 141 | wire rdma_enable; |
| 142 | wire array_1; |
| 143 | wire mb_run; |
| 144 | wire fb_enable; |
| 145 | wire array_2; |
| 146 | wire wb_enable; |
| 147 | wire array_0; |
| 148 | wire sel_wb_arrays; |
| 149 | wire [15:0] cmp_sel_dec; |
| 150 | wire [3:0] cmp_sel; |
| 151 | wire mbist_misc_output_reg_scanin; |
| 152 | wire mbist_misc_output_reg_scanout; |
| 153 | wire [15:0] fb_mux_sel_unreg; |
| 154 | wire [15:0] fb_mux_sel_unreg2; |
| 155 | wire [15:0] fb_mux_sel_unreg3; |
| 156 | wire rdma_enable_d1; |
| 157 | wire fb_enable_d1; |
| 158 | wire fb_enable_d2; |
| 159 | wire wb_enable_d1; |
| 160 | wire wb_enable_d2; |
| 161 | wire cntl_reg_scanin; |
| 162 | wire cntl_reg_scanout; |
| 163 | wire [35:0] cntl_in; |
| 164 | wire [35:0] cntl_out; |
| 165 | wire run3; |
| 166 | wire [16:0] cntl_algr; |
| 167 | wire [16:0] next_algr; |
| 168 | wire sel_nextaddr_reset; |
| 169 | wire sel_nextaddr_restart; |
| 170 | wire overflow; |
| 171 | wire sel_nextaddr_incred; |
| 172 | wire cout_rw; |
| 173 | wire sel_nextaddr_same; |
| 174 | wire [2:0] start_addr; |
| 175 | wire [2:0] restart_addr; |
| 176 | wire [2:0] incred_addr; |
| 177 | wire [2:0] cntl_addr; |
| 178 | wire [2:0] cntl_rw; |
| 179 | wire [2:0] next_rw; |
| 180 | wire cntl_msb; |
| 181 | wire cntl_bisi; |
| 182 | wire mb_default_bisi; |
| 183 | wire mb_user_bisi_rw_mode; |
| 184 | wire [3:0] cntl_array_sel; |
| 185 | wire last_array; |
| 186 | wire [3:0] cntl_cmp_sel; |
| 187 | wire sel_cmp_pass; |
| 188 | wire [1:0] cntl_data_sel; |
| 189 | wire mb_user_data_mode; |
| 190 | wire cntl_addr_mix; |
| 191 | wire mb_user_addr_mode; |
| 192 | wire [3:0] cntl_march_element; |
| 193 | wire sel_march_1_pass; |
| 194 | wire addr_mix; |
| 195 | wire cout_addr; |
| 196 | wire upaddr; |
| 197 | wire march_0; |
| 198 | wire march_1; |
| 199 | wire march_2; |
| 200 | wire march_6; |
| 201 | wire march_7; |
| 202 | wire [3:0] march_element_pre; |
| 203 | wire march_pre_0; |
| 204 | wire march_pre_1; |
| 205 | wire march_pre_2; |
| 206 | wire march_pre_6; |
| 207 | wire march_pre_7; |
| 208 | wire upaddr_pre; |
| 209 | wire [2:0] incr_addr; |
| 210 | wire [2:0] stop_addr; |
| 211 | wire sel_rw_pass; |
| 212 | wire one_cycle_march; |
| 213 | wire march_5; |
| 214 | wire five_cycle_march; |
| 215 | wire march_8; |
| 216 | wire two_cycle_march; |
| 217 | wire mem_wr_pbi; |
| 218 | wire march_3; |
| 219 | wire march_4; |
| 220 | wire rw_1; |
| 221 | wire rw_0; |
| 222 | wire rw_4; |
| 223 | wire mem_wr; |
| 224 | wire bisi_wr_mode; |
| 225 | wire bisi_rd_mode; |
| 226 | wire mem_rd_pbi; |
| 227 | wire mem_rd; |
| 228 | wire [2:0] adj_addr; |
| 229 | wire rw_3; |
| 230 | wire [2:0] mem_addr1; |
| 231 | wire true_data_l; |
| 232 | wire rw_2; |
| 233 | wire true_data; |
| 234 | wire [7:0] data_pat_sel; |
| 235 | wire [7:0] mem_data; |
| 236 | wire [2:0] mem_addr; |
| 237 | wire [3:0] array_sel; |
| 238 | wire cmp_7; |
| 239 | wire cmp_15; |
| 240 | wire [3:0] march_element; |
| 241 | wire [2:0] rw; |
| 242 | wire [3:0] array_sel_cntl_out; |
| 243 | wire array_sel_reg_scanin; |
| 244 | wire array_sel_reg_scanout; |
| 245 | wire [3:0] array_sel_out; |
| 246 | wire [3:0] cmp_sel_cntl_out; |
| 247 | wire cmp_sel_reg_scanin; |
| 248 | wire cmp_sel_reg_scanout; |
| 249 | wire [3:0] cmp_sel_out; |
| 250 | wire mb_user_cmpsel_hold; |
| 251 | wire [3:0] march_element_cntl_out; |
| 252 | wire marche_element_reg_scanin; |
| 253 | wire marche_element_reg_scanout; |
| 254 | wire [3:0] march_element_out; |
| 255 | wire mb_user_bisi_wr_mode; |
| 256 | wire mb_user_bisi_rd_mode; |
| 257 | wire sel_rw_1_pass; |
| 258 | wire sel_rw_2_pass; |
| 259 | wire sel_rw_5_pass; |
| 260 | wire user_bisi_wr_mode_reg_scanin; |
| 261 | wire user_bisi_wr_mode_reg_scanout; |
| 262 | wire user_bisi_wr_mode_in; |
| 263 | wire user_bisi_wr_mode; |
| 264 | wire user_bisi_rd_mode_reg_scanin; |
| 265 | wire user_bisi_rd_mode_reg_scanout; |
| 266 | wire user_bisi_rd_mode_in; |
| 267 | wire user_bisi_rd_mode; |
| 268 | wire [4:0] mb_cmp_sel; |
| 269 | wire [2:0] mb_addr; |
| 270 | wire [7:0] mb_write_data; |
| 271 | wire mb_array_0_rd; |
| 272 | wire mb_array_1_rd; |
| 273 | wire mb_array_2_rd; |
| 274 | wire mb_array_0_wr; |
| 275 | wire mb_array_1_wr; |
| 276 | wire mb_array_2_wr; |
| 277 | wire msb_latch_scanin; |
| 278 | wire msb_latch_scanout; |
| 279 | wire msb_in; |
| 280 | wire msb_out; |
| 281 | wire mb_done; |
| 282 | wire [4:0] done_delay; |
| 283 | wire run3_transition_reg_scanin; |
| 284 | wire run3_transition_reg_scanout; |
| 285 | wire run3_out; |
| 286 | wire run3_transition; |
| 287 | wire done_delay_reg_scanin; |
| 288 | wire done_delay_reg_scanout; |
| 289 | wire [4:0] done_delay_in; |
| 290 | wire mb_rdma_rw_fail; |
| 291 | wire mb_wb_rw_fail; |
| 292 | wire mb_fb_rw_fail; |
| 293 | wire rdma_fail_d; |
| 294 | wire rdma_fail_sticky; |
| 295 | wire wb_fail_d; |
| 296 | wire wb_fail_sticky; |
| 297 | wire fb_fail_d; |
| 298 | wire fb_fail_sticky; |
| 299 | wire mbist_fail_input_reg_scanin; |
| 300 | wire mbist_fail_input_reg_scanout; |
| 301 | wire mbist_fail_sticky; |
| 302 | wire mbist_fail_array; |
| 303 | wire valid_fail; |
| 304 | wire mb_fail; |
| 305 | wire out_mb_tcu_done_reg_scanin; |
| 306 | wire out_mb_tcu_done_reg_scanout; |
| 307 | wire mb_done_out; |
| 308 | wire out_mb_tcu_fail_reg_scanin; |
| 309 | wire out_mb_tcu_fail_reg_scanout; |
| 310 | wire mb_fail_out; |
| 311 | wire out_cmp_sel_reg_scanin; |
| 312 | wire out_cmp_sel_reg_scanout; |
| 313 | wire [4:0] mb_cmpsel_out; |
| 314 | wire out_run_mb_arrays_reg_scanin; |
| 315 | wire out_run_mb_arrays_reg_scanout; |
| 316 | wire mb_run_out; |
| 317 | wire out_data_mb_arrays_delay1_reg_scanin; |
| 318 | wire out_data_mb_arrays_delay1_reg_scanout; |
| 319 | wire [7:0] mb_write_data_delay_out; |
| 320 | wire out_data_mb_arrays_delay2_reg_scanin; |
| 321 | wire out_data_mb_arrays_delay2_reg_scanout; |
| 322 | wire [7:0] mb_write_data_out; |
| 323 | wire out_data_mb_arrays_delay3_reg_scanin; |
| 324 | wire out_data_mb_arrays_delay3_reg_scanout; |
| 325 | wire [7:0] mb_write_data_out_d1; |
| 326 | wire out_addr_mb_arrays_reg_scanin; |
| 327 | wire out_addr_mb_arrays_reg_scanout; |
| 328 | wire [2:0] mb_addr_out; |
| 329 | wire out_wr_mb_arrays_reg_scanin; |
| 330 | wire out_wr_mb_arrays_reg_scanout; |
| 331 | wire mb_array_0_wr_out; |
| 332 | wire mb_array_1_wr_out; |
| 333 | wire mb_array_2_wr_out; |
| 334 | wire out_rd_mb_arrays_reg_scanin; |
| 335 | wire out_rd_mb_arrays_reg_scanout; |
| 336 | wire mb_array_0_rd_out; |
| 337 | wire mb_array_1_rd_out; |
| 338 | wire mb_array_2_rd_out; |
| 339 | wire [7:0] mbist_compare_read_sel_r; |
| 340 | wire spares_scanin; |
| 341 | wire spares_scanout; |
| 342 | |
| 343 | |
| 344 | // Please note that this is going to be used as a place holder. |
| 345 | // The inputs and outputs are defined based on the analysis of cluster memories. |
| 346 | // There are 16 instances of 16*160 rf arrays, where 156 bits of each is |
| 347 | // functionally used. The inputs of these memories are flopped and the outputs |
| 348 | // are not. |
| 349 | |
| 350 | // The plan is to test in this sequential order: |
| 351 | // 1. 4 wb_array's |
| 352 | // 2. 4 rdma_array's |
| 353 | // 3. 4 fb_array's |
| 354 | // The mbist will exercise the 4 arrays, 78 bits at a time. |
| 355 | // |
| 356 | // Functionally, the wb_array and rdma_array outputs get muxed into 78 bits |
| 357 | // and then get flopped. Mbist takes those 78 bits and compare. |
| 358 | // For fb_array, for now, the plan is to take the 624 bits to mbist controller |
| 359 | // and mux them down to 78 bits and then flop them. and finally, use the same |
| 360 | // comparators as for 78 bits from wb/rdma arrays. |
| 361 | |
| 362 | // Very IMPORTANT NOTE: Since there are 624 lines coming in, in order to reduce |
| 363 | // hardware cost due to input muxes, so that memory provides writing 0's or 1's for |
| 364 | // each bit, using two mbist related inputs to the memories: |
| 365 | // |
| 366 | // mbist_run: indicating the memory bist and |
| 367 | // mbist_data0_or1: If 0, during mbist, holding a 0 at the memory inputs, |
| 368 | // If 1, during mbist, holding a 1 at the memory inputs. |
| 369 | // Then the write is decided based on mbist_byte_en and mbist_word_en bits. |
| 370 | // |
| 371 | // changes: |
| 372 | // 06/10/05: (rdma,fb,wb)*_mbist_enable is disable when not in membist mode |
| 373 | // 06/10/05: added address mix logic |
| 374 | // 10/03/05: fb data needs to be 2 cycles compared to wr_en |
| 375 | /////////////////////////////////////////////////////////////////////////////// |
| 376 | // Outputs |
| 377 | /////////////////////////////////////////////////////////////////////////////// |
| 378 | |
| 379 | output mbist_run; |
| 380 | output [2:0] mbist_addr; |
| 381 | |
| 382 | output mbist_wb_array_wr_en; |
| 383 | output mbist_wb_array_rd_en; |
| 384 | output mbist_rdma_array_wr_en; |
| 385 | output mbist_rdma_array_rd_en; |
| 386 | output mbist_fb_array_rd_en; |
| 387 | output mbist_fb_array_wr_en; |
| 388 | |
| 389 | ///output [15:0] mbist_sel_78bits; // picks 1/16 of 623 bits |
| 390 | |
| 391 | output mbist_sel_wb_arrays; // sel=1 for wb and sel=0 for rdma |
| 392 | output [4:0] mbist_cmpsel; // Encoded mux select for wb/rdma array 1/16 |
| 393 | output [2:0] mbist_compare_read_sel; // One hot mux select for wb/rdma array compare data |
| 394 | output [15:0] fb_mux_sel; // picks 1/16 of 623 bits |
| 395 | |
| 396 | output scan_out; |
| 397 | output mbist_done; |
| 398 | output mbist_fail; |
| 399 | |
| 400 | input wb_or_rdma_rw_fail; // fb compare output |
| 401 | input fb_rw_fail; // fb compare output |
| 402 | |
| 403 | ////////////////////////////////////////////////////////////////// |
| 404 | //There are 3 different of arrays in l2b.filbuf, writeback buffer |
| 405 | //and rdma buf |
| 406 | //The following signals go to array directly. |
| 407 | //These are flopped inside the array. |
| 408 | //The enables are used as mux select to pick between functional |
| 409 | //or mbist paths. |
| 410 | ////////////////////////////////////////////////////////////////// |
| 411 | output rdma_mbist_enable; |
| 412 | output [7:0] rdma_mbist_data_in; |
| 413 | output fb_mbist_enable; |
| 414 | output [7:0] fb_mbist_data_in; |
| 415 | output wb_mbist_enable; |
| 416 | output [7:0] wb_mbist_data_in; |
| 417 | |
| 418 | /////////////////////////////////////////////////////////////////////////////// |
| 419 | // Inputs |
| 420 | /////////////////////////////////////////////////////////////////////////////// |
| 421 | |
| 422 | input l2clk; |
| 423 | input scan_in; |
| 424 | input tcu_pce_ov; // scan signals |
| 425 | input tcu_clk_stop; |
| 426 | input tcu_aclk; |
| 427 | input tcu_bclk; |
| 428 | input tcu_scan_en; |
| 429 | |
| 430 | |
| 431 | input mbist_start; |
| 432 | input mbist_user_mode; |
| 433 | input mbist_bisi_mode; |
| 434 | |
| 435 | |
| 436 | |
| 437 | // ///////////////////////////////////////////////////////////////////////////// |
| 438 | // Scan Renames |
| 439 | // ///////////////////////////////////////////////////////////////////////////// |
| 440 | |
| 441 | assign pce_ov = tcu_pce_ov; |
| 442 | assign stop = tcu_clk_stop; |
| 443 | assign siclk = tcu_aclk; |
| 444 | assign soclk = tcu_bclk; |
| 445 | assign se = tcu_scan_en; |
| 446 | |
| 447 | |
| 448 | |
| 449 | //////////////////////////////////////////////////////////////////////////////// |
| 450 | // Clock header |
| 451 | |
| 452 | |
| 453 | |
| 454 | l2b_mb0_ctl_l1clkhdr_ctl_macro clkgen_freeclk ( |
| 455 | .l2clk (l2clk ), |
| 456 | .l1en (1'b1 ), |
| 457 | .l1clk (l1clk ), |
| 458 | .pce_ov(pce_ov), |
| 459 | .stop(stop), |
| 460 | .se(se)); |
| 461 | |
| 462 | |
| 463 | assign clock_enable = start_in | mbist_done | mbist_run | mbist_fail ; |
| 464 | |
| 465 | l2b_mb0_ctl_l1clkhdr_ctl_macro clkgen ( |
| 466 | .l2clk (l2clk ), |
| 467 | .l1en (clock_enable ), |
| 468 | .l1clk (l1clk_pm1 ), |
| 469 | .pce_ov(pce_ov), |
| 470 | .stop(stop), |
| 471 | .se(se) |
| 472 | ); |
| 473 | |
| 474 | |
| 475 | |
| 476 | // ///////////////////////////////////////////////////////////////////////////// |
| 477 | // |
| 478 | // user mode resgisters |
| 479 | // MBIST PGM Control Register |
| 480 | // |
| 481 | // ///////////////////////////////////////////////////////////////////////////// |
| 482 | // ///////////////////////////////////////////////////////////////////////////// |
| 483 | |
| 484 | |
| 485 | //////////////////////////////////////////////////////////////////////////////// |
| 486 | // user control registers |
| 487 | // size |
| 488 | // - user_array_sel 4 |
| 489 | // - user_addr_mode 1 |
| 490 | // - user_start_addr 3 |
| 491 | // - user_stop_addr 3 |
| 492 | // - user_inc_addr 3 |
| 493 | // - user_data_mode 1 |
| 494 | // - user_data 8 |
| 495 | // - user_cmpsel_hold 1 |
| 496 | // - user_cmpsel 3 |
| 497 | // - user_loop_mode 1 |
| 498 | // - ten_n_mode |
| 499 | |
| 500 | |
| 501 | l2b_mb0_ctl_msff_ctl_macro__width_4 array_usr_reg ( |
| 502 | .scan_in(array_usr_reg_scanin), |
| 503 | .scan_out(array_usr_reg_scanout), |
| 504 | .l1clk ( l1clk_pm1 ), |
| 505 | .din ( user_array_sel_in[3:0] ), |
| 506 | .dout ( user_array_sel[3:0] ), |
| 507 | .siclk(siclk), |
| 508 | .soclk(soclk)); |
| 509 | |
| 510 | assign user_array_sel_in[3:0]=user_array_sel[3:0]; |
| 511 | |
| 512 | |
| 513 | // user address mode |
| 514 | |
| 515 | l2b_mb0_ctl_msff_ctl_macro__width_1 user_addr_mode_reg ( |
| 516 | .scan_in(user_addr_mode_reg_scanin), |
| 517 | .scan_out(user_addr_mode_reg_scanout), |
| 518 | .l1clk ( l1clk_pm1 ), |
| 519 | .din ( user_addr_mode_in ), |
| 520 | .dout ( user_addr_mode ), |
| 521 | .siclk(siclk), |
| 522 | .soclk(soclk)); |
| 523 | |
| 524 | assign user_addr_mode_in=user_addr_mode; |
| 525 | |
| 526 | |
| 527 | // user start address |
| 528 | |
| 529 | l2b_mb0_ctl_msff_ctl_macro__width_3 user_start_addr_reg ( |
| 530 | .scan_in(user_start_addr_reg_scanin), |
| 531 | .scan_out(user_start_addr_reg_scanout), |
| 532 | .l1clk ( l1clk_pm1 ), |
| 533 | .din ( user_start_addr_in[2:0] ), |
| 534 | .dout ( user_start_addr[2:0] ), |
| 535 | .siclk(siclk), |
| 536 | .soclk(soclk)); |
| 537 | |
| 538 | |
| 539 | assign user_start_addr_in[2:0]=user_start_addr[2:0]; |
| 540 | |
| 541 | // user stop address |
| 542 | |
| 543 | l2b_mb0_ctl_msff_ctl_macro__width_3 user_stop_addr_reg ( |
| 544 | .scan_in(user_stop_addr_reg_scanin), |
| 545 | .scan_out(user_stop_addr_reg_scanout), |
| 546 | .l1clk ( l1clk_pm1 ), |
| 547 | .din ( user_stop_addr_in[2:0] ), |
| 548 | .dout ( user_stop_addr[2:0] ), |
| 549 | .siclk(siclk), |
| 550 | .soclk(soclk)); |
| 551 | |
| 552 | |
| 553 | assign user_stop_addr_in[2:0]=user_stop_addr[2:0]; |
| 554 | |
| 555 | |
| 556 | // user increment address |
| 557 | |
| 558 | l2b_mb0_ctl_msff_ctl_macro__width_3 user_incr_addr_reg ( |
| 559 | .scan_in(user_incr_addr_reg_scanin), |
| 560 | .scan_out(user_incr_addr_reg_scanout), |
| 561 | .l1clk ( l1clk_pm1 ), |
| 562 | .din ( user_incr_addr_in[2:0] ), |
| 563 | .dout ( user_incr_addr[2:0] ), |
| 564 | .siclk(siclk), |
| 565 | .soclk(soclk)); |
| 566 | |
| 567 | |
| 568 | assign user_incr_addr_in[2:0]=user_incr_addr[2:0]; |
| 569 | |
| 570 | // user data mode |
| 571 | |
| 572 | l2b_mb0_ctl_msff_ctl_macro__width_1 user_data_mode_reg ( |
| 573 | .scan_in(user_data_mode_reg_scanin), |
| 574 | .scan_out(user_data_mode_reg_scanout), |
| 575 | .l1clk ( l1clk_pm1 ), |
| 576 | .din ( user_data_mode_in ), |
| 577 | .dout ( user_data_mode ), |
| 578 | .siclk(siclk), |
| 579 | .soclk(soclk)); |
| 580 | |
| 581 | |
| 582 | assign user_data_mode_in=user_data_mode; |
| 583 | |
| 584 | // user data select |
| 585 | |
| 586 | l2b_mb0_ctl_msff_ctl_macro__width_8 user_data_reg ( |
| 587 | .scan_in(user_data_reg_scanin), |
| 588 | .scan_out(user_data_reg_scanout), |
| 589 | .l1clk ( l1clk_pm1 ), |
| 590 | .din ( user_data_in[7:0] ), |
| 591 | .dout ( user_data[7:0] ), |
| 592 | .siclk(siclk), |
| 593 | .soclk(soclk)); |
| 594 | |
| 595 | |
| 596 | assign user_data_in[7:0] = user_data[7:0]; |
| 597 | |
| 598 | // user cmp sel inc |
| 599 | // if its one, user need to program the cmpselinc register |
| 600 | // otherwise it will loop all cmpsel |
| 601 | |
| 602 | l2b_mb0_ctl_msff_ctl_macro__width_1 user_cmpsel_hold_reg ( |
| 603 | .scan_in(user_cmpsel_hold_reg_scanin), |
| 604 | .scan_out(user_cmpsel_hold_reg_scanout), |
| 605 | .l1clk ( l1clk_pm1 ), |
| 606 | .din ( user_cmpsel_hold_in ), |
| 607 | .dout ( user_cmpsel_hold ), |
| 608 | .siclk(siclk), |
| 609 | .soclk(soclk)); |
| 610 | |
| 611 | |
| 612 | assign user_cmpsel_hold_in=user_cmpsel_hold; |
| 613 | |
| 614 | |
| 615 | |
| 616 | // user cmp sel reg |
| 617 | |
| 618 | l2b_mb0_ctl_msff_ctl_macro__width_4 user_cmpsel_reg ( |
| 619 | .scan_in(user_cmpsel_reg_scanin), |
| 620 | .scan_out(user_cmpsel_reg_scanout), |
| 621 | .l1clk ( l1clk_pm1 ), |
| 622 | .din ( user_cmpsel_in[3:0] ), |
| 623 | .dout ( user_cmpsel[3:0] ), |
| 624 | .siclk(siclk), |
| 625 | .soclk(soclk)); |
| 626 | |
| 627 | assign user_cmpsel_in[3:0]=user_cmpsel[3:0]; |
| 628 | |
| 629 | |
| 630 | // user loop mode |
| 631 | |
| 632 | l2b_mb0_ctl_msff_ctl_macro__width_1 user_loop_mode_reg ( |
| 633 | .scan_in(user_loop_mode_reg_scanin), |
| 634 | .scan_out(user_loop_mode_reg_scanout), |
| 635 | .l1clk ( l1clk_pm1 ), |
| 636 | .din ( user_loop_mode_in ), |
| 637 | .dout ( user_loop_mode ), |
| 638 | .siclk(siclk), |
| 639 | .soclk(soclk)); |
| 640 | |
| 641 | |
| 642 | assign user_loop_mode_in=user_loop_mode; |
| 643 | |
| 644 | |
| 645 | |
| 646 | // 10N Algorithm for bit mapping |
| 647 | |
| 648 | l2b_mb0_ctl_msff_ctl_macro__width_1 ten_n_mode_reg ( |
| 649 | .scan_in(ten_n_mode_reg_scanin), |
| 650 | .scan_out(ten_n_mode_reg_scanout), |
| 651 | .l1clk ( l1clk_pm1 ), |
| 652 | .din ( ten_n_mode_in ), |
| 653 | .dout ( ten_n_mode ), |
| 654 | .siclk(siclk), |
| 655 | .soclk(soclk)); |
| 656 | |
| 657 | |
| 658 | assign ten_n_mode_in=ten_n_mode; |
| 659 | |
| 660 | |
| 661 | // ///////////////////////////////////////////////////////////////////////////// |
| 662 | // |
| 663 | // MBIST Config Register |
| 664 | // |
| 665 | // ///////////////////////////////////////////////////////////////////////////// |
| 666 | // |
| 667 | // A low to high transition on mbist_start will reset and start the engine. |
| 668 | // mbist_start must remain active high for the duration of MBIST. |
| 669 | // If mbist_start deasserts the engine will stop but not reset. |
| 670 | // Once MBIST has completed mb0_done will assert and the fail status |
| 671 | // signals will be valid. |
| 672 | // To run MBIST again the mbist_start signal must transition low then high. |
| 673 | // |
| 674 | // Loop on Address will disable the address mix function. |
| 675 | // |
| 676 | // ///////////////////////////////////////////////////////////////////////////// |
| 677 | |
| 678 | |
| 679 | // flop incoming signals: |
| 680 | |
| 681 | l2b_mb0_ctl_msff_ctl_macro__width_3 input_signals_reg ( |
| 682 | .scan_in(input_signals_reg_scanin), |
| 683 | .scan_out(input_signals_reg_scanout), |
| 684 | .l1clk ( l1clk ), |
| 685 | .din ( {mbist_start,mbist_bisi_mode,mbist_user_mode} ), |
| 686 | .dout ( {start,bisi_mode,user_mode} ), |
| 687 | .siclk(siclk), |
| 688 | .soclk(soclk)); |
| 689 | |
| 690 | |
| 691 | assign start_in=start; |
| 692 | |
| 693 | // 3 cycle delay for the run signal |
| 694 | |
| 695 | |
| 696 | |
| 697 | |
| 698 | l2b_mb0_ctl_msff_ctl_macro__width_2 config_reg ( |
| 699 | .scan_in(config_reg_scanin), |
| 700 | .scan_out(config_reg_scanout), |
| 701 | .l1clk ( l1clk_pm1 ), |
| 702 | .din ( config_in[1:0] ), |
| 703 | .dout ( config_out[1:0] ), |
| 704 | .siclk(siclk), |
| 705 | .soclk(soclk)); |
| 706 | |
| 707 | |
| 708 | assign config_in[0] = start; |
| 709 | assign config_in[1] = config_out[0]; |
| 710 | assign start_transition = config_out[0] & ~config_out[1]; |
| 711 | assign end_transition = ~config_out[0] & config_out[1]; |
| 712 | assign reset_engine = start_transition | loop_again | end_transition; |
| 713 | assign run = config_out[1] ; |
| 714 | |
| 715 | |
| 716 | |
| 717 | l2b_mb0_ctl_msff_ctl_macro__width_1 loop_again_reg ( |
| 718 | .scan_in(loop_again_reg_scanin), |
| 719 | .scan_out(loop_again_reg_scanout), |
| 720 | .l1clk ( l1clk_pm1 ), |
| 721 | .din ( stop_engine_l ), |
| 722 | .dout ( stop_engine_l_q ), |
| 723 | .siclk(siclk), |
| 724 | .soclk(soclk)); |
| 725 | |
| 726 | |
| 727 | assign loop_again=mb_user_loop_mode ? stop_engine_l & ~stop_engine_l_q: 1'b0; |
| 728 | |
| 729 | |
| 730 | |
| 731 | |
| 732 | /////////////////////////////////////////////// |
| 733 | |
| 734 | assign rdma_enable = array_1 & mb_run; |
| 735 | assign fb_enable = array_2 & mb_run; |
| 736 | assign wb_enable = array_0 & mb_run; |
| 737 | |
| 738 | |
| 739 | assign sel_wb_arrays=array_0; |
| 740 | |
| 741 | |
| 742 | |
| 743 | |
| 744 | assign cmp_sel_dec[0] = array_2 & (cmp_sel[3:0]==4'b0000); |
| 745 | assign cmp_sel_dec[1] = array_2 & (cmp_sel[3:0]==4'b0001); |
| 746 | assign cmp_sel_dec[2] = array_2 & (cmp_sel[3:0]==4'b0010); |
| 747 | assign cmp_sel_dec[3] = array_2 & (cmp_sel[3:0]==4'b0011); |
| 748 | assign cmp_sel_dec[4] = array_2 & (cmp_sel[3:0]==4'b0100); |
| 749 | assign cmp_sel_dec[5] = array_2 & (cmp_sel[3:0]==4'b0101); |
| 750 | assign cmp_sel_dec[6] = array_2 & (cmp_sel[3:0]==4'b0110); |
| 751 | assign cmp_sel_dec[7] = array_2 & (cmp_sel[3:0]==4'b0111); |
| 752 | assign cmp_sel_dec[8] = array_2 & (cmp_sel[3:0]==4'b1000); |
| 753 | assign cmp_sel_dec[9] = array_2 & (cmp_sel[3:0]==4'b1001); |
| 754 | assign cmp_sel_dec[10] = array_2 & (cmp_sel[3:0]==4'b1010); |
| 755 | assign cmp_sel_dec[11] = array_2 & (cmp_sel[3:0]==4'b1011); |
| 756 | assign cmp_sel_dec[12] = array_2 & (cmp_sel[3:0]==4'b1100); |
| 757 | assign cmp_sel_dec[13] = array_2 & (cmp_sel[3:0]==4'b1101); |
| 758 | assign cmp_sel_dec[14] = array_2 & (cmp_sel[3:0]==4'b1110); |
| 759 | assign cmp_sel_dec[15] = array_2 & (cmp_sel[3:0]==4'b1111); |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | l2b_mb0_ctl_msff_ctl_macro__width_73 mbist_misc_output_reg ( |
| 766 | .scan_in(mbist_misc_output_reg_scanin), |
| 767 | .scan_out(mbist_misc_output_reg_scanout), |
| 768 | .l1clk ( l1clk_pm1 ), |
| 769 | .din ({ |
| 770 | sel_wb_arrays, |
| 771 | cmp_sel_dec[15:0], |
| 772 | fb_mux_sel_unreg[15:0], |
| 773 | fb_mux_sel_unreg2[15:0], |
| 774 | fb_mux_sel_unreg3[15:0], |
| 775 | rdma_enable, rdma_enable_d1, |
| 776 | fb_enable, fb_enable_d1, fb_enable_d2, |
| 777 | wb_enable, wb_enable_d1, wb_enable_d2 |
| 778 | }), |
| 779 | .dout ({ |
| 780 | |
| 781 | mbist_sel_wb_arrays, |
| 782 | fb_mux_sel_unreg[15:0], |
| 783 | fb_mux_sel_unreg2[15:0], |
| 784 | fb_mux_sel_unreg3[15:0], |
| 785 | fb_mux_sel[15:0], // staged 3 cycles instead of 2 |
| 786 | rdma_enable_d1, rdma_mbist_enable, // requested to delay by one cycle |
| 787 | fb_enable_d1, fb_enable_d2, fb_mbist_enable, |
| 788 | wb_enable_d1, wb_enable_d2, wb_mbist_enable |
| 789 | }), |
| 790 | .siclk(siclk), |
| 791 | .soclk(soclk)); |
| 792 | |
| 793 | |
| 794 | |
| 795 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
| 796 | //////////////////////////////////// //////////////////////////////////// |
| 797 | // CONTROL REG: |
| 798 | //////////////////////////////////// //////////////////////////////////// |
| 799 | |
| 800 | |
| 801 | l2b_mb0_ctl_msff_ctl_macro__width_36 cntl_reg ( |
| 802 | .scan_in(cntl_reg_scanin), |
| 803 | .scan_out(cntl_reg_scanout), |
| 804 | .l1clk ( l1clk_pm1 ), |
| 805 | .din ( cntl_in[35:0] ), |
| 806 | .dout ( cntl_out[35:0] ), |
| 807 | .siclk(siclk), |
| 808 | .soclk(soclk)); |
| 809 | |
| 810 | |
| 811 | assign cntl_in[35:19] = reset_engine ? {17'b000000_0000000000}: |
| 812 | ~run3 ? cntl_algr[16:0]: |
| 813 | next_algr[16:0]; |
| 814 | |
| 815 | |
| 816 | // assign cntl_in[12:3] = reset_engine ? start_addr[7:0]: |
| 817 | // ~run3 ? cntl_addr[7:0]: |
| 818 | // next_addr[7:0]; |
| 819 | |
| 820 | // reset_engine run3 overflow cout_rw output |
| 821 | // --------------------------------------------------------- |
| 822 | // 1 x x x start_addr |
| 823 | // 0 0 x x cntl_addr |
| 824 | // 0 1 1 x restart_addr |
| 825 | // 0 1 0 1 incred_addr |
| 826 | // 0 1 0 0 cntl_addr |
| 827 | |
| 828 | |
| 829 | assign sel_nextaddr_reset = reset_engine; |
| 830 | assign sel_nextaddr_restart = ~reset_engine & run3 & overflow; |
| 831 | assign sel_nextaddr_incred = ~reset_engine & run3 & ~overflow & cout_rw; |
| 832 | assign sel_nextaddr_same = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred) ; |
| 833 | |
| 834 | assign cntl_in[5:3] = ({3{sel_nextaddr_reset}} & start_addr[2:0]) | |
| 835 | ({3{sel_nextaddr_restart}} & restart_addr[2:0]) | |
| 836 | ({3{sel_nextaddr_incred}} & incred_addr[2:0]) | |
| 837 | ({3{sel_nextaddr_same}} & cntl_addr[2:0]); |
| 838 | |
| 839 | |
| 840 | |
| 841 | assign cntl_in[18:6] = 13'b0000000000000; |
| 842 | |
| 843 | |
| 844 | assign cntl_in[2:0] = reset_engine ? 3'b000 : |
| 845 | (~run3 ) ? cntl_rw[2:0]: |
| 846 | next_rw[2:0]; |
| 847 | |
| 848 | |
| 849 | |
| 850 | //////////////////////////////////// //////////////////////////////////// |
| 851 | // NEXT ALGR |
| 852 | //////////////////////////////////// //////////////////////////////////// |
| 853 | |
| 854 | // msb |
| 855 | assign cntl_msb = start_in & cntl_out[ 35]; // done selection |
| 856 | |
| 857 | |
| 858 | assign cntl_bisi = mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[34] : |
| 859 | 1'b1; |
| 860 | |
| 861 | |
| 862 | |
| 863 | // array |
| 864 | assign cntl_array_sel[3:0] = (user_mode | last_array) ? 4'b1111: |
| 865 | cntl_out[33:30]; // array selection |
| 866 | // cmp |
| 867 | assign cntl_cmp_sel[3:0] = sel_cmp_pass ? {4'b1111} : |
| 868 | cntl_out[29:26]; |
| 869 | |
| 870 | // data |
| 871 | assign cntl_data_sel[1:0] = (bisi_mode | mb_user_data_mode) ? 2'b11 : cntl_out[25:24]; // data selection |
| 872 | |
| 873 | // address mix |
| 874 | assign cntl_addr_mix = (mb_user_addr_mode | bisi_mode) ? 1'b1 : cntl_out[ 23]; // address mix |
| 875 | |
| 876 | assign cntl_march_element[3:0] = sel_march_1_pass ? 4'b1111: |
| 877 | cntl_out[22:19]; // march element |
| 878 | |
| 879 | |
| 880 | |
| 881 | assign addr_mix = (bisi_mode | mb_user_addr_mode) ? 1'b0 : |
| 882 | cntl_addr_mix; |
| 883 | |
| 884 | assign cntl_algr[16:0] = {cntl_msb, |
| 885 | cntl_bisi, |
| 886 | cntl_array_sel[3:0], |
| 887 | cntl_cmp_sel[3:0], |
| 888 | cntl_data_sel[1:0], |
| 889 | cntl_addr_mix, |
| 890 | cntl_march_element[3:0]}; |
| 891 | |
| 892 | assign next_algr[16:0] = cout_addr ? cntl_algr[16:0] + 17'h1 : cntl_algr[16:0]; // mbist control |
| 893 | |
| 894 | |
| 895 | |
| 896 | |
| 897 | //////////////////////////////////// //////////////////////////////////// |
| 898 | // NEXT ADDR |
| 899 | //////////////////////////////////// //////////////////////////////////// |
| 900 | |
| 901 | |
| 902 | ///////////////////////// |
| 903 | // address engine |
| 904 | ///////////////////////// |
| 905 | |
| 906 | |
| 907 | assign upaddr = march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ; |
| 908 | |
| 909 | |
| 910 | assign march_element_pre[3:0]=next_algr[3:0]; |
| 911 | |
| 912 | assign march_pre_0 = march_element_pre[3:0]==4'h0; |
| 913 | assign march_pre_1 = march_element_pre[3:0]==4'h1; |
| 914 | assign march_pre_2 = march_element_pre[3:0]==4'h2; |
| 915 | assign march_pre_6 = march_element_pre[3:0]==4'h6; |
| 916 | assign march_pre_7 = march_element_pre[3:0]==4'h7; |
| 917 | |
| 918 | assign upaddr_pre = march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7; |
| 919 | |
| 920 | |
| 921 | assign incr_addr[2:0] = mb_user_addr_mode ? user_incr_addr[2:0] : 3'b001; |
| 922 | |
| 923 | assign start_addr[2:0] = mb_user_addr_mode ? user_start_addr[2:0] : 3'b000; |
| 924 | |
| 925 | |
| 926 | // assign next_addr_out[8:0] = cout_rw ? cntl_addr[8:0] + incr_addr[8:0] : cntl_addr[8:0]; // next address |
| 927 | |
| 928 | |
| 929 | assign incred_addr[2:0] = cntl_addr[2:0] + incr_addr[2:0]; |
| 930 | |
| 931 | |
| 932 | assign overflow = upaddr ? ( cntl_addr[2:0] == stop_addr[2:0]) & (cntl_rw[2:0]==3'b111): |
| 933 | (~cntl_addr[2:0] == start_addr[2:0]) & (cntl_rw[2:0]==3'b111); |
| 934 | |
| 935 | |
| 936 | // assign next_addr[4:0]= overflow ? restart_addr[4:0] : next_addr_out[4:0]; |
| 937 | |
| 938 | assign restart_addr[2:0] = upaddr_pre ? start_addr[2:0] : ~stop_addr[2:0]; |
| 939 | |
| 940 | assign cout_addr = overflow; |
| 941 | |
| 942 | |
| 943 | |
| 944 | |
| 945 | //////////////////////////////////// //////////////////////////////////// |
| 946 | // NEXT RW |
| 947 | //////////////////////////////////// //////////////////////////////////// |
| 948 | |
| 949 | |
| 950 | assign cntl_rw[2:0] = sel_rw_pass ? 3'b111: |
| 951 | cntl_out[ 2: 0]; // read write control |
| 952 | |
| 953 | assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ; |
| 954 | |
| 955 | assign cout_rw = &cntl_rw[2:0]; // carry over for rw |
| 956 | |
| 957 | |
| 958 | |
| 959 | //////////////////////////////////// //////////////////////////////////// |
| 960 | // MBIST CONTROL SIGNAL |
| 961 | // - mem_wr |
| 962 | //////////////////////////////////// //////////////////////////////////// |
| 963 | |
| 964 | |
| 965 | assign one_cycle_march = march_0 | march_5 | march_7; |
| 966 | assign five_cycle_march = march_6 | march_8; |
| 967 | assign two_cycle_march = ~(one_cycle_march | five_cycle_march); |
| 968 | |
| 969 | |
| 970 | ///////////////////////// |
| 971 | // membist write enable |
| 972 | ///////////////////////// |
| 973 | |
| 974 | |
| 975 | assign mem_wr_pbi = run3 & ( |
| 976 | march_0 | |
| 977 | ((march_1 | march_2 | march_3 | march_4 ) & rw_1) | |
| 978 | (march_6 & (rw_0 | rw_1 | rw_4)) | |
| 979 | march_7 | |
| 980 | (march_8 & (rw_0 | rw_1 | rw_4)) |
| 981 | ); |
| 982 | |
| 983 | assign mem_wr = bisi_wr_mode ? 1'b1 : |
| 984 | bisi_rd_mode ? 1'b0 : |
| 985 | mem_wr_pbi; |
| 986 | |
| 987 | ///////////////////////// |
| 988 | // membist read enable |
| 989 | ///////////////////////// |
| 990 | |
| 991 | |
| 992 | |
| 993 | assign mem_rd_pbi = run3 & ~mem_wr; |
| 994 | |
| 995 | |
| 996 | assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi; |
| 997 | |
| 998 | ///////////////////// |
| 999 | // membist address: |
| 1000 | //////////////////// |
| 1001 | |
| 1002 | assign cntl_addr[2:0] = cntl_out[5:3]; |
| 1003 | |
| 1004 | assign adj_addr = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[2:1],~cntl_addr[0]}: |
| 1005 | cntl_addr[2:0] ; |
| 1006 | |
| 1007 | assign mem_addr1[2:0] = upaddr ? adj_addr[2:0]: ~adj_addr[2:0]; |
| 1008 | |
| 1009 | |
| 1010 | |
| 1011 | ///////////////////// |
| 1012 | // true data |
| 1013 | //////////////////// |
| 1014 | |
| 1015 | assign true_data_l = bisi_mode | |
| 1016 | march_0 | |
| 1017 | (march_1 & rw_0) | |
| 1018 | (march_2 & rw_1) | |
| 1019 | (march_3 & rw_0) | |
| 1020 | (march_4 & rw_1) | |
| 1021 | (march_5) | |
| 1022 | (march_6 & (rw_1 | rw_3 | rw_4)) | |
| 1023 | (march_8 & (rw_0 | rw_2)); |
| 1024 | |
| 1025 | assign true_data=~true_data_l; |
| 1026 | |
| 1027 | ///////////////////// |
| 1028 | // membist data: |
| 1029 | //////////////////// |
| 1030 | |
| 1031 | assign data_pat_sel[7:0] = (mb_user_data_mode & bisi_mode) ? ~user_data[7:0]: |
| 1032 | (mb_user_data_mode) ? user_data[7:0]: |
| 1033 | bisi_mode ? 8'hFF: |
| 1034 | (cntl_data_sel[1:0] == 2'h0) ? 8'hAA: |
| 1035 | (cntl_data_sel[1:0] == 2'h1) ? 8'h99: |
| 1036 | (cntl_data_sel[1:0] == 2'h2) ? 8'hCC: |
| 1037 | 8'h00; |
| 1038 | assign mem_data[7:0] = true_data ? data_pat_sel[7:0] : ~data_pat_sel[7:0]; |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | //////////////////////////////////// //////////////////////////////////// |
| 1043 | // STOP ADDR |
| 1044 | //////////////////////////////////// //////////////////////////////////// |
| 1045 | |
| 1046 | |
| 1047 | assign stop_addr[2:0] = user_mode & user_addr_mode ? user_stop_addr[2:0] : |
| 1048 | (array_0 | array_2) ? 3'b111: // wb |
| 1049 | (array_1) ? 3'b011: // rdma |
| 1050 | 3'b111; |
| 1051 | |
| 1052 | |
| 1053 | |
| 1054 | //////////////////////////////////// //////////////////////////////////// |
| 1055 | // ADDR MIX |
| 1056 | //////////////////////////////////// //////////////////////////////////// |
| 1057 | |
| 1058 | |
| 1059 | assign mem_addr[2:0] = (addr_mix & (array_0 | array_2)) ? { mem_addr1[0],mem_addr1[2],mem_addr1[1] } : |
| 1060 | (addr_mix & array_1) ? { mem_addr1[2],mem_addr1[0],mem_addr1[1] } : |
| 1061 | mem_addr1[2:0]; |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | //////////////////////////////////// //////////////////////////////////// |
| 1066 | // SEQ selection |
| 1067 | //////////////////////////////////// //////////////////////////////////// |
| 1068 | |
| 1069 | // array |
| 1070 | |
| 1071 | assign array_0 = array_sel[3:0]==4'h0; |
| 1072 | assign array_1 = array_sel[3:0]==4'h1; |
| 1073 | assign array_2 = array_sel[3:0]==4'h2; |
| 1074 | |
| 1075 | assign last_array= array_2; |
| 1076 | |
| 1077 | // cmp |
| 1078 | // assign cmp_0 = cmp_sel[4:0]==5'b00000; |
| 1079 | // assign cmp_1 = cmp_sel[4:0]==5'b00001; |
| 1080 | // assign cmp_2 = cmp_sel[4:0]==5'b00010; |
| 1081 | // assign cmp_3 = cmp_sel[4:0]==5'b00011; |
| 1082 | // assign cmp_4 = cmp_sel[4:0]==5'b00100; |
| 1083 | // assign cmp_5 = cmp_sel[4:0]==5'b00101; |
| 1084 | // assign cmp_6 = cmp_sel[4:0]==5'b00110; |
| 1085 | assign cmp_7 = cmp_sel[3:0]==4'b0111; |
| 1086 | assign cmp_15 = cmp_sel[3:0]==4'b1111; |
| 1087 | |
| 1088 | // march |
| 1089 | |
| 1090 | assign march_0 = (march_element[3:0]==4'h0); |
| 1091 | assign march_1 = (march_element[3:0]==4'h1); |
| 1092 | assign march_2 = (march_element[3:0]==4'h2); |
| 1093 | assign march_3 = (march_element[3:0]==4'h3); |
| 1094 | assign march_4 = (march_element[3:0]==4'h4); |
| 1095 | assign march_5 = (march_element[3:0]==4'h5); |
| 1096 | assign march_6 = (march_element[3:0]==4'h6); |
| 1097 | assign march_7 = (march_element[3:0]==4'h7); |
| 1098 | assign march_8 = (march_element[3:0]==4'h8); |
| 1099 | |
| 1100 | // rw |
| 1101 | |
| 1102 | assign rw_0 = (rw[2:0]==3'b000); |
| 1103 | assign rw_1 = (rw[2:0]==3'b001); |
| 1104 | assign rw_2 = (rw[2:0]==3'b010); |
| 1105 | assign rw_3 = (rw[2:0]==3'b011); |
| 1106 | assign rw_4 = (rw[2:0]==3'b100); |
| 1107 | // assign rw_5 = (rw[2:0]==3'b101); |
| 1108 | // assign rw_6 = (rw[2:0]==3'b110); |
| 1109 | // assign rw_7 = (rw[2:0]==3'b111); |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | //////////////////////////////////// //////////////////////////////////// |
| 1114 | // SEQ logic |
| 1115 | //////////////////////////////////// //////////////////////////////////// |
| 1116 | |
| 1117 | |
| 1118 | // array logic |
| 1119 | |
| 1120 | assign array_sel_cntl_out[3:0]=cntl_out[33:30]; |
| 1121 | |
| 1122 | |
| 1123 | l2b_mb0_ctl_msff_ctl_macro__width_4 array_sel_reg ( |
| 1124 | .scan_in(array_sel_reg_scanin), |
| 1125 | .scan_out(array_sel_reg_scanout), |
| 1126 | .l1clk ( l1clk_pm1 ), |
| 1127 | .din ( array_sel[3:0] ), |
| 1128 | .dout ( array_sel_out[3:0] ), |
| 1129 | .siclk(siclk), |
| 1130 | .soclk(soclk)); |
| 1131 | |
| 1132 | assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] : |
| 1133 | user_mode ? user_array_sel[3:0] : |
| 1134 | array_sel_cntl_out[3:0]; |
| 1135 | |
| 1136 | |
| 1137 | |
| 1138 | // cmp logic |
| 1139 | |
| 1140 | assign cmp_sel_cntl_out[3:0] = cntl_out[29:26]; |
| 1141 | |
| 1142 | l2b_mb0_ctl_msff_ctl_macro__width_4 cmp_sel_reg ( |
| 1143 | .scan_in(cmp_sel_reg_scanin), |
| 1144 | .scan_out(cmp_sel_reg_scanout), |
| 1145 | .l1clk ( l1clk_pm1 ), |
| 1146 | .din ( cmp_sel[3:0] ), |
| 1147 | .dout ( cmp_sel_out[3:0] ), |
| 1148 | .siclk(siclk), |
| 1149 | .soclk(soclk)); |
| 1150 | |
| 1151 | assign cmp_sel[3:0]= (&cmp_sel_cntl_out[3:0] & ~array_2) ? cmp_sel_out[3:0] : |
| 1152 | mb_user_cmpsel_hold ? user_cmpsel[3:0] : |
| 1153 | cmp_sel_cntl_out[3:0]; |
| 1154 | |
| 1155 | |
| 1156 | // march logic |
| 1157 | |
| 1158 | assign march_element_cntl_out[3:0]=cntl_out[22:19]; |
| 1159 | |
| 1160 | |
| 1161 | l2b_mb0_ctl_msff_ctl_macro__width_4 marche_element_reg ( |
| 1162 | .scan_in(marche_element_reg_scanin), |
| 1163 | .scan_out(marche_element_reg_scanout), |
| 1164 | .l1clk ( l1clk_pm1 ), |
| 1165 | .din ( march_element[3:0] ), |
| 1166 | .dout ( march_element_out ), |
| 1167 | .siclk(siclk), |
| 1168 | .soclk(soclk)); |
| 1169 | |
| 1170 | assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] : |
| 1171 | march_element_cntl_out[3:0]; |
| 1172 | |
| 1173 | |
| 1174 | // rw |
| 1175 | assign rw[2:0]=cntl_out[2:0]; |
| 1176 | |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | ////////////////////////////////////////////////////////////////// |
| 1181 | // SEL_PASS LOGIC |
| 1182 | ////////////////////////////////////////////////////////////////// |
| 1183 | |
| 1184 | |
| 1185 | |
| 1186 | |
| 1187 | // march |
| 1188 | assign sel_march_1_pass = bisi_mode | (ten_n_mode & march_5) | march_8 ; |
| 1189 | |
| 1190 | |
| 1191 | // cmp |
| 1192 | |
| 1193 | assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ? ~cntl_bisi & run3 : |
| 1194 | mb_user_bisi_wr_mode & run3; |
| 1195 | |
| 1196 | assign bisi_rd_mode =mb_default_bisi | mb_user_bisi_rw_mode ? cntl_bisi & run3 : |
| 1197 | mb_user_bisi_rd_mode & run3; |
| 1198 | |
| 1199 | |
| 1200 | |
| 1201 | // cmp |
| 1202 | |
| 1203 | assign sel_cmp_pass= (mb_user_cmpsel_hold) | |
| 1204 | (array_0 & cmp_7) | |
| 1205 | (array_1 & cmp_7) | |
| 1206 | (array_2 & cmp_15) ; |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | // rw |
| 1212 | assign sel_rw_1_pass = bisi_mode | one_cycle_march ; |
| 1213 | |
| 1214 | assign sel_rw_2_pass = two_cycle_march; |
| 1215 | assign sel_rw_5_pass = five_cycle_march; |
| 1216 | |
| 1217 | assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0) | |
| 1218 | (run3 & sel_rw_2_pass & rw_1) | |
| 1219 | (run3 & sel_rw_5_pass & rw_4) ; |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | l2b_mb0_ctl_msff_ctl_macro__width_1 user_bisi_wr_mode_reg ( |
| 1225 | .scan_in(user_bisi_wr_mode_reg_scanin), |
| 1226 | .scan_out(user_bisi_wr_mode_reg_scanout), |
| 1227 | .l1clk ( l1clk_pm1 ), |
| 1228 | .din ( user_bisi_wr_mode_in ), |
| 1229 | .dout ( user_bisi_wr_mode ), |
| 1230 | .siclk(siclk), |
| 1231 | .soclk(soclk)); |
| 1232 | |
| 1233 | assign user_bisi_wr_mode_in=user_bisi_wr_mode; |
| 1234 | |
| 1235 | l2b_mb0_ctl_msff_ctl_macro__width_1 user_bisi_rd_mode_reg ( |
| 1236 | .scan_in(user_bisi_rd_mode_reg_scanin), |
| 1237 | .scan_out(user_bisi_rd_mode_reg_scanout), |
| 1238 | .l1clk ( l1clk_pm1 ), |
| 1239 | .din ( user_bisi_rd_mode_in ), |
| 1240 | .dout ( user_bisi_rd_mode ), |
| 1241 | .siclk(siclk), |
| 1242 | .soclk(soclk)); |
| 1243 | |
| 1244 | assign user_bisi_rd_mode_in=user_bisi_rd_mode; |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | assign mb_user_data_mode = user_mode & user_data_mode; |
| 1249 | assign mb_user_addr_mode = user_mode & user_addr_mode; |
| 1250 | assign mb_user_cmpsel_hold = user_mode & user_cmpsel_hold; |
| 1251 | assign mb_user_loop_mode = user_mode & user_loop_mode; |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | assign mb_user_bisi_wr_mode = user_mode & user_bisi_wr_mode & bisi_mode; |
| 1257 | assign mb_user_bisi_rd_mode = user_mode & user_bisi_rd_mode & bisi_mode; |
| 1258 | |
| 1259 | assign mb_user_bisi_rw_mode = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode; |
| 1260 | |
| 1261 | assign mb_default_bisi = bisi_mode & ~user_mode; |
| 1262 | |
| 1263 | |
| 1264 | |
| 1265 | |
| 1266 | //////////////////////////////////// //////////////////////////////////// |
| 1267 | // membist control assignment |
| 1268 | //////////////////////////////////// //////////////////////////////////// |
| 1269 | |
| 1270 | |
| 1271 | assign mb_cmp_sel[0] = (array_0 | array_1) & ((cmp_sel[3:0]==4'b0100) | (cmp_sel[3:0]==4'b0000)); |
| 1272 | assign mb_cmp_sel[1] = (array_0 | array_1) & ((cmp_sel[3:0]==4'b0101) | (cmp_sel[3:0]==4'b0001)); |
| 1273 | assign mb_cmp_sel[2] = (array_0 | array_1) & ((cmp_sel[3:0]==4'b0110) | (cmp_sel[3:0]==4'b0010)); |
| 1274 | assign mb_cmp_sel[3] = (array_0 | array_1) & ((cmp_sel[3:0]==4'b0111) | (cmp_sel[3:0]==4'b0011)); |
| 1275 | assign mb_cmp_sel[4] = (array_0 | array_1) & (cmp_sel[2]); |
| 1276 | |
| 1277 | |
| 1278 | |
| 1279 | |
| 1280 | assign mb_addr[2:0]=mem_addr[2:0]; |
| 1281 | assign mb_write_data[7:0]=mem_data[7:0]; |
| 1282 | |
| 1283 | |
| 1284 | // only one array read signal should be active |
| 1285 | |
| 1286 | assign mb_array_0_rd = array_0 & mem_rd; |
| 1287 | assign mb_array_1_rd = array_1 & mem_rd; |
| 1288 | assign mb_array_2_rd = array_2 & mem_rd; |
| 1289 | |
| 1290 | |
| 1291 | // only one array write signal should be active |
| 1292 | |
| 1293 | assign mb_array_0_wr = array_0 & mem_wr; |
| 1294 | assign mb_array_1_wr = array_1 & mem_wr; |
| 1295 | assign mb_array_2_wr = array_2 & mem_wr; |
| 1296 | |
| 1297 | |
| 1298 | assign mb_run = run; |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | //////////////////////////////////// //////////////////////////////////// |
| 1303 | // DONE LOGIC |
| 1304 | //////////////////////////////////// //////////////////////////////////// |
| 1305 | |
| 1306 | |
| 1307 | l2b_mb0_ctl_msff_ctl_macro__width_1 msb_latch ( |
| 1308 | .scan_in(msb_latch_scanin), |
| 1309 | .scan_out(msb_latch_scanout), |
| 1310 | .l1clk ( l1clk_pm1 ), |
| 1311 | .din ( msb_in ), |
| 1312 | .dout ( msb_out ), |
| 1313 | .siclk(siclk), |
| 1314 | .soclk(soclk)); |
| 1315 | |
| 1316 | assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 : |
| 1317 | (cntl_msb) ? 1'b1 : |
| 1318 | msb_out; |
| 1319 | |
| 1320 | |
| 1321 | assign stop_engine_l = start_in & cntl_msb; |
| 1322 | |
| 1323 | |
| 1324 | assign mb_done=msb_out & (done_delay[4:0]==5'b11110); |
| 1325 | |
| 1326 | assign run3 = &done_delay[4:1] & ~stop_engine_l & start_in; |
| 1327 | |
| 1328 | |
| 1329 | l2b_mb0_ctl_msff_ctl_macro__width_1 run3_transition_reg ( |
| 1330 | .scan_in(run3_transition_reg_scanin), |
| 1331 | .scan_out(run3_transition_reg_scanout), |
| 1332 | .l1clk ( l1clk_pm1 ), |
| 1333 | .din ( run3 ), |
| 1334 | .dout ( run3_out ), |
| 1335 | .siclk(siclk), |
| 1336 | .soclk(soclk)); |
| 1337 | |
| 1338 | assign run3_transition = run3 & ~run3_out; |
| 1339 | |
| 1340 | l2b_mb0_ctl_msff_ctl_macro__width_5 done_delay_reg ( |
| 1341 | .scan_in(done_delay_reg_scanin), |
| 1342 | .scan_out(done_delay_reg_scanout), |
| 1343 | .l1clk ( l1clk_pm1 ), |
| 1344 | .din ( done_delay_in[4:0] ), |
| 1345 | .dout ( done_delay[4:0] ), |
| 1346 | .siclk(siclk), |
| 1347 | .soclk(soclk)); |
| 1348 | |
| 1349 | |
| 1350 | |
| 1351 | assign done_delay_in[4:0] = run3 ? 5'b11111 : |
| 1352 | mb_done ? 5'b11110 : |
| 1353 | (run & ~run3) ? done_delay[4:0] + 5'b00001 : |
| 1354 | 5'b00000; |
| 1355 | |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | //////////////////////////////////// //////////////////////////////////// |
| 1360 | // FAIL LOGIC |
| 1361 | //////////////////////////////////// //////////////////////////////////// |
| 1362 | |
| 1363 | // mb_*_fail are the true fail signals |
| 1364 | |
| 1365 | assign mb_rdma_rw_fail = (~sel_wb_arrays & ~wb_or_rdma_rw_fail); |
| 1366 | assign mb_wb_rw_fail = ( sel_wb_arrays & ~wb_or_rdma_rw_fail); |
| 1367 | |
| 1368 | |
| 1369 | assign mb_fb_rw_fail = ~fb_rw_fail; |
| 1370 | |
| 1371 | assign rdma_fail_d=run3_transition ? 1'b0 : mb_rdma_rw_fail | rdma_fail_sticky; |
| 1372 | assign wb_fail_d =run3_transition ? 1'b0 : mb_wb_rw_fail | wb_fail_sticky; |
| 1373 | assign fb_fail_d =run3_transition ? 1'b0 : mb_fb_rw_fail | fb_fail_sticky; |
| 1374 | |
| 1375 | |
| 1376 | |
| 1377 | l2b_mb0_ctl_msff_ctl_macro__width_3 mbist_fail_input_reg ( |
| 1378 | .scan_in(mbist_fail_input_reg_scanin), |
| 1379 | .scan_out(mbist_fail_input_reg_scanout), |
| 1380 | .l1clk ( l1clk_pm1 ), |
| 1381 | .din ({rdma_fail_d, |
| 1382 | wb_fail_d, |
| 1383 | fb_fail_d |
| 1384 | }), |
| 1385 | .dout ({rdma_fail_sticky, |
| 1386 | wb_fail_sticky, |
| 1387 | fb_fail_sticky |
| 1388 | }), |
| 1389 | .siclk(siclk), |
| 1390 | .soclk(soclk)); |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | assign mbist_fail_sticky = rdma_fail_sticky | |
| 1395 | wb_fail_sticky | |
| 1396 | fb_fail_sticky; |
| 1397 | |
| 1398 | |
| 1399 | assign mbist_fail_array = mb_rdma_rw_fail | |
| 1400 | mb_wb_rw_fail | |
| 1401 | mb_fb_rw_fail ; |
| 1402 | |
| 1403 | |
| 1404 | assign valid_fail=run3 | (stop_engine_l & ~mb_done); |
| 1405 | assign mb_fail = mb_done ? mbist_fail_sticky : mbist_fail_array & valid_fail; |
| 1406 | |
| 1407 | ////////////////////////////////////////////////////////////////// |
| 1408 | // OUTPUT FLOP: |
| 1409 | ////////////////////////////////////////////////////////////////// |
| 1410 | |
| 1411 | // mb_done |
| 1412 | |
| 1413 | |
| 1414 | l2b_mb0_ctl_msff_ctl_macro__width_1 out_mb_tcu_done_reg ( |
| 1415 | .scan_in(out_mb_tcu_done_reg_scanin), |
| 1416 | .scan_out(out_mb_tcu_done_reg_scanout), |
| 1417 | .l1clk ( l1clk_pm1 ), |
| 1418 | .din ( mb_done ), |
| 1419 | .dout ( mb_done_out ), |
| 1420 | .siclk(siclk), |
| 1421 | .soclk(soclk)); |
| 1422 | |
| 1423 | |
| 1424 | // mb_fail |
| 1425 | |
| 1426 | |
| 1427 | l2b_mb0_ctl_msff_ctl_macro__width_1 out_mb_tcu_fail_reg ( |
| 1428 | .scan_in(out_mb_tcu_fail_reg_scanin), |
| 1429 | .scan_out(out_mb_tcu_fail_reg_scanout), |
| 1430 | .l1clk ( l1clk_pm1 ), |
| 1431 | .din ( mb_fail ), |
| 1432 | .dout ( mb_fail_out ), |
| 1433 | .siclk(siclk), |
| 1434 | .soclk(soclk)); |
| 1435 | |
| 1436 | |
| 1437 | |
| 1438 | |
| 1439 | // out cmpsel |
| 1440 | |
| 1441 | |
| 1442 | l2b_mb0_ctl_msff_ctl_macro__width_5 out_cmp_sel_reg ( |
| 1443 | .scan_in(out_cmp_sel_reg_scanin), |
| 1444 | .scan_out(out_cmp_sel_reg_scanout), |
| 1445 | .l1clk ( l1clk_pm1 ), |
| 1446 | .din ({ |
| 1447 | mb_cmp_sel[4:0] } ), |
| 1448 | .dout ({ |
| 1449 | mb_cmpsel_out[4:0]} ), |
| 1450 | .siclk(siclk), |
| 1451 | .soclk(soclk)); |
| 1452 | |
| 1453 | |
| 1454 | // thes are all the output flops to arrays |
| 1455 | // for the following signals: |
| 1456 | // |
| 1457 | // - run |
| 1458 | // - data |
| 1459 | // - address |
| 1460 | |
| 1461 | |
| 1462 | l2b_mb0_ctl_msff_ctl_macro__width_1 out_run_mb_arrays_reg ( |
| 1463 | .scan_in(out_run_mb_arrays_reg_scanin), |
| 1464 | .scan_out(out_run_mb_arrays_reg_scanout), |
| 1465 | .l1clk ( l1clk_pm1 ), |
| 1466 | .din ( mb_run), |
| 1467 | .dout ( mb_run_out), |
| 1468 | .siclk(siclk), |
| 1469 | .soclk(soclk)); |
| 1470 | |
| 1471 | // data 8 bits delay 1 |
| 1472 | |
| 1473 | l2b_mb0_ctl_msff_ctl_macro__width_8 out_data_mb_arrays_delay1_reg ( |
| 1474 | .scan_in(out_data_mb_arrays_delay1_reg_scanin), |
| 1475 | .scan_out(out_data_mb_arrays_delay1_reg_scanout), |
| 1476 | .l1clk ( l1clk_pm1 ), |
| 1477 | .din ( mb_write_data[7:0]), |
| 1478 | .dout ( mb_write_data_delay_out[7:0]), |
| 1479 | .siclk(siclk), |
| 1480 | .soclk(soclk)); |
| 1481 | |
| 1482 | |
| 1483 | // data 8 bits delay 2 |
| 1484 | |
| 1485 | l2b_mb0_ctl_msff_ctl_macro__width_8 out_data_mb_arrays_delay2_reg ( |
| 1486 | .scan_in(out_data_mb_arrays_delay2_reg_scanin), |
| 1487 | .scan_out(out_data_mb_arrays_delay2_reg_scanout), |
| 1488 | .l1clk ( l1clk_pm1 ), |
| 1489 | .din ( mb_write_data_delay_out[7:0]), |
| 1490 | .dout ( mb_write_data_out[7:0]), |
| 1491 | .siclk(siclk), |
| 1492 | .soclk(soclk)); |
| 1493 | |
| 1494 | |
| 1495 | // data 8 bits delay 3 only for fb |
| 1496 | |
| 1497 | l2b_mb0_ctl_msff_ctl_macro__width_8 out_data_mb_arrays_delay3_reg ( |
| 1498 | .scan_in(out_data_mb_arrays_delay3_reg_scanin), |
| 1499 | .scan_out(out_data_mb_arrays_delay3_reg_scanout), |
| 1500 | .l1clk ( l1clk_pm1 ), |
| 1501 | .din ( mb_write_data_out[7:0]), |
| 1502 | .dout ( mb_write_data_out_d1[7:0]), |
| 1503 | .siclk(siclk), |
| 1504 | .soclk(soclk)); |
| 1505 | |
| 1506 | // address 16 bits |
| 1507 | |
| 1508 | |
| 1509 | l2b_mb0_ctl_msff_ctl_macro__width_3 out_addr_mb_arrays_reg ( |
| 1510 | .scan_in(out_addr_mb_arrays_reg_scanin), |
| 1511 | .scan_out(out_addr_mb_arrays_reg_scanout), |
| 1512 | .l1clk ( l1clk_pm1 ), |
| 1513 | .din ( mb_addr[2:0]), |
| 1514 | .dout ( mb_addr_out[2:0]), |
| 1515 | .siclk(siclk), |
| 1516 | .soclk(soclk)); |
| 1517 | |
| 1518 | |
| 1519 | // write enable |
| 1520 | |
| 1521 | l2b_mb0_ctl_msff_ctl_macro__width_3 out_wr_mb_arrays_reg ( |
| 1522 | .scan_in(out_wr_mb_arrays_reg_scanin), |
| 1523 | .scan_out(out_wr_mb_arrays_reg_scanout), |
| 1524 | .l1clk ( l1clk_pm1 ), |
| 1525 | .din ( { |
| 1526 | mb_array_0_wr, |
| 1527 | mb_array_1_wr, |
| 1528 | mb_array_2_wr |
| 1529 | } ), |
| 1530 | .dout ({ |
| 1531 | mb_array_0_wr_out, |
| 1532 | mb_array_1_wr_out, |
| 1533 | mb_array_2_wr_out |
| 1534 | } ), |
| 1535 | .siclk(siclk), |
| 1536 | .soclk(soclk)); |
| 1537 | |
| 1538 | |
| 1539 | // read enable |
| 1540 | |
| 1541 | l2b_mb0_ctl_msff_ctl_macro__width_3 out_rd_mb_arrays_reg ( |
| 1542 | .scan_in(out_rd_mb_arrays_reg_scanin), |
| 1543 | .scan_out(out_rd_mb_arrays_reg_scanout), |
| 1544 | .l1clk ( l1clk_pm1 ), |
| 1545 | .din ( { |
| 1546 | mb_array_0_rd, |
| 1547 | mb_array_1_rd, |
| 1548 | mb_array_2_rd |
| 1549 | } ), |
| 1550 | .dout ({ |
| 1551 | mb_array_0_rd_out, |
| 1552 | mb_array_1_rd_out, |
| 1553 | mb_array_2_rd_out |
| 1554 | } ), |
| 1555 | .siclk(siclk), |
| 1556 | .soclk(soclk)); |
| 1557 | |
| 1558 | |
| 1559 | // port name re-assignment |
| 1560 | |
| 1561 | |
| 1562 | assign mbist_run =mb_run_out; |
| 1563 | assign rdma_mbist_data_in[7:0] =mb_write_data_out[7:0]; |
| 1564 | assign wb_mbist_data_in[7:0] =mb_write_data_out[7:0]; |
| 1565 | assign fb_mbist_data_in[7:0] =mb_write_data_out_d1[7:0]; |
| 1566 | |
| 1567 | assign mbist_addr[2:0] =mb_addr_out[2:0]; |
| 1568 | assign mbist_cmpsel[4:0] =mb_cmpsel_out[4:0]; |
| 1569 | assign mbist_fail =mb_fail_out; |
| 1570 | assign mbist_done =mb_done_out; |
| 1571 | |
| 1572 | assign mbist_wb_array_wr_en =mb_array_0_wr_out; |
| 1573 | assign mbist_rdma_array_wr_en =mb_array_1_wr_out; |
| 1574 | assign mbist_fb_array_wr_en =mb_array_2_wr_out; |
| 1575 | |
| 1576 | assign mbist_wb_array_rd_en =mb_array_0_rd_out; |
| 1577 | assign mbist_rdma_array_rd_en =mb_array_1_rd_out; |
| 1578 | assign mbist_fb_array_rd_en =mb_array_2_rd_out; |
| 1579 | |
| 1580 | // mbist_compare_read |
| 1581 | |
| 1582 | assign mbist_compare_read_sel_r[0] = ~mbist_cmpsel[4] & mbist_cmpsel[0]; |
| 1583 | assign mbist_compare_read_sel_r[1] = ~mbist_cmpsel[4] & mbist_cmpsel[1]; |
| 1584 | assign mbist_compare_read_sel_r[2] = ~mbist_cmpsel[4] & mbist_cmpsel[2]; |
| 1585 | assign mbist_compare_read_sel_r[3] = ~mbist_cmpsel[4] & mbist_cmpsel[3]; |
| 1586 | assign mbist_compare_read_sel_r[4] = mbist_cmpsel[4] & mbist_cmpsel[0]; |
| 1587 | assign mbist_compare_read_sel_r[5] = mbist_cmpsel[4] & mbist_cmpsel[1]; |
| 1588 | assign mbist_compare_read_sel_r[6] = mbist_cmpsel[4] & mbist_cmpsel[2]; |
| 1589 | assign mbist_compare_read_sel_r[7] = mbist_cmpsel[4] & mbist_cmpsel[3]; |
| 1590 | |
| 1591 | assign mbist_compare_read_sel[2] = mbist_compare_read_sel_r[4] | mbist_compare_read_sel_r[5] | mbist_compare_read_sel_r[6] | mbist_compare_read_sel_r[7]; |
| 1592 | assign mbist_compare_read_sel[1] = mbist_compare_read_sel_r[2] | mbist_compare_read_sel_r[3] | mbist_compare_read_sel_r[6] | mbist_compare_read_sel_r[7]; |
| 1593 | assign mbist_compare_read_sel[0] = mbist_compare_read_sel_r[1] | mbist_compare_read_sel_r[3] | mbist_compare_read_sel_r[5] | mbist_compare_read_sel_r[7]; |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | // spare gates: |
| 1598 | |
| 1599 | |
| 1600 | l2b_mb0_ctl_spare_ctl_macro__num_2 spares ( |
| 1601 | .scan_in(spares_scanin), |
| 1602 | .scan_out(spares_scanout), |
| 1603 | .l1clk (l1clk_pm1), |
| 1604 | .siclk(siclk), |
| 1605 | .soclk(soclk) |
| 1606 | ); |
| 1607 | |
| 1608 | |
| 1609 | |
| 1610 | supply0 vss; // <- port for ground |
| 1611 | supply1 vdd; // <- port for power |
| 1612 | // ///////////////////////////////////////////////////////////////////////////// |
| 1613 | |
| 1614 | // fixscan start: |
| 1615 | assign array_usr_reg_scanin = scan_in ; |
| 1616 | assign user_addr_mode_reg_scanin = array_usr_reg_scanout ; |
| 1617 | assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout; |
| 1618 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; |
| 1619 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; |
| 1620 | assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout; |
| 1621 | assign user_data_reg_scanin = user_data_mode_reg_scanout; |
| 1622 | assign user_cmpsel_hold_reg_scanin = user_data_reg_scanout ; |
| 1623 | assign user_cmpsel_reg_scanin = user_cmpsel_hold_reg_scanout; |
| 1624 | assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout ; |
| 1625 | assign ten_n_mode_reg_scanin = user_loop_mode_reg_scanout; |
| 1626 | assign input_signals_reg_scanin = ten_n_mode_reg_scanout ; |
| 1627 | assign config_reg_scanin = input_signals_reg_scanout; |
| 1628 | assign loop_again_reg_scanin = config_reg_scanout ; |
| 1629 | assign mbist_misc_output_reg_scanin = loop_again_reg_scanout ; |
| 1630 | assign cntl_reg_scanin = mbist_misc_output_reg_scanout; |
| 1631 | assign array_sel_reg_scanin = cntl_reg_scanout ; |
| 1632 | assign cmp_sel_reg_scanin = array_sel_reg_scanout ; |
| 1633 | assign marche_element_reg_scanin = cmp_sel_reg_scanout ; |
| 1634 | assign user_bisi_wr_mode_reg_scanin = marche_element_reg_scanout; |
| 1635 | assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout; |
| 1636 | assign msb_latch_scanin = user_bisi_rd_mode_reg_scanout; |
| 1637 | assign run3_transition_reg_scanin = msb_latch_scanout ; |
| 1638 | assign done_delay_reg_scanin = run3_transition_reg_scanout; |
| 1639 | assign mbist_fail_input_reg_scanin = done_delay_reg_scanout ; |
| 1640 | assign out_mb_tcu_done_reg_scanin = mbist_fail_input_reg_scanout; |
| 1641 | assign out_mb_tcu_fail_reg_scanin = out_mb_tcu_done_reg_scanout; |
| 1642 | assign out_cmp_sel_reg_scanin = out_mb_tcu_fail_reg_scanout; |
| 1643 | assign out_run_mb_arrays_reg_scanin = out_cmp_sel_reg_scanout ; |
| 1644 | assign out_data_mb_arrays_delay1_reg_scanin = out_run_mb_arrays_reg_scanout; |
| 1645 | assign out_data_mb_arrays_delay2_reg_scanin = out_data_mb_arrays_delay1_reg_scanout; |
| 1646 | assign out_data_mb_arrays_delay3_reg_scanin = out_data_mb_arrays_delay2_reg_scanout; |
| 1647 | assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_delay3_reg_scanout; |
| 1648 | assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout; |
| 1649 | assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout; |
| 1650 | assign spares_scanin = out_rd_mb_arrays_reg_scanout; |
| 1651 | assign scan_out = spares_scanout ; |
| 1652 | // fixscan end: |
| 1653 | endmodule |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | // any PARAMS parms go into naming of macro |
| 1661 | |
| 1662 | module l2b_mb0_ctl_l1clkhdr_ctl_macro ( |
| 1663 | l2clk, |
| 1664 | l1en, |
| 1665 | pce_ov, |
| 1666 | stop, |
| 1667 | se, |
| 1668 | l1clk); |
| 1669 | |
| 1670 | |
| 1671 | input l2clk; |
| 1672 | input l1en; |
| 1673 | input pce_ov; |
| 1674 | input stop; |
| 1675 | input se; |
| 1676 | output l1clk; |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | |
| 1681 | |
| 1682 | cl_sc1_l1hdr_8x c_0 ( |
| 1683 | |
| 1684 | |
| 1685 | .l2clk(l2clk), |
| 1686 | .pce(l1en), |
| 1687 | .l1clk(l1clk), |
| 1688 | .se(se), |
| 1689 | .pce_ov(pce_ov), |
| 1690 | .stop(stop) |
| 1691 | ); |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | endmodule |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | // any PARAMS parms go into naming of macro |
| 1710 | |
| 1711 | module l2b_mb0_ctl_msff_ctl_macro__width_4 ( |
| 1712 | din, |
| 1713 | l1clk, |
| 1714 | scan_in, |
| 1715 | siclk, |
| 1716 | soclk, |
| 1717 | dout, |
| 1718 | scan_out); |
| 1719 | wire [3:0] fdin; |
| 1720 | wire [2:0] so; |
| 1721 | |
| 1722 | input [3:0] din; |
| 1723 | input l1clk; |
| 1724 | input scan_in; |
| 1725 | |
| 1726 | |
| 1727 | input siclk; |
| 1728 | input soclk; |
| 1729 | |
| 1730 | output [3:0] dout; |
| 1731 | output scan_out; |
| 1732 | assign fdin[3:0] = din[3:0]; |
| 1733 | |
| 1734 | |
| 1735 | |
| 1736 | |
| 1737 | |
| 1738 | |
| 1739 | dff #(4) d0_0 ( |
| 1740 | .l1clk(l1clk), |
| 1741 | .siclk(siclk), |
| 1742 | .soclk(soclk), |
| 1743 | .d(fdin[3:0]), |
| 1744 | .si({scan_in,so[2:0]}), |
| 1745 | .so({so[2:0],scan_out}), |
| 1746 | .q(dout[3:0]) |
| 1747 | ); |
| 1748 | |
| 1749 | |
| 1750 | |
| 1751 | |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | endmodule |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | |
| 1774 | // any PARAMS parms go into naming of macro |
| 1775 | |
| 1776 | module l2b_mb0_ctl_msff_ctl_macro__width_1 ( |
| 1777 | din, |
| 1778 | l1clk, |
| 1779 | scan_in, |
| 1780 | siclk, |
| 1781 | soclk, |
| 1782 | dout, |
| 1783 | scan_out); |
| 1784 | wire [0:0] fdin; |
| 1785 | |
| 1786 | input [0:0] din; |
| 1787 | input l1clk; |
| 1788 | input scan_in; |
| 1789 | |
| 1790 | |
| 1791 | input siclk; |
| 1792 | input soclk; |
| 1793 | |
| 1794 | output [0:0] dout; |
| 1795 | output scan_out; |
| 1796 | assign fdin[0:0] = din[0:0]; |
| 1797 | |
| 1798 | |
| 1799 | |
| 1800 | |
| 1801 | |
| 1802 | |
| 1803 | dff #(1) d0_0 ( |
| 1804 | .l1clk(l1clk), |
| 1805 | .siclk(siclk), |
| 1806 | .soclk(soclk), |
| 1807 | .d(fdin[0:0]), |
| 1808 | .si(scan_in), |
| 1809 | .so(scan_out), |
| 1810 | .q(dout[0:0]) |
| 1811 | ); |
| 1812 | |
| 1813 | |
| 1814 | |
| 1815 | |
| 1816 | |
| 1817 | |
| 1818 | |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | |
| 1824 | endmodule |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | |
| 1829 | |
| 1830 | |
| 1831 | |
| 1832 | |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | // any PARAMS parms go into naming of macro |
| 1839 | |
| 1840 | module l2b_mb0_ctl_msff_ctl_macro__width_3 ( |
| 1841 | din, |
| 1842 | l1clk, |
| 1843 | scan_in, |
| 1844 | siclk, |
| 1845 | soclk, |
| 1846 | dout, |
| 1847 | scan_out); |
| 1848 | wire [2:0] fdin; |
| 1849 | wire [1:0] so; |
| 1850 | |
| 1851 | input [2:0] din; |
| 1852 | input l1clk; |
| 1853 | input scan_in; |
| 1854 | |
| 1855 | |
| 1856 | input siclk; |
| 1857 | input soclk; |
| 1858 | |
| 1859 | output [2:0] dout; |
| 1860 | output scan_out; |
| 1861 | assign fdin[2:0] = din[2:0]; |
| 1862 | |
| 1863 | |
| 1864 | |
| 1865 | |
| 1866 | |
| 1867 | |
| 1868 | dff #(3) d0_0 ( |
| 1869 | .l1clk(l1clk), |
| 1870 | .siclk(siclk), |
| 1871 | .soclk(soclk), |
| 1872 | .d(fdin[2:0]), |
| 1873 | .si({scan_in,so[1:0]}), |
| 1874 | .so({so[1:0],scan_out}), |
| 1875 | .q(dout[2:0]) |
| 1876 | ); |
| 1877 | |
| 1878 | |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | endmodule |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | |
| 1896 | |
| 1897 | |
| 1898 | |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | // any PARAMS parms go into naming of macro |
| 1904 | |
| 1905 | module l2b_mb0_ctl_msff_ctl_macro__width_8 ( |
| 1906 | din, |
| 1907 | l1clk, |
| 1908 | scan_in, |
| 1909 | siclk, |
| 1910 | soclk, |
| 1911 | dout, |
| 1912 | scan_out); |
| 1913 | wire [7:0] fdin; |
| 1914 | wire [6:0] so; |
| 1915 | |
| 1916 | input [7:0] din; |
| 1917 | input l1clk; |
| 1918 | input scan_in; |
| 1919 | |
| 1920 | |
| 1921 | input siclk; |
| 1922 | input soclk; |
| 1923 | |
| 1924 | output [7:0] dout; |
| 1925 | output scan_out; |
| 1926 | assign fdin[7:0] = din[7:0]; |
| 1927 | |
| 1928 | |
| 1929 | |
| 1930 | |
| 1931 | |
| 1932 | |
| 1933 | dff #(8) d0_0 ( |
| 1934 | .l1clk(l1clk), |
| 1935 | .siclk(siclk), |
| 1936 | .soclk(soclk), |
| 1937 | .d(fdin[7:0]), |
| 1938 | .si({scan_in,so[6:0]}), |
| 1939 | .so({so[6:0],scan_out}), |
| 1940 | .q(dout[7:0]) |
| 1941 | ); |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | endmodule |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | // any PARAMS parms go into naming of macro |
| 1969 | |
| 1970 | module l2b_mb0_ctl_msff_ctl_macro__width_2 ( |
| 1971 | din, |
| 1972 | l1clk, |
| 1973 | scan_in, |
| 1974 | siclk, |
| 1975 | soclk, |
| 1976 | dout, |
| 1977 | scan_out); |
| 1978 | wire [1:0] fdin; |
| 1979 | wire [0:0] so; |
| 1980 | |
| 1981 | input [1:0] din; |
| 1982 | input l1clk; |
| 1983 | input scan_in; |
| 1984 | |
| 1985 | |
| 1986 | input siclk; |
| 1987 | input soclk; |
| 1988 | |
| 1989 | output [1:0] dout; |
| 1990 | output scan_out; |
| 1991 | assign fdin[1:0] = din[1:0]; |
| 1992 | |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | dff #(2) d0_0 ( |
| 1999 | .l1clk(l1clk), |
| 2000 | .siclk(siclk), |
| 2001 | .soclk(soclk), |
| 2002 | .d(fdin[1:0]), |
| 2003 | .si({scan_in,so[0:0]}), |
| 2004 | .so({so[0:0],scan_out}), |
| 2005 | .q(dout[1:0]) |
| 2006 | ); |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | endmodule |
| 2020 | |
| 2021 | |
| 2022 | |
| 2023 | |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | |
| 2032 | |
| 2033 | // any PARAMS parms go into naming of macro |
| 2034 | |
| 2035 | module l2b_mb0_ctl_msff_ctl_macro__width_73 ( |
| 2036 | din, |
| 2037 | l1clk, |
| 2038 | scan_in, |
| 2039 | siclk, |
| 2040 | soclk, |
| 2041 | dout, |
| 2042 | scan_out); |
| 2043 | wire [72:0] fdin; |
| 2044 | wire [71:0] so; |
| 2045 | |
| 2046 | input [72:0] din; |
| 2047 | input l1clk; |
| 2048 | input scan_in; |
| 2049 | |
| 2050 | |
| 2051 | input siclk; |
| 2052 | input soclk; |
| 2053 | |
| 2054 | output [72:0] dout; |
| 2055 | output scan_out; |
| 2056 | assign fdin[72:0] = din[72:0]; |
| 2057 | |
| 2058 | |
| 2059 | |
| 2060 | |
| 2061 | |
| 2062 | |
| 2063 | dff #(73) d0_0 ( |
| 2064 | .l1clk(l1clk), |
| 2065 | .siclk(siclk), |
| 2066 | .soclk(soclk), |
| 2067 | .d(fdin[72:0]), |
| 2068 | .si({scan_in,so[71:0]}), |
| 2069 | .so({so[71:0],scan_out}), |
| 2070 | .q(dout[72:0]) |
| 2071 | ); |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | endmodule |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | // any PARAMS parms go into naming of macro |
| 2099 | |
| 2100 | module l2b_mb0_ctl_msff_ctl_macro__width_36 ( |
| 2101 | din, |
| 2102 | l1clk, |
| 2103 | scan_in, |
| 2104 | siclk, |
| 2105 | soclk, |
| 2106 | dout, |
| 2107 | scan_out); |
| 2108 | wire [35:0] fdin; |
| 2109 | wire [34:0] so; |
| 2110 | |
| 2111 | input [35:0] din; |
| 2112 | input l1clk; |
| 2113 | input scan_in; |
| 2114 | |
| 2115 | |
| 2116 | input siclk; |
| 2117 | input soclk; |
| 2118 | |
| 2119 | output [35:0] dout; |
| 2120 | output scan_out; |
| 2121 | assign fdin[35:0] = din[35:0]; |
| 2122 | |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | |
| 2128 | dff #(36) d0_0 ( |
| 2129 | .l1clk(l1clk), |
| 2130 | .siclk(siclk), |
| 2131 | .soclk(soclk), |
| 2132 | .d(fdin[35:0]), |
| 2133 | .si({scan_in,so[34:0]}), |
| 2134 | .so({so[34:0],scan_out}), |
| 2135 | .q(dout[35:0]) |
| 2136 | ); |
| 2137 | |
| 2138 | |
| 2139 | |
| 2140 | |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | |
| 2149 | endmodule |
| 2150 | |
| 2151 | |
| 2152 | |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | // any PARAMS parms go into naming of macro |
| 2164 | |
| 2165 | module l2b_mb0_ctl_msff_ctl_macro__width_5 ( |
| 2166 | din, |
| 2167 | l1clk, |
| 2168 | scan_in, |
| 2169 | siclk, |
| 2170 | soclk, |
| 2171 | dout, |
| 2172 | scan_out); |
| 2173 | wire [4:0] fdin; |
| 2174 | wire [3:0] so; |
| 2175 | |
| 2176 | input [4:0] din; |
| 2177 | input l1clk; |
| 2178 | input scan_in; |
| 2179 | |
| 2180 | |
| 2181 | input siclk; |
| 2182 | input soclk; |
| 2183 | |
| 2184 | output [4:0] dout; |
| 2185 | output scan_out; |
| 2186 | assign fdin[4:0] = din[4:0]; |
| 2187 | |
| 2188 | |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | dff #(5) d0_0 ( |
| 2194 | .l1clk(l1clk), |
| 2195 | .siclk(siclk), |
| 2196 | .soclk(soclk), |
| 2197 | .d(fdin[4:0]), |
| 2198 | .si({scan_in,so[3:0]}), |
| 2199 | .so({so[3:0],scan_out}), |
| 2200 | .q(dout[4:0]) |
| 2201 | ); |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | |
| 2212 | |
| 2213 | |
| 2214 | endmodule |
| 2215 | |
| 2216 | |
| 2217 | |
| 2218 | |
| 2219 | |
| 2220 | |
| 2221 | |
| 2222 | |
| 2223 | |
| 2224 | // Description: Spare gate macro for control blocks |
| 2225 | // |
| 2226 | // Param num controls the number of times the macro is added |
| 2227 | // flops=0 can be used to use only combination spare logic |
| 2228 | |
| 2229 | |
| 2230 | module l2b_mb0_ctl_spare_ctl_macro__num_2 ( |
| 2231 | l1clk, |
| 2232 | scan_in, |
| 2233 | siclk, |
| 2234 | soclk, |
| 2235 | scan_out); |
| 2236 | wire si_0; |
| 2237 | wire so_0; |
| 2238 | wire spare0_flop_unused; |
| 2239 | wire spare0_buf_32x_unused; |
| 2240 | wire spare0_nand3_8x_unused; |
| 2241 | wire spare0_inv_8x_unused; |
| 2242 | wire spare0_aoi22_4x_unused; |
| 2243 | wire spare0_buf_8x_unused; |
| 2244 | wire spare0_oai22_4x_unused; |
| 2245 | wire spare0_inv_16x_unused; |
| 2246 | wire spare0_nand2_16x_unused; |
| 2247 | wire spare0_nor3_4x_unused; |
| 2248 | wire spare0_nand2_8x_unused; |
| 2249 | wire spare0_buf_16x_unused; |
| 2250 | wire spare0_nor2_16x_unused; |
| 2251 | wire spare0_inv_32x_unused; |
| 2252 | wire si_1; |
| 2253 | wire so_1; |
| 2254 | wire spare1_flop_unused; |
| 2255 | wire spare1_buf_32x_unused; |
| 2256 | wire spare1_nand3_8x_unused; |
| 2257 | wire spare1_inv_8x_unused; |
| 2258 | wire spare1_aoi22_4x_unused; |
| 2259 | wire spare1_buf_8x_unused; |
| 2260 | wire spare1_oai22_4x_unused; |
| 2261 | wire spare1_inv_16x_unused; |
| 2262 | wire spare1_nand2_16x_unused; |
| 2263 | wire spare1_nor3_4x_unused; |
| 2264 | wire spare1_nand2_8x_unused; |
| 2265 | wire spare1_buf_16x_unused; |
| 2266 | wire spare1_nor2_16x_unused; |
| 2267 | wire spare1_inv_32x_unused; |
| 2268 | |
| 2269 | |
| 2270 | input l1clk; |
| 2271 | input scan_in; |
| 2272 | input siclk; |
| 2273 | input soclk; |
| 2274 | output scan_out; |
| 2275 | |
| 2276 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 2277 | .siclk(siclk), |
| 2278 | .soclk(soclk), |
| 2279 | .si(si_0), |
| 2280 | .so(so_0), |
| 2281 | .d(1'b0), |
| 2282 | .q(spare0_flop_unused)); |
| 2283 | assign si_0 = scan_in; |
| 2284 | |
| 2285 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 2286 | .out(spare0_buf_32x_unused)); |
| 2287 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 2288 | .in1(1'b1), |
| 2289 | .in2(1'b1), |
| 2290 | .out(spare0_nand3_8x_unused)); |
| 2291 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 2292 | .out(spare0_inv_8x_unused)); |
| 2293 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 2294 | .in01(1'b1), |
| 2295 | .in10(1'b1), |
| 2296 | .in11(1'b1), |
| 2297 | .out(spare0_aoi22_4x_unused)); |
| 2298 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 2299 | .out(spare0_buf_8x_unused)); |
| 2300 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 2301 | .in01(1'b1), |
| 2302 | .in10(1'b1), |
| 2303 | .in11(1'b1), |
| 2304 | .out(spare0_oai22_4x_unused)); |
| 2305 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 2306 | .out(spare0_inv_16x_unused)); |
| 2307 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 2308 | .in1(1'b1), |
| 2309 | .out(spare0_nand2_16x_unused)); |
| 2310 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 2311 | .in1(1'b0), |
| 2312 | .in2(1'b0), |
| 2313 | .out(spare0_nor3_4x_unused)); |
| 2314 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 2315 | .in1(1'b1), |
| 2316 | .out(spare0_nand2_8x_unused)); |
| 2317 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 2318 | .out(spare0_buf_16x_unused)); |
| 2319 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 2320 | .in1(1'b0), |
| 2321 | .out(spare0_nor2_16x_unused)); |
| 2322 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 2323 | .out(spare0_inv_32x_unused)); |
| 2324 | |
| 2325 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 2326 | .siclk(siclk), |
| 2327 | .soclk(soclk), |
| 2328 | .si(si_1), |
| 2329 | .so(so_1), |
| 2330 | .d(1'b0), |
| 2331 | .q(spare1_flop_unused)); |
| 2332 | assign si_1 = so_0; |
| 2333 | |
| 2334 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 2335 | .out(spare1_buf_32x_unused)); |
| 2336 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 2337 | .in1(1'b1), |
| 2338 | .in2(1'b1), |
| 2339 | .out(spare1_nand3_8x_unused)); |
| 2340 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 2341 | .out(spare1_inv_8x_unused)); |
| 2342 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 2343 | .in01(1'b1), |
| 2344 | .in10(1'b1), |
| 2345 | .in11(1'b1), |
| 2346 | .out(spare1_aoi22_4x_unused)); |
| 2347 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 2348 | .out(spare1_buf_8x_unused)); |
| 2349 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 2350 | .in01(1'b1), |
| 2351 | .in10(1'b1), |
| 2352 | .in11(1'b1), |
| 2353 | .out(spare1_oai22_4x_unused)); |
| 2354 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 2355 | .out(spare1_inv_16x_unused)); |
| 2356 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 2357 | .in1(1'b1), |
| 2358 | .out(spare1_nand2_16x_unused)); |
| 2359 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 2360 | .in1(1'b0), |
| 2361 | .in2(1'b0), |
| 2362 | .out(spare1_nor3_4x_unused)); |
| 2363 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 2364 | .in1(1'b1), |
| 2365 | .out(spare1_nand2_8x_unused)); |
| 2366 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 2367 | .out(spare1_buf_16x_unused)); |
| 2368 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 2369 | .in1(1'b0), |
| 2370 | .out(spare1_nor2_16x_unused)); |
| 2371 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 2372 | .out(spare1_inv_32x_unused)); |
| 2373 | assign scan_out = so_1; |
| 2374 | |
| 2375 | |
| 2376 | |
| 2377 | endmodule |
| 2378 | |