| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_arbdat_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2t_arbdat_dp ( |
| 36 | tcu_pce_ov, |
| 37 | tcu_aclk, |
| 38 | tcu_bclk, |
| 39 | tcu_scan_en, |
| 40 | tcu_clk_stop, |
| 41 | tcu_dectest, |
| 42 | tcu_muxtest, |
| 43 | ique_iq_arbdp_data_px2, |
| 44 | snpd_snpq_arbdp_data_px2, |
| 45 | mb_data_read_data, |
| 46 | misbuf_buf_rd_en, |
| 47 | mbdata_cmp_sel, |
| 48 | l2t_mb2_wdata, |
| 49 | mbdata_fail_bot, |
| 50 | tag_data_array_wr_active_c1, |
| 51 | misbuf_arb_l2rd_en, |
| 52 | arb_mux2_snpsel_px2, |
| 53 | arb_mux3_bufsel_px2, |
| 54 | arb_mux4_c1sel_px2, |
| 55 | arb_decc_data_sel_c9, |
| 56 | arb_bist_or_diag_acc_c1, |
| 57 | arbdec_arbdp_poison_c1, |
| 58 | bist_data_data_c1, |
| 59 | bist_data_enable_c1, |
| 60 | decc_arbdp_data_c8, |
| 61 | arb_dword_mask_c8, |
| 62 | arbdec_arbdp_inst_bufidhi_c1, |
| 63 | sel_diag_store_data_c7, |
| 64 | l2clk, |
| 65 | scan_in, |
| 66 | l2t_mb2_run, |
| 67 | scan_out, |
| 68 | st_ack_data, |
| 69 | arbdat_arbdp_oque_int_ret_c7, |
| 70 | arbdat_arbdp_store_data_c2, |
| 71 | arbdat_arbdata_wr_data_c2, |
| 72 | arbdat_mbdata_inst_data_c8, |
| 73 | arbdat_csr_inst_wr_data_c8, |
| 74 | arbdat_word_lower_cmp_c8, |
| 75 | arbdat_word_upper_cmp_c8, |
| 76 | arb_inst_vld_c2_prev, |
| 77 | dec_col_offset_prev_c1, |
| 78 | arbadr_arbdp_addr5to4_c1, |
| 79 | tag_l2d_col_offset_c2); |
| 80 | wire stop; |
| 81 | wire pce_ov; |
| 82 | wire siclk; |
| 83 | wire soclk; |
| 84 | wire se; |
| 85 | wire muxtst; |
| 86 | wire test; |
| 87 | wire ff_read_mbdata_reg1_scanin; |
| 88 | wire ff_read_mbdata_reg1_scanout; |
| 89 | wire ff_read_mbdata_reg2_scanin; |
| 90 | wire ff_read_mbdata_reg2_scanout; |
| 91 | wire arb_mux2_snpsel_px2_n; |
| 92 | wire arb_mux3_bufsel_px2_n; |
| 93 | wire arb_mux4_c1sel_px2_n; |
| 94 | wire ff_data_c11_scanin; |
| 95 | wire ff_data_c11_scanout; |
| 96 | wire ff_data_c12_scanin; |
| 97 | wire ff_data_c12_scanout; |
| 98 | wire ff_decc_data_c91_scanin; |
| 99 | wire ff_decc_data_c91_scanout; |
| 100 | wire ff_decc_data_c92_scanin; |
| 101 | wire ff_decc_data_c92_scanout; |
| 102 | wire arb_decc_data_sel_c9_n; |
| 103 | wire poison_qual_c1; |
| 104 | wire tag_data_array_wr_active_c1_n; |
| 105 | wire arbdec_arbdp_inst_bufidhi; |
| 106 | wire arbdec_arbdp_inst_bufidhi_n; |
| 107 | wire postecc_1_poison1; |
| 108 | wire postecc_1_poison0; |
| 109 | wire bist_data_enable_c1_n; |
| 110 | wire [63:0] arbdp_wr_data_c2_buff; |
| 111 | wire arb_bist_or_diag_acc_c1_n; |
| 112 | wire ff_data31to0_c2_scanin; |
| 113 | wire ff_data31to0_c2_scanout; |
| 114 | wire postecc_1_poison_33; |
| 115 | wire postecc_1_poison_32; |
| 116 | wire ff_data63to32_c2_scanin; |
| 117 | wire ff_data63to32_c2_scanout; |
| 118 | wire ff_ecc0to6_c2_scanin; |
| 119 | wire ff_ecc0to6_c2_scanout; |
| 120 | wire ff_ecc7to13_c2_scanin; |
| 121 | wire ff_ecc7to13_c2_scanout; |
| 122 | wire ff_data_c21_scanin; |
| 123 | wire ff_data_c21_scanout; |
| 124 | wire ff_data_c22_scanin; |
| 125 | wire ff_data_c22_scanout; |
| 126 | wire ff_data_c31_scanin; |
| 127 | wire ff_data_c31_scanout; |
| 128 | wire ff_data_c32_scanin; |
| 129 | wire ff_data_c32_scanout; |
| 130 | wire ff_data_c41_scanin; |
| 131 | wire ff_data_c41_scanout; |
| 132 | wire ff_data_c42_scanin; |
| 133 | wire ff_data_c42_scanout; |
| 134 | wire ff_data_c51_scanin; |
| 135 | wire ff_data_c51_scanout; |
| 136 | wire ff_data_c52_scanin; |
| 137 | wire ff_data_c52_scanout; |
| 138 | wire ff_data_c521_scanin; |
| 139 | wire ff_data_c521_scanout; |
| 140 | wire ff_data_c522_scanin; |
| 141 | wire ff_data_c522_scanout; |
| 142 | wire ff_data_c61_scanin; |
| 143 | wire ff_data_c61_scanout; |
| 144 | wire ff_data_c62_scanin; |
| 145 | wire ff_data_c62_scanout; |
| 146 | wire ff_data_c71_scanin; |
| 147 | wire ff_data_c71_scanout; |
| 148 | wire ff_data_c72_scanin; |
| 149 | wire ff_data_c72_scanout; |
| 150 | wire ff_data_c81_scanin; |
| 151 | wire ff_data_c81_scanout; |
| 152 | wire ff_data_c82_scanin; |
| 153 | wire ff_data_c82_scanout; |
| 154 | wire sel_diag_store_data_c8; |
| 155 | wire sel_diag_store_data_c8_n; |
| 156 | wire sel_diag_store_data_c7_n; |
| 157 | wire arb_dword_mask_c8_0_n; |
| 158 | wire sel_mux0_data_c6_0; |
| 159 | wire sel_mux0_data_c6_1; |
| 160 | wire arb_dword_mask_c8_7_n; |
| 161 | wire l2t_mb2_run_r1; |
| 162 | wire [7:0] l2t_mb2_wdata_r2; |
| 163 | wire arb_dword_mask_c8_1_n; |
| 164 | wire sel_mux1_data_c6_0; |
| 165 | wire sel_mux1_data_c6_1; |
| 166 | wire arb_dword_mask_c8_6_n; |
| 167 | wire arb_dword_mask_c8_2_n; |
| 168 | wire sel_mux2_data_c6_0; |
| 169 | wire sel_mux2_data_c6_1; |
| 170 | wire arb_dword_mask_c8_5_n; |
| 171 | wire arb_dword_mask_c8_3_n; |
| 172 | wire sel_mux3_data_c6_0; |
| 173 | wire sel_mux3_data_c6_1; |
| 174 | wire arb_dword_mask_c8_4_n; |
| 175 | wire sel_mux4_data_c6_0; |
| 176 | wire sel_mux4_data_c6_1; |
| 177 | wire sel_mux5_data_c6_0; |
| 178 | wire sel_mux5_data_c6_1; |
| 179 | wire sel_mux6_data_c6_0; |
| 180 | wire sel_mux6_data_c6_1; |
| 181 | wire sel_mux7_data_c6_0; |
| 182 | wire sel_mux7_data_c6_1; |
| 183 | wire mbdata_test_active; |
| 184 | wire misbuf_buf_rd_en_r2_qual; |
| 185 | wire misbuf_buf_rd_en_r2; |
| 186 | wire [31:0] mbdata_cmp_data; |
| 187 | wire mbdata_fail_unreg_w; |
| 188 | wire mbdata_fail_unreg; |
| 189 | wire misbuf_buf_rd_en_r2_n; |
| 190 | wire [7:0] l2t_mb2_wdata_r4; |
| 191 | wire ff_mbdata_mbist_reg_scanin; |
| 192 | wire ff_mbdata_mbist_reg_scanout; |
| 193 | wire [7:0] l2t_mb2_wdata_r1; |
| 194 | wire [7:0] l2t_mb2_wdata_r3; |
| 195 | wire misbuf_buf_rd_en_r1; |
| 196 | wire arb_inst_vld_c2_prev_n; |
| 197 | wire [1:0] arbadr_arbdp_addr5to4_c1_n; |
| 198 | wire col_offset_sel_c1_n; |
| 199 | wire col_offset_sel_c1; |
| 200 | wire [3:0] dec_col_offset_c1; |
| 201 | wire ff_col_offset_sel_c2_scanin; |
| 202 | wire ff_col_offset_sel_c2_scanout; |
| 203 | wire [3:0] dec_col_offset_c2; |
| 204 | wire [3:0] col_offset_dec_prev_c2; |
| 205 | wire col_offset_sel_c2; |
| 206 | wire col_offset_sel_c2_n; |
| 207 | wire [3:0] tag_l2d_col_offset_c2_1; |
| 208 | wire [3:0] tag_l2d_col_offset_c2_2; |
| 209 | |
| 210 | |
| 211 | input tcu_pce_ov; |
| 212 | input tcu_aclk; |
| 213 | input tcu_bclk; |
| 214 | input tcu_scan_en; |
| 215 | input tcu_clk_stop; |
| 216 | input tcu_dectest; |
| 217 | input tcu_muxtest; |
| 218 | |
| 219 | |
| 220 | input [63:0] ique_iq_arbdp_data_px2; // IQ data |
| 221 | |
| 222 | input [63:0] snpd_snpq_arbdp_data_px2 ; // from snpd |
| 223 | |
| 224 | input [63:0] mb_data_read_data; // data read from the Miss Buffer. |
| 225 | input misbuf_buf_rd_en; |
| 226 | input [3:0] mbdata_cmp_sel; |
| 227 | input [7:0] l2t_mb2_wdata; |
| 228 | output mbdata_fail_bot; |
| 229 | input tag_data_array_wr_active_c1; // tag data scrub write |
| 230 | |
| 231 | |
| 232 | |
| 233 | input misbuf_arb_l2rd_en; // clk enable for latching L2 arb Miss Buffer data. |
| 234 | |
| 235 | // from arb. |
| 236 | input arb_mux2_snpsel_px2; // sel snp data over mbf data |
| 237 | input arb_mux3_bufsel_px2; // sel buf or IQ data. |
| 238 | input arb_mux4_c1sel_px2; // sel stall data. |
| 239 | input arb_decc_data_sel_c9; // scrub data sel for stores. |
| 240 | input arb_bist_or_diag_acc_c1; // sel bist or diag data. |
| 241 | input arbdec_arbdp_poison_c1; // NEW_PIN ( pin is to the left ). |
| 242 | |
| 243 | // from databist |
| 244 | input [7:0] bist_data_data_c1 ; // PIN grown from 2 bits in int_2.0 |
| 245 | input bist_data_enable_c1 ; |
| 246 | |
| 247 | input [63:0] decc_arbdp_data_c8; // from decc. |
| 248 | |
| 249 | // partial store related mask |
| 250 | input [7:0] arb_dword_mask_c8; // from arbdec. |
| 251 | input arbdec_arbdp_inst_bufidhi_c1; // from arbdec. |
| 252 | |
| 253 | input sel_diag_store_data_c7; // BS and SR 12/22/03, store ack generation for diagnostic store |
| 254 | |
| 255 | input l2clk; |
| 256 | input scan_in; |
| 257 | input l2t_mb2_run; |
| 258 | |
| 259 | output scan_out; |
| 260 | output [63:0] st_ack_data; // BS and SR 11/12/03 N2 Xbar Packet format change, |
| 261 | // BS and SR 12/22/03, store ack generation for diagnostic store |
| 262 | |
| 263 | output [17:0] arbdat_arbdp_oque_int_ret_c7; // interrupt vector |
| 264 | output [77:0] arbdat_arbdp_store_data_c2; // store data with ecc., |
| 265 | output [38:0] arbdat_arbdata_wr_data_c2; // for tag write |
| 266 | output [63:0] arbdat_mbdata_inst_data_c8; // for mbdata write ( merged data ). |
| 267 | |
| 268 | output [63:0] arbdat_csr_inst_wr_data_c8;// added for timing reasons. previously |
| 269 | // was using arbdat_mbdata_inst_data_c8. |
| 270 | // New pin added POST_2.0. Place pins |
| 271 | // @ the bottom and align with appropriate |
| 272 | // bit position pitch |
| 273 | |
| 274 | //output [6:0] arbdat_csr_bist_wr_data_c8; // added pin for tstub functionality. |
| 275 | // Place pins at the bottom. align |
| 276 | // with the appropriate bit position pitch. |
| 277 | // New pin added POST_2.0 |
| 278 | |
| 279 | |
| 280 | output arbdat_word_lower_cmp_c8; // addr 0x4; from arbdata |
| 281 | output arbdat_word_upper_cmp_c8; // addr 0x0; from arbdata |
| 282 | |
| 283 | assign stop = tcu_clk_stop; |
| 284 | assign pce_ov = tcu_pce_ov; |
| 285 | assign siclk = tcu_aclk; |
| 286 | assign soclk = tcu_bclk; |
| 287 | assign se = tcu_scan_en; |
| 288 | assign muxtst = tcu_muxtest; |
| 289 | assign test = tcu_dectest; |
| 290 | |
| 291 | |
| 292 | |
| 293 | //assign scan_out = 1'b0; |
| 294 | |
| 295 | |
| 296 | wire [63:0] st_ack_data_muxout; |
| 297 | |
| 298 | |
| 299 | wire [63:0] arbdp_mux0_data_px2; |
| 300 | wire [63:0] arbdp_mux1_data_px2; |
| 301 | wire [63:0] arbdp_mux2_data_px2; |
| 302 | |
| 303 | wire [63:0] arbdp_inst_data_c1; |
| 304 | wire [63:0] arbdp_inst_data_c2; |
| 305 | wire [13:0] arbdp_inst_ecc_c1; |
| 306 | wire [13:0] arbdp_inst_ecc_raw_c1; |
| 307 | wire [13:0] arbdp_inst_ecc_raw_c1_inv; |
| 308 | wire [13:0] arbdp_inst_ecc_c2; |
| 309 | wire [63:0] arbdp_inst_data_c3; |
| 310 | wire [63:0] arbdp_inst_data_c4; |
| 311 | wire [63:0] arbdp_inst_data_c5; |
| 312 | wire [63:0] arbdp_inst_data_c52; // BS 03/11/04 extra cycle for mem access |
| 313 | wire [63:0] arbdp_inst_data_c6; |
| 314 | wire [63:0] arbdp_inst_data_c7; |
| 315 | wire [63:0] arbdp_inst_data_c8; |
| 316 | |
| 317 | wire [77:0] arbdp_bist_data_c1 ; |
| 318 | wire [63:0] bist_or_diag_data_c1 ; |
| 319 | wire [63:0] store_data_c1; |
| 320 | wire [13:0] bist_or_diag_ecc_c1 ; |
| 321 | wire [63:0] postecc_data_c1; |
| 322 | wire [63:0] poison_data_c1; |
| 323 | wire [63:0] arbdp_wr_data_c1 ; |
| 324 | wire [63:0] arbdp_wr_data_c2; |
| 325 | wire [13:0] arbdp_wr_ecc_c1 ; |
| 326 | |
| 327 | wire [63:0] decc_data_c9; // data from decc is flopped here. |
| 328 | |
| 329 | wire [63:0] mbf_data_px2;// Mbf instruction |
| 330 | |
| 331 | //********************************* |
| 332 | // Miss Buffer data processing. |
| 333 | //********************************* |
| 334 | |
| 335 | // assign se = 1'b0; |
| 336 | //inv_macro misbuf_arb_l2rd_en_inv_slice (width=1) |
| 337 | // ( |
| 338 | // .dout (misbuf_arb_l2rd_en_n), |
| 339 | // .din (misbuf_arb_l2rd_en) |
| 340 | // ); |
| 341 | // |
| 342 | //inv_macro se_inv_slice (width=1) |
| 343 | // ( |
| 344 | // .dout (se_n), |
| 345 | // .din (se) |
| 346 | // ); |
| 347 | // |
| 348 | // |
| 349 | //lib_clken_buf_cust clk_buf_mbdata |
| 350 | // ( |
| 351 | // .clk (en_clk_mbdata), |
| 352 | // .l2clk (l2clk), |
| 353 | // .enb_l (misbuf_arb_l2rd_en_n), |
| 354 | // .tmb_l (se_n) |
| 355 | // ); |
| 356 | |
| 357 | |
| 358 | l2t_arbdat_dp_msff_macro__stack_32c__width_32 ff_read_mbdata_reg1 |
| 359 | ( |
| 360 | .scan_in(ff_read_mbdata_reg1_scanin), |
| 361 | .scan_out(ff_read_mbdata_reg1_scanout), |
| 362 | .din (mb_data_read_data[63:32]), |
| 363 | .clk (l2clk), |
| 364 | .dout (mbf_data_px2[63:32]), |
| 365 | .en (misbuf_arb_l2rd_en), |
| 366 | .se(se), |
| 367 | .siclk(siclk), |
| 368 | .soclk(soclk), |
| 369 | .pce_ov(pce_ov), |
| 370 | .stop(stop) |
| 371 | |
| 372 | ); |
| 373 | |
| 374 | l2t_arbdat_dp_msff_macro__stack_32c__width_32 ff_read_mbdata_reg2 |
| 375 | ( |
| 376 | .scan_in(ff_read_mbdata_reg2_scanin), |
| 377 | .scan_out(ff_read_mbdata_reg2_scanout), |
| 378 | .din (mb_data_read_data[31:0]), |
| 379 | .clk (l2clk), |
| 380 | .dout (mbf_data_px2[31:0]), |
| 381 | .en (misbuf_arb_l2rd_en), |
| 382 | .se(se), |
| 383 | .siclk(siclk), |
| 384 | .soclk(soclk), |
| 385 | .pce_ov(pce_ov), |
| 386 | .stop(stop) |
| 387 | |
| 388 | ); |
| 389 | |
| 390 | |
| 391 | //*************************************** |
| 392 | // Arbiter muxes for data. |
| 393 | // Store data can come from 5 srcs. |
| 394 | // IQ, MB, diagnostic write, BIST or scrub. |
| 395 | //*************************************** |
| 396 | |
| 397 | l2t_arbdat_dp_inv_macro__width_1 arb_mux2_snpsel_px2_inv_slice |
| 398 | ( |
| 399 | .dout (arb_mux2_snpsel_px2_n), |
| 400 | .din (arb_mux2_snpsel_px2) |
| 401 | ); |
| 402 | |
| 403 | |
| 404 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux0_data_px1 |
| 405 | ( |
| 406 | .dout ( arbdp_mux0_data_px2[63:32] ) , |
| 407 | .din0 (mbf_data_px2[63:32] ), // miss buffer data |
| 408 | .din1 (snpd_snpq_arbdp_data_px2[63:32]), // SNP data. |
| 409 | .sel0 (arb_mux2_snpsel_px2_n), // select buffer data |
| 410 | .sel1 (arb_mux2_snpsel_px2) |
| 411 | ); |
| 412 | |
| 413 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux0_data_px2 |
| 414 | ( |
| 415 | .dout ( arbdp_mux0_data_px2[31:0] ) , |
| 416 | .din0 (mbf_data_px2[31:0] ), // miss buffer data |
| 417 | .din1 (snpd_snpq_arbdp_data_px2[31:0]), // SNP data. |
| 418 | .sel0 (arb_mux2_snpsel_px2_n), // select buffer data |
| 419 | .sel1 (arb_mux2_snpsel_px2) |
| 420 | ); |
| 421 | |
| 422 | l2t_arbdat_dp_inv_macro__width_1 arb_mux3_bufsel_px2_inv_slice |
| 423 | ( |
| 424 | .dout (arb_mux3_bufsel_px2_n), |
| 425 | .din (arb_mux3_bufsel_px2) |
| 426 | ); |
| 427 | |
| 428 | |
| 429 | |
| 430 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux1_data_px1 |
| 431 | ( |
| 432 | .dout ( arbdp_mux1_data_px2[63:32] ) , |
| 433 | .din0(arbdp_mux0_data_px2[63:32] ), // miss buffer/snp data |
| 434 | .din1(ique_iq_arbdp_data_px2[63:32]), // IQ data. |
| 435 | .sel0(arb_mux3_bufsel_px2), // select buffer data |
| 436 | .sel1(arb_mux3_bufsel_px2_n) |
| 437 | ); |
| 438 | |
| 439 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux1_data_px2 |
| 440 | ( |
| 441 | .dout ( arbdp_mux1_data_px2[31:0] ) , |
| 442 | .din0(arbdp_mux0_data_px2[31:0] ), // miss buffer/snp data |
| 443 | .din1(ique_iq_arbdp_data_px2[31:0]), // IQ data. |
| 444 | .sel0(arb_mux3_bufsel_px2), // select buffer data |
| 445 | .sel1(arb_mux3_bufsel_px2_n) |
| 446 | ); |
| 447 | |
| 448 | |
| 449 | // A mux flop can be used for C1 data instead of a mux2 + flop. |
| 450 | |
| 451 | l2t_arbdat_dp_inv_macro__width_1 arb_mux4_c1sel_px2_inv_slice |
| 452 | ( |
| 453 | .dout (arb_mux4_c1sel_px2_n), |
| 454 | .din (arb_mux4_c1sel_px2) |
| 455 | ); |
| 456 | |
| 457 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux2_instr_px1 |
| 458 | ( |
| 459 | .dout (arbdp_mux2_data_px2[63:32]) , |
| 460 | .din0(arbdp_mux1_data_px2[63:32]), |
| 461 | .din1(arbdp_inst_data_c1[63:32]), |
| 462 | .sel0(arb_mux4_c1sel_px2_n), |
| 463 | .sel1(arb_mux4_c1sel_px2) |
| 464 | ); |
| 465 | |
| 466 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux2_instr_px2 |
| 467 | ( |
| 468 | .dout (arbdp_mux2_data_px2[31:0]) , |
| 469 | .din0(arbdp_mux1_data_px2[31:0]), |
| 470 | .din1(arbdp_inst_data_c1[31:0]), |
| 471 | .sel0(arb_mux4_c1sel_px2_n), |
| 472 | .sel1(arb_mux4_c1sel_px2) |
| 473 | ); |
| 474 | |
| 475 | l2t_arbdat_dp_msff_macro__stack_32c__width_32 ff_data_c11 |
| 476 | (.din(arbdp_mux2_data_px2[63:32]), .clk(l2clk), |
| 477 | .scan_in(ff_data_c11_scanin), |
| 478 | .scan_out(ff_data_c11_scanout), |
| 479 | .dout(arbdp_inst_data_c1[63:32]), .en(1'b1), |
| 480 | .se(se), |
| 481 | .siclk(siclk), |
| 482 | .soclk(soclk), |
| 483 | .pce_ov(pce_ov), |
| 484 | .stop(stop) |
| 485 | ); |
| 486 | |
| 487 | l2t_arbdat_dp_msff_macro__stack_32c__width_32 ff_data_c12 |
| 488 | (.din(arbdp_mux2_data_px2[31:0]), .clk(l2clk), |
| 489 | .scan_in(ff_data_c12_scanin), |
| 490 | .scan_out(ff_data_c12_scanout), |
| 491 | .dout(arbdp_inst_data_c1[31:0]), .en(1'b1), |
| 492 | .se(se), |
| 493 | .siclk(siclk), |
| 494 | .soclk(soclk), |
| 495 | .pce_ov(pce_ov), |
| 496 | .stop(stop) |
| 497 | ); |
| 498 | |
| 499 | |
| 500 | // data ecc data flopped to C9 |
| 501 | l2t_arbdat_dp_msff_macro__stack_32c__width_32 ff_decc_data_c91 |
| 502 | ( |
| 503 | .scan_in(ff_decc_data_c91_scanin), |
| 504 | .scan_out(ff_decc_data_c91_scanout), |
| 505 | .din(decc_arbdp_data_c8[63:32]), |
| 506 | .clk(l2clk), |
| 507 | .dout(decc_data_c9[63:32]), |
| 508 | .en(1'b1), |
| 509 | .se(se), |
| 510 | .siclk(siclk), |
| 511 | .soclk(soclk), |
| 512 | .pce_ov(pce_ov), |
| 513 | .stop(stop) |
| 514 | |
| 515 | ); |
| 516 | |
| 517 | l2t_arbdat_dp_msff_macro__stack_32c__width_32 ff_decc_data_c92 |
| 518 | ( |
| 519 | .scan_in(ff_decc_data_c92_scanin), |
| 520 | .scan_out(ff_decc_data_c92_scanout), |
| 521 | .din(decc_arbdp_data_c8[31:0]), |
| 522 | .clk(l2clk), |
| 523 | .dout(decc_data_c9[31:0]), |
| 524 | .en(1'b1), |
| 525 | .se(se), |
| 526 | .siclk(siclk), |
| 527 | .soclk(soclk), |
| 528 | .pce_ov(pce_ov), |
| 529 | .stop(stop) |
| 530 | |
| 531 | ); |
| 532 | |
| 533 | // normal store data is a combination of scrub/store data. |
| 534 | |
| 535 | l2t_arbdat_dp_inv_macro__width_1 arb_decc_data_sel_c9_inv_slice |
| 536 | ( |
| 537 | .dout (arb_decc_data_sel_c9_n ), |
| 538 | .din (arb_decc_data_sel_c9 ) |
| 539 | ); |
| 540 | |
| 541 | l2t_arbdat_dp_and_macro__width_1 poison_qual_c1_slice // BS 04/28/04 sync up with N1 TO 1.0 |
| 542 | ( |
| 543 | .dout (poison_qual_c1), |
| 544 | .din0 (arb_decc_data_sel_c9_n), |
| 545 | .din1 (arbdec_arbdp_poison_c1) |
| 546 | ); |
| 547 | |
| 548 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_store_data_c11 |
| 549 | (.dout (store_data_c1[63:32]), |
| 550 | .din0(decc_data_c9[63:32]), // scrub data |
| 551 | .din1(arbdp_inst_data_c1[63:32]), // store data. |
| 552 | .sel0(arb_decc_data_sel_c9),// decc scrub data sel |
| 553 | .sel1(arb_decc_data_sel_c9_n));// no decc scrub |
| 554 | |
| 555 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_store_data_c12 |
| 556 | (.dout (store_data_c1[31:0]), |
| 557 | .din0(decc_data_c9[31:0]), // scrub data |
| 558 | .din1(arbdp_inst_data_c1[31:0]), // store data. |
| 559 | .sel0(arb_decc_data_sel_c9),// decc scrub data sel |
| 560 | .sel1(arb_decc_data_sel_c9_n));// no decc scrub |
| 561 | |
| 562 | l2t_pgen32b_dp ecc_bit31to0 |
| 563 | ( .dout(postecc_data_c1[31:0]), |
| 564 | .parity(arbdp_inst_ecc_raw_c1[6:0]), |
| 565 | .din(store_data_c1[31:0]) |
| 566 | ); |
| 567 | |
| 568 | l2t_pgen32b_dp ecc_bit63to32 |
| 569 | ( |
| 570 | .dout(postecc_data_c1[63:32]), |
| 571 | .parity(arbdp_inst_ecc_raw_c1[13:7]), |
| 572 | .din(store_data_c1[63:32]) |
| 573 | ); |
| 574 | |
| 575 | // BS 06/13/04 added Notdata logic |
| 576 | |
| 577 | // in case bit 116 is set for stores,swaps,ldstubs,cswaps, write Notdata |
| 578 | // into L2 data array. we do this by flipping the ecc bits when bit 116 = 1. |
| 579 | // if bit 116 of PCX packet (bufidhi bit) = 1'b1, Ecc bits of both 4 byte chunks get |
| 580 | // flipped irrespective of whether it is a low cas, high cas |
| 581 | // or whole cas, or partial store/swap/ldstub to lower or higher 4 byte chunk. |
| 582 | |
| 583 | // in case of a Data Sccrub access , cannot rely on arbdec_arbdp_inst_bufidhi_c1 |
| 584 | // as pipe is stalled and whatever is in the IQ at that point might be holding this |
| 585 | // signal to 1 or 0. Hence force arbdec_arbdp_inst_bufidhi to 1'b0 in case |
| 586 | // of the data scrub so that the computed ecc gets written by the scrub write and |
| 587 | // not the flipped ECC : fix for bug 102779 |
| 588 | |
| 589 | l2t_arbdat_dp_inv_macro__width_1 inv_tag_scrub_wr |
| 590 | (.dout (tag_data_array_wr_active_c1_n), |
| 591 | .din (tag_data_array_wr_active_c1) |
| 592 | ); |
| 593 | |
| 594 | l2t_arbdat_dp_and_macro__ports_2__width_1 bufid1_and_not_scrub |
| 595 | (.dout (arbdec_arbdp_inst_bufidhi), |
| 596 | .din0 (arbdec_arbdp_inst_bufidhi_c1), |
| 597 | .din1 (tag_data_array_wr_active_c1_n) |
| 598 | ); |
| 599 | |
| 600 | l2t_arbdat_dp_inv_macro__width_1 inv_bufidhi_c1 |
| 601 | (.dout (arbdec_arbdp_inst_bufidhi_n), |
| 602 | .din (arbdec_arbdp_inst_bufidhi) |
| 603 | ); |
| 604 | |
| 605 | l2t_arbdat_dp_inv_macro__width_14 inv_inst_ecc_raw_c1 |
| 606 | (.dout (arbdp_inst_ecc_raw_c1_inv[13:0]), |
| 607 | .din (arbdp_inst_ecc_raw_c1[13:0]) |
| 608 | ); |
| 609 | |
| 610 | |
| 611 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14c__width_14 mux_store_ecc_c1 |
| 612 | (.dout (arbdp_inst_ecc_c1[13:0]), |
| 613 | .din0(arbdp_inst_ecc_raw_c1_inv[13:0]), // flipped ECC |
| 614 | .din1(arbdp_inst_ecc_raw_c1[13:0]), // generated ECC |
| 615 | .sel0(arbdec_arbdp_inst_bufidhi),// select flipped ecc |
| 616 | .sel1(arbdec_arbdp_inst_bufidhi_n));// select generated ecc |
| 617 | |
| 618 | assign arbdp_bist_data_c1[38:0] = {bist_data_data_c1[6:0], |
| 619 | bist_data_data_c1[7:0], |
| 620 | bist_data_data_c1[7:0], |
| 621 | bist_data_data_c1[7:0], |
| 622 | bist_data_data_c1[7:0] } ; |
| 623 | |
| 624 | assign arbdp_bist_data_c1[77:39] = {bist_data_data_c1[6:0], |
| 625 | bist_data_data_c1[7:0], |
| 626 | bist_data_data_c1[7:0], |
| 627 | bist_data_data_c1[7:0], |
| 628 | bist_data_data_c1[7:0] } ; |
| 629 | |
| 630 | |
| 631 | // Apply poison bit Xor to the |
| 632 | // 2 LSBs of each 32 Bit word. |
| 633 | |
| 634 | //assign poison_data_c1[31:0] = { postecc_data_c1[31:2], |
| 635 | // ( postecc_data_c1[1] ^ poison_qual_c1), // BS 04/28/04 sync up with N1 TO 1.0 |
| 636 | // ( postecc_data_c1[0] ^ poison_qual_c1) |
| 637 | // }; |
| 638 | |
| 639 | l2t_arbdat_dp_xor_macro__width_1 postecc_1_poison_slice1 |
| 640 | ( |
| 641 | .din1 (poison_qual_c1), // BS 04/28/04 sync up with N1 TO 1.0 |
| 642 | .din0 (postecc_data_c1[1]), |
| 643 | .dout (postecc_1_poison1) |
| 644 | ); |
| 645 | |
| 646 | l2t_arbdat_dp_xor_macro__width_1 postecc_1_poison_slice0 |
| 647 | ( |
| 648 | .din1 (poison_qual_c1), // BS 04/28/04 sync up with N1 TO 1.0 |
| 649 | .din0 (postecc_data_c1[0]), |
| 650 | .dout (postecc_1_poison0) |
| 651 | ); |
| 652 | |
| 653 | |
| 654 | assign poison_data_c1[31:0] = {postecc_data_c1[31:2],postecc_1_poison1,postecc_1_poison0}; |
| 655 | |
| 656 | |
| 657 | |
| 658 | // bits 31:0 |
| 659 | |
| 660 | l2t_arbdat_dp_inv_macro__width_1 bist_data_enable_c1_inv_slice |
| 661 | ( |
| 662 | .dout (bist_data_enable_c1_n ), |
| 663 | .din (bist_data_enable_c1 ) |
| 664 | ); |
| 665 | |
| 666 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux1_bist_diag_data_c1 |
| 667 | (.dout (bist_or_diag_data_c1[31:0]), // bist or diag data |
| 668 | .din0(arbdp_bist_data_c1[38:7]), // bist data |
| 669 | .din1(arbdp_wr_data_c2_buff[38:7]), // diagnostic data |
| 670 | .sel0(bist_data_enable_c1), // bist enable |
| 671 | .sel1(bist_data_enable_c1_n)); // diagnostic enable(or def) |
| 672 | |
| 673 | l2t_arbdat_dp_inv_macro__width_1 arb_bist_or_diag_acc_c1_inv_slice |
| 674 | ( |
| 675 | .dout (arb_bist_or_diag_acc_c1_n ), |
| 676 | .din (arb_bist_or_diag_acc_c1 ) |
| 677 | ); |
| 678 | |
| 679 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_wr_data_c1_63to32 |
| 680 | (.dout (arbdp_wr_data_c1[31:0]), |
| 681 | .din0(poison_data_c1[31:0]), // new data from mb or iq |
| 682 | .din1(bist_or_diag_data_c1[31:0]), // bist or diag data |
| 683 | .sel0(arb_bist_or_diag_acc_c1_n), // default |
| 684 | .sel1(arb_bist_or_diag_acc_c1)); // bist or diagnostic enable. |
| 685 | |
| 686 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_data31to0_c2 |
| 687 | ( |
| 688 | .scan_in(ff_data31to0_c2_scanin), |
| 689 | .scan_out(ff_data31to0_c2_scanout), |
| 690 | .din(arbdp_wr_data_c1[31:0]), |
| 691 | .clk(l2clk), |
| 692 | .dout(arbdp_wr_data_c2[31:0]), |
| 693 | .en(1'b1), |
| 694 | .se(se), |
| 695 | .siclk(siclk), |
| 696 | .soclk(soclk), |
| 697 | .pce_ov(pce_ov), |
| 698 | .stop(stop) |
| 699 | ); |
| 700 | |
| 701 | l2t_arbdat_dp_buff_macro__dbuff_16x__stack_32c__width_32 buff_arbdp_wr_data_c2a |
| 702 | ( |
| 703 | .dout (arbdp_wr_data_c2_buff[31:0]), |
| 704 | .din (arbdp_wr_data_c2[31:0]) |
| 705 | ); |
| 706 | |
| 707 | |
| 708 | // bits 63:32 |
| 709 | |
| 710 | // Apply poison bit Xor to the |
| 711 | // 2 LSBs of each 32 Bit word. |
| 712 | //assign poison_data_c1[63:32] = { postecc_data_c1[63:34], |
| 713 | // ( postecc_data_c1[33] ^ ), // BS 04/28/04 sync up with N1 TO 1.0 |
| 714 | // ( postecc_data_c1[32] ^ ) }; // BS 04/28/04 sync up with N1 TO 1.0 |
| 715 | |
| 716 | l2t_arbdat_dp_xor_macro__width_1 postecc_1_poison_slice33 |
| 717 | ( |
| 718 | .dout (postecc_1_poison_33), |
| 719 | .din0 (postecc_data_c1[33]), |
| 720 | .din1 (poison_qual_c1) // BS 04/28/04 sync up with N1 TO 1.0 |
| 721 | ); |
| 722 | |
| 723 | l2t_arbdat_dp_xor_macro__width_1 postecc_1_poison_xor_slice32 |
| 724 | ( |
| 725 | .dout (postecc_1_poison_32), |
| 726 | .din0 (postecc_data_c1[32]), |
| 727 | .din1 (poison_qual_c1) // BS 04/28/04 sync up with N1 TO 1.0 |
| 728 | ); |
| 729 | |
| 730 | assign poison_data_c1[63:32] = {postecc_data_c1[63:34],postecc_1_poison_33,postecc_1_poison_32}; |
| 731 | |
| 732 | |
| 733 | |
| 734 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux2_bist_diag_data_c1 |
| 735 | (.dout(bist_or_diag_data_c1[63:32]), // bist or diag data |
| 736 | .din0(arbdp_bist_data_c1[77:46]), // bist data |
| 737 | .din1(arbdp_wr_data_c2_buff[38:7]), // diagnostic data |
| 738 | .sel0(bist_data_enable_c1), // bist enable |
| 739 | .sel1(bist_data_enable_c1_n)); // diagnostic enable(or def) |
| 740 | |
| 741 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_wr_data_c1 |
| 742 | (.dout (arbdp_wr_data_c1[63:32]), |
| 743 | .din0(poison_data_c1[63:32]), // new data from mb or iq |
| 744 | .din1(bist_or_diag_data_c1[63:32]), // bist or diag data |
| 745 | .sel0(arb_bist_or_diag_acc_c1_n), // default |
| 746 | .sel1(arb_bist_or_diag_acc_c1)); // bist or diagnostic enable |
| 747 | |
| 748 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_data63to32_c2 |
| 749 | ( |
| 750 | .scan_in(ff_data63to32_c2_scanin), |
| 751 | .scan_out(ff_data63to32_c2_scanout), |
| 752 | .din(arbdp_wr_data_c1[63:32]), |
| 753 | .clk(l2clk), |
| 754 | .dout(arbdp_wr_data_c2[63:32]), |
| 755 | .en(1'b1), |
| 756 | .se(se), |
| 757 | .siclk(siclk), |
| 758 | .soclk(soclk), |
| 759 | .pce_ov(pce_ov), |
| 760 | .stop(stop) |
| 761 | ); |
| 762 | |
| 763 | |
| 764 | |
| 765 | l2t_arbdat_dp_buff_macro__dbuff_16x__stack_32c__width_32 buff_arbdp_wr_data_c2b |
| 766 | ( |
| 767 | .dout (arbdp_wr_data_c2_buff[63:32]), |
| 768 | .din (arbdp_wr_data_c2[63:32]) |
| 769 | ); |
| 770 | |
| 771 | // ecc bits [6:0] |
| 772 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 mux1_bist_diag_ecc_c1 |
| 773 | (.dout (bist_or_diag_ecc_c1[6:0]), // bist or diag ecc |
| 774 | .din0(arbdp_bist_data_c1[6:0]), // bist ecc |
| 775 | .din1(arbdp_wr_data_c2_buff[6:0]), // diagnostic ecc |
| 776 | .sel0(bist_data_enable_c1), // bist enable |
| 777 | .sel1(bist_data_enable_c1_n)); // diagnostic enable(or def) |
| 778 | |
| 779 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 mux_wr_ecc0to6_c1 |
| 780 | (.dout (arbdp_wr_ecc_c1[6:0]), |
| 781 | .din0(arbdp_inst_ecc_c1[6:0]),// ecc for new data from mb or iq |
| 782 | .din1(bist_or_diag_ecc_c1[6:0]), // bist or diag ecc |
| 783 | .sel0(arb_bist_or_diag_acc_c1_n), // default |
| 784 | .sel1(arb_bist_or_diag_acc_c1)); // bist or diagnostic enable |
| 785 | |
| 786 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_7c__width_7 ff_ecc0to6_c2 |
| 787 | ( |
| 788 | .scan_in(ff_ecc0to6_c2_scanin), |
| 789 | .scan_out(ff_ecc0to6_c2_scanout), |
| 790 | .din(arbdp_wr_ecc_c1[6:0]), |
| 791 | .clk(l2clk), |
| 792 | .dout(arbdp_inst_ecc_c2[6:0]), |
| 793 | .en(1'b1), |
| 794 | .se(se), |
| 795 | .siclk(siclk), |
| 796 | .soclk(soclk), |
| 797 | .pce_ov(pce_ov), |
| 798 | .stop(stop) |
| 799 | ); |
| 800 | |
| 801 | |
| 802 | // ecc bits [13:7] |
| 803 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 mux2_bist_diag_ecc_c1 |
| 804 | (.dout (bist_or_diag_ecc_c1[13:7]), // bist or diag ecc |
| 805 | .din0(arbdp_bist_data_c1[45:39]), // bist ecc |
| 806 | .din1(arbdp_wr_data_c2_buff[6:0]), // diagnostic ecc |
| 807 | .sel0(bist_data_enable_c1), // bist enable |
| 808 | .sel1(bist_data_enable_c1_n)); // diagnostic enable(or def) |
| 809 | |
| 810 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 mux_wr_ecc7to13_c2 |
| 811 | (.dout (arbdp_wr_ecc_c1[13:7]), |
| 812 | .din0(arbdp_inst_ecc_c1[13:7]), //eccfor new data from mb or iq |
| 813 | .din1(bist_or_diag_ecc_c1[13:7]),// bist or diag ecc |
| 814 | .sel0(arb_bist_or_diag_acc_c1_n),// default |
| 815 | .sel1(arb_bist_or_diag_acc_c1)); // bist or diagnostic enable |
| 816 | |
| 817 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_7c__width_7 ff_ecc7to13_c2 |
| 818 | (.din(arbdp_wr_ecc_c1[13:7]), .clk(l2clk), |
| 819 | .scan_in(ff_ecc7to13_c2_scanin), |
| 820 | .scan_out(ff_ecc7to13_c2_scanout), |
| 821 | .dout(arbdp_inst_ecc_c2[13:7]), .en(1'b1), |
| 822 | .se(se), |
| 823 | .siclk(siclk), |
| 824 | .soclk(soclk), |
| 825 | .pce_ov(pce_ov), |
| 826 | .stop(stop) |
| 827 | ); |
| 828 | |
| 829 | |
| 830 | |
| 831 | // stdecc to l2d and l2b. |
| 832 | assign arbdat_arbdp_store_data_c2= { arbdp_wr_data_c2[63:32], arbdp_inst_ecc_c2[13:7], |
| 833 | arbdp_wr_data_c2[31:0], arbdp_inst_ecc_c2[6:0] } ; |
| 834 | |
| 835 | |
| 836 | |
| 837 | |
| 838 | //********************************************** |
| 839 | // C3.. C8 staging flops. |
| 840 | //********************************************** |
| 841 | |
| 842 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_data_c21 |
| 843 | (.din(arbdp_inst_data_c1[63:32]), .clk(l2clk), |
| 844 | .scan_in(ff_data_c21_scanin), |
| 845 | .scan_out(ff_data_c21_scanout), |
| 846 | .dout(arbdp_inst_data_c2[63:32]), .en(1'b1), |
| 847 | .se(se), |
| 848 | .siclk(siclk), |
| 849 | .soclk(soclk), |
| 850 | .pce_ov(pce_ov), |
| 851 | .stop(stop) |
| 852 | ); |
| 853 | |
| 854 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_data_c22 |
| 855 | (.din(arbdp_inst_data_c1[31:0]), .clk(l2clk), |
| 856 | .scan_in(ff_data_c22_scanin), |
| 857 | .scan_out(ff_data_c22_scanout), |
| 858 | .dout(arbdp_inst_data_c2[31:0]), .en(1'b1), |
| 859 | .se(se), |
| 860 | .siclk(siclk), |
| 861 | .soclk(soclk), |
| 862 | .pce_ov(pce_ov), |
| 863 | .stop(stop) |
| 864 | ); |
| 865 | |
| 866 | assign arbdat_arbdata_wr_data_c2 = arbdp_inst_data_c2[38:0] ; // data to the tag for diagnostic |
| 867 | // writes. |
| 868 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c31 |
| 869 | (.din(arbdp_inst_data_c2[63:32]), .clk(l2clk), |
| 870 | .scan_in(ff_data_c31_scanin), |
| 871 | .scan_out(ff_data_c31_scanout), |
| 872 | .dout(arbdp_inst_data_c3[63:32]), .en(1'b1), |
| 873 | .se(se), |
| 874 | .siclk(siclk), |
| 875 | .soclk(soclk), |
| 876 | .pce_ov(pce_ov), |
| 877 | .stop(stop) |
| 878 | ); |
| 879 | |
| 880 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c32 |
| 881 | (.din(arbdp_inst_data_c2[31:0]), .clk(l2clk), |
| 882 | .scan_in(ff_data_c32_scanin), |
| 883 | .scan_out(ff_data_c32_scanout), |
| 884 | .dout(arbdp_inst_data_c3[31:0]), .en(1'b1), |
| 885 | .se(se), |
| 886 | .siclk(siclk), |
| 887 | .soclk(soclk), |
| 888 | .pce_ov(pce_ov), |
| 889 | .stop(stop) |
| 890 | ); |
| 891 | |
| 892 | // diagostic writes. |
| 893 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c41 |
| 894 | (.din(arbdp_inst_data_c3[63:32]), .clk(l2clk), |
| 895 | .scan_in(ff_data_c41_scanin), |
| 896 | .scan_out(ff_data_c41_scanout), |
| 897 | .dout(arbdp_inst_data_c4[63:32]), .en(1'b1), |
| 898 | .se(se), |
| 899 | .siclk(siclk), |
| 900 | .soclk(soclk), |
| 901 | .pce_ov(pce_ov), |
| 902 | .stop(stop) |
| 903 | ); |
| 904 | |
| 905 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c42 |
| 906 | (.din(arbdp_inst_data_c3[31:0]), .clk(l2clk), |
| 907 | .scan_in(ff_data_c42_scanin), |
| 908 | .scan_out(ff_data_c42_scanout), |
| 909 | .dout(arbdp_inst_data_c4[31:0]), .en(1'b1), |
| 910 | .se(se), |
| 911 | .siclk(siclk), |
| 912 | .soclk(soclk), |
| 913 | .pce_ov(pce_ov), |
| 914 | .stop(stop) |
| 915 | ); |
| 916 | |
| 917 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c51 |
| 918 | (.din(arbdp_inst_data_c4[63:32]), .clk(l2clk), |
| 919 | .scan_in(ff_data_c51_scanin), |
| 920 | .scan_out(ff_data_c51_scanout), |
| 921 | .dout(arbdp_inst_data_c5[63:32]), .en(1'b1), |
| 922 | .se(se), |
| 923 | .siclk(siclk), |
| 924 | .soclk(soclk), |
| 925 | .pce_ov(pce_ov), |
| 926 | .stop(stop) |
| 927 | ); |
| 928 | |
| 929 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c52 |
| 930 | (.din(arbdp_inst_data_c4[31:0]), .clk(l2clk), |
| 931 | .scan_in(ff_data_c52_scanin), |
| 932 | .scan_out(ff_data_c52_scanout), |
| 933 | .dout(arbdp_inst_data_c5[31:0]), .en(1'b1), |
| 934 | .se(se), |
| 935 | .siclk(siclk), |
| 936 | .soclk(soclk), |
| 937 | .pce_ov(pce_ov), |
| 938 | .stop(stop) |
| 939 | ); |
| 940 | |
| 941 | // BS 03/11/04 extra cycle for mem access |
| 942 | |
| 943 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c521 |
| 944 | (.din(arbdp_inst_data_c5[63:32]), .clk(l2clk), |
| 945 | .scan_in(ff_data_c521_scanin), |
| 946 | .scan_out(ff_data_c521_scanout), |
| 947 | .dout(arbdp_inst_data_c52[63:32]), .en(1'b1), |
| 948 | .se(se), |
| 949 | .siclk(siclk), |
| 950 | .soclk(soclk), |
| 951 | .pce_ov(pce_ov), |
| 952 | .stop(stop) |
| 953 | ); |
| 954 | |
| 955 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c522 |
| 956 | (.din(arbdp_inst_data_c5[31:0]), .clk(l2clk), |
| 957 | .scan_in(ff_data_c522_scanin), |
| 958 | .scan_out(ff_data_c522_scanout), |
| 959 | .dout(arbdp_inst_data_c52[31:0]), .en(1'b1), |
| 960 | .se(se), |
| 961 | .siclk(siclk), |
| 962 | .soclk(soclk), |
| 963 | .pce_ov(pce_ov), |
| 964 | .stop(stop) |
| 965 | ); |
| 966 | |
| 967 | |
| 968 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c61 |
| 969 | (.din(arbdp_inst_data_c52[63:32]), .clk(l2clk), |
| 970 | .scan_in(ff_data_c61_scanin), |
| 971 | .scan_out(ff_data_c61_scanout), |
| 972 | .dout(arbdp_inst_data_c6[63:32]), .en(1'b1), |
| 973 | .se(se), |
| 974 | .siclk(siclk), |
| 975 | .soclk(soclk), |
| 976 | .pce_ov(pce_ov), |
| 977 | .stop(stop) |
| 978 | ); |
| 979 | |
| 980 | l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ff_data_c62 |
| 981 | (.din(arbdp_inst_data_c52[31:0]), .clk(l2clk), |
| 982 | .scan_in(ff_data_c62_scanin), |
| 983 | .scan_out(ff_data_c62_scanout), |
| 984 | .dout(arbdp_inst_data_c6[31:0]), .en(1'b1), |
| 985 | .se(se), |
| 986 | .siclk(siclk), |
| 987 | .soclk(soclk), |
| 988 | .pce_ov(pce_ov), |
| 989 | .stop(stop) |
| 990 | ); |
| 991 | |
| 992 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_data_c71 |
| 993 | (.din(arbdp_inst_data_c6[63:32]), .clk(l2clk), |
| 994 | .scan_in(ff_data_c71_scanin), |
| 995 | .scan_out(ff_data_c71_scanout), |
| 996 | .dout(arbdp_inst_data_c7[63:32]), .en(1'b1), |
| 997 | .se(se), |
| 998 | .siclk(siclk), |
| 999 | .soclk(soclk), |
| 1000 | .pce_ov(pce_ov), |
| 1001 | .stop(stop) |
| 1002 | ); |
| 1003 | |
| 1004 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_data_c72 |
| 1005 | (.din(arbdp_inst_data_c6[31:0]), .clk(l2clk), |
| 1006 | .scan_in(ff_data_c72_scanin), |
| 1007 | .scan_out(ff_data_c72_scanout), |
| 1008 | .dout(arbdp_inst_data_c7[31:0]), .en(1'b1), |
| 1009 | .se(se), |
| 1010 | .siclk(siclk), |
| 1011 | .soclk(soclk), |
| 1012 | .pce_ov(pce_ov), |
| 1013 | .stop(stop) |
| 1014 | ); |
| 1015 | |
| 1016 | assign arbdat_arbdp_oque_int_ret_c7 = arbdp_inst_data_c7[17:0] ; // interrupt vector to oque. |
| 1017 | |
| 1018 | l2t_arbdat_dp_msff_macro__dmsff_32x__minbuff_1__stack_32c__width_32 ff_data_c81 |
| 1019 | (.din(arbdp_inst_data_c7[63:32]), .clk(l2clk), |
| 1020 | .scan_in(ff_data_c81_scanin), |
| 1021 | .scan_out(ff_data_c81_scanout), |
| 1022 | .dout(arbdp_inst_data_c8[63:32]), .en(1'b1), |
| 1023 | .se(se), |
| 1024 | .siclk(siclk), |
| 1025 | .soclk(soclk), |
| 1026 | .pce_ov(pce_ov), |
| 1027 | .stop(stop) |
| 1028 | ); |
| 1029 | |
| 1030 | l2t_arbdat_dp_msff_macro__dmsff_32x__minbuff_1__stack_32c__width_32 ff_data_c82 |
| 1031 | (.din(arbdp_inst_data_c7[31:0]), .clk(l2clk), |
| 1032 | .scan_in(ff_data_c82_scanin), |
| 1033 | .scan_out(ff_data_c82_scanout), |
| 1034 | .dout(arbdp_inst_data_c8[31:0]), .en(1'b1), |
| 1035 | .se(se), |
| 1036 | .siclk(siclk), |
| 1037 | .soclk(soclk), |
| 1038 | .pce_ov(pce_ov), |
| 1039 | .stop(stop) |
| 1040 | ); |
| 1041 | |
| 1042 | // BS and SR 12/22/03, store ack generation for diagnostic store |
| 1043 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_st_ack_data1 |
| 1044 | ( |
| 1045 | .dout (st_ack_data_muxout[63:32]), |
| 1046 | .din0 (arbdp_inst_data_c8[63:32]), |
| 1047 | .din1 (arbdp_inst_data_c7[63:32]), |
| 1048 | .sel0 (sel_diag_store_data_c8), // for diagnostic store ack cases |
| 1049 | .sel1 (sel_diag_store_data_c8_n) // for default cases |
| 1050 | ); |
| 1051 | |
| 1052 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_st_ack_data2 |
| 1053 | ( |
| 1054 | .dout (st_ack_data_muxout[31:0]), |
| 1055 | .din0 (arbdp_inst_data_c8[31:0]), |
| 1056 | .din1 (arbdp_inst_data_c7[31:0]), |
| 1057 | .sel0 (sel_diag_store_data_c8), // for diagnostic store ack cases |
| 1058 | .sel1 (sel_diag_store_data_c8_n) // for default cases |
| 1059 | ); |
| 1060 | |
| 1061 | // BS and SR 12/22/03, store ack generation for diagnostic store |
| 1062 | l2t_arbdat_dp_inv_macro__width_1 inv_sel_diag_store_data_c8 |
| 1063 | ( |
| 1064 | .dout (sel_diag_store_data_c7_n ), |
| 1065 | .din (sel_diag_store_data_c7 ) |
| 1066 | ); |
| 1067 | |
| 1068 | |
| 1069 | l2t_arbdat_dp_buff_macro__dbuff_32x__stack_32c__width_32 buff1_st_ack_data |
| 1070 | ( |
| 1071 | .dout (st_ack_data[63:32]), |
| 1072 | .din (st_ack_data_muxout[63:32]) |
| 1073 | ); |
| 1074 | |
| 1075 | |
| 1076 | l2t_arbdat_dp_buff_macro__dbuff_32x__stack_32c__width_32 buff2_st_ack_data |
| 1077 | ( |
| 1078 | .dout (st_ack_data[31:0]), |
| 1079 | .din (st_ack_data_muxout[31:0]) |
| 1080 | ); |
| 1081 | |
| 1082 | |
| 1083 | //********************************************** |
| 1084 | // MERGE operation for partial stores. |
| 1085 | //********************************************** |
| 1086 | l2t_arbdat_dp_inv_macro__dinv_4x__width_1 arb_dword_mask_c8_0_inv_slice |
| 1087 | ( |
| 1088 | .dout (arb_dword_mask_c8_0_n ), |
| 1089 | .din (arb_dword_mask_c8[0] ) |
| 1090 | ); |
| 1091 | |
| 1092 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux0 |
| 1093 | ( |
| 1094 | .dout ({sel_mux0_data_c6_0,sel_mux0_data_c6_1}), |
| 1095 | .din0 ({arb_dword_mask_c8_7_n,arb_dword_mask_c8[7]}), |
| 1096 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1097 | ); |
| 1098 | |
| 1099 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux0_data_c6 |
| 1100 | (.dout (arbdat_mbdata_inst_data_c8[63:56]), |
| 1101 | .din0(arbdp_inst_data_c8[63:56]), |
| 1102 | .din1(decc_arbdp_data_c8[63:56]), |
| 1103 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1104 | .sel0(sel_mux0_data_c6_0), |
| 1105 | .sel1(sel_mux0_data_c6_1), |
| 1106 | .muxtst(muxtst), |
| 1107 | .test(test) |
| 1108 | ); |
| 1109 | |
| 1110 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_1_inv_slice |
| 1111 | ( |
| 1112 | .dout (arb_dword_mask_c8_1_n ), |
| 1113 | .din (arb_dword_mask_c8[1] ) |
| 1114 | ); |
| 1115 | |
| 1116 | |
| 1117 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux1 |
| 1118 | ( |
| 1119 | .dout ({sel_mux1_data_c6_0,sel_mux1_data_c6_1}), |
| 1120 | .din0 ({arb_dword_mask_c8_6_n,arb_dword_mask_c8[6]}), |
| 1121 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1122 | ); |
| 1123 | |
| 1124 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux1_data_c6 |
| 1125 | ( |
| 1126 | .dout (arbdat_mbdata_inst_data_c8[55:48]), |
| 1127 | .din0(arbdp_inst_data_c8[55:48]), |
| 1128 | .din1(decc_arbdp_data_c8[55:48]), |
| 1129 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1130 | .sel0 (sel_mux1_data_c6_0), |
| 1131 | .sel1 (sel_mux1_data_c6_1), |
| 1132 | .muxtst(muxtst), |
| 1133 | .test(test) |
| 1134 | ); |
| 1135 | |
| 1136 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_2_inv_slice |
| 1137 | ( |
| 1138 | .dout (arb_dword_mask_c8_2_n ), |
| 1139 | .din (arb_dword_mask_c8[2] ) |
| 1140 | ); |
| 1141 | |
| 1142 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux2 |
| 1143 | ( |
| 1144 | .dout ({sel_mux2_data_c6_0,sel_mux2_data_c6_1}), |
| 1145 | .din0 ({arb_dword_mask_c8_5_n,arb_dword_mask_c8[5]}), |
| 1146 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1147 | ); |
| 1148 | |
| 1149 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux2_data_c6 |
| 1150 | ( |
| 1151 | .dout (arbdat_mbdata_inst_data_c8[47:40]), |
| 1152 | .din0(arbdp_inst_data_c8[47:40]), |
| 1153 | .din1(decc_arbdp_data_c8[47:40]), |
| 1154 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1155 | .sel0 (sel_mux2_data_c6_0), |
| 1156 | .sel1 (sel_mux2_data_c6_1), |
| 1157 | .muxtst(muxtst), |
| 1158 | .test(test) |
| 1159 | ); |
| 1160 | |
| 1161 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_3_inv_slice |
| 1162 | ( |
| 1163 | .dout (arb_dword_mask_c8_3_n ), |
| 1164 | .din (arb_dword_mask_c8[3] ) |
| 1165 | ); |
| 1166 | |
| 1167 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux3 |
| 1168 | ( |
| 1169 | .dout ({sel_mux3_data_c6_0,sel_mux3_data_c6_1}), |
| 1170 | .din0 ({arb_dword_mask_c8_4_n,arb_dword_mask_c8[4]}), |
| 1171 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1172 | ); |
| 1173 | |
| 1174 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux3_data_c6 |
| 1175 | ( |
| 1176 | .dout (arbdat_mbdata_inst_data_c8[39:32]), |
| 1177 | .din0(arbdp_inst_data_c8[39:32]), |
| 1178 | .din1(decc_arbdp_data_c8[39:32]), |
| 1179 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1180 | .sel0 (sel_mux3_data_c6_0), |
| 1181 | .sel1 (sel_mux3_data_c6_1), |
| 1182 | .muxtst(muxtst), |
| 1183 | .test(test) |
| 1184 | ); |
| 1185 | |
| 1186 | |
| 1187 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_4_inv_slice |
| 1188 | ( |
| 1189 | .dout (arb_dword_mask_c8_4_n ), |
| 1190 | .din (arb_dword_mask_c8[4] ) |
| 1191 | ); |
| 1192 | |
| 1193 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux4 |
| 1194 | ( |
| 1195 | .dout ({sel_mux4_data_c6_0,sel_mux4_data_c6_1}), |
| 1196 | .din0 ({arb_dword_mask_c8_3_n,arb_dword_mask_c8[3]}), |
| 1197 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1198 | ); |
| 1199 | |
| 1200 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux4_data_c6 |
| 1201 | ( |
| 1202 | .dout (arbdat_mbdata_inst_data_c8[31:24]), |
| 1203 | .din0(arbdp_inst_data_c8[31:24]), |
| 1204 | .din1(decc_arbdp_data_c8[31:24]), |
| 1205 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1206 | .sel0 (sel_mux4_data_c6_0), |
| 1207 | .sel1 (sel_mux4_data_c6_1), |
| 1208 | .muxtst(muxtst), |
| 1209 | .test(test) |
| 1210 | ); |
| 1211 | |
| 1212 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_5_inv_slice |
| 1213 | ( |
| 1214 | .dout (arb_dword_mask_c8_5_n ), |
| 1215 | .din (arb_dword_mask_c8[5] ) |
| 1216 | ); |
| 1217 | |
| 1218 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux5 |
| 1219 | ( |
| 1220 | .dout ({sel_mux5_data_c6_0,sel_mux5_data_c6_1}), |
| 1221 | .din0 ({arb_dword_mask_c8_2_n,arb_dword_mask_c8[2]}), |
| 1222 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1223 | ); |
| 1224 | |
| 1225 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux5_data_c6 |
| 1226 | ( |
| 1227 | .dout (arbdat_mbdata_inst_data_c8[23:16]), |
| 1228 | .din0(arbdp_inst_data_c8[23:16]), |
| 1229 | .din1(decc_arbdp_data_c8[23:16]), |
| 1230 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1231 | .sel0 (sel_mux5_data_c6_0), |
| 1232 | .sel1 (sel_mux5_data_c6_1), |
| 1233 | .muxtst(muxtst), |
| 1234 | .test(test) |
| 1235 | ); |
| 1236 | |
| 1237 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_6_inv_slice |
| 1238 | ( |
| 1239 | .dout (arb_dword_mask_c8_6_n ), |
| 1240 | .din (arb_dword_mask_c8[6] ) |
| 1241 | ); |
| 1242 | |
| 1243 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux6 |
| 1244 | ( |
| 1245 | .dout ({sel_mux6_data_c6_0,sel_mux6_data_c6_1}), |
| 1246 | .din0 ({arb_dword_mask_c8_1_n,arb_dword_mask_c8[1]}), |
| 1247 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1248 | ); |
| 1249 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux6_data_c6 |
| 1250 | ( |
| 1251 | .dout (arbdat_mbdata_inst_data_c8[15:8]), |
| 1252 | .din0(arbdp_inst_data_c8[15:8]), |
| 1253 | .din1(decc_arbdp_data_c8[15:8]), |
| 1254 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1255 | .sel0 (sel_mux6_data_c6_0), |
| 1256 | .sel1 (sel_mux6_data_c6_1), |
| 1257 | .muxtst(muxtst), |
| 1258 | .test(test) |
| 1259 | ); |
| 1260 | |
| 1261 | l2t_arbdat_dp_inv_macro__width_1 arb_dword_mask_c8_7_inv_slice |
| 1262 | ( |
| 1263 | .dout (arb_dword_mask_c8_7_n ), |
| 1264 | .din (arb_dword_mask_c8[7] ) |
| 1265 | ); |
| 1266 | |
| 1267 | l2t_arbdat_dp_nor_macro__dnor_16x__width_2 nor_select_gen_mux7 |
| 1268 | ( |
| 1269 | .dout ({sel_mux7_data_c6_0,sel_mux7_data_c6_1}), |
| 1270 | .din0 ({arb_dword_mask_c8_0_n,arb_dword_mask_c8[0]}), |
| 1271 | .din1 ({l2t_mb2_run_r1,l2t_mb2_run_r1}) |
| 1272 | ); |
| 1273 | |
| 1274 | l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 mux7_data_c6 |
| 1275 | ( |
| 1276 | .dout (arbdat_mbdata_inst_data_c8[7:0]), |
| 1277 | .din0(arbdp_inst_data_c8[7:0]), |
| 1278 | .din1(decc_arbdp_data_c8[7:0]), |
| 1279 | .din2(l2t_mb2_wdata_r2[7:0]), |
| 1280 | .sel0 (sel_mux7_data_c6_0), |
| 1281 | .sel1 (sel_mux7_data_c6_1), |
| 1282 | .muxtst(muxtst), |
| 1283 | .test(test) |
| 1284 | ); |
| 1285 | |
| 1286 | |
| 1287 | //*************************************** |
| 1288 | // CAS COMPARATORS |
| 1289 | //*************************************** |
| 1290 | |
| 1291 | // CAS instruction to addr 0x4 |
| 1292 | //assign arbdat_word_lower_cmp_c8 = ( arbdp_inst_data_c8[31:0] == decc_arbdp_data_c8[31:0] ) ; |
| 1293 | |
| 1294 | l2t_arbdat_dp_cmp_macro__width_32 cas_cmp1 |
| 1295 | ( |
| 1296 | .din0(decc_arbdp_data_c8[31:0]), |
| 1297 | .din1(arbdp_inst_data_c8[31:0]), |
| 1298 | .dout(arbdat_word_lower_cmp_c8) |
| 1299 | ); |
| 1300 | |
| 1301 | // CAS instruction to addr 0x0 |
| 1302 | //assign arbdat_word_upper_cmp_c8 = ( arbdp_inst_data_c8[63:32] == decc_arbdp_data_c8[63:32] ) ; |
| 1303 | |
| 1304 | l2t_arbdat_dp_cmp_macro__width_32 cas_cmp2 |
| 1305 | ( |
| 1306 | .din0(decc_arbdp_data_c8[63:32]), |
| 1307 | .din1(arbdp_inst_data_c8[63:32]), |
| 1308 | .dout(arbdat_word_upper_cmp_c8) |
| 1309 | ); |
| 1310 | |
| 1311 | //********************************************** |
| 1312 | // C8 data sent to the CSR block for writes. |
| 1313 | //********************************************** |
| 1314 | |
| 1315 | assign arbdat_csr_inst_wr_data_c8 = arbdp_inst_data_c8 ; |
| 1316 | |
| 1317 | //assign arbdat_csr_bist_wr_data_c8 = arbdp_inst_data_c8[6:0] ; |
| 1318 | |
| 1319 | // Removed arbdat_csr_bist_wr_data_c8 2-1 mux. |
| 1320 | |
| 1321 | ///////////////////////////////////////////////////////////// |
| 1322 | // MBDATA MBIST SIGNALS |
| 1323 | ///////////////////////////////////////////////////////////// |
| 1324 | |
| 1325 | l2t_arbdat_dp_or_macro__width_1 or_mbdata_mbist_active |
| 1326 | ( |
| 1327 | .dout (mbdata_test_active), |
| 1328 | .din0 (mbdata_cmp_sel[0]), |
| 1329 | .din1 (mbdata_cmp_sel[1]) |
| 1330 | ); |
| 1331 | |
| 1332 | l2t_arbdat_dp_and_macro__width_1 and_enable_mbdata_rd |
| 1333 | ( |
| 1334 | .dout (misbuf_buf_rd_en_r2_qual), |
| 1335 | .din0 (mbdata_test_active), |
| 1336 | .din1 (misbuf_buf_rd_en_r2) |
| 1337 | ); |
| 1338 | |
| 1339 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 mux_mb_data_read_data0 |
| 1340 | ( |
| 1341 | .dout (mbdata_cmp_data[31:0]), |
| 1342 | .din0 (mbf_data_px2[31:0]), |
| 1343 | .din1 (mbf_data_px2[63:32]), |
| 1344 | .sel0 (mbdata_cmp_sel[0]), |
| 1345 | .sel1 (mbdata_cmp_sel[1]) |
| 1346 | ); |
| 1347 | |
| 1348 | l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c__width_1 mux_mbdata_fail_unreg |
| 1349 | ( |
| 1350 | .dout (mbdata_fail_unreg_w), |
| 1351 | .din0 (mbdata_fail_unreg), |
| 1352 | .din1 (1'b1), |
| 1353 | .sel0 (misbuf_buf_rd_en_r2_qual), |
| 1354 | .sel1 (misbuf_buf_rd_en_r2_n) |
| 1355 | ); |
| 1356 | |
| 1357 | l2t_arbdat_dp_inv_macro__width_1 inv_misbuf_buf_rd_en_r2 |
| 1358 | ( |
| 1359 | .dout (misbuf_buf_rd_en_r2_n), |
| 1360 | .din (misbuf_buf_rd_en_r2_qual) |
| 1361 | ); |
| 1362 | |
| 1363 | l2t_arbdat_dp_cmp_macro__dcmp_8x__width_32 cmp_mbdata_cmp_data |
| 1364 | ( |
| 1365 | .dout (mbdata_fail_unreg), |
| 1366 | .din0 ({4{l2t_mb2_wdata_r4[7:0]}}), |
| 1367 | .din1 (mbdata_cmp_data[31:0]) |
| 1368 | ); |
| 1369 | |
| 1370 | |
| 1371 | l2t_arbdat_dp_msff_macro__stack_38c__width_38 ff_mbdata_mbist_reg |
| 1372 | ( |
| 1373 | .scan_in(ff_mbdata_mbist_reg_scanin), |
| 1374 | .scan_out(ff_mbdata_mbist_reg_scanout), |
| 1375 | .dout ({mbdata_fail_bot, |
| 1376 | l2t_mb2_run_r1, |
| 1377 | l2t_mb2_wdata_r1[7:0], |
| 1378 | l2t_mb2_wdata_r2[7:0], |
| 1379 | l2t_mb2_wdata_r3[7:0], |
| 1380 | l2t_mb2_wdata_r4[7:0], |
| 1381 | misbuf_buf_rd_en_r1, |
| 1382 | misbuf_buf_rd_en_r2, |
| 1383 | sel_diag_store_data_c8, |
| 1384 | sel_diag_store_data_c8_n}), |
| 1385 | .din ({mbdata_fail_unreg_w, |
| 1386 | l2t_mb2_run, |
| 1387 | l2t_mb2_wdata[7:0], |
| 1388 | l2t_mb2_wdata_r1[7:0], |
| 1389 | l2t_mb2_wdata_r2[7:0], |
| 1390 | l2t_mb2_wdata_r3[7:0], |
| 1391 | misbuf_buf_rd_en, |
| 1392 | misbuf_buf_rd_en_r1, |
| 1393 | sel_diag_store_data_c7, |
| 1394 | sel_diag_store_data_c7_n}), |
| 1395 | .clk (l2clk), |
| 1396 | .en (1'b1), |
| 1397 | .se(se), |
| 1398 | .siclk(siclk), |
| 1399 | .soclk(soclk), |
| 1400 | .pce_ov(pce_ov), |
| 1401 | .stop(stop) |
| 1402 | ); |
| 1403 | |
| 1404 | |
| 1405 | ///////////////////// col offset generation ///////////////////////// |
| 1406 | |
| 1407 | input arb_inst_vld_c2_prev ; |
| 1408 | input [3:0] dec_col_offset_prev_c1; |
| 1409 | input [1:0] arbadr_arbdp_addr5to4_c1; |
| 1410 | output [3:0] tag_l2d_col_offset_c2; |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | l2t_arbdat_dp_inv_macro__dinv_8x__width_4 inv_col_offset_sel_c2 |
| 1415 | ( |
| 1416 | .dout ({arb_inst_vld_c2_prev_n,arbadr_arbdp_addr5to4_c1_n[1:0],col_offset_sel_c1_n}), |
| 1417 | .din ({arb_inst_vld_c2_prev,arbadr_arbdp_addr5to4_c1[1:0],col_offset_sel_c1}) |
| 1418 | ); |
| 1419 | |
| 1420 | l2t_arbdat_dp_nor_macro__dnor_8x__width_1 nor_col_offset_sel_c1 |
| 1421 | ( |
| 1422 | .dout (col_offset_sel_c1), |
| 1423 | .din0 (arb_inst_vld_c2_prev_n), |
| 1424 | .din1 (bist_data_enable_c1) |
| 1425 | ); |
| 1426 | |
| 1427 | l2t_arbdat_dp_and_macro__dinv_8x__dnand_8x__width_4 and_dec_col_offset_c1 |
| 1428 | ( |
| 1429 | .dout (dec_col_offset_c1[3:0]), |
| 1430 | .din0 ({arbadr_arbdp_addr5to4_c1[1],arbadr_arbdp_addr5to4_c1[1], |
| 1431 | arbadr_arbdp_addr5to4_c1_n[1],arbadr_arbdp_addr5to4_c1_n[1]}), |
| 1432 | .din1 ({arbadr_arbdp_addr5to4_c1[0],arbadr_arbdp_addr5to4_c1_n[0], |
| 1433 | arbadr_arbdp_addr5to4_c1[0],arbadr_arbdp_addr5to4_c1_n[0]}) |
| 1434 | ); |
| 1435 | |
| 1436 | |
| 1437 | l2t_arbdat_dp_msff_macro__dmsff_32x__stack_10c__width_10 ff_col_offset_sel_c2 |
| 1438 | ( |
| 1439 | .scan_in(ff_col_offset_sel_c2_scanin), |
| 1440 | .scan_out(ff_col_offset_sel_c2_scanout), |
| 1441 | .din({dec_col_offset_c1[3:0],dec_col_offset_prev_c1[3:0], |
| 1442 | col_offset_sel_c1,col_offset_sel_c1_n}), |
| 1443 | .clk(l2clk), |
| 1444 | .en(1'b1), |
| 1445 | .dout({dec_col_offset_c2[3:0],col_offset_dec_prev_c2[3:0], |
| 1446 | col_offset_sel_c2,col_offset_sel_c2_n}), |
| 1447 | .se(se), |
| 1448 | .siclk(siclk), |
| 1449 | .soclk(soclk), |
| 1450 | .pce_ov(pce_ov), |
| 1451 | .stop(stop) |
| 1452 | ); |
| 1453 | |
| 1454 | l2t_arbdat_dp_nand_macro__dnand_16x__stack_4r__width_4 nand_tag_l2d_col_offset_c2_a |
| 1455 | ( |
| 1456 | .dout (tag_l2d_col_offset_c2_1[3:0]), |
| 1457 | .din0 (col_offset_dec_prev_c2[3:0]), |
| 1458 | .din1 ({4{col_offset_sel_c2_n}}) |
| 1459 | ); |
| 1460 | |
| 1461 | |
| 1462 | l2t_arbdat_dp_nand_macro__dnand_16x__stack_4r__width_4 nand_tag_l2d_col_offset_c2_b |
| 1463 | ( |
| 1464 | .dout (tag_l2d_col_offset_c2_2[3:0]), |
| 1465 | .din0 (dec_col_offset_c2[3:0]), |
| 1466 | .din1 ({4{col_offset_sel_c2}}) |
| 1467 | ); |
| 1468 | |
| 1469 | |
| 1470 | l2t_arbdat_dp_nand_macro__dnand_32x__stack_4r__width_4 nand_tag_l2d_col_offset_c2 |
| 1471 | ( |
| 1472 | .dout ({tag_l2d_col_offset_c2[0], tag_l2d_col_offset_c2[1], |
| 1473 | tag_l2d_col_offset_c2[2], tag_l2d_col_offset_c2[3]}), |
| 1474 | .din0 (tag_l2d_col_offset_c2_1[3:0]), |
| 1475 | .din1 (tag_l2d_col_offset_c2_2[3:0]) |
| 1476 | ); |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | // fixscan start: |
| 1482 | assign ff_read_mbdata_reg1_scanin = scan_in ; |
| 1483 | assign ff_read_mbdata_reg2_scanin = ff_read_mbdata_reg1_scanout; |
| 1484 | assign ff_data_c11_scanin = ff_read_mbdata_reg2_scanout; |
| 1485 | assign ff_data_c12_scanin = ff_data_c11_scanout ; |
| 1486 | assign ff_decc_data_c91_scanin = ff_data_c12_scanout ; |
| 1487 | assign ff_decc_data_c92_scanin = ff_decc_data_c91_scanout ; |
| 1488 | assign ff_data31to0_c2_scanin = ff_decc_data_c92_scanout ; |
| 1489 | assign ff_data63to32_c2_scanin = ff_data31to0_c2_scanout ; |
| 1490 | assign ff_ecc0to6_c2_scanin = ff_data63to32_c2_scanout ; |
| 1491 | assign ff_ecc7to13_c2_scanin = ff_ecc0to6_c2_scanout ; |
| 1492 | assign ff_data_c21_scanin = ff_ecc7to13_c2_scanout ; |
| 1493 | assign ff_data_c22_scanin = ff_data_c21_scanout ; |
| 1494 | assign ff_data_c31_scanin = ff_data_c22_scanout ; |
| 1495 | assign ff_data_c32_scanin = ff_data_c31_scanout ; |
| 1496 | assign ff_data_c41_scanin = ff_data_c32_scanout ; |
| 1497 | assign ff_data_c42_scanin = ff_data_c41_scanout ; |
| 1498 | assign ff_data_c51_scanin = ff_data_c42_scanout ; |
| 1499 | assign ff_data_c52_scanin = ff_data_c51_scanout ; |
| 1500 | assign ff_data_c521_scanin = ff_data_c52_scanout ; |
| 1501 | assign ff_data_c522_scanin = ff_data_c521_scanout ; |
| 1502 | assign ff_data_c61_scanin = ff_data_c522_scanout ; |
| 1503 | assign ff_data_c62_scanin = ff_data_c61_scanout ; |
| 1504 | assign ff_data_c71_scanin = ff_data_c62_scanout ; |
| 1505 | assign ff_data_c72_scanin = ff_data_c71_scanout ; |
| 1506 | assign ff_data_c81_scanin = ff_data_c72_scanout ; |
| 1507 | assign ff_data_c82_scanin = ff_data_c81_scanout ; |
| 1508 | assign ff_mbdata_mbist_reg_scanin = ff_data_c82_scanout ; |
| 1509 | assign ff_col_offset_sel_c2_scanin = ff_mbdata_mbist_reg_scanout; |
| 1510 | assign scan_out = ff_col_offset_sel_c2_scanout; |
| 1511 | // fixscan end: |
| 1512 | endmodule |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | // any PARAMS parms go into naming of macro |
| 1522 | |
| 1523 | module l2t_arbdat_dp_msff_macro__stack_32c__width_32 ( |
| 1524 | din, |
| 1525 | clk, |
| 1526 | en, |
| 1527 | se, |
| 1528 | scan_in, |
| 1529 | siclk, |
| 1530 | soclk, |
| 1531 | pce_ov, |
| 1532 | stop, |
| 1533 | dout, |
| 1534 | scan_out); |
| 1535 | wire l1clk; |
| 1536 | wire siclk_out; |
| 1537 | wire soclk_out; |
| 1538 | wire [30:0] so; |
| 1539 | |
| 1540 | input [31:0] din; |
| 1541 | |
| 1542 | |
| 1543 | input clk; |
| 1544 | input en; |
| 1545 | input se; |
| 1546 | input scan_in; |
| 1547 | input siclk; |
| 1548 | input soclk; |
| 1549 | input pce_ov; |
| 1550 | input stop; |
| 1551 | |
| 1552 | |
| 1553 | |
| 1554 | output [31:0] dout; |
| 1555 | |
| 1556 | |
| 1557 | output scan_out; |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | cl_dp1_l1hdr_8x c0_0 ( |
| 1563 | .l2clk(clk), |
| 1564 | .pce(en), |
| 1565 | .aclk(siclk), |
| 1566 | .bclk(soclk), |
| 1567 | .l1clk(l1clk), |
| 1568 | .se(se), |
| 1569 | .pce_ov(pce_ov), |
| 1570 | .stop(stop), |
| 1571 | .siclk_out(siclk_out), |
| 1572 | .soclk_out(soclk_out) |
| 1573 | ); |
| 1574 | dff #(32) d0_0 ( |
| 1575 | .l1clk(l1clk), |
| 1576 | .siclk(siclk_out), |
| 1577 | .soclk(soclk_out), |
| 1578 | .d(din[31:0]), |
| 1579 | .si({scan_in,so[30:0]}), |
| 1580 | .so({so[30:0],scan_out}), |
| 1581 | .q(dout[31:0]) |
| 1582 | ); |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | |
| 1598 | |
| 1599 | |
| 1600 | |
| 1601 | |
| 1602 | |
| 1603 | endmodule |
| 1604 | |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | // |
| 1614 | // invert macro |
| 1615 | // |
| 1616 | // |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | module l2t_arbdat_dp_inv_macro__width_1 ( |
| 1623 | din, |
| 1624 | dout); |
| 1625 | input [0:0] din; |
| 1626 | output [0:0] dout; |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | |
| 1631 | |
| 1632 | |
| 1633 | inv #(1) d0_0 ( |
| 1634 | .in(din[0:0]), |
| 1635 | .out(dout[0:0]) |
| 1636 | ); |
| 1637 | |
| 1638 | |
| 1639 | |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | endmodule |
| 1647 | |
| 1648 | |
| 1649 | |
| 1650 | |
| 1651 | |
| 1652 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1653 | // also for pass-gate with decoder |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | // any PARAMS parms go into naming of macro |
| 1660 | |
| 1661 | module l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32c__width_32 ( |
| 1662 | din0, |
| 1663 | sel0, |
| 1664 | din1, |
| 1665 | sel1, |
| 1666 | dout); |
| 1667 | wire buffout0; |
| 1668 | wire buffout1; |
| 1669 | |
| 1670 | input [31:0] din0; |
| 1671 | input sel0; |
| 1672 | input [31:0] din1; |
| 1673 | input sel1; |
| 1674 | output [31:0] dout; |
| 1675 | |
| 1676 | |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | cl_dp1_muxbuff2_8x c0_0 ( |
| 1681 | .in0(sel0), |
| 1682 | .in1(sel1), |
| 1683 | .out0(buffout0), |
| 1684 | .out1(buffout1) |
| 1685 | ); |
| 1686 | mux2s #(32) d0_0 ( |
| 1687 | .sel0(buffout0), |
| 1688 | .sel1(buffout1), |
| 1689 | .in0(din0[31:0]), |
| 1690 | .in1(din1[31:0]), |
| 1691 | .dout(dout[31:0]) |
| 1692 | ); |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | endmodule |
| 1707 | |
| 1708 | |
| 1709 | // |
| 1710 | // and macro for ports = 2,3,4 |
| 1711 | // |
| 1712 | // |
| 1713 | |
| 1714 | |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 | module l2t_arbdat_dp_and_macro__width_1 ( |
| 1719 | din0, |
| 1720 | din1, |
| 1721 | dout); |
| 1722 | input [0:0] din0; |
| 1723 | input [0:0] din1; |
| 1724 | output [0:0] dout; |
| 1725 | |
| 1726 | |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | |
| 1731 | and2 #(1) d0_0 ( |
| 1732 | .in0(din0[0:0]), |
| 1733 | .in1(din1[0:0]), |
| 1734 | .out(dout[0:0]) |
| 1735 | ); |
| 1736 | |
| 1737 | |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | |
| 1742 | |
| 1743 | |
| 1744 | |
| 1745 | endmodule |
| 1746 | |
| 1747 | |
| 1748 | |
| 1749 | |
| 1750 | // |
| 1751 | // xor macro for ports = 2,3 |
| 1752 | // |
| 1753 | // |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | module l2t_arbdat_dp_xor_macro__dxor_8x__ports_3__width_1 ( |
| 1760 | din0, |
| 1761 | din1, |
| 1762 | din2, |
| 1763 | dout); |
| 1764 | input [0:0] din0; |
| 1765 | input [0:0] din1; |
| 1766 | input [0:0] din2; |
| 1767 | output [0:0] dout; |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | xor3 #(1) d0_0 ( |
| 1774 | .in0(din0[0:0]), |
| 1775 | .in1(din1[0:0]), |
| 1776 | .in2(din2[0:0]), |
| 1777 | .out(dout[0:0]) |
| 1778 | ); |
| 1779 | |
| 1780 | |
| 1781 | |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | |
| 1787 | endmodule |
| 1788 | |
| 1789 | |
| 1790 | |
| 1791 | |
| 1792 | |
| 1793 | // |
| 1794 | // xor macro for ports = 2,3 |
| 1795 | // |
| 1796 | // |
| 1797 | |
| 1798 | |
| 1799 | |
| 1800 | |
| 1801 | |
| 1802 | module l2t_arbdat_dp_xor_macro__dxor_8x__ports_2__width_1 ( |
| 1803 | din0, |
| 1804 | din1, |
| 1805 | dout); |
| 1806 | input [0:0] din0; |
| 1807 | input [0:0] din1; |
| 1808 | output [0:0] dout; |
| 1809 | |
| 1810 | |
| 1811 | |
| 1812 | |
| 1813 | |
| 1814 | xor2 #(1) d0_0 ( |
| 1815 | .in0(din0[0:0]), |
| 1816 | .in1(din1[0:0]), |
| 1817 | .out(dout[0:0]) |
| 1818 | ); |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | endmodule |
| 1828 | |
| 1829 | |
| 1830 | |
| 1831 | |
| 1832 | |
| 1833 | // |
| 1834 | // and macro for ports = 2,3,4 |
| 1835 | // |
| 1836 | // |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | |
| 1842 | module l2t_arbdat_dp_and_macro__ports_2__width_1 ( |
| 1843 | din0, |
| 1844 | din1, |
| 1845 | dout); |
| 1846 | input [0:0] din0; |
| 1847 | input [0:0] din1; |
| 1848 | output [0:0] dout; |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | |
| 1855 | and2 #(1) d0_0 ( |
| 1856 | .in0(din0[0:0]), |
| 1857 | .in1(din1[0:0]), |
| 1858 | .out(dout[0:0]) |
| 1859 | ); |
| 1860 | |
| 1861 | |
| 1862 | |
| 1863 | |
| 1864 | |
| 1865 | |
| 1866 | |
| 1867 | |
| 1868 | |
| 1869 | endmodule |
| 1870 | |
| 1871 | |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | // |
| 1876 | // invert macro |
| 1877 | // |
| 1878 | // |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | module l2t_arbdat_dp_inv_macro__width_14 ( |
| 1885 | din, |
| 1886 | dout); |
| 1887 | input [13:0] din; |
| 1888 | output [13:0] dout; |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | inv #(14) d0_0 ( |
| 1896 | .in(din[13:0]), |
| 1897 | .out(dout[13:0]) |
| 1898 | ); |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | |
| 1906 | |
| 1907 | |
| 1908 | endmodule |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1915 | // also for pass-gate with decoder |
| 1916 | |
| 1917 | |
| 1918 | |
| 1919 | |
| 1920 | |
| 1921 | // any PARAMS parms go into naming of macro |
| 1922 | |
| 1923 | module l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14c__width_14 ( |
| 1924 | din0, |
| 1925 | sel0, |
| 1926 | din1, |
| 1927 | sel1, |
| 1928 | dout); |
| 1929 | wire buffout0; |
| 1930 | wire buffout1; |
| 1931 | |
| 1932 | input [13:0] din0; |
| 1933 | input sel0; |
| 1934 | input [13:0] din1; |
| 1935 | input sel1; |
| 1936 | output [13:0] dout; |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | |
| 1942 | cl_dp1_muxbuff2_8x c0_0 ( |
| 1943 | .in0(sel0), |
| 1944 | .in1(sel1), |
| 1945 | .out0(buffout0), |
| 1946 | .out1(buffout1) |
| 1947 | ); |
| 1948 | mux2s #(14) d0_0 ( |
| 1949 | .sel0(buffout0), |
| 1950 | .sel1(buffout1), |
| 1951 | .in0(din0[13:0]), |
| 1952 | .in1(din1[13:0]), |
| 1953 | .dout(dout[13:0]) |
| 1954 | ); |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | endmodule |
| 1969 | |
| 1970 | |
| 1971 | // |
| 1972 | // xor macro for ports = 2,3 |
| 1973 | // |
| 1974 | // |
| 1975 | |
| 1976 | |
| 1977 | |
| 1978 | |
| 1979 | |
| 1980 | module l2t_arbdat_dp_xor_macro__width_1 ( |
| 1981 | din0, |
| 1982 | din1, |
| 1983 | dout); |
| 1984 | input [0:0] din0; |
| 1985 | input [0:0] din1; |
| 1986 | output [0:0] dout; |
| 1987 | |
| 1988 | |
| 1989 | |
| 1990 | |
| 1991 | |
| 1992 | xor2 #(1) d0_0 ( |
| 1993 | .in0(din0[0:0]), |
| 1994 | .in1(din1[0:0]), |
| 1995 | .out(dout[0:0]) |
| 1996 | ); |
| 1997 | |
| 1998 | |
| 1999 | |
| 2000 | |
| 2001 | |
| 2002 | |
| 2003 | |
| 2004 | |
| 2005 | endmodule |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | // any PARAMS parms go into naming of macro |
| 2016 | |
| 2017 | module l2t_arbdat_dp_msff_macro__dmsff_32x__stack_32c__width_32 ( |
| 2018 | din, |
| 2019 | clk, |
| 2020 | en, |
| 2021 | se, |
| 2022 | scan_in, |
| 2023 | siclk, |
| 2024 | soclk, |
| 2025 | pce_ov, |
| 2026 | stop, |
| 2027 | dout, |
| 2028 | scan_out); |
| 2029 | wire l1clk; |
| 2030 | wire siclk_out; |
| 2031 | wire soclk_out; |
| 2032 | wire [30:0] so; |
| 2033 | |
| 2034 | input [31:0] din; |
| 2035 | |
| 2036 | |
| 2037 | input clk; |
| 2038 | input en; |
| 2039 | input se; |
| 2040 | input scan_in; |
| 2041 | input siclk; |
| 2042 | input soclk; |
| 2043 | input pce_ov; |
| 2044 | input stop; |
| 2045 | |
| 2046 | |
| 2047 | |
| 2048 | output [31:0] dout; |
| 2049 | |
| 2050 | |
| 2051 | output scan_out; |
| 2052 | |
| 2053 | |
| 2054 | |
| 2055 | |
| 2056 | cl_dp1_l1hdr_8x c0_0 ( |
| 2057 | .l2clk(clk), |
| 2058 | .pce(en), |
| 2059 | .aclk(siclk), |
| 2060 | .bclk(soclk), |
| 2061 | .l1clk(l1clk), |
| 2062 | .se(se), |
| 2063 | .pce_ov(pce_ov), |
| 2064 | .stop(stop), |
| 2065 | .siclk_out(siclk_out), |
| 2066 | .soclk_out(soclk_out) |
| 2067 | ); |
| 2068 | dff #(32) d0_0 ( |
| 2069 | .l1clk(l1clk), |
| 2070 | .siclk(siclk_out), |
| 2071 | .soclk(soclk_out), |
| 2072 | .d(din[31:0]), |
| 2073 | .si({scan_in,so[30:0]}), |
| 2074 | .so({so[30:0],scan_out}), |
| 2075 | .q(dout[31:0]) |
| 2076 | ); |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | endmodule |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | |
| 2102 | |
| 2103 | |
| 2104 | |
| 2105 | |
| 2106 | |
| 2107 | // |
| 2108 | // buff macro |
| 2109 | // |
| 2110 | // |
| 2111 | |
| 2112 | |
| 2113 | |
| 2114 | |
| 2115 | |
| 2116 | module l2t_arbdat_dp_buff_macro__dbuff_16x__stack_32c__width_32 ( |
| 2117 | din, |
| 2118 | dout); |
| 2119 | input [31:0] din; |
| 2120 | output [31:0] dout; |
| 2121 | |
| 2122 | |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | buff #(32) d0_0 ( |
| 2128 | .in(din[31:0]), |
| 2129 | .out(dout[31:0]) |
| 2130 | ); |
| 2131 | |
| 2132 | |
| 2133 | |
| 2134 | |
| 2135 | |
| 2136 | |
| 2137 | |
| 2138 | |
| 2139 | endmodule |
| 2140 | |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2146 | // also for pass-gate with decoder |
| 2147 | |
| 2148 | |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | // any PARAMS parms go into naming of macro |
| 2153 | |
| 2154 | module l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 ( |
| 2155 | din0, |
| 2156 | sel0, |
| 2157 | din1, |
| 2158 | sel1, |
| 2159 | dout); |
| 2160 | wire buffout0; |
| 2161 | wire buffout1; |
| 2162 | |
| 2163 | input [6:0] din0; |
| 2164 | input sel0; |
| 2165 | input [6:0] din1; |
| 2166 | input sel1; |
| 2167 | output [6:0] dout; |
| 2168 | |
| 2169 | |
| 2170 | |
| 2171 | |
| 2172 | |
| 2173 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2174 | .in0(sel0), |
| 2175 | .in1(sel1), |
| 2176 | .out0(buffout0), |
| 2177 | .out1(buffout1) |
| 2178 | ); |
| 2179 | mux2s #(7) d0_0 ( |
| 2180 | .sel0(buffout0), |
| 2181 | .sel1(buffout1), |
| 2182 | .in0(din0[6:0]), |
| 2183 | .in1(din1[6:0]), |
| 2184 | .dout(dout[6:0]) |
| 2185 | ); |
| 2186 | |
| 2187 | |
| 2188 | |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | |
| 2194 | |
| 2195 | |
| 2196 | |
| 2197 | |
| 2198 | |
| 2199 | endmodule |
| 2200 | |
| 2201 | |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | // any PARAMS parms go into naming of macro |
| 2207 | |
| 2208 | module l2t_arbdat_dp_msff_macro__dmsff_32x__stack_7c__width_7 ( |
| 2209 | din, |
| 2210 | clk, |
| 2211 | en, |
| 2212 | se, |
| 2213 | scan_in, |
| 2214 | siclk, |
| 2215 | soclk, |
| 2216 | pce_ov, |
| 2217 | stop, |
| 2218 | dout, |
| 2219 | scan_out); |
| 2220 | wire l1clk; |
| 2221 | wire siclk_out; |
| 2222 | wire soclk_out; |
| 2223 | wire [5:0] so; |
| 2224 | |
| 2225 | input [6:0] din; |
| 2226 | |
| 2227 | |
| 2228 | input clk; |
| 2229 | input en; |
| 2230 | input se; |
| 2231 | input scan_in; |
| 2232 | input siclk; |
| 2233 | input soclk; |
| 2234 | input pce_ov; |
| 2235 | input stop; |
| 2236 | |
| 2237 | |
| 2238 | |
| 2239 | output [6:0] dout; |
| 2240 | |
| 2241 | |
| 2242 | output scan_out; |
| 2243 | |
| 2244 | |
| 2245 | |
| 2246 | |
| 2247 | cl_dp1_l1hdr_8x c0_0 ( |
| 2248 | .l2clk(clk), |
| 2249 | .pce(en), |
| 2250 | .aclk(siclk), |
| 2251 | .bclk(soclk), |
| 2252 | .l1clk(l1clk), |
| 2253 | .se(se), |
| 2254 | .pce_ov(pce_ov), |
| 2255 | .stop(stop), |
| 2256 | .siclk_out(siclk_out), |
| 2257 | .soclk_out(soclk_out) |
| 2258 | ); |
| 2259 | dff #(7) d0_0 ( |
| 2260 | .l1clk(l1clk), |
| 2261 | .siclk(siclk_out), |
| 2262 | .soclk(soclk_out), |
| 2263 | .d(din[6:0]), |
| 2264 | .si({scan_in,so[5:0]}), |
| 2265 | .so({so[5:0],scan_out}), |
| 2266 | .q(dout[6:0]) |
| 2267 | ); |
| 2268 | |
| 2269 | |
| 2270 | |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | |
| 2278 | |
| 2279 | |
| 2280 | |
| 2281 | |
| 2282 | |
| 2283 | |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | endmodule |
| 2289 | |
| 2290 | |
| 2291 | |
| 2292 | |
| 2293 | |
| 2294 | |
| 2295 | |
| 2296 | |
| 2297 | |
| 2298 | |
| 2299 | |
| 2300 | |
| 2301 | |
| 2302 | // any PARAMS parms go into naming of macro |
| 2303 | |
| 2304 | module l2t_arbdat_dp_msff_macro__dmsff_4x__stack_32c__width_32 ( |
| 2305 | din, |
| 2306 | clk, |
| 2307 | en, |
| 2308 | se, |
| 2309 | scan_in, |
| 2310 | siclk, |
| 2311 | soclk, |
| 2312 | pce_ov, |
| 2313 | stop, |
| 2314 | dout, |
| 2315 | scan_out); |
| 2316 | wire l1clk; |
| 2317 | wire siclk_out; |
| 2318 | wire soclk_out; |
| 2319 | wire [30:0] so; |
| 2320 | |
| 2321 | input [31:0] din; |
| 2322 | |
| 2323 | |
| 2324 | input clk; |
| 2325 | input en; |
| 2326 | input se; |
| 2327 | input scan_in; |
| 2328 | input siclk; |
| 2329 | input soclk; |
| 2330 | input pce_ov; |
| 2331 | input stop; |
| 2332 | |
| 2333 | |
| 2334 | |
| 2335 | output [31:0] dout; |
| 2336 | |
| 2337 | |
| 2338 | output scan_out; |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | |
| 2343 | cl_dp1_l1hdr_8x c0_0 ( |
| 2344 | .l2clk(clk), |
| 2345 | .pce(en), |
| 2346 | .aclk(siclk), |
| 2347 | .bclk(soclk), |
| 2348 | .l1clk(l1clk), |
| 2349 | .se(se), |
| 2350 | .pce_ov(pce_ov), |
| 2351 | .stop(stop), |
| 2352 | .siclk_out(siclk_out), |
| 2353 | .soclk_out(soclk_out) |
| 2354 | ); |
| 2355 | dff #(32) d0_0 ( |
| 2356 | .l1clk(l1clk), |
| 2357 | .siclk(siclk_out), |
| 2358 | .soclk(soclk_out), |
| 2359 | .d(din[31:0]), |
| 2360 | .si({scan_in,so[30:0]}), |
| 2361 | .so({so[30:0],scan_out}), |
| 2362 | .q(dout[31:0]) |
| 2363 | ); |
| 2364 | |
| 2365 | |
| 2366 | |
| 2367 | |
| 2368 | |
| 2369 | |
| 2370 | |
| 2371 | |
| 2372 | |
| 2373 | |
| 2374 | |
| 2375 | |
| 2376 | |
| 2377 | |
| 2378 | |
| 2379 | |
| 2380 | |
| 2381 | |
| 2382 | |
| 2383 | |
| 2384 | endmodule |
| 2385 | |
| 2386 | |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | |
| 2392 | |
| 2393 | |
| 2394 | |
| 2395 | |
| 2396 | |
| 2397 | |
| 2398 | // any PARAMS parms go into naming of macro |
| 2399 | |
| 2400 | module l2t_arbdat_dp_msff_macro__dmsff_32x__minbuff_1__stack_32c__width_32 ( |
| 2401 | din, |
| 2402 | clk, |
| 2403 | en, |
| 2404 | se, |
| 2405 | scan_in, |
| 2406 | siclk, |
| 2407 | soclk, |
| 2408 | pce_ov, |
| 2409 | stop, |
| 2410 | dout, |
| 2411 | scan_out); |
| 2412 | wire l1clk; |
| 2413 | wire siclk_out; |
| 2414 | wire soclk_out; |
| 2415 | wire [30:0] so; |
| 2416 | |
| 2417 | input [31:0] din; |
| 2418 | |
| 2419 | |
| 2420 | input clk; |
| 2421 | input en; |
| 2422 | input se; |
| 2423 | input scan_in; |
| 2424 | input siclk; |
| 2425 | input soclk; |
| 2426 | input pce_ov; |
| 2427 | input stop; |
| 2428 | |
| 2429 | |
| 2430 | |
| 2431 | output [31:0] dout; |
| 2432 | |
| 2433 | |
| 2434 | output scan_out; |
| 2435 | |
| 2436 | |
| 2437 | |
| 2438 | |
| 2439 | cl_dp1_l1hdr_8x c0_0 ( |
| 2440 | .l2clk(clk), |
| 2441 | .pce(en), |
| 2442 | .aclk(siclk), |
| 2443 | .bclk(soclk), |
| 2444 | .l1clk(l1clk), |
| 2445 | .se(se), |
| 2446 | .pce_ov(pce_ov), |
| 2447 | .stop(stop), |
| 2448 | .siclk_out(siclk_out), |
| 2449 | .soclk_out(soclk_out) |
| 2450 | ); |
| 2451 | dff #(32) d0_0 ( |
| 2452 | .l1clk(l1clk), |
| 2453 | .siclk(siclk_out), |
| 2454 | .soclk(soclk_out), |
| 2455 | .d(din[31:0]), |
| 2456 | .si({scan_in,so[30:0]}), |
| 2457 | .so({so[30:0],scan_out}), |
| 2458 | .q(dout[31:0]) |
| 2459 | ); |
| 2460 | |
| 2461 | |
| 2462 | |
| 2463 | |
| 2464 | |
| 2465 | |
| 2466 | |
| 2467 | |
| 2468 | |
| 2469 | |
| 2470 | |
| 2471 | |
| 2472 | |
| 2473 | |
| 2474 | |
| 2475 | |
| 2476 | |
| 2477 | |
| 2478 | |
| 2479 | |
| 2480 | endmodule |
| 2481 | |
| 2482 | |
| 2483 | |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | |
| 2488 | |
| 2489 | |
| 2490 | // |
| 2491 | // buff macro |
| 2492 | // |
| 2493 | // |
| 2494 | |
| 2495 | |
| 2496 | |
| 2497 | |
| 2498 | |
| 2499 | module l2t_arbdat_dp_buff_macro__dbuff_32x__stack_32c__width_32 ( |
| 2500 | din, |
| 2501 | dout); |
| 2502 | input [31:0] din; |
| 2503 | output [31:0] dout; |
| 2504 | |
| 2505 | |
| 2506 | |
| 2507 | |
| 2508 | |
| 2509 | |
| 2510 | buff #(32) d0_0 ( |
| 2511 | .in(din[31:0]), |
| 2512 | .out(dout[31:0]) |
| 2513 | ); |
| 2514 | |
| 2515 | |
| 2516 | |
| 2517 | |
| 2518 | |
| 2519 | |
| 2520 | |
| 2521 | |
| 2522 | endmodule |
| 2523 | |
| 2524 | |
| 2525 | |
| 2526 | |
| 2527 | |
| 2528 | // |
| 2529 | // invert macro |
| 2530 | // |
| 2531 | // |
| 2532 | |
| 2533 | |
| 2534 | |
| 2535 | |
| 2536 | |
| 2537 | module l2t_arbdat_dp_inv_macro__dinv_4x__width_1 ( |
| 2538 | din, |
| 2539 | dout); |
| 2540 | input [0:0] din; |
| 2541 | output [0:0] dout; |
| 2542 | |
| 2543 | |
| 2544 | |
| 2545 | |
| 2546 | |
| 2547 | |
| 2548 | inv #(1) d0_0 ( |
| 2549 | .in(din[0:0]), |
| 2550 | .out(dout[0:0]) |
| 2551 | ); |
| 2552 | |
| 2553 | |
| 2554 | |
| 2555 | |
| 2556 | |
| 2557 | |
| 2558 | |
| 2559 | |
| 2560 | |
| 2561 | endmodule |
| 2562 | |
| 2563 | |
| 2564 | |
| 2565 | |
| 2566 | |
| 2567 | // |
| 2568 | // nor macro for ports = 2,3 |
| 2569 | // |
| 2570 | // |
| 2571 | |
| 2572 | |
| 2573 | |
| 2574 | |
| 2575 | |
| 2576 | module l2t_arbdat_dp_nor_macro__dnor_16x__width_2 ( |
| 2577 | din0, |
| 2578 | din1, |
| 2579 | dout); |
| 2580 | input [1:0] din0; |
| 2581 | input [1:0] din1; |
| 2582 | output [1:0] dout; |
| 2583 | |
| 2584 | |
| 2585 | |
| 2586 | |
| 2587 | |
| 2588 | |
| 2589 | nor2 #(2) d0_0 ( |
| 2590 | .in0(din0[1:0]), |
| 2591 | .in1(din1[1:0]), |
| 2592 | .out(dout[1:0]) |
| 2593 | ); |
| 2594 | |
| 2595 | |
| 2596 | |
| 2597 | |
| 2598 | |
| 2599 | |
| 2600 | |
| 2601 | endmodule |
| 2602 | |
| 2603 | |
| 2604 | |
| 2605 | |
| 2606 | |
| 2607 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2608 | // also for pass-gate with decoder |
| 2609 | |
| 2610 | |
| 2611 | |
| 2612 | |
| 2613 | |
| 2614 | // any PARAMS parms go into naming of macro |
| 2615 | |
| 2616 | module l2t_arbdat_dp_mux_macro__dmux_32x__mux_pgpe__ports_3__stack_8c__width_8 ( |
| 2617 | din0, |
| 2618 | din1, |
| 2619 | din2, |
| 2620 | sel0, |
| 2621 | sel1, |
| 2622 | muxtst, |
| 2623 | test, |
| 2624 | dout); |
| 2625 | wire psel0; |
| 2626 | wire psel1; |
| 2627 | wire psel2; |
| 2628 | |
| 2629 | input [7:0] din0; |
| 2630 | input [7:0] din1; |
| 2631 | input [7:0] din2; |
| 2632 | input sel0; |
| 2633 | input sel1; |
| 2634 | input muxtst; |
| 2635 | input test; |
| 2636 | output [7:0] dout; |
| 2637 | |
| 2638 | |
| 2639 | |
| 2640 | |
| 2641 | |
| 2642 | cl_dp1_penc3_8x c0_0 ( |
| 2643 | .sel0(sel0), |
| 2644 | .sel1(sel1), |
| 2645 | .psel0(psel0), |
| 2646 | .psel1(psel1), |
| 2647 | .psel2(psel2), |
| 2648 | .test(test) |
| 2649 | ); |
| 2650 | |
| 2651 | mux3 #(8) d0_0 ( |
| 2652 | .sel0(psel0), |
| 2653 | .sel1(psel1), |
| 2654 | .sel2(psel2), |
| 2655 | .in0(din0[7:0]), |
| 2656 | .in1(din1[7:0]), |
| 2657 | .in2(din2[7:0]), |
| 2658 | .dout(dout[7:0]), |
| 2659 | .muxtst(muxtst) |
| 2660 | ); |
| 2661 | |
| 2662 | |
| 2663 | |
| 2664 | |
| 2665 | |
| 2666 | |
| 2667 | |
| 2668 | |
| 2669 | |
| 2670 | |
| 2671 | |
| 2672 | |
| 2673 | |
| 2674 | endmodule |
| 2675 | |
| 2676 | |
| 2677 | // |
| 2678 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 2679 | // |
| 2680 | // |
| 2681 | |
| 2682 | |
| 2683 | |
| 2684 | |
| 2685 | |
| 2686 | module l2t_arbdat_dp_cmp_macro__width_32 ( |
| 2687 | din0, |
| 2688 | din1, |
| 2689 | dout); |
| 2690 | input [31:0] din0; |
| 2691 | input [31:0] din1; |
| 2692 | output dout; |
| 2693 | |
| 2694 | |
| 2695 | |
| 2696 | |
| 2697 | |
| 2698 | |
| 2699 | cmp #(32) m0_0 ( |
| 2700 | .in0(din0[31:0]), |
| 2701 | .in1(din1[31:0]), |
| 2702 | .out(dout) |
| 2703 | ); |
| 2704 | |
| 2705 | |
| 2706 | |
| 2707 | |
| 2708 | |
| 2709 | |
| 2710 | |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | endmodule |
| 2715 | |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | |
| 2720 | // |
| 2721 | // or macro for ports = 2,3 |
| 2722 | // |
| 2723 | // |
| 2724 | |
| 2725 | |
| 2726 | |
| 2727 | |
| 2728 | |
| 2729 | module l2t_arbdat_dp_or_macro__width_1 ( |
| 2730 | din0, |
| 2731 | din1, |
| 2732 | dout); |
| 2733 | input [0:0] din0; |
| 2734 | input [0:0] din1; |
| 2735 | output [0:0] dout; |
| 2736 | |
| 2737 | |
| 2738 | |
| 2739 | |
| 2740 | |
| 2741 | |
| 2742 | or2 #(1) d0_0 ( |
| 2743 | .in0(din0[0:0]), |
| 2744 | .in1(din1[0:0]), |
| 2745 | .out(dout[0:0]) |
| 2746 | ); |
| 2747 | |
| 2748 | |
| 2749 | |
| 2750 | |
| 2751 | |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | |
| 2756 | endmodule |
| 2757 | |
| 2758 | |
| 2759 | |
| 2760 | |
| 2761 | |
| 2762 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2763 | // also for pass-gate with decoder |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | |
| 2769 | // any PARAMS parms go into naming of macro |
| 2770 | |
| 2771 | module l2t_arbdat_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c__width_1 ( |
| 2772 | din0, |
| 2773 | sel0, |
| 2774 | din1, |
| 2775 | sel1, |
| 2776 | dout); |
| 2777 | wire buffout0; |
| 2778 | wire buffout1; |
| 2779 | |
| 2780 | input [0:0] din0; |
| 2781 | input sel0; |
| 2782 | input [0:0] din1; |
| 2783 | input sel1; |
| 2784 | output [0:0] dout; |
| 2785 | |
| 2786 | |
| 2787 | |
| 2788 | |
| 2789 | |
| 2790 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2791 | .in0(sel0), |
| 2792 | .in1(sel1), |
| 2793 | .out0(buffout0), |
| 2794 | .out1(buffout1) |
| 2795 | ); |
| 2796 | mux2s #(1) d0_0 ( |
| 2797 | .sel0(buffout0), |
| 2798 | .sel1(buffout1), |
| 2799 | .in0(din0[0:0]), |
| 2800 | .in1(din1[0:0]), |
| 2801 | .dout(dout[0:0]) |
| 2802 | ); |
| 2803 | |
| 2804 | |
| 2805 | |
| 2806 | |
| 2807 | |
| 2808 | |
| 2809 | |
| 2810 | |
| 2811 | |
| 2812 | |
| 2813 | |
| 2814 | |
| 2815 | |
| 2816 | endmodule |
| 2817 | |
| 2818 | |
| 2819 | // |
| 2820 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 2821 | // |
| 2822 | // |
| 2823 | |
| 2824 | |
| 2825 | |
| 2826 | |
| 2827 | |
| 2828 | module l2t_arbdat_dp_cmp_macro__dcmp_8x__width_32 ( |
| 2829 | din0, |
| 2830 | din1, |
| 2831 | dout); |
| 2832 | input [31:0] din0; |
| 2833 | input [31:0] din1; |
| 2834 | output dout; |
| 2835 | |
| 2836 | |
| 2837 | |
| 2838 | |
| 2839 | |
| 2840 | |
| 2841 | cmp #(32) m0_0 ( |
| 2842 | .in0(din0[31:0]), |
| 2843 | .in1(din1[31:0]), |
| 2844 | .out(dout) |
| 2845 | ); |
| 2846 | |
| 2847 | |
| 2848 | |
| 2849 | |
| 2850 | |
| 2851 | |
| 2852 | |
| 2853 | |
| 2854 | |
| 2855 | |
| 2856 | endmodule |
| 2857 | |
| 2858 | |
| 2859 | |
| 2860 | |
| 2861 | |
| 2862 | |
| 2863 | |
| 2864 | |
| 2865 | |
| 2866 | // any PARAMS parms go into naming of macro |
| 2867 | |
| 2868 | module l2t_arbdat_dp_msff_macro__stack_38c__width_38 ( |
| 2869 | din, |
| 2870 | clk, |
| 2871 | en, |
| 2872 | se, |
| 2873 | scan_in, |
| 2874 | siclk, |
| 2875 | soclk, |
| 2876 | pce_ov, |
| 2877 | stop, |
| 2878 | dout, |
| 2879 | scan_out); |
| 2880 | wire l1clk; |
| 2881 | wire siclk_out; |
| 2882 | wire soclk_out; |
| 2883 | wire [36:0] so; |
| 2884 | |
| 2885 | input [37:0] din; |
| 2886 | |
| 2887 | |
| 2888 | input clk; |
| 2889 | input en; |
| 2890 | input se; |
| 2891 | input scan_in; |
| 2892 | input siclk; |
| 2893 | input soclk; |
| 2894 | input pce_ov; |
| 2895 | input stop; |
| 2896 | |
| 2897 | |
| 2898 | |
| 2899 | output [37:0] dout; |
| 2900 | |
| 2901 | |
| 2902 | output scan_out; |
| 2903 | |
| 2904 | |
| 2905 | |
| 2906 | |
| 2907 | cl_dp1_l1hdr_8x c0_0 ( |
| 2908 | .l2clk(clk), |
| 2909 | .pce(en), |
| 2910 | .aclk(siclk), |
| 2911 | .bclk(soclk), |
| 2912 | .l1clk(l1clk), |
| 2913 | .se(se), |
| 2914 | .pce_ov(pce_ov), |
| 2915 | .stop(stop), |
| 2916 | .siclk_out(siclk_out), |
| 2917 | .soclk_out(soclk_out) |
| 2918 | ); |
| 2919 | dff #(38) d0_0 ( |
| 2920 | .l1clk(l1clk), |
| 2921 | .siclk(siclk_out), |
| 2922 | .soclk(soclk_out), |
| 2923 | .d(din[37:0]), |
| 2924 | .si({scan_in,so[36:0]}), |
| 2925 | .so({so[36:0],scan_out}), |
| 2926 | .q(dout[37:0]) |
| 2927 | ); |
| 2928 | |
| 2929 | |
| 2930 | |
| 2931 | |
| 2932 | |
| 2933 | |
| 2934 | |
| 2935 | |
| 2936 | |
| 2937 | |
| 2938 | |
| 2939 | |
| 2940 | |
| 2941 | |
| 2942 | |
| 2943 | |
| 2944 | |
| 2945 | |
| 2946 | |
| 2947 | |
| 2948 | endmodule |
| 2949 | |
| 2950 | |
| 2951 | |
| 2952 | |
| 2953 | |
| 2954 | |
| 2955 | |
| 2956 | |
| 2957 | |
| 2958 | // |
| 2959 | // invert macro |
| 2960 | // |
| 2961 | // |
| 2962 | |
| 2963 | |
| 2964 | |
| 2965 | |
| 2966 | |
| 2967 | module l2t_arbdat_dp_inv_macro__dinv_8x__width_4 ( |
| 2968 | din, |
| 2969 | dout); |
| 2970 | input [3:0] din; |
| 2971 | output [3:0] dout; |
| 2972 | |
| 2973 | |
| 2974 | |
| 2975 | |
| 2976 | |
| 2977 | |
| 2978 | inv #(4) d0_0 ( |
| 2979 | .in(din[3:0]), |
| 2980 | .out(dout[3:0]) |
| 2981 | ); |
| 2982 | |
| 2983 | |
| 2984 | |
| 2985 | |
| 2986 | |
| 2987 | |
| 2988 | |
| 2989 | |
| 2990 | |
| 2991 | endmodule |
| 2992 | |
| 2993 | |
| 2994 | |
| 2995 | |
| 2996 | |
| 2997 | // |
| 2998 | // nor macro for ports = 2,3 |
| 2999 | // |
| 3000 | // |
| 3001 | |
| 3002 | |
| 3003 | |
| 3004 | |
| 3005 | |
| 3006 | module l2t_arbdat_dp_nor_macro__dnor_8x__width_1 ( |
| 3007 | din0, |
| 3008 | din1, |
| 3009 | dout); |
| 3010 | input [0:0] din0; |
| 3011 | input [0:0] din1; |
| 3012 | output [0:0] dout; |
| 3013 | |
| 3014 | |
| 3015 | |
| 3016 | |
| 3017 | |
| 3018 | |
| 3019 | nor2 #(1) d0_0 ( |
| 3020 | .in0(din0[0:0]), |
| 3021 | .in1(din1[0:0]), |
| 3022 | .out(dout[0:0]) |
| 3023 | ); |
| 3024 | |
| 3025 | |
| 3026 | |
| 3027 | |
| 3028 | |
| 3029 | |
| 3030 | |
| 3031 | endmodule |
| 3032 | |
| 3033 | |
| 3034 | |
| 3035 | |
| 3036 | |
| 3037 | // |
| 3038 | // and macro for ports = 2,3,4 |
| 3039 | // |
| 3040 | // |
| 3041 | |
| 3042 | |
| 3043 | |
| 3044 | |
| 3045 | |
| 3046 | module l2t_arbdat_dp_and_macro__dinv_8x__dnand_8x__width_4 ( |
| 3047 | din0, |
| 3048 | din1, |
| 3049 | dout); |
| 3050 | input [3:0] din0; |
| 3051 | input [3:0] din1; |
| 3052 | output [3:0] dout; |
| 3053 | |
| 3054 | |
| 3055 | |
| 3056 | |
| 3057 | |
| 3058 | |
| 3059 | and2 #(4) d0_0 ( |
| 3060 | .in0(din0[3:0]), |
| 3061 | .in1(din1[3:0]), |
| 3062 | .out(dout[3:0]) |
| 3063 | ); |
| 3064 | |
| 3065 | |
| 3066 | |
| 3067 | |
| 3068 | |
| 3069 | |
| 3070 | |
| 3071 | |
| 3072 | |
| 3073 | endmodule |
| 3074 | |
| 3075 | |
| 3076 | |
| 3077 | |
| 3078 | |
| 3079 | |
| 3080 | |
| 3081 | |
| 3082 | |
| 3083 | // any PARAMS parms go into naming of macro |
| 3084 | |
| 3085 | module l2t_arbdat_dp_msff_macro__dmsff_32x__stack_10c__width_10 ( |
| 3086 | din, |
| 3087 | clk, |
| 3088 | en, |
| 3089 | se, |
| 3090 | scan_in, |
| 3091 | siclk, |
| 3092 | soclk, |
| 3093 | pce_ov, |
| 3094 | stop, |
| 3095 | dout, |
| 3096 | scan_out); |
| 3097 | wire l1clk; |
| 3098 | wire siclk_out; |
| 3099 | wire soclk_out; |
| 3100 | wire [8:0] so; |
| 3101 | |
| 3102 | input [9:0] din; |
| 3103 | |
| 3104 | |
| 3105 | input clk; |
| 3106 | input en; |
| 3107 | input se; |
| 3108 | input scan_in; |
| 3109 | input siclk; |
| 3110 | input soclk; |
| 3111 | input pce_ov; |
| 3112 | input stop; |
| 3113 | |
| 3114 | |
| 3115 | |
| 3116 | output [9:0] dout; |
| 3117 | |
| 3118 | |
| 3119 | output scan_out; |
| 3120 | |
| 3121 | |
| 3122 | |
| 3123 | |
| 3124 | cl_dp1_l1hdr_8x c0_0 ( |
| 3125 | .l2clk(clk), |
| 3126 | .pce(en), |
| 3127 | .aclk(siclk), |
| 3128 | .bclk(soclk), |
| 3129 | .l1clk(l1clk), |
| 3130 | .se(se), |
| 3131 | .pce_ov(pce_ov), |
| 3132 | .stop(stop), |
| 3133 | .siclk_out(siclk_out), |
| 3134 | .soclk_out(soclk_out) |
| 3135 | ); |
| 3136 | dff #(10) d0_0 ( |
| 3137 | .l1clk(l1clk), |
| 3138 | .siclk(siclk_out), |
| 3139 | .soclk(soclk_out), |
| 3140 | .d(din[9:0]), |
| 3141 | .si({scan_in,so[8:0]}), |
| 3142 | .so({so[8:0],scan_out}), |
| 3143 | .q(dout[9:0]) |
| 3144 | ); |
| 3145 | |
| 3146 | |
| 3147 | |
| 3148 | |
| 3149 | |
| 3150 | |
| 3151 | |
| 3152 | |
| 3153 | |
| 3154 | |
| 3155 | |
| 3156 | |
| 3157 | |
| 3158 | |
| 3159 | |
| 3160 | |
| 3161 | |
| 3162 | |
| 3163 | |
| 3164 | |
| 3165 | endmodule |
| 3166 | |
| 3167 | |
| 3168 | |
| 3169 | |
| 3170 | |
| 3171 | |
| 3172 | |
| 3173 | |
| 3174 | |
| 3175 | // |
| 3176 | // nand macro for ports = 2,3,4 |
| 3177 | // |
| 3178 | // |
| 3179 | |
| 3180 | |
| 3181 | |
| 3182 | |
| 3183 | |
| 3184 | module l2t_arbdat_dp_nand_macro__dnand_16x__stack_4r__width_4 ( |
| 3185 | din0, |
| 3186 | din1, |
| 3187 | dout); |
| 3188 | input [3:0] din0; |
| 3189 | input [3:0] din1; |
| 3190 | output [3:0] dout; |
| 3191 | |
| 3192 | |
| 3193 | |
| 3194 | |
| 3195 | |
| 3196 | |
| 3197 | nand2 #(4) d0_0 ( |
| 3198 | .in0(din0[3:0]), |
| 3199 | .in1(din1[3:0]), |
| 3200 | .out(dout[3:0]) |
| 3201 | ); |
| 3202 | |
| 3203 | |
| 3204 | |
| 3205 | |
| 3206 | |
| 3207 | |
| 3208 | |
| 3209 | |
| 3210 | |
| 3211 | endmodule |
| 3212 | |
| 3213 | |
| 3214 | |
| 3215 | |
| 3216 | |
| 3217 | // |
| 3218 | // nand macro for ports = 2,3,4 |
| 3219 | // |
| 3220 | // |
| 3221 | |
| 3222 | |
| 3223 | |
| 3224 | |
| 3225 | |
| 3226 | module l2t_arbdat_dp_nand_macro__dnand_32x__stack_4r__width_4 ( |
| 3227 | din0, |
| 3228 | din1, |
| 3229 | dout); |
| 3230 | input [3:0] din0; |
| 3231 | input [3:0] din1; |
| 3232 | output [3:0] dout; |
| 3233 | |
| 3234 | |
| 3235 | |
| 3236 | |
| 3237 | |
| 3238 | |
| 3239 | nand2 #(4) d0_0 ( |
| 3240 | .in0(din0[3:0]), |
| 3241 | .in1(din1[3:0]), |
| 3242 | .out(dout[3:0]) |
| 3243 | ); |
| 3244 | |
| 3245 | |
| 3246 | |
| 3247 | |
| 3248 | |
| 3249 | |
| 3250 | |
| 3251 | |
| 3252 | |
| 3253 | endmodule |
| 3254 | |
| 3255 | |
| 3256 | |
| 3257 | |