| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_dirbuf_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2t_dirbuf_ctl ( |
| 36 | rd_en_c4, |
| 37 | wr_en_c4, |
| 38 | dir_inval_mask_c4, |
| 39 | rw_row_en_c4, |
| 40 | rw_panel_en_c4, |
| 41 | dir_rw_entry_c4, |
| 42 | lkup_row_en_c4, |
| 43 | lkup_panel_en_c4, |
| 44 | lkup_wr_data_c4, |
| 45 | dir_clear_c4, |
| 46 | ic_dc_dir, |
| 47 | arbadr_arbdp_addr4_c4, |
| 48 | arb_force_hit_c4, |
| 49 | addr_index_bit5, |
| 50 | l2t_mb0_run, |
| 51 | l2t_mb0_mask, |
| 52 | l2t_mb0_addr, |
| 53 | l2t_mb0_row_panel_en, |
| 54 | l2t_mb0_row_row_en, |
| 55 | l2t_mb0_row_lookup_en, |
| 56 | l2t_mb0_lookup_wdata, |
| 57 | l2t_mb0_row_wr_en, |
| 58 | l2t_mb0_row_rd_en, |
| 59 | l1clk, |
| 60 | scan_in, |
| 61 | scan_out, |
| 62 | dirlbf_force_hit_c4, |
| 63 | dirlbf_lkup_en_c4_buf, |
| 64 | dirlbf_inval_mask_c4_buf, |
| 65 | dirlbf_rw_dec_c4_buf, |
| 66 | dirlbf_rd_en_c4_buf, |
| 67 | dirlbf_wr_en_c4_buf, |
| 68 | dirlbf_rw_entry_c4_buf, |
| 69 | dirlbf_lkup_wr_data_c4_buf, |
| 70 | dirlbf_dir_clear_c4_buf, |
| 71 | aclk, |
| 72 | bclk); |
| 73 | wire siclk; |
| 74 | wire soclk; |
| 75 | wire ff_l2t_mb0_run_r1_scanin; |
| 76 | wire ff_l2t_mb0_run_r1_scanout; |
| 77 | wire l2t_mb0_run_r1; |
| 78 | wire mb0_row_row_en; |
| 79 | wire dirlbf_force_hit_c41; |
| 80 | wire [5:0] rw_index; |
| 81 | wire l2t_mb0_row_wr_en_qual; |
| 82 | wire l2t_mb0_row_rd_en_qual; |
| 83 | wire address_bit4_0; |
| 84 | wire ic_address_bit4; |
| 85 | wire address_bit4_1; |
| 86 | wire dc_address_bit4; |
| 87 | wire address_bit4; |
| 88 | wire sel_address_bit4; |
| 89 | wire dir_wr_par_c4; |
| 90 | wire cam_row_select; |
| 91 | wire rw_row_select; |
| 92 | wire [3:0] dirlbf_rw_dec_c4_buf_fnl; |
| 93 | wire [3:0] dirlbf_lkup_en_c4_buf_fnl; |
| 94 | |
| 95 | |
| 96 | input rd_en_c4; |
| 97 | input wr_en_c4; |
| 98 | input [7:0] dir_inval_mask_c4; |
| 99 | input [1:0] rw_row_en_c4; |
| 100 | input [3:0] rw_panel_en_c4; |
| 101 | input [5:0] dir_rw_entry_c4; // BS and SR 11/18/03 Reverse Directory change |
| 102 | input [1:0] lkup_row_en_c4; // qualified already |
| 103 | input [3:0] lkup_panel_en_c4; // qualified already |
| 104 | input [14:0] lkup_wr_data_c4; // BS and SR 11/18/03 Reverse Directory change |
| 105 | input dir_clear_c4; |
| 106 | input ic_dc_dir; |
| 107 | input arbadr_arbdp_addr4_c4; |
| 108 | input arb_force_hit_c4; |
| 109 | input addr_index_bit5; |
| 110 | |
| 111 | input l2t_mb0_run; |
| 112 | input [7:0] l2t_mb0_mask; |
| 113 | input [5:0] l2t_mb0_addr; |
| 114 | input [3:0] l2t_mb0_row_panel_en; |
| 115 | input l2t_mb0_row_row_en; |
| 116 | input [3:0] l2t_mb0_row_lookup_en; |
| 117 | input [15:0] l2t_mb0_lookup_wdata; |
| 118 | input l2t_mb0_row_wr_en; |
| 119 | input l2t_mb0_row_rd_en; |
| 120 | input l1clk; |
| 121 | input scan_in; |
| 122 | output scan_out; |
| 123 | |
| 124 | output dirlbf_force_hit_c4; |
| 125 | output [3:0] dirlbf_lkup_en_c4_buf ; |
| 126 | output [7:0] dirlbf_inval_mask_c4_buf ; |
| 127 | output [3:0] dirlbf_rw_dec_c4_buf; |
| 128 | output dirlbf_rd_en_c4_buf ; |
| 129 | output dirlbf_wr_en_c4_buf ; |
| 130 | output [5:0] dirlbf_rw_entry_c4_buf; // BS and SR 11/18/03 Reverse Directory change |
| 131 | output [15:0] dirlbf_lkup_wr_data_c4_buf; // 14(top) to 0(bottom) |
| 132 | output dirlbf_dir_clear_c4_buf; |
| 133 | |
| 134 | |
| 135 | input aclk; |
| 136 | input bclk; |
| 137 | |
| 138 | assign siclk = aclk; |
| 139 | assign soclk = bclk; |
| 140 | |
| 141 | // |
| 142 | // Muxing of MBIST and functional signals |
| 143 | // |
| 144 | |
| 145 | l2t_dirbuf_ctl_msff_ctl_macro__width_1 ff_l2t_mb0_run_r1 |
| 146 | ( |
| 147 | .din(l2t_mb0_run), |
| 148 | .l1clk(l1clk), |
| 149 | //.en(1'b1), |
| 150 | .scan_in(ff_l2t_mb0_run_r1_scanin), |
| 151 | .scan_out(ff_l2t_mb0_run_r1_scanout), |
| 152 | .dout(l2t_mb0_run_r1), |
| 153 | .siclk(siclk), |
| 154 | .soclk(soclk) |
| 155 | ); |
| 156 | |
| 157 | |
| 158 | |
| 159 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_mb0_row_row_en_wdata |
| 160 | ( |
| 161 | .dout ({dirlbf_force_hit_c4,mb0_row_row_en}), |
| 162 | .din0 ({1'b0,l2t_mb0_row_row_en}), |
| 163 | .din1 ({dirlbf_force_hit_c41,1'b0}), |
| 164 | .sel0 (l2t_mb0_run_r1), |
| 165 | .sel1 (~l2t_mb0_run_r1) |
| 166 | ); |
| 167 | |
| 168 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_dirlbf_inval_mask_c4_buf |
| 169 | ( |
| 170 | .dout (dirlbf_inval_mask_c4_buf[7:0]), |
| 171 | .din0 (dir_inval_mask_c4[7:0]), |
| 172 | .din1 (l2t_mb0_mask[7:0]), |
| 173 | .sel0 (~l2t_mb0_run_r1), |
| 174 | .sel1 (l2t_mb0_run_r1) |
| 175 | ); |
| 176 | |
| 177 | |
| 178 | |
| 179 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 mux_rw_index |
| 180 | ( |
| 181 | .dout (rw_index[5:0]), |
| 182 | .din0 ({addr_index_bit5,dir_rw_entry_c4[4:0]}), |
| 183 | .din1 (dir_rw_entry_c4[5:0]), |
| 184 | .sel0 (~dirlbf_wr_en_c4_buf), |
| 185 | .sel1 (dirlbf_wr_en_c4_buf) |
| 186 | ); |
| 187 | |
| 188 | |
| 189 | assign l2t_mb0_row_wr_en_qual = l2t_mb0_row_wr_en & l2t_mb0_row_row_en; |
| 190 | assign l2t_mb0_row_rd_en_qual = l2t_mb0_row_rd_en & l2t_mb0_row_row_en; |
| 191 | |
| 192 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_dirlbf_rd_wr_entry_c4_buf |
| 193 | ( |
| 194 | .dout ({dirlbf_rw_entry_c4_buf[5:0],dirlbf_wr_en_c4_buf,dirlbf_rd_en_c4_buf}), |
| 195 | .din0 ({rw_index[5:0],wr_en_c4,rd_en_c4}), |
| 196 | .din1 ({l2t_mb0_addr[5:0],l2t_mb0_row_wr_en_qual,l2t_mb0_row_rd_en_qual}), |
| 197 | .sel0 (~l2t_mb0_run_r1), |
| 198 | .sel1 (l2t_mb0_run_r1) |
| 199 | ); |
| 200 | |
| 201 | |
| 202 | |
| 203 | assign address_bit4_0 = ~(ic_address_bit4 & ic_dc_dir); |
| 204 | assign address_bit4_1 = ~(dc_address_bit4 & ~ic_dc_dir); |
| 205 | assign address_bit4 = ~(address_bit4_0 & address_bit4_1); |
| 206 | |
| 207 | assign dirlbf_force_hit_c41 = arb_force_hit_c4 | (lkup_row_en_c4[0] & lkup_row_en_c4[1]); |
| 208 | |
| 209 | |
| 210 | assign sel_address_bit4 = (dirlbf_wr_en_c4_buf | dirlbf_rd_en_c4_buf); |
| 211 | |
| 212 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_address_bit4 |
| 213 | ( |
| 214 | .dout ({dc_address_bit4,ic_address_bit4}), |
| 215 | .din0 ({dir_rw_entry_c4[5],dir_rw_entry_c4[5]}), |
| 216 | .din1 ({lkup_row_en_c4[1],arbadr_arbdp_addr4_c4}), |
| 217 | .sel0 (sel_address_bit4), |
| 218 | .sel1 (~sel_address_bit4) |
| 219 | ); |
| 220 | |
| 221 | |
| 222 | //prty_macro prty_dir_wr_par_c4 (width=16) |
| 223 | // ( |
| 224 | // .dout (dir_wr_par_c4), |
| 225 | // .din ({1'b0,address_bit4,lkup_wr_data_c4[13:0]}) |
| 226 | // ); |
| 227 | |
| 228 | assign dir_wr_par_c4 = ^(lkup_wr_data_c4[13:0]) ^ address_bit4; |
| 229 | |
| 230 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_dirlbf_lkup_wr_data_c4_buf |
| 231 | ( |
| 232 | .dout (dirlbf_lkup_wr_data_c4_buf[15:0]), |
| 233 | .din0 ({lkup_wr_data_c4[14],dir_wr_par_c4,address_bit4,lkup_wr_data_c4[12:0]}), |
| 234 | .din1 (l2t_mb0_lookup_wdata[15:0]), |
| 235 | .sel0 (~l2t_mb0_run_r1), |
| 236 | .sel1 (l2t_mb0_run_r1) |
| 237 | ); |
| 238 | |
| 239 | |
| 240 | |
| 241 | assign cam_row_select = |(lkup_row_en_c4[1:0]); |
| 242 | assign rw_row_select = ((|(rw_row_en_c4[1:0])) | mb0_row_row_en); |
| 243 | assign dirlbf_dir_clear_c4_buf = dir_clear_c4; |
| 244 | |
| 245 | assign dirlbf_rw_dec_c4_buf_fnl[3:0] = rw_panel_en_c4[3:0] & {4{rw_row_select}}; |
| 246 | |
| 247 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_dirlbf_rw_dec_c4_buf |
| 248 | ( |
| 249 | .dout (dirlbf_rw_dec_c4_buf[3:0]), |
| 250 | .din0 (dirlbf_rw_dec_c4_buf_fnl[3:0]), |
| 251 | .din1 (l2t_mb0_row_panel_en), |
| 252 | .sel0 (~l2t_mb0_run_r1), |
| 253 | .sel1 (l2t_mb0_run_r1) |
| 254 | ); |
| 255 | |
| 256 | |
| 257 | |
| 258 | assign dirlbf_lkup_en_c4_buf_fnl[3:0] = lkup_panel_en_c4[3:0] & {4{cam_row_select}}; |
| 259 | |
| 260 | //assign mbist_lookup_en[3:0] = l2t_mb0_row_lookup_en[3:0] & {4{l2t_mb0_row_row_en}}; |
| 261 | |
| 262 | l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_dirlbf_lkup_en_c4_buf |
| 263 | ( |
| 264 | .dout (dirlbf_lkup_en_c4_buf[3:0]), |
| 265 | .din0 (dirlbf_lkup_en_c4_buf_fnl[3:0]), |
| 266 | .din1 (l2t_mb0_row_lookup_en[3:0]), |
| 267 | .sel0 (~l2t_mb0_run_r1), |
| 268 | .sel1 (l2t_mb0_run_r1) |
| 269 | ); |
| 270 | |
| 271 | |
| 272 | |
| 273 | |
| 274 | // fixscan start: |
| 275 | assign ff_l2t_mb0_run_r1_scanin = scan_in ; |
| 276 | assign scan_out = ff_l2t_mb0_run_r1_scanout; |
| 277 | // fixscan end: |
| 278 | endmodule |
| 279 | |
| 280 | |
| 281 | |
| 282 | |
| 283 | |
| 284 | |
| 285 | // any PARAMS parms go into naming of macro |
| 286 | |
| 287 | module l2t_dirbuf_ctl_msff_ctl_macro__width_1 ( |
| 288 | din, |
| 289 | l1clk, |
| 290 | scan_in, |
| 291 | siclk, |
| 292 | soclk, |
| 293 | dout, |
| 294 | scan_out); |
| 295 | wire [0:0] fdin; |
| 296 | |
| 297 | input [0:0] din; |
| 298 | input l1clk; |
| 299 | input scan_in; |
| 300 | |
| 301 | |
| 302 | input siclk; |
| 303 | input soclk; |
| 304 | |
| 305 | output [0:0] dout; |
| 306 | output scan_out; |
| 307 | assign fdin[0:0] = din[0:0]; |
| 308 | |
| 309 | |
| 310 | |
| 311 | |
| 312 | |
| 313 | |
| 314 | dff #(1) d0_0 ( |
| 315 | .l1clk(l1clk), |
| 316 | .siclk(siclk), |
| 317 | .soclk(soclk), |
| 318 | .d(fdin[0:0]), |
| 319 | .si(scan_in), |
| 320 | .so(scan_out), |
| 321 | .q(dout[0:0]) |
| 322 | ); |
| 323 | |
| 324 | |
| 325 | |
| 326 | |
| 327 | |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | |
| 333 | |
| 334 | |
| 335 | endmodule |
| 336 | |
| 337 | |
| 338 | |
| 339 | |
| 340 | |
| 341 | |
| 342 | |
| 343 | |
| 344 | |
| 345 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 346 | // also for pass-gate with decoder |
| 347 | |
| 348 | |
| 349 | |
| 350 | |
| 351 | |
| 352 | // any PARAMS parms go into naming of macro |
| 353 | |
| 354 | module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 ( |
| 355 | din0, |
| 356 | sel0, |
| 357 | din1, |
| 358 | sel1, |
| 359 | dout); |
| 360 | input [1:0] din0; |
| 361 | input sel0; |
| 362 | input [1:0] din1; |
| 363 | input sel1; |
| 364 | output [1:0] dout; |
| 365 | |
| 366 | |
| 367 | |
| 368 | |
| 369 | |
| 370 | assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) | |
| 371 | ( {2{sel1}} & din1[1:0]); |
| 372 | |
| 373 | |
| 374 | |
| 375 | |
| 376 | |
| 377 | endmodule |
| 378 | |
| 379 | |
| 380 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 381 | // also for pass-gate with decoder |
| 382 | |
| 383 | |
| 384 | |
| 385 | |
| 386 | |
| 387 | // any PARAMS parms go into naming of macro |
| 388 | |
| 389 | module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 ( |
| 390 | din0, |
| 391 | sel0, |
| 392 | din1, |
| 393 | sel1, |
| 394 | dout); |
| 395 | input [7:0] din0; |
| 396 | input sel0; |
| 397 | input [7:0] din1; |
| 398 | input sel1; |
| 399 | output [7:0] dout; |
| 400 | |
| 401 | |
| 402 | |
| 403 | |
| 404 | |
| 405 | assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) | |
| 406 | ( {8{sel1}} & din1[7:0]); |
| 407 | |
| 408 | |
| 409 | |
| 410 | |
| 411 | |
| 412 | endmodule |
| 413 | |
| 414 | |
| 415 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 416 | // also for pass-gate with decoder |
| 417 | |
| 418 | |
| 419 | |
| 420 | |
| 421 | |
| 422 | // any PARAMS parms go into naming of macro |
| 423 | |
| 424 | module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 ( |
| 425 | din0, |
| 426 | sel0, |
| 427 | din1, |
| 428 | sel1, |
| 429 | dout); |
| 430 | input [5:0] din0; |
| 431 | input sel0; |
| 432 | input [5:0] din1; |
| 433 | input sel1; |
| 434 | output [5:0] dout; |
| 435 | |
| 436 | |
| 437 | |
| 438 | |
| 439 | |
| 440 | assign dout[5:0] = ( {6{sel0}} & din0[5:0] ) | |
| 441 | ( {6{sel1}} & din1[5:0]); |
| 442 | |
| 443 | |
| 444 | |
| 445 | |
| 446 | |
| 447 | endmodule |
| 448 | |
| 449 | |
| 450 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 451 | // also for pass-gate with decoder |
| 452 | |
| 453 | |
| 454 | |
| 455 | |
| 456 | |
| 457 | // any PARAMS parms go into naming of macro |
| 458 | |
| 459 | module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 ( |
| 460 | din0, |
| 461 | sel0, |
| 462 | din1, |
| 463 | sel1, |
| 464 | dout); |
| 465 | input [15:0] din0; |
| 466 | input sel0; |
| 467 | input [15:0] din1; |
| 468 | input sel1; |
| 469 | output [15:0] dout; |
| 470 | |
| 471 | |
| 472 | |
| 473 | |
| 474 | |
| 475 | assign dout[15:0] = ( {16{sel0}} & din0[15:0] ) | |
| 476 | ( {16{sel1}} & din1[15:0]); |
| 477 | |
| 478 | |
| 479 | |
| 480 | |
| 481 | |
| 482 | endmodule |
| 483 | |
| 484 | |
| 485 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 486 | // also for pass-gate with decoder |
| 487 | |
| 488 | |
| 489 | |
| 490 | |
| 491 | |
| 492 | // any PARAMS parms go into naming of macro |
| 493 | |
| 494 | module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 ( |
| 495 | din0, |
| 496 | sel0, |
| 497 | din1, |
| 498 | sel1, |
| 499 | dout); |
| 500 | input [3:0] din0; |
| 501 | input sel0; |
| 502 | input [3:0] din1; |
| 503 | input sel1; |
| 504 | output [3:0] dout; |
| 505 | |
| 506 | |
| 507 | |
| 508 | |
| 509 | |
| 510 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 511 | ( {4{sel1}} & din1[3:0]); |
| 512 | |
| 513 | |
| 514 | |
| 515 | |
| 516 | |
| 517 | endmodule |
| 518 | |