| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_dmo_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2t_dmo_dp ( |
| 36 | tcu_l2t_coresel, |
| 37 | l2t_tcu_dmo_out_prev, |
| 38 | mbist_dmo_data_out, |
| 39 | l2clk, |
| 40 | tcu_clk_stop, |
| 41 | tcu_pce_ov, |
| 42 | tcu_aclk, |
| 43 | tcu_bclk, |
| 44 | tcu_scan_en, |
| 45 | scan_in, |
| 46 | scan_out, |
| 47 | l2t_tcu_dmo_out, |
| 48 | io_cmp_sync_en, |
| 49 | tcu_l2t_shscan_clk_stop, |
| 50 | tcu_l2t_shscan_clk_stop_d2); |
| 51 | wire stop; |
| 52 | wire pce_ov; |
| 53 | wire siclk; |
| 54 | wire soclk; |
| 55 | wire se; |
| 56 | wire [38:0] l2t_tcu_dmo_out_unreg; |
| 57 | wire ff_dmo_data_scanin; |
| 58 | wire ff_dmo_data_scanout; |
| 59 | wire ff_dmo_data_1_scanin; |
| 60 | wire ff_dmo_data_1_scanout; |
| 61 | wire io_cmp_sync_en_r1; |
| 62 | wire ff_shadow_scan_clk_stop_scanin; |
| 63 | wire ff_shadow_scan_clk_stop_scanout; |
| 64 | |
| 65 | |
| 66 | |
| 67 | input tcu_l2t_coresel; // 1= select current bank dmo out |
| 68 | input [38:0] l2t_tcu_dmo_out_prev; // dmo output from prev bank |
| 69 | //input tcu_l2t_tag_or_data_sel; |
| 70 | //input [38:0] decc_ret_diag_data_c7; // dmo data tag or data data |
| 71 | //input [27:0] tagd_evict_tag_c3; // dmo data tag or data data |
| 72 | input [38:0] mbist_dmo_data_out; |
| 73 | |
| 74 | input l2clk; |
| 75 | input tcu_clk_stop; |
| 76 | input tcu_pce_ov; |
| 77 | input tcu_aclk; |
| 78 | input tcu_bclk; |
| 79 | input tcu_scan_en; |
| 80 | input scan_in; |
| 81 | output scan_out; |
| 82 | output [38:0] l2t_tcu_dmo_out; // dmo output from this bank |
| 83 | |
| 84 | input io_cmp_sync_en; |
| 85 | input tcu_l2t_shscan_clk_stop; |
| 86 | output tcu_l2t_shscan_clk_stop_d2; |
| 87 | |
| 88 | assign stop = tcu_clk_stop; |
| 89 | assign pce_ov = tcu_pce_ov; |
| 90 | assign siclk = tcu_aclk; |
| 91 | assign soclk = tcu_bclk; |
| 92 | assign se = tcu_scan_en; |
| 93 | |
| 94 | //mux_macro mux_data_tag_dmo_data (width=39,ports=2,mux=aope,stack=39c) |
| 95 | // ( |
| 96 | // .dout (mbist_dmo_data_out[38:0]), |
| 97 | // .din0 ({11'b0,tagd_evict_tag_c3[27:0]}), |
| 98 | // .din1 (decc_ret_diag_data_c7[38:0]), |
| 99 | // .sel0 (tcu_l2t_tag_or_data_sel) |
| 100 | // ); |
| 101 | // |
| 102 | |
| 103 | |
| 104 | l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_19 mux_dmo_data |
| 105 | ( |
| 106 | .dout (l2t_tcu_dmo_out_unreg[18:0]), |
| 107 | .din0 (l2t_tcu_dmo_out_prev[18:0]), |
| 108 | .din1 (mbist_dmo_data_out[18:0]), |
| 109 | .sel0 (tcu_l2t_coresel) |
| 110 | ); |
| 111 | |
| 112 | l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_20 mux_dmo_data_1 |
| 113 | ( |
| 114 | .dout (l2t_tcu_dmo_out_unreg[38:19]), |
| 115 | .din0 (l2t_tcu_dmo_out_prev[38:19]), |
| 116 | .din1 (mbist_dmo_data_out[38:19]), |
| 117 | .sel0 (tcu_l2t_coresel) |
| 118 | ); |
| 119 | |
| 120 | |
| 121 | |
| 122 | |
| 123 | l2t_msff_macro__dmsff_32x__stack_20r__width_19 ff_dmo_data |
| 124 | ( |
| 125 | .scan_in(ff_dmo_data_scanin), |
| 126 | .scan_out(ff_dmo_data_scanout), |
| 127 | .dout (l2t_tcu_dmo_out[18:0]), |
| 128 | .din (l2t_tcu_dmo_out_unreg[18:0]), |
| 129 | .clk (l2clk), |
| 130 | .en (1'b1), |
| 131 | .se(se), |
| 132 | .siclk(siclk), |
| 133 | .soclk(soclk), |
| 134 | .pce_ov(pce_ov), |
| 135 | .stop(stop) |
| 136 | ); |
| 137 | |
| 138 | |
| 139 | |
| 140 | l2t_msff_macro__dmsff_32x__stack_22r__width_21 ff_dmo_data_1 |
| 141 | ( |
| 142 | .scan_in(ff_dmo_data_1_scanin), |
| 143 | .scan_out(ff_dmo_data_1_scanout), |
| 144 | .dout ({io_cmp_sync_en_r1,l2t_tcu_dmo_out[38:19]}), |
| 145 | .din ({io_cmp_sync_en,l2t_tcu_dmo_out_unreg[38:19]}), |
| 146 | .clk (l2clk), |
| 147 | .en (1'b1), |
| 148 | .se(se), |
| 149 | .siclk(siclk), |
| 150 | .soclk(soclk), |
| 151 | .pce_ov(pce_ov), |
| 152 | .stop(stop) |
| 153 | ); |
| 154 | |
| 155 | |
| 156 | l2t_msff_macro__dmsff_32x__stack_2r__width_1 ff_shadow_scan_clk_stop |
| 157 | ( |
| 158 | .scan_in(ff_shadow_scan_clk_stop_scanin), |
| 159 | .scan_out(ff_shadow_scan_clk_stop_scanout), |
| 160 | .dout (tcu_l2t_shscan_clk_stop_d2), |
| 161 | .din (tcu_l2t_shscan_clk_stop), |
| 162 | .clk (l2clk), |
| 163 | .en (io_cmp_sync_en_r1), |
| 164 | .se(se), |
| 165 | .siclk(siclk), |
| 166 | .soclk(soclk), |
| 167 | .pce_ov(pce_ov), |
| 168 | .stop(stop) |
| 169 | ); |
| 170 | |
| 171 | |
| 172 | |
| 173 | // fixscan start: |
| 174 | assign ff_dmo_data_scanin = scan_in ; |
| 175 | assign ff_dmo_data_1_scanin = ff_dmo_data_scanout ; |
| 176 | assign ff_shadow_scan_clk_stop_scanin = ff_dmo_data_1_scanout ; |
| 177 | assign scan_out = ff_shadow_scan_clk_stop_scanout; |
| 178 | // fixscan end: |
| 179 | endmodule |
| 180 | |
| 181 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 182 | // also for pass-gate with decoder |
| 183 | |
| 184 | |
| 185 | // any PARAMS parms go into naming of macro |
| 186 | |
| 187 | module l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_19 ( |
| 188 | din0, |
| 189 | din1, |
| 190 | sel0, |
| 191 | dout); |
| 192 | wire psel0; |
| 193 | wire psel1; |
| 194 | |
| 195 | input [18:0] din0; |
| 196 | input [18:0] din1; |
| 197 | input sel0; |
| 198 | output [18:0] dout; |
| 199 | |
| 200 | |
| 201 | |
| 202 | |
| 203 | |
| 204 | cl_dp1_penc2_8x c0_0 ( |
| 205 | .sel0(sel0), |
| 206 | .psel0(psel0), |
| 207 | .psel1(psel1) |
| 208 | ); |
| 209 | |
| 210 | mux2s #(19) d0_0 ( |
| 211 | .sel0(psel0), |
| 212 | .sel1(psel1), |
| 213 | .in0(din0[18:0]), |
| 214 | .in1(din1[18:0]), |
| 215 | .dout(dout[18:0]) |
| 216 | ); |
| 217 | |
| 218 | |
| 219 | |
| 220 | |
| 221 | |
| 222 | |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | |
| 228 | |
| 229 | |
| 230 | endmodule |
| 231 | |
| 232 | |
| 233 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 234 | // also for pass-gate with decoder |
| 235 | |
| 236 | |
| 237 | // any PARAMS parms go into naming of macro |
| 238 | |
| 239 | module l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_20 ( |
| 240 | din0, |
| 241 | din1, |
| 242 | sel0, |
| 243 | dout); |
| 244 | wire psel0; |
| 245 | wire psel1; |
| 246 | |
| 247 | input [19:0] din0; |
| 248 | input [19:0] din1; |
| 249 | input sel0; |
| 250 | output [19:0] dout; |
| 251 | |
| 252 | |
| 253 | |
| 254 | |
| 255 | |
| 256 | cl_dp1_penc2_8x c0_0 ( |
| 257 | .sel0(sel0), |
| 258 | .psel0(psel0), |
| 259 | .psel1(psel1) |
| 260 | ); |
| 261 | |
| 262 | mux2s #(20) d0_0 ( |
| 263 | .sel0(psel0), |
| 264 | .sel1(psel1), |
| 265 | .in0(din0[19:0]), |
| 266 | .in1(din1[19:0]), |
| 267 | .dout(dout[19:0]) |
| 268 | ); |
| 269 | |
| 270 | |
| 271 | |
| 272 | |
| 273 | |
| 274 | |
| 275 | |
| 276 | |
| 277 | |
| 278 | |
| 279 | |
| 280 | |
| 281 | |
| 282 | endmodule |
| 283 | |
| 284 | |
| 285 | |
| 286 | |
| 287 | // any PARAMS parms go into naming of macro |
| 288 | |
| 289 | module l2t_msff_macro__dmsff_32x__stack_20r__width_19 ( |
| 290 | din, |
| 291 | clk, |
| 292 | en, |
| 293 | se, |
| 294 | scan_in, |
| 295 | siclk, |
| 296 | soclk, |
| 297 | pce_ov, |
| 298 | stop, |
| 299 | dout, |
| 300 | scan_out); |
| 301 | wire l1clk; |
| 302 | wire siclk_out; |
| 303 | wire soclk_out; |
| 304 | wire [17:0] so; |
| 305 | |
| 306 | input [18:0] din; |
| 307 | |
| 308 | |
| 309 | input clk; |
| 310 | input en; |
| 311 | input se; |
| 312 | input scan_in; |
| 313 | input siclk; |
| 314 | input soclk; |
| 315 | input pce_ov; |
| 316 | input stop; |
| 317 | |
| 318 | |
| 319 | |
| 320 | output [18:0] dout; |
| 321 | |
| 322 | |
| 323 | output scan_out; |
| 324 | |
| 325 | |
| 326 | |
| 327 | |
| 328 | cl_dp1_l1hdr_8x c0_0 ( |
| 329 | .l2clk(clk), |
| 330 | .pce(en), |
| 331 | .aclk(siclk), |
| 332 | .bclk(soclk), |
| 333 | .l1clk(l1clk), |
| 334 | .se(se), |
| 335 | .pce_ov(pce_ov), |
| 336 | .stop(stop), |
| 337 | .siclk_out(siclk_out), |
| 338 | .soclk_out(soclk_out) |
| 339 | ); |
| 340 | dff #(19) d0_0 ( |
| 341 | .l1clk(l1clk), |
| 342 | .siclk(siclk_out), |
| 343 | .soclk(soclk_out), |
| 344 | .d(din[18:0]), |
| 345 | .si({scan_in,so[17:0]}), |
| 346 | .so({so[17:0],scan_out}), |
| 347 | .q(dout[18:0]) |
| 348 | ); |
| 349 | |
| 350 | |
| 351 | |
| 352 | |
| 353 | |
| 354 | |
| 355 | |
| 356 | |
| 357 | |
| 358 | |
| 359 | |
| 360 | |
| 361 | |
| 362 | |
| 363 | |
| 364 | |
| 365 | |
| 366 | |
| 367 | |
| 368 | |
| 369 | endmodule |
| 370 | |
| 371 | |
| 372 | |
| 373 | |
| 374 | // any PARAMS parms go into naming of macro |
| 375 | |
| 376 | module l2t_msff_macro__dmsff_32x__stack_22r__width_21 ( |
| 377 | din, |
| 378 | clk, |
| 379 | en, |
| 380 | se, |
| 381 | scan_in, |
| 382 | siclk, |
| 383 | soclk, |
| 384 | pce_ov, |
| 385 | stop, |
| 386 | dout, |
| 387 | scan_out); |
| 388 | wire l1clk; |
| 389 | wire siclk_out; |
| 390 | wire soclk_out; |
| 391 | wire [19:0] so; |
| 392 | |
| 393 | input [20:0] din; |
| 394 | |
| 395 | |
| 396 | input clk; |
| 397 | input en; |
| 398 | input se; |
| 399 | input scan_in; |
| 400 | input siclk; |
| 401 | input soclk; |
| 402 | input pce_ov; |
| 403 | input stop; |
| 404 | |
| 405 | |
| 406 | |
| 407 | output [20:0] dout; |
| 408 | |
| 409 | |
| 410 | output scan_out; |
| 411 | |
| 412 | |
| 413 | |
| 414 | |
| 415 | cl_dp1_l1hdr_8x c0_0 ( |
| 416 | .l2clk(clk), |
| 417 | .pce(en), |
| 418 | .aclk(siclk), |
| 419 | .bclk(soclk), |
| 420 | .l1clk(l1clk), |
| 421 | .se(se), |
| 422 | .pce_ov(pce_ov), |
| 423 | .stop(stop), |
| 424 | .siclk_out(siclk_out), |
| 425 | .soclk_out(soclk_out) |
| 426 | ); |
| 427 | dff #(21) d0_0 ( |
| 428 | .l1clk(l1clk), |
| 429 | .siclk(siclk_out), |
| 430 | .soclk(soclk_out), |
| 431 | .d(din[20:0]), |
| 432 | .si({scan_in,so[19:0]}), |
| 433 | .so({so[19:0],scan_out}), |
| 434 | .q(dout[20:0]) |
| 435 | ); |
| 436 | |
| 437 | |
| 438 | |
| 439 | |
| 440 | |
| 441 | |
| 442 | |
| 443 | |
| 444 | |
| 445 | |
| 446 | |
| 447 | |
| 448 | |
| 449 | |
| 450 | |
| 451 | |
| 452 | |
| 453 | |
| 454 | |
| 455 | |
| 456 | endmodule |
| 457 | |
| 458 | |
| 459 | |
| 460 | |
| 461 | |
| 462 | |
| 463 | |
| 464 | |
| 465 | // any PARAMS parms go into naming of macro |
| 466 | |
| 467 | module l2t_msff_macro__dmsff_32x__stack_2r__width_1 ( |
| 468 | din, |
| 469 | clk, |
| 470 | en, |
| 471 | se, |
| 472 | scan_in, |
| 473 | siclk, |
| 474 | soclk, |
| 475 | pce_ov, |
| 476 | stop, |
| 477 | dout, |
| 478 | scan_out); |
| 479 | wire l1clk; |
| 480 | wire siclk_out; |
| 481 | wire soclk_out; |
| 482 | |
| 483 | input [0:0] din; |
| 484 | |
| 485 | |
| 486 | input clk; |
| 487 | input en; |
| 488 | input se; |
| 489 | input scan_in; |
| 490 | input siclk; |
| 491 | input soclk; |
| 492 | input pce_ov; |
| 493 | input stop; |
| 494 | |
| 495 | |
| 496 | |
| 497 | output [0:0] dout; |
| 498 | |
| 499 | |
| 500 | output scan_out; |
| 501 | |
| 502 | |
| 503 | |
| 504 | |
| 505 | cl_dp1_l1hdr_8x c0_0 ( |
| 506 | .l2clk(clk), |
| 507 | .pce(en), |
| 508 | .aclk(siclk), |
| 509 | .bclk(soclk), |
| 510 | .l1clk(l1clk), |
| 511 | .se(se), |
| 512 | .pce_ov(pce_ov), |
| 513 | .stop(stop), |
| 514 | .siclk_out(siclk_out), |
| 515 | .soclk_out(soclk_out) |
| 516 | ); |
| 517 | dff #(1) d0_0 ( |
| 518 | .l1clk(l1clk), |
| 519 | .siclk(siclk_out), |
| 520 | .soclk(soclk_out), |
| 521 | .d(din[0:0]), |
| 522 | .si(scan_in), |
| 523 | .so(scan_out), |
| 524 | .q(dout[0:0]) |
| 525 | ); |
| 526 | |
| 527 | |
| 528 | |
| 529 | |
| 530 | |
| 531 | |
| 532 | |
| 533 | |
| 534 | |
| 535 | |
| 536 | |
| 537 | |
| 538 | |
| 539 | |
| 540 | |
| 541 | |
| 542 | |
| 543 | |
| 544 | |
| 545 | |
| 546 | endmodule |
| 547 | |
| 548 | |
| 549 | |