| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_filbuf_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define ADDR_MAP_HI 39 |
| 36 | `define ADDR_MAP_LO 32 |
| 37 | `define IO_ADDR_BIT 39 |
| 38 | |
| 39 | // CMP space |
| 40 | `define DRAM_DATA_LO 8'h00 |
| 41 | `define DRAM_DATA_HI 8'h7f |
| 42 | |
| 43 | // IOP space |
| 44 | `define JBUS1 8'h80 |
| 45 | `define HASH_TBL_NRAM_CSR 8'h81 |
| 46 | `define RESERVED_1 8'h82 |
| 47 | `define ENET_MAC_CSR 8'h83 |
| 48 | `define ENET_ING_CSR 8'h84 |
| 49 | `define ENET_EGR_CMD_CSR 8'h85 |
| 50 | `define ENET_EGR_DP_CSR 8'h86 |
| 51 | `define RESERVED_2_LO 8'h87 |
| 52 | `define RESERVED_2_HI 8'h92 |
| 53 | `define BSC_CSR 8'h93 |
| 54 | `define RESERVED_3 8'h94 |
| 55 | `define RAND_GEN_CSR 8'h95 |
| 56 | `define CLOCK_UNIT_CSR 8'h96 |
| 57 | `define DRAM_CSR 8'h97 |
| 58 | `define IOB_MAN_CSR 8'h98 |
| 59 | `define TAP_CSR 8'h99 |
| 60 | `define RESERVED_4_L0 8'h9a |
| 61 | `define RESERVED_4_HI 8'h9d |
| 62 | `define CPU_ASI 8'h9e |
| 63 | `define IOB_INT_CSR 8'h9f |
| 64 | |
| 65 | // L2 space |
| 66 | `define L2C_CSR_LO 8'ha0 |
| 67 | `define L2C_CSR_HI 8'hbf |
| 68 | |
| 69 | // More IOP space |
| 70 | `define JBUS2_LO 8'hc0 |
| 71 | `define JBUS2_HI 8'hfe |
| 72 | `define SPI_CSR 8'hff |
| 73 | |
| 74 | |
| 75 | //Cache Crossbar Width and Field Defines |
| 76 | //====================================== |
| 77 | `define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change |
| 78 | `define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change |
| 79 | `define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change |
| 80 | `define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change |
| 81 | `define CPX_WIDTH11 134 |
| 82 | `define CPX_WIDTH11c 134c |
| 83 | `define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change |
| 84 | |
| 85 | `define PCX_VLD 123 //PCX packet valid |
| 86 | `define PCX_RQ_HI 122 //PCX request type field |
| 87 | `define PCX_RQ_LO 118 |
| 88 | `define PCX_NC 117 //PCX non-cacheable bit |
| 89 | `define PCX_R 117 //PCX read/!write bit |
| 90 | `define PCX_CP_HI 116 //PCX cpu_id field |
| 91 | `define PCX_CP_LO 114 |
| 92 | `define PCX_TH_HI 113 //PCX Thread field |
| 93 | `define PCX_TH_LO 112 |
| 94 | `define PCX_BF_HI 111 //PCX buffer id field |
| 95 | `define PCX_INVALL 111 |
| 96 | `define PCX_BF_LO 109 |
| 97 | `define PCX_WY_HI 108 //PCX replaced L1 way field |
| 98 | `define PCX_WY_LO 107 |
| 99 | `define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01 |
| 100 | `define PCX_P_LO 107 |
| 101 | `define PCX_SZ_HI 106 //PCX load/store size field |
| 102 | `define PCX_SZ_LO 104 |
| 103 | `define PCX_ERR_HI 106 //PCX error field |
| 104 | `define PCX_ERR_LO 104 |
| 105 | `define PCX_AD_HI 103 //PCX address field |
| 106 | `define PCX_AD_LO 64 |
| 107 | `define PCX_DA_HI 63 //PCX Store data |
| 108 | `define PCX_DA_LO 0 |
| 109 | |
| 110 | `define PCX_SZ_1B 3'b000 // encoding for 1B access |
| 111 | `define PCX_SZ_2B 3'b001 // encoding for 2B access |
| 112 | `define PCX_SZ_4B 3'b010 // encoding for 4B access |
| 113 | `define PCX_SZ_8B 3'b011 // encoding for 8B access |
| 114 | `define PCX_SZ_16B 3'b100 // encoding for 16B access |
| 115 | |
| 116 | `define CPX_VLD 145 //CPX payload packet valid |
| 117 | |
| 118 | `define CPX_RQ_HI 144 //CPX Request type |
| 119 | `define CPX_RQ_LO 141 |
| 120 | `define CPX_L2MISS 140 |
| 121 | `define CPX_ERR_HI 140 //CPX error field |
| 122 | `define CPX_ERR_LO 138 |
| 123 | `define CPX_NC 137 //CPX non-cacheable |
| 124 | `define CPX_R 137 //CPX read/!write bit |
| 125 | `define CPX_TH_HI 136 //CPX thread ID field |
| 126 | `define CPX_TH_LO 134 |
| 127 | |
| 128 | //bits 133:128 are shared by different fields |
| 129 | //for different packet types. |
| 130 | |
| 131 | `define CPX_IN_HI 133 //CPX Interrupt source |
| 132 | `define CPX_IN_LO 128 |
| 133 | |
| 134 | `define CPX_WYVLD 133 //CPX replaced way valid |
| 135 | `define CPX_WY_HI 132 //CPX replaced I$/D$ way |
| 136 | `define CPX_WY_LO 131 |
| 137 | `define CPX_BF_HI 130 //CPX buffer ID field - 3 bits |
| 138 | `define CPX_BF_LO 128 |
| 139 | |
| 140 | `define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits |
| 141 | `define CPX_SI_LO 128 //used for invalidates |
| 142 | |
| 143 | `define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01 |
| 144 | `define CPX_P_LO 130 |
| 145 | |
| 146 | `define CPX_ASI 130 //CPX forward request to ASI |
| 147 | `define CPX_IF4B 130 |
| 148 | `define CPX_IINV 124 |
| 149 | `define CPX_DINV 123 |
| 150 | `define CPX_INVPA5 122 |
| 151 | `define CPX_INVPA4 121 |
| 152 | `define CPX_CPUID_HI 120 |
| 153 | `define CPX_CPUID_LO 118 |
| 154 | `define CPX_INV_PA_HI 116 |
| 155 | `define CPX_INV_PA_LO 112 |
| 156 | `define CPX_INV_IDX_HI 117 |
| 157 | `define CPX_INV_IDX_LO 112 |
| 158 | |
| 159 | `define CPX_DA_HI 127 //CPX data payload |
| 160 | `define CPX_DA_LO 0 |
| 161 | |
| 162 | `define LOAD_RQ 5'b00000 |
| 163 | `define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 164 | `define IMISS_RQ 5'b10000 |
| 165 | `define STORE_RQ 5'b00001 |
| 166 | `define CAS1_RQ 5'b00010 |
| 167 | `define CAS2_RQ 5'b00011 |
| 168 | `define SWAP_RQ 5'b00111 |
| 169 | `define STRLOAD_RQ 5'b00100 |
| 170 | `define STRST_RQ 5'b00101 |
| 171 | `define STQ_RQ 5'b00111 |
| 172 | `define INT_RQ 5'b01001 |
| 173 | `define FWD_RQ 5'b01101 |
| 174 | `define FWD_RPY 5'b01110 |
| 175 | `define RSVD_RQ 5'b11111 |
| 176 | |
| 177 | `define LOAD_RET 4'b0000 |
| 178 | `define INV_RET 4'b0011 |
| 179 | `define ST_ACK 4'b0100 |
| 180 | `define AT_ACK 4'b0011 |
| 181 | `define INT_RET 4'b0111 |
| 182 | `define TEST_RET 4'b0101 |
| 183 | `define FP_RET 4'b1000 |
| 184 | `define IFILL_RET 4'b0001 |
| 185 | `define EVICT_REQ 4'b0011 |
| 186 | //`define INVAL_ACK 4'b1000 |
| 187 | `define INVAL_ACK 4'b0100 |
| 188 | `define ERR_RET 4'b1100 |
| 189 | `define STRLOAD_RET 4'b0010 |
| 190 | `define STRST_ACK 4'b0110 |
| 191 | `define FWD_RQ_RET 4'b1010 |
| 192 | `define FWD_RPY_RET 4'b1011 |
| 193 | `define RSVD_RET 4'b1111 |
| 194 | |
| 195 | //End cache crossbar defines |
| 196 | |
| 197 | |
| 198 | // Number of COS supported by EECU |
| 199 | `define EECU_COS_NUM 2 |
| 200 | |
| 201 | |
| 202 | // |
| 203 | // BSC bus sizes |
| 204 | // ============= |
| 205 | // |
| 206 | |
| 207 | // General |
| 208 | `define BSC_ADDRESS 40 |
| 209 | `define MAX_XFER_LEN 7'b0 |
| 210 | `define XFER_LEN_WIDTH 6 |
| 211 | |
| 212 | // CTags |
| 213 | `define BSC_CTAG_SZ 12 |
| 214 | `define EICU_CTAG_PRE 5'b11101 |
| 215 | `define EICU_CTAG_REM 7 |
| 216 | `define EIPU_CTAG_PRE 3'b011 |
| 217 | `define EIPU_CTAG_REM 9 |
| 218 | `define EECU_CTAG_PRE 8'b11010000 |
| 219 | `define EECU_CTAG_REM 4 |
| 220 | `define EEPU_CTAG_PRE 6'b010000 |
| 221 | `define EEPU_CTAG_REM 6 |
| 222 | `define L2C_CTAG_PRE 2'b00 |
| 223 | `define L2C_CTAG_REM 10 |
| 224 | `define JBI_CTAG_PRE 2'b10 |
| 225 | `define JBI_CTAG_REM 10 |
| 226 | // reinstated temporarily |
| 227 | `define PCI_CTAG_PRE 7'b1101100 |
| 228 | `define PCI_CTAG_REM 5 |
| 229 | |
| 230 | |
| 231 | // CoS |
| 232 | `define EICU_COS 1'b0 |
| 233 | `define EIPU_COS 1'b1 |
| 234 | `define EECU_COS 1'b0 |
| 235 | `define EEPU_COS 1'b1 |
| 236 | `define PCI_COS 1'b0 |
| 237 | |
| 238 | // L2$ Bank |
| 239 | `define BSC_L2_BNK_HI 8 |
| 240 | `define BSC_L2_BNK_LO 6 |
| 241 | |
| 242 | // L2$ Req |
| 243 | `define BSC_L2_REQ_SZ 62 |
| 244 | `define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code |
| 245 | `define BSC_L2_BUS 64 |
| 246 | `define BSC_L2_CTAG_HI 61 |
| 247 | `define BSC_L2_CTAG_LO 50 |
| 248 | `define BSC_L2_ADD_HI 49 |
| 249 | `define BSC_L2_ADD_LO 10 |
| 250 | `define BSC_L2_LEN_HI 9 |
| 251 | `define BSC_L2_LEN_LO 3 |
| 252 | `define BSC_L2_ALLOC 2 |
| 253 | `define BSC_L2_COS 1 |
| 254 | `define BSC_L2_READ 0 |
| 255 | |
| 256 | // L2$ Ack |
| 257 | `define L2_BSC_ACK_SZ 16 |
| 258 | `define L2_BSC_BUS 64 |
| 259 | `define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address |
| 260 | `define L2_BSC_CBA_LO 13 |
| 261 | `define L2_BSC_READ 12 |
| 262 | `define L2_BSC_CTAG_HI 11 |
| 263 | `define L2_BSC_CTAG_LO 0 |
| 264 | |
| 265 | // Enet Egress Command Unit |
| 266 | `define EECU_REQ_BUS 44 |
| 267 | `define EECU_REQ_SZ 44 |
| 268 | `define EECU_R_QID_HI 43 |
| 269 | `define EECU_R_QID_LO 40 |
| 270 | `define EECU_R_ADD_HI 39 |
| 271 | `define EECU_R_ADD_LO 0 |
| 272 | |
| 273 | `define EECU_ACK_BUS 64 |
| 274 | `define EECU_ACK_SZ 5 |
| 275 | `define EECU_A_NACK 4 |
| 276 | `define EECU_A_QID_HI 3 |
| 277 | `define EECU_A_QID_LO 0 |
| 278 | |
| 279 | |
| 280 | // Enet Egress Packet Unit |
| 281 | `define EEPU_REQ_BUS 55 |
| 282 | `define EEPU_REQ_SZ 55 |
| 283 | `define EEPU_R_TLEN_HI 54 |
| 284 | `define EEPU_R_TLEN_LO 48 |
| 285 | `define EEPU_R_SOF 47 |
| 286 | `define EEPU_R_EOF 46 |
| 287 | `define EEPU_R_PORT_HI 45 |
| 288 | `define EEPU_R_PORT_LO 44 |
| 289 | `define EEPU_R_QID_HI 43 |
| 290 | `define EEPU_R_QID_LO 40 |
| 291 | `define EEPU_R_ADD_HI 39 |
| 292 | `define EEPU_R_ADD_LO 0 |
| 293 | |
| 294 | // This is cleaved in between Egress Datapath Ack's |
| 295 | `define EEPU_ACK_BUS 6 |
| 296 | `define EEPU_ACK_SZ 6 |
| 297 | `define EEPU_A_EOF 5 |
| 298 | `define EEPU_A_NACK 4 |
| 299 | `define EEPU_A_QID_HI 3 |
| 300 | `define EEPU_A_QID_LO 0 |
| 301 | |
| 302 | |
| 303 | // Enet Egress Datapath |
| 304 | `define EEDP_ACK_BUS 128 |
| 305 | `define EEDP_ACK_SZ 28 |
| 306 | `define EEDP_A_NACK 27 |
| 307 | `define EEDP_A_QID_HI 26 |
| 308 | `define EEDP_A_QID_LO 21 |
| 309 | `define EEDP_A_SOF 20 |
| 310 | `define EEDP_A_EOF 19 |
| 311 | `define EEDP_A_LEN_HI 18 |
| 312 | `define EEDP_A_LEN_LO 12 |
| 313 | `define EEDP_A_TAG_HI 11 |
| 314 | `define EEDP_A_TAG_LO 0 |
| 315 | `define EEDP_A_PORT_HI 5 |
| 316 | `define EEDP_A_PORT_LO 4 |
| 317 | `define EEDP_A_PORT_WIDTH 2 |
| 318 | |
| 319 | |
| 320 | // In-Order / Ordered Queue: EEPU |
| 321 | // Tag is: TLEN, SOF, EOF, QID = 15 |
| 322 | `define EEPU_TAG_ARY (7+1+1+6) |
| 323 | `define EEPU_ENTRIES 16 |
| 324 | `define EEPU_E_IDX 4 |
| 325 | `define EEPU_PORTS 4 |
| 326 | `define EEPU_P_IDX 2 |
| 327 | |
| 328 | // Nack + Tag Info + CTag |
| 329 | `define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12) |
| 330 | `define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX) |
| 331 | |
| 332 | |
| 333 | // ENET Ingress Queue Management Req |
| 334 | `define EICU_REQ_BUS 64 |
| 335 | `define EICU_REQ_SZ 62 |
| 336 | `define EICU_R_CTAG_HI 61 |
| 337 | `define EICU_R_CTAG_LO 50 |
| 338 | `define EICU_R_ADD_HI 49 |
| 339 | `define EICU_R_ADD_LO 10 |
| 340 | `define EICU_R_LEN_HI 9 |
| 341 | `define EICU_R_LEN_LO 3 |
| 342 | `define EICU_R_COS 1 |
| 343 | `define EICU_R_READ 0 |
| 344 | |
| 345 | |
| 346 | // ENET Ingress Queue Management Ack |
| 347 | `define EICU_ACK_BUS 64 |
| 348 | `define EICU_ACK_SZ 14 |
| 349 | `define EICU_A_NACK 13 |
| 350 | `define EICU_A_READ 12 |
| 351 | `define EICU_A_CTAG_HI 11 |
| 352 | `define EICU_A_CTAG_LO 0 |
| 353 | |
| 354 | |
| 355 | // Enet Ingress Packet Unit |
| 356 | `define EIPU_REQ_BUS 128 |
| 357 | `define EIPU_REQ_SZ 59 |
| 358 | `define EIPU_R_CTAG_HI 58 |
| 359 | `define EIPU_R_CTAG_LO 50 |
| 360 | `define EIPU_R_ADD_HI 49 |
| 361 | `define EIPU_R_ADD_LO 10 |
| 362 | `define EIPU_R_LEN_HI 9 |
| 363 | `define EIPU_R_LEN_LO 3 |
| 364 | `define EIPU_R_COS 1 |
| 365 | `define EIPU_R_READ 0 |
| 366 | |
| 367 | |
| 368 | // ENET Ingress Packet Unit Ack |
| 369 | `define EIPU_ACK_BUS 10 |
| 370 | `define EIPU_ACK_SZ 10 |
| 371 | `define EIPU_A_NACK 9 |
| 372 | `define EIPU_A_CTAG_HI 8 |
| 373 | `define EIPU_A_CTAG_LO 0 |
| 374 | |
| 375 | |
| 376 | // In-Order / Ordered Queue: PCI |
| 377 | // Tag is: CTAG |
| 378 | `define PCI_TAG_ARY 12 |
| 379 | `define PCI_ENTRIES 16 |
| 380 | `define PCI_E_IDX 4 |
| 381 | `define PCI_PORTS 2 |
| 382 | |
| 383 | // PCI-X Request |
| 384 | `define PCI_REQ_BUS 64 |
| 385 | `define PCI_REQ_SZ 62 |
| 386 | `define PCI_R_CTAG_HI 61 |
| 387 | `define PCI_R_CTAG_LO 50 |
| 388 | `define PCI_R_ADD_HI 49 |
| 389 | `define PCI_R_ADD_LO 10 |
| 390 | `define PCI_R_LEN_HI 9 |
| 391 | `define PCI_R_LEN_LO 3 |
| 392 | `define PCI_R_COS 1 |
| 393 | `define PCI_R_READ 0 |
| 394 | |
| 395 | // PCI_X Acknowledge |
| 396 | `define PCI_ACK_BUS 64 |
| 397 | `define PCI_ACK_SZ 14 |
| 398 | `define PCI_A_NACK 13 |
| 399 | `define PCI_A_READ 12 |
| 400 | `define PCI_A_CTAG_HI 11 |
| 401 | `define PCI_A_CTAG_LO 0 |
| 402 | |
| 403 | |
| 404 | `define BSC_MAX_REQ_SZ 62 |
| 405 | |
| 406 | |
| 407 | // |
| 408 | // BSC array sizes |
| 409 | //================ |
| 410 | // |
| 411 | `define BSC_REQ_ARY_INDEX 6 |
| 412 | `define BSC_REQ_ARY_DEPTH 64 |
| 413 | `define BSC_REQ_ARY_WIDTH 62 |
| 414 | `define BSC_REQ_NXT_WIDTH 12 |
| 415 | `define BSC_ACK_ARY_INDEX 6 |
| 416 | `define BSC_ACK_ARY_DEPTH 64 |
| 417 | `define BSC_ACK_ARY_WIDTH 14 |
| 418 | `define BSC_ACK_NXT_WIDTH 12 |
| 419 | `define BSC_PAY_ARY_INDEX 6 |
| 420 | `define BSC_PAY_ARY_DEPTH 64 |
| 421 | `define BSC_PAY_ARY_WIDTH 256 |
| 422 | |
| 423 | // ECC syndrome bits per memory element |
| 424 | `define BSC_PAY_ECC 10 |
| 425 | `define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH) |
| 426 | |
| 427 | |
| 428 | // |
| 429 | // BSC Port Definitions |
| 430 | // ==================== |
| 431 | // |
| 432 | // Bits 7 to 4 of curr_port_id |
| 433 | `define BSC_PORT_NULL 4'h0 |
| 434 | `define BSC_PORT_SC 4'h1 |
| 435 | `define BSC_PORT_EICU 4'h2 |
| 436 | `define BSC_PORT_EIPU 4'h3 |
| 437 | `define BSC_PORT_EECU 4'h4 |
| 438 | `define BSC_PORT_EEPU 4'h8 |
| 439 | `define BSC_PORT_PCI 4'h9 |
| 440 | |
| 441 | // Number of ports of each type |
| 442 | `define BSC_PORT_SC_CNT 8 |
| 443 | |
| 444 | // Bits needed to represent above |
| 445 | `define BSC_PORT_SC_IDX 3 |
| 446 | |
| 447 | // How wide the linked list pointers are |
| 448 | // 60b for no payload (2CoS) |
| 449 | // 80b for payload (2CoS) |
| 450 | |
| 451 | //`define BSC_OBJ_PTR 80 |
| 452 | //`define BSC_HD1_HI 69 |
| 453 | //`define BSC_HD1_LO 60 |
| 454 | //`define BSC_TL1_HI 59 |
| 455 | //`define BSC_TL1_LO 50 |
| 456 | //`define BSC_CT1_HI 49 |
| 457 | //`define BSC_CT1_LO 40 |
| 458 | //`define BSC_HD0_HI 29 |
| 459 | //`define BSC_HD0_LO 20 |
| 460 | //`define BSC_TL0_HI 19 |
| 461 | //`define BSC_TL0_LO 10 |
| 462 | //`define BSC_CT0_HI 9 |
| 463 | //`define BSC_CT0_LO 0 |
| 464 | |
| 465 | `define BSC_OBJP_PTR 48 |
| 466 | `define BSC_PYP1_HI 47 |
| 467 | `define BSC_PYP1_LO 42 |
| 468 | `define BSC_HDP1_HI 41 |
| 469 | `define BSC_HDP1_LO 36 |
| 470 | `define BSC_TLP1_HI 35 |
| 471 | `define BSC_TLP1_LO 30 |
| 472 | `define BSC_CTP1_HI 29 |
| 473 | `define BSC_CTP1_LO 24 |
| 474 | `define BSC_PYP0_HI 23 |
| 475 | `define BSC_PYP0_LO 18 |
| 476 | `define BSC_HDP0_HI 17 |
| 477 | `define BSC_HDP0_LO 12 |
| 478 | `define BSC_TLP0_HI 11 |
| 479 | `define BSC_TLP0_LO 6 |
| 480 | `define BSC_CTP0_HI 5 |
| 481 | `define BSC_CTP0_LO 0 |
| 482 | |
| 483 | `define BSC_PTR_WIDTH 192 |
| 484 | `define BSC_PTR_REQ_HI 191 |
| 485 | `define BSC_PTR_REQ_LO 144 |
| 486 | `define BSC_PTR_REQP_HI 143 |
| 487 | `define BSC_PTR_REQP_LO 96 |
| 488 | `define BSC_PTR_ACK_HI 95 |
| 489 | `define BSC_PTR_ACK_LO 48 |
| 490 | `define BSC_PTR_ACKP_HI 47 |
| 491 | `define BSC_PTR_ACKP_LO 0 |
| 492 | |
| 493 | `define BSC_PORT_SC_PTR 96 // R, R+P |
| 494 | `define BSC_PORT_EECU_PTR 48 // A+P |
| 495 | `define BSC_PORT_EICU_PTR 96 // A, A+P |
| 496 | `define BSC_PORT_EIPU_PTR 48 // A |
| 497 | |
| 498 | // I2C STATES in DRAMctl |
| 499 | `define I2C_CMD_NOP 4'b0000 |
| 500 | `define I2C_CMD_START 4'b0001 |
| 501 | `define I2C_CMD_STOP 4'b0010 |
| 502 | `define I2C_CMD_WRITE 4'b0100 |
| 503 | `define I2C_CMD_READ 4'b1000 |
| 504 | |
| 505 | |
| 506 | // |
| 507 | // IOB defines |
| 508 | // =========== |
| 509 | // |
| 510 | `define IOB_ADDR_WIDTH 40 |
| 511 | `define IOB_LOCAL_ADDR_WIDTH 32 |
| 512 | |
| 513 | `define IOB_CPU_INDEX 3 |
| 514 | `define IOB_CPU_WIDTH 8 |
| 515 | `define IOB_THR_INDEX 2 |
| 516 | `define IOB_THR_WIDTH 4 |
| 517 | `define IOB_CPUTHR_INDEX 5 |
| 518 | `define IOB_CPUTHR_WIDTH 32 |
| 519 | |
| 520 | `define IOB_MONDO_DATA_INDEX 5 |
| 521 | `define IOB_MONDO_DATA_DEPTH 32 |
| 522 | `define IOB_MONDO_DATA_WIDTH 64 |
| 523 | `define IOB_MONDO_SRC_WIDTH 5 |
| 524 | `define IOB_MONDO_BUSY 5 |
| 525 | |
| 526 | `define IOB_INT_TAB_INDEX 6 |
| 527 | `define IOB_INT_TAB_DEPTH 64 |
| 528 | |
| 529 | `define IOB_INT_STAT_WIDTH 32 |
| 530 | `define IOB_INT_STAT_HI 31 |
| 531 | `define IOB_INT_STAT_LO 0 |
| 532 | |
| 533 | `define IOB_INT_VEC_WIDTH 6 |
| 534 | `define IOB_INT_VEC_HI 5 |
| 535 | `define IOB_INT_VEC_LO 0 |
| 536 | |
| 537 | `define IOB_INT_CPU_WIDTH 5 |
| 538 | `define IOB_INT_CPU_HI 12 |
| 539 | `define IOB_INT_CPU_LO 8 |
| 540 | |
| 541 | `define IOB_INT_MASK 2 |
| 542 | `define IOB_INT_CLEAR 1 |
| 543 | `define IOB_INT_PEND 0 |
| 544 | |
| 545 | `define IOB_DISP_TYPE_HI 17 |
| 546 | `define IOB_DISP_TYPE_LO 16 |
| 547 | `define IOB_DISP_THR_HI 12 |
| 548 | `define IOB_DISP_THR_LO 8 |
| 549 | `define IOB_DISP_VEC_HI 5 |
| 550 | `define IOB_DISP_VEC_LO 0 |
| 551 | |
| 552 | `define IOB_JBI_RESET 1 |
| 553 | `define IOB_ENET_RESET 0 |
| 554 | |
| 555 | `define IOB_RESET_STAT_WIDTH 3 |
| 556 | `define IOB_RESET_STAT_HI 3 |
| 557 | `define IOB_RESET_STAT_LO 1 |
| 558 | |
| 559 | `define IOB_SERNUM_WIDTH 64 |
| 560 | |
| 561 | `define IOB_FUSE_WIDTH 22 |
| 562 | |
| 563 | `define IOB_TMSTAT_THERM 63 |
| 564 | |
| 565 | `define IOB_POR_TT 6'b01 // power-on-reset trap type |
| 566 | |
| 567 | `define IOB_CPU_BUF_INDEX 4 |
| 568 | |
| 569 | `define IOB_INT_BUF_INDEX 4 |
| 570 | `define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width |
| 571 | |
| 572 | `define IOB_IO_BUF_INDEX 4 |
| 573 | `define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width |
| 574 | |
| 575 | `define IOB_L2_VIS_BUF_INDEX 5 |
| 576 | `define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width |
| 577 | |
| 578 | `define IOB_INT_AVEC_WIDTH 16 // availibility vector width |
| 579 | `define IOB_ACK_AVEC_WIDTH 16 // availibility vector width |
| 580 | |
| 581 | // fixme - double check address mapping |
| 582 | // CREG in `IOB_INT_CSR space |
| 583 | `define IOB_DEV_ADDR_MASK 32'hfffffe07 |
| 584 | `define IOB_CREG_INTSTAT 32'h00000000 |
| 585 | `define IOB_CREG_MDATA0 32'h00000400 |
| 586 | `define IOB_CREG_MDATA1 32'h00000500 |
| 587 | `define IOB_CREG_MBUSY 32'h00000900 |
| 588 | `define IOB_THR_ADDR_MASK 32'hffffff07 |
| 589 | `define IOB_CREG_MDATA0_ALIAS 32'h00000600 |
| 590 | `define IOB_CREG_MDATA1_ALIAS 32'h00000700 |
| 591 | `define IOB_CREG_MBUSY_ALIAS 32'h00000b00 |
| 592 | |
| 593 | // CREG in `IOB_MAN_CSR space |
| 594 | `define IOB_CREG_INTMAN 32'h00000000 |
| 595 | `define IOB_CREG_INTCTL 32'h00000400 |
| 596 | `define IOB_CREG_INTVECDISP 32'h00000800 |
| 597 | `define IOB_CREG_RESETSTAT 32'h00000810 |
| 598 | `define IOB_CREG_SERNUM 32'h00000820 |
| 599 | `define IOB_CREG_TMSTATCTRL 32'h00000828 |
| 600 | `define IOB_CREG_COREAVAIL 32'h00000830 |
| 601 | `define IOB_CREG_SSYSRESET 32'h00000838 |
| 602 | `define IOB_CREG_FUSESTAT 32'h00000840 |
| 603 | `define IOB_CREG_JINTV 32'h00000a00 |
| 604 | |
| 605 | `define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 |
| 606 | `define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 |
| 607 | `define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 |
| 608 | `define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 |
| 609 | `define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 |
| 610 | `define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 |
| 611 | `define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 |
| 612 | `define IOB_CREG_DBG_ENET_CTRL 32'h00002000 |
| 613 | `define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 |
| 614 | `define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 |
| 615 | `define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 |
| 616 | `define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 |
| 617 | `define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 |
| 618 | `define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 |
| 619 | `define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 |
| 620 | `define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 |
| 621 | `define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 |
| 622 | `define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 |
| 623 | `define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 |
| 624 | `define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 |
| 625 | `define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 |
| 626 | `define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 |
| 627 | |
| 628 | `define IOB_CREG_TESTSTUB 32'h80000000 |
| 629 | |
| 630 | // Address map for TAP access of SPARC ASI |
| 631 | `define IOB_ASI_PC 4'b0000 |
| 632 | `define IOB_ASI_BIST 4'b0001 |
| 633 | `define IOB_ASI_MARGIN 4'b0010 |
| 634 | `define IOB_ASI_DEFEATURE 4'b0011 |
| 635 | `define IOB_ASI_L1DD 4'b0100 |
| 636 | `define IOB_ASI_L1ID 4'b0101 |
| 637 | `define IOB_ASI_L1DT 4'b0110 |
| 638 | |
| 639 | `define IOB_INT 2'b00 |
| 640 | `define IOB_RESET 2'b01 |
| 641 | `define IOB_IDLE 2'b10 |
| 642 | `define IOB_RESUME 2'b11 |
| 643 | |
| 644 | // |
| 645 | // CIOP UCB Bus Width |
| 646 | // ================== |
| 647 | // |
| 648 | `define IOB_EECU_WIDTH 16 // ethernet egress command |
| 649 | `define EECU_IOB_WIDTH 16 |
| 650 | |
| 651 | `define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously) |
| 652 | `define NRAM_IOB_WIDTH 4 |
| 653 | |
| 654 | `define IOB_JBI_WIDTH 16 // JBI |
| 655 | `define JBI_IOB_WIDTH 16 |
| 656 | |
| 657 | `define IOB_ENET_ING_WIDTH 32 // ethernet ingress |
| 658 | `define ENET_ING_IOB_WIDTH 8 |
| 659 | |
| 660 | `define IOB_ENET_EGR_WIDTH 4 // ethernet egress |
| 661 | `define ENET_EGR_IOB_WIDTH 4 |
| 662 | |
| 663 | `define IOB_ENET_MAC_WIDTH 4 // ethernet MAC |
| 664 | `define ENET_MAC_IOB_WIDTH 4 |
| 665 | |
| 666 | `define IOB_DRAM_WIDTH 4 // DRAM controller |
| 667 | `define DRAM_IOB_WIDTH 4 |
| 668 | |
| 669 | `define IOB_BSC_WIDTH 4 // BSC |
| 670 | `define BSC_IOB_WIDTH 4 |
| 671 | |
| 672 | `define IOB_SPI_WIDTH 4 // SPI (Boot ROM) |
| 673 | `define SPI_IOB_WIDTH 4 |
| 674 | |
| 675 | `define IOB_CLK_WIDTH 4 // clk unit |
| 676 | `define CLK_IOB_WIDTH 4 |
| 677 | |
| 678 | `define IOB_CLSP_WIDTH 4 // clk spine unit |
| 679 | `define CLSP_IOB_WIDTH 4 |
| 680 | |
| 681 | `define IOB_TAP_WIDTH 8 // TAP |
| 682 | `define TAP_IOB_WIDTH 8 |
| 683 | |
| 684 | |
| 685 | // |
| 686 | // CIOP UCB Buf ID Type |
| 687 | // ==================== |
| 688 | // |
| 689 | `define UCB_BID_CMP 2'b00 |
| 690 | `define UCB_BID_TAP 2'b01 |
| 691 | |
| 692 | // |
| 693 | // Interrupt Device ID |
| 694 | // =================== |
| 695 | // |
| 696 | // Caution: DUMMY_DEV_ID has to be 9 bit wide |
| 697 | // for fields to line up properly in the IOB. |
| 698 | `define DUMMY_DEV_ID 9'h10 // 16 |
| 699 | `define UNCOR_ECC_DEV_ID 7'd17 // 17 |
| 700 | |
| 701 | // |
| 702 | // Soft Error related definitions |
| 703 | // ============================== |
| 704 | // |
| 705 | `define COR_ECC_CNT_WIDTH 16 |
| 706 | |
| 707 | |
| 708 | // |
| 709 | // CMP clock |
| 710 | // ========= |
| 711 | // |
| 712 | |
| 713 | `define CMP_CLK_PERIOD 1333 |
| 714 | |
| 715 | |
| 716 | // |
| 717 | // NRAM/IO Interface |
| 718 | // ================= |
| 719 | // |
| 720 | |
| 721 | `define DRAM_CLK_PERIOD 6000 |
| 722 | |
| 723 | `define NRAM_IO_DQ_WIDTH 32 |
| 724 | `define IO_NRAM_DQ_WIDTH 32 |
| 725 | |
| 726 | `define NRAM_IO_ADDR_WIDTH 15 |
| 727 | `define NRAM_IO_BA_WIDTH 2 |
| 728 | |
| 729 | |
| 730 | // |
| 731 | // NRAM/ENET Interface |
| 732 | // =================== |
| 733 | // |
| 734 | |
| 735 | `define NRAM_ENET_DATA_WIDTH 64 |
| 736 | `define ENET_NRAM_ADDR_WIDTH 20 |
| 737 | |
| 738 | `define NRAM_DBG_DATA_WIDTH 40 |
| 739 | |
| 740 | |
| 741 | // |
| 742 | // IO/FCRAM Interface |
| 743 | // ================== |
| 744 | // |
| 745 | |
| 746 | `define FCRAM_DATA1_HI 63 |
| 747 | `define FCRAM_DATA1_LO 32 |
| 748 | `define FCRAM_DATA0_HI 31 |
| 749 | `define FCRAM_DATA0_LO 0 |
| 750 | |
| 751 | // |
| 752 | // PCI Interface |
| 753 | // ================== |
| 754 | // Load/store size encodings |
| 755 | // ------------------------- |
| 756 | // Size encoding |
| 757 | // 000 - byte |
| 758 | // 001 - half-word |
| 759 | // 010 - word |
| 760 | // 011 - double-word |
| 761 | // 100 - quad |
| 762 | `define LDST_SZ_BYTE 3'b000 |
| 763 | `define LDST_SZ_HALF_WORD 3'b001 |
| 764 | `define LDST_SZ_WORD 3'b010 |
| 765 | `define LDST_SZ_DOUBLE_WORD 3'b011 |
| 766 | `define LDST_SZ_QUAD 3'b100 |
| 767 | |
| 768 | // |
| 769 | // JBI<->SCTAG Interface |
| 770 | // ======================= |
| 771 | // Outbound Header Format |
| 772 | `define JBI_BTU_OUT_ADDR_LO 0 |
| 773 | `define JBI_BTU_OUT_ADDR_HI 42 |
| 774 | `define JBI_BTU_OUT_RSV0_LO 43 |
| 775 | `define JBI_BTU_OUT_RSV0_HI 43 |
| 776 | `define JBI_BTU_OUT_TYPE_LO 44 |
| 777 | `define JBI_BTU_OUT_TYPE_HI 48 |
| 778 | `define JBI_BTU_OUT_RSV1_LO 49 |
| 779 | `define JBI_BTU_OUT_RSV1_HI 51 |
| 780 | `define JBI_BTU_OUT_REPLACE_LO 52 |
| 781 | `define JBI_BTU_OUT_REPLACE_HI 56 |
| 782 | `define JBI_BTU_OUT_RSV2_LO 57 |
| 783 | `define JBI_BTU_OUT_RSV2_HI 59 |
| 784 | `define JBI_BTU_OUT_BTU_ID_LO 60 |
| 785 | `define JBI_BTU_OUT_BTU_ID_HI 71 |
| 786 | `define JBI_BTU_OUT_DATA_RTN 72 |
| 787 | `define JBI_BTU_OUT_RSV3_LO 73 |
| 788 | `define JBI_BTU_OUT_RSV3_HI 75 |
| 789 | `define JBI_BTU_OUT_CE 76 |
| 790 | `define JBI_BTU_OUT_RSV4_LO 77 |
| 791 | `define JBI_BTU_OUT_RSV4_HI 79 |
| 792 | `define JBI_BTU_OUT_UE 80 |
| 793 | `define JBI_BTU_OUT_RSV5_LO 81 |
| 794 | `define JBI_BTU_OUT_RSV5_HI 83 |
| 795 | `define JBI_BTU_OUT_DRAM 84 |
| 796 | `define JBI_BTU_OUT_RSV6_LO 85 |
| 797 | `define JBI_BTU_OUT_RSV6_HI 127 |
| 798 | |
| 799 | // Inbound Header Format |
| 800 | `define JBI_SCTAG_IN_ADDR_LO 0 |
| 801 | `define JBI_SCTAG_IN_ADDR_HI 39 |
| 802 | `define JBI_SCTAG_IN_SZ_LO 40 |
| 803 | `define JBI_SCTAG_IN_SZ_HI 42 |
| 804 | `define JBI_SCTAG_IN_RSV0 43 |
| 805 | `define JBI_SCTAG_IN_TAG_LO 44 |
| 806 | `define JBI_SCTAG_IN_TAG_HI 55 |
| 807 | `define JBI_SCTAG_IN_REQ_LO 56 |
| 808 | `define JBI_SCTAG_IN_REQ_HI 58 |
| 809 | `define JBI_SCTAG_IN_POISON 59 |
| 810 | `define JBI_SCTAG_IN_RSV1_LO 60 |
| 811 | `define JBI_SCTAG_IN_RSV1_HI 63 |
| 812 | |
| 813 | `define JBI_SCTAG_REQ_WRI 3'b100 |
| 814 | `define JBI_SCTAG_REQ_WR8 3'b010 |
| 815 | `define JBI_SCTAG_REQ_RDD 3'b001 |
| 816 | `define JBI_SCTAG_REQ_WRI_BIT 2 |
| 817 | `define JBI_SCTAG_REQ_WR8_BIT 1 |
| 818 | `define JBI_SCTAG_REQ_RDD_BIT 0 |
| 819 | |
| 820 | // |
| 821 | // JBI->IOB Mondo Header Format |
| 822 | // ============================ |
| 823 | // |
| 824 | `define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1 |
| 825 | `define JBI_IOB_MONDO_RSV1_LO 13 |
| 826 | `define JBI_IOB_MONDO_TRG_HI 12 // interrupt target |
| 827 | `define JBI_IOB_MONDO_TRG_LO 8 |
| 828 | `define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0 |
| 829 | `define JBI_IOB_MONDO_RSV0_LO 5 |
| 830 | `define JBI_IOB_MONDO_SRC_HI 4 // interrupt source |
| 831 | `define JBI_IOB_MONDO_SRC_LO 0 |
| 832 | |
| 833 | `define JBI_IOB_MONDO_RSV1_WIDTH 3 |
| 834 | `define JBI_IOB_MONDO_TRG_WIDTH 5 |
| 835 | `define JBI_IOB_MONDO_RSV0_WIDTH 3 |
| 836 | `define JBI_IOB_MONDO_SRC_WIDTH 5 |
| 837 | |
| 838 | // JBI->IOB Mondo Bus Width/Cycle |
| 839 | // ============================== |
| 840 | // Cycle 1 Header[15:8] |
| 841 | // Cycle 2 Header[ 7:0] |
| 842 | // Cycle 3 J_AD[127:120] |
| 843 | // Cycle 4 J_AD[119:112] |
| 844 | // ..... |
| 845 | // Cycle 18 J_AD[ 7: 0] |
| 846 | `define JBI_IOB_MONDO_BUS_WIDTH 8 |
| 847 | `define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data |
| 848 | |
| 849 | |
| 850 | |
| 851 | |
| 852 | `define IQ_SIZE 8 |
| 853 | `define OQ_SIZE 12 |
| 854 | `define TAG_WIDTH 28 |
| 855 | `define TAG_WIDTH_LESS1 27 |
| 856 | `define TAG_WIDTHr 28r |
| 857 | `define TAG_WIDTHc 28c |
| 858 | `define TAG_WIDTH6 22 |
| 859 | `define TAG_WIDTH6r 22r |
| 860 | `define TAG_WIDTH6c 22c |
| 861 | |
| 862 | |
| 863 | `define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 864 | |
| 865 | // BS and SR 11/12/03 N2 Xbar Packet format change |
| 866 | |
| 867 | `define MBD_ECC_HI 105 |
| 868 | `define MBD_ECC_HI_PLUS1 106 |
| 869 | `define MBD_ECC_HI_PLUS5 110 |
| 870 | `define MBD_ECC_LO 100 |
| 871 | `define MBD_EVICT 99 |
| 872 | `define MBD_DEP 98 |
| 873 | `define MBD_TECC 97 |
| 874 | `define MBD_ENTRY_HI 96 |
| 875 | `define MBD_ENTRY_LO 93 |
| 876 | |
| 877 | `define MBD_POISON 92 |
| 878 | `define MBD_RDMA_HI 91 |
| 879 | `define MBD_RDMA_LO 90 |
| 880 | `define MBD_RQ_HI 89 |
| 881 | `define MBD_RQ_LO 85 |
| 882 | `define MBD_NC 84 |
| 883 | `define MBD_RSVD 83 |
| 884 | `define MBD_CP_HI 82 |
| 885 | `define MBD_CP_LO 80 |
| 886 | `define MBD_TH_HI 79 |
| 887 | `define MBD_TH_LO 77 |
| 888 | `define MBD_BF_HI 76 |
| 889 | `define MBD_BF_LO 74 |
| 890 | `define MBD_WY_HI 73 |
| 891 | `define MBD_WY_LO 72 |
| 892 | `define MBD_SZ_HI 71 |
| 893 | `define MBD_SZ_LO 64 |
| 894 | `define MBD_DATA_HI 63 |
| 895 | `define MBD_DATA_LO 0 |
| 896 | |
| 897 | // BS and SR 11/12/03 N2 Xbar Packet format change |
| 898 | `define L2_FBF 40 |
| 899 | `define L2_MBF 39 |
| 900 | `define L2_SNP 38 |
| 901 | `define L2_CTRUE 37 |
| 902 | `define L2_EVICT 36 |
| 903 | `define L2_DEP 35 |
| 904 | `define L2_TECC 34 |
| 905 | `define L2_ENTRY_HI 33 |
| 906 | `define L2_ENTRY_LO 29 |
| 907 | |
| 908 | `define L2_POISON 28 |
| 909 | `define L2_RDMA_HI 27 |
| 910 | `define L2_RDMA_LO 26 |
| 911 | // BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit |
| 912 | `define L2_RQTYP_HI 25 |
| 913 | `define L2_RQTYP_LO 21 |
| 914 | `define L2_NC 20 |
| 915 | `define L2_RSVD 19 |
| 916 | `define L2_CPUID_HI 18 |
| 917 | `define L2_CPUID_LO 16 |
| 918 | `define L2_TID_HI 15 |
| 919 | `define L2_TID_LO 13 |
| 920 | `define L2_BUFID_HI 12 |
| 921 | `define L2_BUFID_LO 10 |
| 922 | `define L2_L1WY_HI 9 |
| 923 | `define L2_L1WY_LO 8 |
| 924 | `define L2_SZ_HI 7 |
| 925 | `define L2_SZ_LO 0 |
| 926 | |
| 927 | |
| 928 | `define ERR_MEU 63 |
| 929 | `define ERR_MEC 62 |
| 930 | `define ERR_RW 61 |
| 931 | `define ERR_ASYNC 60 |
| 932 | `define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54] |
| 933 | `define ERR_TID_LO 54 |
| 934 | `define ERR_LDAC 53 |
| 935 | `define ERR_LDAU 52 |
| 936 | `define ERR_LDWC 51 |
| 937 | `define ERR_LDWU 50 |
| 938 | `define ERR_LDRC 49 |
| 939 | `define ERR_LDRU 48 |
| 940 | `define ERR_LDSC 47 |
| 941 | `define ERR_LDSU 46 |
| 942 | `define ERR_LTC 45 |
| 943 | `define ERR_LRU 44 |
| 944 | `define ERR_LVU 43 |
| 945 | `define ERR_DAC 42 |
| 946 | `define ERR_DAU 41 |
| 947 | `define ERR_DRC 40 |
| 948 | `define ERR_DRU 39 |
| 949 | `define ERR_DSC 38 |
| 950 | `define ERR_DSU 37 |
| 951 | `define ERR_VEC 36 |
| 952 | `define ERR_VEU 35 |
| 953 | `define ERR_LVC 34 |
| 954 | `define ERR_SYN_HI 31 |
| 955 | `define ERR_SYN_LO 0 |
| 956 | |
| 957 | |
| 958 | |
| 959 | `define ERR_MEND 51 |
| 960 | `define ERR_NDRW 50 |
| 961 | `define ERR_NDSP 49 |
| 962 | `define ERR_NDDM 48 |
| 963 | `define ERR_NDVCID_HI 45 |
| 964 | `define ERR_NDVCID_LO 40 |
| 965 | `define ERR_NDADR_HI 39 |
| 966 | `define ERR_NDADR_LO 4 |
| 967 | |
| 968 | |
| 969 | // Phase 2 : SIU Inteface and format change |
| 970 | |
| 971 | `define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 972 | `define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 973 | `define JBI_HDR_SZ4 23 |
| 974 | `define JBI_HDR_SZc 27c |
| 975 | `define JBI_HDR_SZ4c 23c |
| 976 | |
| 977 | `define JBI_ADDR_LO 0 |
| 978 | `define JBI_ADDR_HI 7 |
| 979 | `define JBI_SZ_LO 8 |
| 980 | `define JBI_SZ_HI 15 |
| 981 | // `define JBI_RSVD 16 NOt used |
| 982 | `define JBI_CTAG_LO 16 |
| 983 | `define JBI_CTAG_HI 23 |
| 984 | `define JBI_RQ_RD 24 |
| 985 | `define JBI_RQ_WR8 25 |
| 986 | `define JBI_RQ_WR64 26 |
| 987 | `define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27 |
| 988 | `define JBI_OPES_HI 30 |
| 989 | `define JBI_RQ_POISON 31 |
| 990 | `define JBI_ENTRY_LO 32 |
| 991 | `define JBI_ENTRY_HI 33 |
| 992 | |
| 993 | // Phase 2 : SIU Inteface and format change |
| 994 | // BS and SR 11/12/03 N2 Xbar Packet format change : |
| 995 | `define JBINST_SZ_LO 0 |
| 996 | `define JBINST_SZ_HI 7 |
| 997 | // `define JBINST_RSVD 8 NOT used |
| 998 | `define JBINST_CTAG_LO 8 |
| 999 | `define JBINST_CTAG_HI 15 |
| 1000 | `define JBINST_RQ_RD 16 |
| 1001 | `define JBINST_RQ_WR8 17 |
| 1002 | `define JBINST_RQ_WR64 18 |
| 1003 | `define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19 |
| 1004 | `define JBINST_OPES_HI 22 |
| 1005 | `define JBINST_ENTRY_LO 23 |
| 1006 | `define JBINST_ENTRY_HI 24 |
| 1007 | `define JBINST_POISON 25 |
| 1008 | |
| 1009 | |
| 1010 | `define ST_REQ_ST 1 |
| 1011 | `define LD_REQ_ST 2 |
| 1012 | `define IDLE 0 |
| 1013 | |
| 1014 | |
| 1015 | |
| 1016 | |
| 1017 | //////////////////////////////////////////////////////////////////////// |
| 1018 | // Local header file includes / local defines |
| 1019 | //////////////////////////////////////////////////////////////////////// |
| 1020 | |
| 1021 | module l2t_filbuf_ctl ( |
| 1022 | tcu_pce_ov, |
| 1023 | tcu_aclk, |
| 1024 | tcu_bclk, |
| 1025 | tcu_scan_en, |
| 1026 | rdmat_rdmard_cerr_c12, |
| 1027 | rdmat_rdmard_uerr_c12, |
| 1028 | rdmat_rdmard_notdata_c12, |
| 1029 | rdmat_ev_cerr_r6, |
| 1030 | rdmat_ev_uerr_r6, |
| 1031 | filbuf_fbtag_wr_ptr, |
| 1032 | filbuf_fbtag_wr_en, |
| 1033 | filbuf_buf_rd_en, |
| 1034 | filbuf_fbtag_rd_ptr, |
| 1035 | scan_out, |
| 1036 | filbuf_tag_evict_way_c3, |
| 1037 | filbuf_tag_hit_c2, |
| 1038 | filbuf_arb_tag_hit_frm_mb_c2, |
| 1039 | filbuf_misbuf_tag_hit_frm_mb_c2, |
| 1040 | filbuf_fbd_rd_en_c2, |
| 1041 | filbuf_fbd_rd_entry_c2, |
| 1042 | filbuf_mcu_l2t_chunk_id_r1, |
| 1043 | filbuf_mcu_l2t_data_vld_r1, |
| 1044 | filbuf_fbd_wr_entry_r1, |
| 1045 | l2t_mcu_rd_req_id, |
| 1046 | filbuf_fb_count_eq_0, |
| 1047 | filbuf_misbuf_entry_avail, |
| 1048 | filbuf_misbuf_match_c2, |
| 1049 | filbuf_misbuf_fbid_d2, |
| 1050 | filbuf_fbf_enc_ld_mbid_r1, |
| 1051 | filbuf_fbf_ready_miss_r1, |
| 1052 | filbuf_fbf_enc_dep_mbid_c4, |
| 1053 | filbuf_fbf_st_or_dep_rdy_c4, |
| 1054 | filbuf_misbuf_nofill_d2, |
| 1055 | filbuf_misbuf_stinst_match_c2, |
| 1056 | filbuf_misbuf_ue_offmode_c7, |
| 1057 | filbuf_misbuf_ce_offmode_c7, |
| 1058 | filbuf_l2d_fb_hit_c3, |
| 1059 | filbuf_vuad_bypassed_c3, |
| 1060 | filbuf_arb_l2rd_en, |
| 1061 | filbuf_arbdp_way_px2, |
| 1062 | filbuf_arbdp_tecc_px2, |
| 1063 | filbuf_arbdp_entry_px2, |
| 1064 | filbuf_arb_vld_px1, |
| 1065 | filbuf_corr_err_c8, |
| 1066 | filbuf_uncorr_err_c8, |
| 1067 | filbuf_mcu_scb_mecc_err_d1, |
| 1068 | filbuf_mcu_scb_secc_err_d1, |
| 1069 | filbuf_spc_corr_err_c6, |
| 1070 | filbuf_spc_uncorr_err_c6, |
| 1071 | filbuf_spc_rd_vld_c6, |
| 1072 | filbuf_bsc_corr_err_c12, |
| 1073 | filbuf_ld64_fb_hit_c12, |
| 1074 | filbuf_dis_cerr_c3, |
| 1075 | filbuf_dis_uerr_c3, |
| 1076 | filbuf_dis_nderr_c3, |
| 1077 | misbuf_vuad_ce_err_c8, |
| 1078 | misbuf_filbuf_next_vld_c4, |
| 1079 | misbuf_filbuf_next_link_c4, |
| 1080 | misbuf_mbf_delete_c4, |
| 1081 | misbuf_hit_c4, |
| 1082 | misbuf_mbf_insert_c4, |
| 1083 | mbdata_filbuf_mbf_entry, |
| 1084 | misbuf_filbuf_mcu_pick, |
| 1085 | misbuf_filbuf_fbid, |
| 1086 | misbuf_filbuf_way, |
| 1087 | misbuf_filbuf_way_fbid_vld, |
| 1088 | misbuf_mbf_insert_mbid_c4, |
| 1089 | mbdata_filbuf_rqtyp_d1, |
| 1090 | mbdata_filbuf_rsvd_d1, |
| 1091 | arb_decdp_imiss_inst_c2, |
| 1092 | arbdec_arbdp_inst_mb_entry_c1, |
| 1093 | arb_decdp_cas1_inst_c2, |
| 1094 | arbdec_arbdp_rdma_inst_c1, |
| 1095 | tag_misbuf_rdma_reg_vld_c2, |
| 1096 | deccck_scrd_uncorr_err_c8, |
| 1097 | deccck_scrd_corr_err_c8, |
| 1098 | deccck_bscd_corr_err_c8, |
| 1099 | deccck_bscd_uncorr_err_c8, |
| 1100 | deccck_bscd_notdata_err_c8, |
| 1101 | tagdp_tag_error_c8, |
| 1102 | tag_rd64_complete_c11, |
| 1103 | tag_cerr_ack_tmp_c4, |
| 1104 | tag_uerr_ack_tmp_c4, |
| 1105 | tag_spc_rd_cond_c3, |
| 1106 | csr_filbuf_scrub_ready, |
| 1107 | arb_filbuf_fbsel_c1, |
| 1108 | arb_fill_vld_c2, |
| 1109 | arb_filbuf_hit_off_c1, |
| 1110 | arb_inst_vld_c2_prev, |
| 1111 | arb_decdp_wr8_inst_c2, |
| 1112 | arbdec_arbdp_inst_mb_c2, |
| 1113 | arb_decdp_ld64_inst_c2, |
| 1114 | fb_cam_match, |
| 1115 | csr_l2_bypass_mode_on, |
| 1116 | csr_l2_dir_map_on, |
| 1117 | mcu_l2t_data_vld_r0, |
| 1118 | mcu_l2t_rd_req_id_r0, |
| 1119 | mcu_l2t_chunk_id_r0, |
| 1120 | mcu_l2t_secc_err_r2, |
| 1121 | mcu_l2t_mecc_err_r2, |
| 1122 | mcu_l2t_scb_mecc_err, |
| 1123 | mcu_l2t_scb_secc_err, |
| 1124 | tag_rdma_gate_off_c2, |
| 1125 | wmr_l, |
| 1126 | scan_in, |
| 1127 | l2clk, |
| 1128 | l2t_mb2_run, |
| 1129 | l2t_mb2_fbtag_wr_en, |
| 1130 | l2t_mb2_fbtag_rd_en, |
| 1131 | l2t_mb2_addr, |
| 1132 | fb_mbist_cam_hit, |
| 1133 | fb_mbist_cam_sel, |
| 1134 | mbist_run); |
| 1135 | wire pce_ov; |
| 1136 | wire stop; |
| 1137 | wire siclk; |
| 1138 | wire soclk; |
| 1139 | wire se; |
| 1140 | wire l1clk; |
| 1141 | wire spares_scanin; |
| 1142 | wire spares_scanout; |
| 1143 | wire reset_flop_scanin; |
| 1144 | wire reset_flop_scanout; |
| 1145 | wire ff_mcu_pick_d1_scanin; |
| 1146 | wire ff_mcu_pick_d1_scanout; |
| 1147 | wire [7:0] mbist_fbtag_wr_ptr; |
| 1148 | wire [2:0] l2t_mb2_addr_r3; |
| 1149 | wire ff_l2t_mb2_run_r1_scanin; |
| 1150 | wire ff_l2t_mb2_run_r1_scanout; |
| 1151 | wire l2t_mb2_fbtag_rd_en_r1; |
| 1152 | wire l2t_mb2_fbtag_rd_en_r2; |
| 1153 | wire l2t_mb2_fbtag_wr_en_r1; |
| 1154 | wire l2t_mb2_fbtag_wr_en_r2; |
| 1155 | wire [2:0] l2t_mb2_addr_r1; |
| 1156 | wire [2:0] l2t_mb2_addr_r2; |
| 1157 | wire mbist_run_r1; |
| 1158 | wire l2t_mb2_fbtag_rd_en_r3; |
| 1159 | wire fb_mbist_cam_sel_r1; |
| 1160 | wire l2t_mb2_run_r1; |
| 1161 | wire l2t_mb2_fbtag_wr_en_r3; |
| 1162 | wire ff_filbuf_misbuf_fbid_d2_scanin; |
| 1163 | wire ff_filbuf_misbuf_fbid_d2_scanout; |
| 1164 | wire ff_fill_vld_c3_scanin; |
| 1165 | wire ff_fill_vld_c3_scanout; |
| 1166 | wire ff_l2_bypass_mode_on_scanin; |
| 1167 | wire ff_l2_bypass_mode_on_scanout; |
| 1168 | wire ff_l2_dir_map_on_d1_scanin; |
| 1169 | wire ff_l2_dir_map_on_d1_scanout; |
| 1170 | wire ff_rdma_inst_c2_scanin; |
| 1171 | wire ff_rdma_inst_c2_scanout; |
| 1172 | wire rdma_inst_c2; |
| 1173 | wire ff_arb_filbuf_inst_vld_c2_scanin; |
| 1174 | wire ff_arb_filbuf_inst_vld_c2_scanout; |
| 1175 | wire arb_filbuf_inst_vld_c2; |
| 1176 | wire ff_fb_set_valid_d2_scanin; |
| 1177 | wire ff_fb_set_valid_d2_scanout; |
| 1178 | wire ff_valid_bit_scanin; |
| 1179 | wire ff_valid_bit_scanout; |
| 1180 | wire ff_fb_count_scanin; |
| 1181 | wire ff_fb_count_scanout; |
| 1182 | wire ff_rqtyp_d2_scanin; |
| 1183 | wire ff_rqtyp_d2_scanout; |
| 1184 | wire ff_snp_d2_scanin; |
| 1185 | wire ff_snp_d2_scanout; |
| 1186 | wire ff_stinst_0_scanin; |
| 1187 | wire ff_stinst_0_scanout; |
| 1188 | wire ff_stinst_1_scanin; |
| 1189 | wire ff_stinst_1_scanout; |
| 1190 | wire ff_stinst_2_scanin; |
| 1191 | wire ff_stinst_2_scanout; |
| 1192 | wire ff_stinst_3_scanin; |
| 1193 | wire ff_stinst_3_scanout; |
| 1194 | wire ff_stinst_4_scanin; |
| 1195 | wire ff_stinst_4_scanout; |
| 1196 | wire ff_stinst_5_scanin; |
| 1197 | wire ff_stinst_5_scanout; |
| 1198 | wire ff_stinst_6_scanin; |
| 1199 | wire ff_stinst_6_scanout; |
| 1200 | wire ff_stinst_7_scanin; |
| 1201 | wire ff_stinst_7_scanout; |
| 1202 | wire ff_nofill_0_scanin; |
| 1203 | wire ff_nofill_0_scanout; |
| 1204 | wire ff_nofill_1_scanin; |
| 1205 | wire ff_nofill_1_scanout; |
| 1206 | wire ff_nofill_2_scanin; |
| 1207 | wire ff_nofill_2_scanout; |
| 1208 | wire ff_nofill_3_scanin; |
| 1209 | wire ff_nofill_3_scanout; |
| 1210 | wire ff_nofill_4_scanin; |
| 1211 | wire ff_nofill_4_scanout; |
| 1212 | wire ff_nofill_5_scanin; |
| 1213 | wire ff_nofill_5_scanout; |
| 1214 | wire ff_nofill_6_scanin; |
| 1215 | wire ff_nofill_6_scanout; |
| 1216 | wire ff_nofill_7_scanin; |
| 1217 | wire ff_nofill_7_scanout; |
| 1218 | wire ff_fb_hit_off_c1_d1_scanin; |
| 1219 | wire ff_fb_hit_off_c1_d1_scanout; |
| 1220 | wire fb_hit_off_c1_d1; |
| 1221 | wire fb_mbist_cam_hit_unreg; |
| 1222 | wire ff_fb_cam_hit_vec_scanin; |
| 1223 | wire ff_fb_cam_hit_vec_scanout; |
| 1224 | wire [7:0] fb_cam_match_d1; |
| 1225 | wire filbuf_tag_hit_frm_mb_c2; |
| 1226 | wire ff_imiss_ld64_fb_hit_c3_scanin; |
| 1227 | wire ff_imiss_ld64_fb_hit_c3_scanout; |
| 1228 | wire ff_l2d_fb_hit_c3_scanin; |
| 1229 | wire ff_l2d_fb_hit_c3_scanout; |
| 1230 | wire ff_qual_hit_vec_c3_scanin; |
| 1231 | wire ff_qual_hit_vec_c3_scanout; |
| 1232 | wire ff_qual_hit_vec_c4_scanin; |
| 1233 | wire ff_qual_hit_vec_c4_scanout; |
| 1234 | wire ff_bypassed_scanin; |
| 1235 | wire ff_bypassed_scanout; |
| 1236 | wire ff_fill_entry_num_c2_scanin; |
| 1237 | wire ff_fill_entry_num_c2_scanout; |
| 1238 | wire ff_fill_entry_num_c3_scanin; |
| 1239 | wire ff_fill_entry_num_c3_scanout; |
| 1240 | wire ff_inst_vld_c3_scanin; |
| 1241 | wire ff_inst_vld_c3_scanout; |
| 1242 | wire ff_misbuf_filbuf_fbid_d1_scanin; |
| 1243 | wire ff_misbuf_filbuf_fbid_d1_scanout; |
| 1244 | wire ff_misbuf_filbuf_way_d1_scanin; |
| 1245 | wire ff_misbuf_filbuf_way_d1_scanout; |
| 1246 | wire ff_misbuf_filbuf_way_vld_d1_scanin; |
| 1247 | wire ff_misbuf_filbuf_way_vld_d1_scanout; |
| 1248 | wire ff_way0_scanin; |
| 1249 | wire ff_way0_scanout; |
| 1250 | wire ff_way1_scanin; |
| 1251 | wire ff_way1_scanout; |
| 1252 | wire ff_way2_scanin; |
| 1253 | wire ff_way2_scanout; |
| 1254 | wire ff_way3_scanin; |
| 1255 | wire ff_way3_scanout; |
| 1256 | wire ff_way4_scanin; |
| 1257 | wire ff_way4_scanout; |
| 1258 | wire ff_way5_scanin; |
| 1259 | wire ff_way5_scanout; |
| 1260 | wire ff_way6_scanin; |
| 1261 | wire ff_way6_scanout; |
| 1262 | wire ff_way7_scanin; |
| 1263 | wire ff_way7_scanout; |
| 1264 | wire ff_way_vld_scanin; |
| 1265 | wire ff_way_vld_scanout; |
| 1266 | wire ff_data_vld_r0_d1_scanin; |
| 1267 | wire ff_data_vld_r0_d1_scanout; |
| 1268 | wire ff_data_vld_r1_scanin; |
| 1269 | wire ff_data_vld_r1_scanout; |
| 1270 | wire ff_mcu_l2t_chunk_id_r0_d1_scanin; |
| 1271 | wire ff_mcu_l2t_chunk_id_r0_d1_scanout; |
| 1272 | wire ff_mcu_l2t_chunk_id_r1_scanin; |
| 1273 | wire ff_mcu_l2t_chunk_id_r1_scanout; |
| 1274 | wire ff_l2t_req_id_r0_d1_scanin; |
| 1275 | wire ff_l2t_req_id_r0_d1_scanout; |
| 1276 | wire ff_l2t_req_id_r1_scanin; |
| 1277 | wire ff_l2t_req_id_r1_scanout; |
| 1278 | wire ff_mcu_cnt_scanin; |
| 1279 | wire ff_mcu_cnt_scanout; |
| 1280 | wire mcu_count_state1; |
| 1281 | wire mcu_count_state3; |
| 1282 | wire ready_imiss_r0_d1; |
| 1283 | wire ff_cas1_inst_c3_scanin; |
| 1284 | wire ff_cas1_inst_c3_scanout; |
| 1285 | wire ff_cas1_inst_c4_scanin; |
| 1286 | wire ff_cas1_inst_c4_scanout; |
| 1287 | wire ff_fb_hit_vec_c3_scanin; |
| 1288 | wire ff_fb_hit_vec_c3_scanout; |
| 1289 | wire ff_fb_hit_vec_c4_scanin; |
| 1290 | wire ff_fb_hit_vec_c4_scanout; |
| 1291 | wire ff_fb_l2_ready_scanin; |
| 1292 | wire ff_fb_l2_ready_scanout; |
| 1293 | wire ff_l2_pick_d1_scanin; |
| 1294 | wire ff_l2_pick_d1_scanout; |
| 1295 | wire ff_l2_wait_scanin; |
| 1296 | wire ff_l2_wait_scanout; |
| 1297 | wire ff_l2_entry_px2_scanin; |
| 1298 | wire ff_l2_entry_px2_scanout; |
| 1299 | wire ff_l2_way_px2_scanin; |
| 1300 | wire ff_l2_way_px2_scanout; |
| 1301 | wire ff_mbf_entry_d2_scanin; |
| 1302 | wire ff_mbf_entry_d2_scanout; |
| 1303 | wire ff_mbid0_scanin; |
| 1304 | wire ff_mbid0_scanout; |
| 1305 | wire ff_mbid1_scanin; |
| 1306 | wire ff_mbid1_scanout; |
| 1307 | wire ff_mbid2_scanin; |
| 1308 | wire ff_mbid2_scanout; |
| 1309 | wire ff_mbid3_scanin; |
| 1310 | wire ff_mbid3_scanout; |
| 1311 | wire ff_mbid4_scanin; |
| 1312 | wire ff_mbid4_scanout; |
| 1313 | wire ff_mbid5_scanin; |
| 1314 | wire ff_mbid5_scanout; |
| 1315 | wire ff_mbid6_scanin; |
| 1316 | wire ff_mbid6_scanout; |
| 1317 | wire ff_mbid7_scanin; |
| 1318 | wire ff_mbid7_scanout; |
| 1319 | wire ff_fill_complete_c4_scanin; |
| 1320 | wire ff_fill_complete_c4_scanout; |
| 1321 | wire ff_fb_next_link_vld_scanin; |
| 1322 | wire ff_fb_next_link_vld_scanout; |
| 1323 | wire ff_enc_hit_vec_c3_scanin; |
| 1324 | wire ff_enc_hit_vec_c3_scanout; |
| 1325 | wire ff_fill_entry_c2_scanin; |
| 1326 | wire ff_fill_entry_c2_scanout; |
| 1327 | wire ff_fill_entry_c3_scanin; |
| 1328 | wire ff_fill_entry_c3_scanout; |
| 1329 | wire dbginit_l; |
| 1330 | wire ff_l2_rd_state_scanin; |
| 1331 | wire ff_l2_rd_state_scanout; |
| 1332 | wire ff_l2_rd_state_quad0_scanin; |
| 1333 | wire ff_l2_rd_state_quad0_scanout; |
| 1334 | wire ff_l2_rd_state_quad1_scanin; |
| 1335 | wire ff_l2_rd_state_quad1_scanout; |
| 1336 | wire ff_l2_rd_ptr_scanin; |
| 1337 | wire ff_l2_rd_ptr_scanout; |
| 1338 | wire ff_secc_err_r3_scanin; |
| 1339 | wire ff_secc_err_r3_scanout; |
| 1340 | wire ff_mecc_err_r3_scanin; |
| 1341 | wire ff_mecc_err_r3_scanout; |
| 1342 | wire ff_data_vld_r2_scanin; |
| 1343 | wire ff_data_vld_r2_scanout; |
| 1344 | wire ff_data_vld_r3_scanin; |
| 1345 | wire ff_data_vld_r3_scanout; |
| 1346 | wire ff_mcu_rd_req_id_r2_scanin; |
| 1347 | wire ff_mcu_rd_req_id_r2_scanout; |
| 1348 | wire ff_mcu_rd_req_id_r3_scanin; |
| 1349 | wire ff_mcu_rd_req_id_r3_scanout; |
| 1350 | wire ff_wr8_inst_c3_scanin; |
| 1351 | wire ff_wr8_inst_c3_scanout; |
| 1352 | wire ff_wr8_inst_c4_scanin; |
| 1353 | wire ff_wr8_inst_c4_scanout; |
| 1354 | wire ff_fb_cerr_scanin; |
| 1355 | wire ff_fb_cerr_scanout; |
| 1356 | wire ff_fb_uerr_scanin; |
| 1357 | wire ff_fb_uerr_scanout; |
| 1358 | wire filbuf_misbuf_ue_offmode_c3; |
| 1359 | wire filbuf_misbuf_ce_offmode_c3; |
| 1360 | wire ff_filbuf_misbuf_ue_offmode_scanin; |
| 1361 | wire ff_filbuf_misbuf_ue_offmode_scanout; |
| 1362 | wire ff_filbuf_misbuf_ce_offmode_scanin; |
| 1363 | wire ff_filbuf_misbuf_ce_offmode_scanout; |
| 1364 | wire ff_filbuf_corr_err_c4_scanin; |
| 1365 | wire ff_filbuf_corr_err_c4_scanout; |
| 1366 | wire ff_filbuf_corr_err_c5_scanin; |
| 1367 | wire ff_filbuf_corr_err_c5_scanout; |
| 1368 | wire ff_filbuf_corr_err_c52_scanin; |
| 1369 | wire ff_filbuf_corr_err_c52_scanout; |
| 1370 | wire ff_filbuf_corr_err_c6_scanin; |
| 1371 | wire ff_filbuf_corr_err_c6_scanout; |
| 1372 | wire ff_filbuf_corr_err_c7_scanin; |
| 1373 | wire ff_filbuf_corr_err_c7_scanout; |
| 1374 | wire ff_filbuf_corr_err_c8_scanin; |
| 1375 | wire ff_filbuf_corr_err_c8_scanout; |
| 1376 | wire ff_filbuf_uncorr_err_c4_scanin; |
| 1377 | wire ff_filbuf_uncorr_err_c4_scanout; |
| 1378 | wire ff_filbuf_uncorr_err_c5_scanin; |
| 1379 | wire ff_filbuf_uncorr_err_c5_scanout; |
| 1380 | wire ff_filbuf_uncorr_err_c52_scanin; |
| 1381 | wire ff_filbuf_uncorr_err_c52_scanout; |
| 1382 | wire ff_filbuf_uncorr_err_c6_scanin; |
| 1383 | wire ff_filbuf_uncorr_err_c6_scanout; |
| 1384 | wire ff_filbuf_uncorr_err_c7_scanin; |
| 1385 | wire ff_filbuf_uncorr_err_c7_scanout; |
| 1386 | wire ff_filbuf_uncorr_err_c8_scanin; |
| 1387 | wire ff_filbuf_uncorr_err_c8_scanout; |
| 1388 | wire ff_filbuf_hit_c3_scanin; |
| 1389 | wire ff_filbuf_hit_c3_scanout; |
| 1390 | wire ff_filbuf_hit_c4_scanin; |
| 1391 | wire ff_filbuf_hit_c4_scanout; |
| 1392 | wire filbuf_hit_c4; |
| 1393 | wire ff_imiss_inst_c3_scanin; |
| 1394 | wire ff_imiss_inst_c3_scanout; |
| 1395 | wire imiss_inst_c3; |
| 1396 | wire ff_imiss_inst_c4_scanin; |
| 1397 | wire ff_imiss_inst_c4_scanout; |
| 1398 | wire imiss_inst_c4; |
| 1399 | wire ff_ld64_inst_c3_scanin; |
| 1400 | wire ff_ld64_inst_c3_scanout; |
| 1401 | wire ld64_inst_c3; |
| 1402 | wire ff_spc_rd_vld_c4_scanin; |
| 1403 | wire ff_spc_rd_vld_c4_scanout; |
| 1404 | wire ff_spc_rd_vld_c5_scanin; |
| 1405 | wire ff_spc_rd_vld_c5_scanout; |
| 1406 | wire ff_spc_rd_vld_c52_scanin; |
| 1407 | wire ff_spc_rd_vld_c52_scanout; |
| 1408 | wire ff_spc_rd_vld_c6_scanin; |
| 1409 | wire ff_spc_rd_vld_c6_scanout; |
| 1410 | wire ff_fbcerr0_d1_scanin; |
| 1411 | wire ff_fbcerr0_d1_scanout; |
| 1412 | wire ff_fbuerr0_d1_scanin; |
| 1413 | wire ff_fbuerr0_d1_scanout; |
| 1414 | wire ff_spc_corr_err_c4_scanin; |
| 1415 | wire ff_spc_corr_err_c4_scanout; |
| 1416 | wire ff_spc_corr_err_c5_scanin; |
| 1417 | wire ff_spc_corr_err_c5_scanout; |
| 1418 | wire ff_spc_corr_err_c52_scanin; |
| 1419 | wire ff_spc_corr_err_c52_scanout; |
| 1420 | wire ff_spc_corr_err_c6_scanin; |
| 1421 | wire ff_spc_corr_err_c6_scanout; |
| 1422 | wire ff_spc_uncorr_err_c4_scanin; |
| 1423 | wire ff_spc_uncorr_err_c4_scanout; |
| 1424 | wire ff_spc_uncorr_err_c5_scanin; |
| 1425 | wire ff_spc_uncorr_err_c5_scanout; |
| 1426 | wire ff_spc_uncorr_err_c52_scanin; |
| 1427 | wire ff_spc_uncorr_err_c52_scanout; |
| 1428 | wire ff_spc_uncorr_err_c6_scanin; |
| 1429 | wire ff_spc_uncorr_err_c6_scanout; |
| 1430 | wire ff_bsc_corr_err_c4_scanin; |
| 1431 | wire ff_bsc_corr_err_c4_scanout; |
| 1432 | wire bsc_corr_err_c4; |
| 1433 | wire ff_bsc_corr_err_c5_scanin; |
| 1434 | wire ff_bsc_corr_err_c5_scanout; |
| 1435 | wire bsc_corr_err_c5; |
| 1436 | wire ff_bsc_corr_err_c52_scanin; |
| 1437 | wire ff_bsc_corr_err_c52_scanout; |
| 1438 | wire bsc_corr_err_c52; |
| 1439 | wire ff_bsc_corr_err_c6_scanin; |
| 1440 | wire ff_bsc_corr_err_c6_scanout; |
| 1441 | wire bsc_corr_err_c6; |
| 1442 | wire ff_bsc_corr_err_c7_scanin; |
| 1443 | wire ff_bsc_corr_err_c7_scanout; |
| 1444 | wire bsc_corr_err_c7; |
| 1445 | wire ff_bsc_corr_err_c8_scanin; |
| 1446 | wire ff_bsc_corr_err_c8_scanout; |
| 1447 | wire bsc_corr_err_c8; |
| 1448 | wire ff_bsc_corr_err_c9_scanin; |
| 1449 | wire ff_bsc_corr_err_c9_scanout; |
| 1450 | wire bsc_corr_err_c9; |
| 1451 | wire ff_bsc_corr_err_c10_scanin; |
| 1452 | wire ff_bsc_corr_err_c10_scanout; |
| 1453 | wire bsc_corr_err_c10; |
| 1454 | wire ff_bsc_corr_err_c11_scanin; |
| 1455 | wire ff_bsc_corr_err_c11_scanout; |
| 1456 | wire bsc_corr_err_c11; |
| 1457 | wire ff_bsc_corr_err_c12_scanin; |
| 1458 | wire ff_bsc_corr_err_c12_scanout; |
| 1459 | wire bsc_corr_err_c12; |
| 1460 | wire ff_ld64_fb_hit_c4_scanin; |
| 1461 | wire ff_ld64_fb_hit_c4_scanout; |
| 1462 | wire ld64_fb_hit_c4; |
| 1463 | wire ff_ld64_fb_hit_c5_scanin; |
| 1464 | wire ff_ld64_fb_hit_c5_scanout; |
| 1465 | wire ld64_fb_hit_c5; |
| 1466 | wire ff_ld64_fb_hit_c52_scanin; |
| 1467 | wire ff_ld64_fb_hit_c52_scanout; |
| 1468 | wire ld64_fb_hit_c52; |
| 1469 | wire ff_ld64_fb_hit_c6_scanin; |
| 1470 | wire ff_ld64_fb_hit_c6_scanout; |
| 1471 | wire ld64_fb_hit_c6; |
| 1472 | wire ff_ld64_fb_hit_c7_scanin; |
| 1473 | wire ff_ld64_fb_hit_c7_scanout; |
| 1474 | wire ld64_fb_hit_c7; |
| 1475 | wire ff_ld64_fb_hit_c8_scanin; |
| 1476 | wire ff_ld64_fb_hit_c8_scanout; |
| 1477 | wire ld64_fb_hit_c8; |
| 1478 | wire ff_ld64_fb_hit_c9_scanin; |
| 1479 | wire ff_ld64_fb_hit_c9_scanout; |
| 1480 | wire ld64_fb_hit_c9; |
| 1481 | wire ff_ld64_fb_hit_c10_scanin; |
| 1482 | wire ff_ld64_fb_hit_c10_scanout; |
| 1483 | wire ld64_fb_hit_c10; |
| 1484 | wire ff_ld64_fb_hit_c11_scanin; |
| 1485 | wire ff_ld64_fb_hit_c11_scanout; |
| 1486 | wire ld64_fb_hit_c11; |
| 1487 | wire ff_ld64_fb_hit_c12_scanin; |
| 1488 | wire ff_ld64_fb_hit_c12_scanout; |
| 1489 | wire ld64_fb_hit_c12; |
| 1490 | wire ff_mcu_scb_mecc_err_d1_scanin; |
| 1491 | wire ff_mcu_scb_mecc_err_d1_scanout; |
| 1492 | wire ff_mcu_scb_secc_err_d1_scanin; |
| 1493 | wire ff_mcu_scb_secc_err_d1_scanout; |
| 1494 | wire ff_fb_uerr_pend_scanin; |
| 1495 | wire ff_fb_uerr_pend_scanout; |
| 1496 | wire fb_nduerr_pend_set; |
| 1497 | wire fb_nduerr_pend_reset; |
| 1498 | wire fb_nduerr_pend_in; |
| 1499 | wire fb_nduerr_pend; |
| 1500 | wire ff_fb_nduerr_pend_scanin; |
| 1501 | wire ff_fb_nduerr_pend_scanout; |
| 1502 | wire ff_fb_cerr_pend_scanin; |
| 1503 | wire ff_fb_cerr_pend_scanout; |
| 1504 | wire fb_ndcerr_pend_set; |
| 1505 | wire fb_ndcerr_pend_reset; |
| 1506 | wire fb_ndcerr_pend_in; |
| 1507 | wire fb_ndcerr_pend; |
| 1508 | wire ff_fb_ndcerr_pend_scanin; |
| 1509 | wire ff_fb_ndcerr_pend_scanout; |
| 1510 | wire ff_fb_tecc_pend_scanin; |
| 1511 | wire ff_fb_tecc_pend_scanout; |
| 1512 | wire ff_fb_tecc_pend_d1_scanin; |
| 1513 | wire ff_fb_tecc_pend_d1_scanout; |
| 1514 | |
| 1515 | |
| 1516 | input tcu_pce_ov; |
| 1517 | input tcu_aclk; |
| 1518 | input tcu_bclk; |
| 1519 | input tcu_scan_en; |
| 1520 | |
| 1521 | // from rdmat. |
| 1522 | input rdmat_rdmard_cerr_c12; |
| 1523 | input rdmat_rdmard_uerr_c12; |
| 1524 | input rdmat_rdmard_notdata_c12; |
| 1525 | input rdmat_ev_cerr_r6; |
| 1526 | input rdmat_ev_uerr_r6; |
| 1527 | // to fbtag. |
| 1528 | output [7:0] filbuf_fbtag_wr_ptr; // PH1 write. |
| 1529 | output filbuf_fbtag_wr_en; // PH1 write. |
| 1530 | output filbuf_buf_rd_en; // to fbtag. |
| 1531 | output [7:0] filbuf_fbtag_rd_ptr ; // to fbtag. |
| 1532 | output scan_out; |
| 1533 | |
| 1534 | // to tag |
| 1535 | output [3:0] filbuf_tag_evict_way_c3;// BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Miss |
| 1536 | output filbuf_tag_hit_c2 ; |
| 1537 | output filbuf_arb_tag_hit_frm_mb_c2; |
| 1538 | output filbuf_misbuf_tag_hit_frm_mb_c2; |
| 1539 | output filbuf_fbd_rd_en_c2; // to fbdata via tag |
| 1540 | output [2:0] filbuf_fbd_rd_entry_c2; // to fbdata via tag |
| 1541 | output [1:0] filbuf_mcu_l2t_chunk_id_r1; // to tag |
| 1542 | output filbuf_mcu_l2t_data_vld_r1; // to tag |
| 1543 | output [2:0] filbuf_fbd_wr_entry_r1 ; |
| 1544 | |
| 1545 | // to mcu |
| 1546 | output [2:0] l2t_mcu_rd_req_id ; |
| 1547 | |
| 1548 | // to misbuf. |
| 1549 | output filbuf_fb_count_eq_0; // to misbuf for csr inst ready |
| 1550 | output filbuf_misbuf_entry_avail ; // to misbuf for mcu pick |
| 1551 | output filbuf_misbuf_match_c2; // to misbuf for eviction and |
| 1552 | output [2:0] filbuf_misbuf_fbid_d2; |
| 1553 | output [4:0] filbuf_fbf_enc_ld_mbid_r1; // BS & SR 11/04/03, MB grows to 32 |
| 1554 | output filbuf_fbf_ready_miss_r1; |
| 1555 | output [4:0] filbuf_fbf_enc_dep_mbid_c4; // BS & SR 11/04/03, MB grows to 32 |
| 1556 | output filbuf_fbf_st_or_dep_rdy_c4; |
| 1557 | output filbuf_misbuf_nofill_d2; // to misbuf |
| 1558 | output filbuf_misbuf_stinst_match_c2; // NEW_PIN |
| 1559 | output filbuf_misbuf_ue_offmode_c7; |
| 1560 | output filbuf_misbuf_ce_offmode_c7; |
| 1561 | |
| 1562 | // to l2d |
| 1563 | output filbuf_l2d_fb_hit_c3; // used in C5 to select between |
| 1564 | |
| 1565 | // to vuad dp |
| 1566 | output filbuf_vuad_bypassed_c3; |
| 1567 | |
| 1568 | |
| 1569 | // to arb |
| 1570 | output filbuf_arb_l2rd_en; // to arbaddr |
| 1571 | output [3:0] filbuf_arbdp_way_px2; // goes to arb and arbdec. |
| 1572 | output filbuf_arbdp_tecc_px2; |
| 1573 | output [2:0] filbuf_arbdp_entry_px2; |
| 1574 | output filbuf_arb_vld_px1; // to arb |
| 1575 | |
| 1576 | // to csr |
| 1577 | output filbuf_corr_err_c8 ; // to csr |
| 1578 | output filbuf_uncorr_err_c8 ; // to csr |
| 1579 | output filbuf_mcu_scb_mecc_err_d1; |
| 1580 | output filbuf_mcu_scb_secc_err_d1; |
| 1581 | |
| 1582 | // to decc will take c6 for timing reasons |
| 1583 | //output filbuf_spc_corr_err_c7; // to decc |
| 1584 | //output filbuf_spc_uncorr_err_c7; // to decc |
| 1585 | //output filbuf_spc_rd_vld_c7; // to decc |
| 1586 | output filbuf_spc_corr_err_c6; // to decc |
| 1587 | output filbuf_spc_uncorr_err_c6; // to decc |
| 1588 | output filbuf_spc_rd_vld_c6; // to decc |
| 1589 | |
| 1590 | |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | output filbuf_bsc_corr_err_c12; // to decc NEW_PIN |
| 1595 | output filbuf_ld64_fb_hit_c12; // to decc NEW_PIN |
| 1596 | |
| 1597 | // to oqu. |
| 1598 | output filbuf_dis_cerr_c3; |
| 1599 | output filbuf_dis_uerr_c3; |
| 1600 | output [1:0] filbuf_dis_nderr_c3; |
| 1601 | |
| 1602 | // from misbuf |
| 1603 | input misbuf_vuad_ce_err_c8; |
| 1604 | input misbuf_filbuf_next_vld_c4; |
| 1605 | input [4:0] misbuf_filbuf_next_link_c4; // BS & SR 11/04/03, MB grows to 32 |
| 1606 | input misbuf_mbf_delete_c4; |
| 1607 | input misbuf_hit_c4; |
| 1608 | input misbuf_mbf_insert_c4; |
| 1609 | input [4:0] mbdata_filbuf_mbf_entry; // BS & SR 11/04/03, MB grows to 32 |
| 1610 | input misbuf_filbuf_mcu_pick; |
| 1611 | input [2:0] misbuf_filbuf_fbid; |
| 1612 | input [3:0] misbuf_filbuf_way ; |
| 1613 | input misbuf_filbuf_way_fbid_vld ; |
| 1614 | input [4:0] misbuf_mbf_insert_mbid_c4; // BS & SR 11/04/03, MB grows to 32 |
| 1615 | |
| 1616 | // from mbdata. |
| 1617 | input [4:0] mbdata_filbuf_rqtyp_d1; // from mbdata. |
| 1618 | input mbdata_filbuf_rsvd_d1; // RSVD bit from mbdata |
| 1619 | |
| 1620 | // from arbdec |
| 1621 | input arb_decdp_imiss_inst_c2; |
| 1622 | // int 5.0 changes |
| 1623 | // input arb_decdp_ld_inst_c2; // NEW_PIN |
| 1624 | input [2:0] arbdec_arbdp_inst_mb_entry_c1; |
| 1625 | |
| 1626 | input arb_decdp_cas1_inst_c2;// from arbdec |
| 1627 | |
| 1628 | |
| 1629 | input arbdec_arbdp_rdma_inst_c1; // POST_3.0 pin From arbdec Left |
| 1630 | input tag_misbuf_rdma_reg_vld_c2; // POST_3.0 pin from tag Bottom. |
| 1631 | |
| 1632 | // from decc. |
| 1633 | input deccck_scrd_uncorr_err_c8; |
| 1634 | input deccck_scrd_corr_err_c8; |
| 1635 | input deccck_bscd_corr_err_c8; |
| 1636 | input deccck_bscd_uncorr_err_c8; |
| 1637 | input deccck_bscd_notdata_err_c8; |
| 1638 | |
| 1639 | // from tagd |
| 1640 | input tagdp_tag_error_c8; // from tagd/ |
| 1641 | |
| 1642 | // from tag |
| 1643 | input tag_rd64_complete_c11; // from tag. NEW_PIN |
| 1644 | input tag_cerr_ack_tmp_c4; |
| 1645 | input tag_uerr_ack_tmp_c4; // POST_2.0 pins |
| 1646 | input tag_spc_rd_cond_c3; // POST_3.2 pins |
| 1647 | |
| 1648 | |
| 1649 | // from csr block |
| 1650 | input csr_filbuf_scrub_ready ; |
| 1651 | |
| 1652 | // from arb |
| 1653 | input arb_filbuf_fbsel_c1; // from arb |
| 1654 | input arb_fill_vld_c2; |
| 1655 | input arb_filbuf_hit_off_c1; // from arb. used to disable hits. |
| 1656 | //input arb_filbuf_inst_vld_c2; |
| 1657 | input arb_inst_vld_c2_prev; |
| 1658 | input arb_decdp_wr8_inst_c2; |
| 1659 | |
| 1660 | // from arbdec |
| 1661 | input arbdec_arbdp_inst_mb_c2 ; |
| 1662 | input arb_decdp_ld64_inst_c2; |
| 1663 | |
| 1664 | |
| 1665 | // from fbtag |
| 1666 | input [7:0] fb_cam_match; |
| 1667 | |
| 1668 | // from csr |
| 1669 | input csr_l2_bypass_mode_on ; |
| 1670 | input csr_l2_dir_map_on ; // NEW_PIN |
| 1671 | |
| 1672 | // from BTU |
| 1673 | input mcu_l2t_data_vld_r0; // data vld r0 |
| 1674 | input [2:0] mcu_l2t_rd_req_id_r0 ; // req id r0 |
| 1675 | input [1:0] mcu_l2t_chunk_id_r0; // 16B chunk address. |
| 1676 | input mcu_l2t_secc_err_r2; |
| 1677 | input mcu_l2t_mecc_err_r2; |
| 1678 | input mcu_l2t_scb_mecc_err; |
| 1679 | input mcu_l2t_scb_secc_err; |
| 1680 | |
| 1681 | // from scbug.evict |
| 1682 | |
| 1683 | // from filbuf. |
| 1684 | input tag_rdma_gate_off_c2; |
| 1685 | |
| 1686 | input wmr_l; |
| 1687 | input scan_in; |
| 1688 | input l2clk; |
| 1689 | |
| 1690 | // mbist |
| 1691 | input l2t_mb2_run; |
| 1692 | input l2t_mb2_fbtag_wr_en; |
| 1693 | input l2t_mb2_fbtag_rd_en; |
| 1694 | input [2:0] l2t_mb2_addr; |
| 1695 | output fb_mbist_cam_hit; |
| 1696 | input fb_mbist_cam_sel; |
| 1697 | |
| 1698 | input mbist_run; |
| 1699 | |
| 1700 | wire mcu_pick_d1; |
| 1701 | wire [7:0] fb_wr_ptr_d1; |
| 1702 | wire [2:0] enc_wr_ptr_d1; |
| 1703 | wire [7:0] clear_err_c3; |
| 1704 | |
| 1705 | wire filbuf_misbuf_ue_offmode_c4,filbuf_misbuf_ue_offmode_c5,filbuf_misbuf_ue_offmode_c52; |
| 1706 | wire filbuf_misbuf_ue_offmode_c6; |
| 1707 | |
| 1708 | wire filbuf_misbuf_ce_offmode_c4,filbuf_misbuf_ce_offmode_c5,filbuf_misbuf_ce_offmode_c52; |
| 1709 | wire filbuf_misbuf_ce_offmode_c6; |
| 1710 | |
| 1711 | |
| 1712 | // fb control bits. |
| 1713 | wire [7:0] fb_set_valid, fb_valid_prev , fb_valid ; |
| 1714 | wire [7:0] fb_stinst; |
| 1715 | wire [7:0] fb_nofill; |
| 1716 | wire [7:0] fb_l2_ready_in, fb_l2_ready; |
| 1717 | wire [7:0] fb_bypassed_in, fb_bypassed ; |
| 1718 | wire [3:0] way0, way1, way2, way3; |
| 1719 | wire [3:0] way4, way5, way6, way7; |
| 1720 | wire [7:0] fb_way_vld_in, fb_way_vld; |
| 1721 | wire [4:0] mbid0, mbid1, mbid2, mbid3; // BS & SR 11/04/03, MB grows to 32 |
| 1722 | wire [4:0] mbid4, mbid5, mbid6, mbid7; // BS & SR 11/04/03, MB grows to 32 |
| 1723 | wire [7:0] fb_next_link_vld_in, fb_next_link_vld; |
| 1724 | wire [7:0] fb_cerr, fb_uerr ; |
| 1725 | wire fb_cerr_pend; |
| 1726 | wire fb_uerr_pend; |
| 1727 | wire fb_tecc_pend; |
| 1728 | |
| 1729 | // SR Changes for new MCU protocol 4/8/04 |
| 1730 | wire fb_imissinst_d2; |
| 1731 | wire [7:0] fb_imissinst; |
| 1732 | wire [1:0] ff_stinst_din_input; |
| 1733 | |
| 1734 | |
| 1735 | |
| 1736 | wire [7:0] fill_entry_num_c3, fill_complete_c3, fill_complete_c4; |
| 1737 | wire fill_vld_c3 ; |
| 1738 | wire fb_count_en, fb_count_rst; |
| 1739 | wire [3:0] fb_count_prev, fb_count_plus1, fb_count_minus1 ; |
| 1740 | wire [3:0] fb_count; |
| 1741 | |
| 1742 | wire [4:0] mbf_rqtyp_d2; |
| 1743 | wire [7:0] fb_set_valid_d2; |
| 1744 | wire fb_stinst_d2; |
| 1745 | |
| 1746 | wire l2_bypass_mode_on_d1 ; |
| 1747 | wire [2:0] misbuf_filbuf_fbid_d1; |
| 1748 | wire [3:0] misbuf_filbuf_way_d1 ; |
| 1749 | wire misbuf_filbuf_way_vld_d1 ; |
| 1750 | wire [7:0] dec_mb_fb_id_d1; |
| 1751 | |
| 1752 | wire [7:0] fb_hit_vec_c2 ; |
| 1753 | wire imiss_ld64_fb_hit_c2, imiss_ld64_fb_hit_c3 ; |
| 1754 | |
| 1755 | wire [1:0] mcu_return_cnt, mcu_return_cnt_plus1 ; |
| 1756 | wire mcu_cnt_reset; |
| 1757 | wire mcu_data_vld_r1; |
| 1758 | wire [2:0] mcu_rd_req_id_r1; |
| 1759 | wire cas1_inst_c3, cas1_inst_c4; |
| 1760 | wire mcu_count_state0, mcu_count_state2 ; |
| 1761 | wire [7:0] fb_hit_vec_c3, fb_hit_vec_c4 ; |
| 1762 | wire [7:0] dec_rdreq_id_r0_d1; |
| 1763 | |
| 1764 | wire dep_ptr_wr_en_c4, non_dep_mbf_insert_c4; |
| 1765 | wire [7:0] dep_wr_ptr_c4, non_dep_wr_ptr_c4; |
| 1766 | wire [4:0] mbf_entry_d2; // BS & SR 11/04/03, MB grows to 32 |
| 1767 | wire [7:0] sel_def_mbid; |
| 1768 | |
| 1769 | |
| 1770 | wire [4:0] mbid0_in, mbid1_in, mbid2_in, mbid3_in; // BS & SR 11/04/03, MB grows to 32 |
| 1771 | wire [4:0] mbid4_in, mbid5_in, mbid6_in, mbid7_in;// BS & SR 11/04/03, MB grows to 32 |
| 1772 | |
| 1773 | wire [7:0] fb_l2_rd_ptr_in; |
| 1774 | wire [7:0] fb_l2_rd_ptr; |
| 1775 | |
| 1776 | wire [4:0] mux1_mbid_r1, mux2_mbid_r1 ; // BS & SR 11/04/03, MB grows to 32 |
| 1777 | wire [4:0] mux1_dep_mbid_c4, mux2_dep_mbid_c4 ; // BS & SR 11/04/03, MB grows to 32 |
| 1778 | wire ready_ld_r0_d1 ; |
| 1779 | wire fill_entry_0to3_c4 ; |
| 1780 | wire [7:0] fill_entry_num_c1, fill_entry_num_c2 ; |
| 1781 | |
| 1782 | wire pick_s0, pick_s1, pick_s2, pick_s3 ; |
| 1783 | wire pick_s0_quad0, pick_s1_quad0, pick_s2_quad0, pick_s3_quad0 ; |
| 1784 | wire pick_s0_quad1, pick_s1_quad1, pick_s2_quad1, pick_s3_quad1 ; |
| 1785 | wire pick_quad_s0, pick_quad_s1 ; |
| 1786 | |
| 1787 | wire [3:0] pick_quad0_in, pick_quad1_in ; |
| 1788 | wire [1:0] pick_quad_in ; |
| 1789 | wire [3:0] pick_quad0_sel, pick_quad1_sel; |
| 1790 | wire [1:0] pick_quad_sel; // int 5.0 |
| 1791 | |
| 1792 | wire [7:0] l2_pick_vec; |
| 1793 | wire l2_pick, l2_pick_d1 ; |
| 1794 | wire l2_wait_in, l2_wait; |
| 1795 | |
| 1796 | wire init_pick_state; |
| 1797 | wire sel_l2st_lshift, sel_l2st_same; |
| 1798 | wire [3:0] l2_rd_state_lshift, l2_rd_state_in, l2_rd_state ; |
| 1799 | |
| 1800 | wire sel_l2st_lshift_quad0, sel_l2st_same_quad0; |
| 1801 | wire [3:0] l2_rd_state_lshift_quad0, l2_rd_state_in_quad0, l2_rd_state_quad0 ; |
| 1802 | |
| 1803 | wire sel_l2st_lshift_quad1, sel_l2st_same_quad1; |
| 1804 | wire [3:0] l2_rd_state_lshift_quad1, l2_rd_state_in_quad1, l2_rd_state_quad1 ; |
| 1805 | |
| 1806 | wire [2:0] enc_l2_rd_ptr ; |
| 1807 | wire [3:0] mux1_way, mux2_way, fill_way ; |
| 1808 | |
| 1809 | wire l2t_l2d_fb_hit_c2; // used in C5 to select between |
| 1810 | wire sel_c2_entry; |
| 1811 | wire [2:0] fb_rd_entry_c2; |
| 1812 | wire [2:0] enc_hit_vec_c2, enc_hit_vec_c3 ; |
| 1813 | wire [2:0] fill_entry_c2; |
| 1814 | |
| 1815 | wire mecc_err_r3, secc_err_r3; |
| 1816 | wire filbuf_corr_err_c3, filbuf_corr_err_c4, filbuf_corr_err_c5, filbuf_corr_err_c52; // BS 03/11/04 extra cycle for mem access |
| 1817 | wire filbuf_corr_err_c6, filbuf_corr_err_c7 ; |
| 1818 | wire filbuf_uncorr_err_c3, filbuf_uncorr_err_c4, filbuf_uncorr_err_c5, filbuf_uncorr_err_c52; // BS 03/11/04 extra cycle for mem access |
| 1819 | wire filbuf_uncorr_err_c6, filbuf_uncorr_err_c7 ; |
| 1820 | wire mcu_data_vld_r2, mcu_data_vld_r3 ; |
| 1821 | wire [2:0] mcu_rd_req_id_r2, mcu_rd_req_id_r3 ; |
| 1822 | wire [7:0] fb_cerr_in, fb_uerr_in ; |
| 1823 | wire [7:0] fb_cerr_prev, fb_uerr_prev ; |
| 1824 | |
| 1825 | wire filbuf_hit_c3; |
| 1826 | wire spc_rd_vld_c3; |
| 1827 | wire spc_rd_vld_c4, spc_rd_vld_c5 , spc_rd_vld_c52 ; // BS 03/11/04 extra cycle for mem access |
| 1828 | wire spc_rd_vld_c6, spc_rd_vld_c7 ; |
| 1829 | wire spc_corr_err_c3, spc_corr_err_c4, spc_corr_err_c5, spc_corr_err_c52; // BS 03/11/04 extra cycle for mem access |
| 1830 | wire spc_corr_err_c6, spc_corr_err_c7 ; |
| 1831 | wire spc_uncorr_err_c3, spc_uncorr_err_c4, spc_uncorr_err_c5, spc_uncorr_err_c52 ; // BS 03/11/04 extra cycle for mem access |
| 1832 | wire spc_uncorr_err_c6, spc_uncorr_err_c7 ; |
| 1833 | wire fb_uerr_pend_set, fb_uerr_pend_reset, fb_uerr_pend_in ; |
| 1834 | wire fb_cerr_pend_set, fb_cerr_pend_reset, fb_cerr_pend_in ; |
| 1835 | wire fb_tecc_pend_set, fb_tecc_pend_reset; |
| 1836 | wire fb_tecc_pend_in; |
| 1837 | |
| 1838 | wire filbuf_hit_c2; |
| 1839 | wire fb_nofill_d2; |
| 1840 | |
| 1841 | wire [7:0] no_fill_entry_dequeue_c3; |
| 1842 | wire en_dequeue_c3; |
| 1843 | wire en_hit_dequeue_c2; |
| 1844 | wire ready_ld64_r0_d1; |
| 1845 | wire mbf_rsvd_d2; |
| 1846 | wire fb_nofill_rst; |
| 1847 | wire qual_hit_vec_c2, qual_hit_vec_c3, qual_hit_vec_c4; |
| 1848 | |
| 1849 | wire [7:0] dep_wr_qual_c4; |
| 1850 | |
| 1851 | wire [2:0] fill_entry_c3; |
| 1852 | wire sel_c2_fill_entry; |
| 1853 | wire sel_c3_fill_entry; |
| 1854 | wire sel_def_hit_entry_mux1; |
| 1855 | wire l2_dir_map_on_d1; |
| 1856 | wire mcu_data_vld_r0_d1; |
| 1857 | |
| 1858 | wire [1:0] mcu_l2t_chunk_id_r0_d1; |
| 1859 | wire [2:0] mcu_rd_req_id_r0_d1; |
| 1860 | wire fbhit_cerr_err_c3, fbhit_uerr_err_c3 ; |
| 1861 | wire bsc_corr_err_c3, ld64_fb_hit_c3; |
| 1862 | wire wr8_inst_c3, wr8_inst_c4; |
| 1863 | wire dbb_rst_l; |
| 1864 | wire [7:0] dec_fill_entry_c3; |
| 1865 | wire cerr_ack_c4, uerr_ack_c4 ; |
| 1866 | wire inst_vld_c3; |
| 1867 | wire fbcerr0_d1, fbuerr0_d1; |
| 1868 | |
| 1869 | |
| 1870 | wire [7:0] fill_complete_sel ; |
| 1871 | wire fill_complete_4to7_def, fill_complete_0to3_def ; |
| 1872 | wire [7:0] fb_l2_rd_ptr_sel; |
| 1873 | wire way_mux1_def, way_mux2_def ; |
| 1874 | wire rdreq_0to3_def, rdreq_4to7_def ; |
| 1875 | |
| 1876 | wire [7:0] dep_wr_ptr_c4_rst, non_dep_wr_ptr_c4_rst; |
| 1877 | wire [7:0] fb_set_valid_d2_rst; |
| 1878 | wire fb_tecc_pend_d1; |
| 1879 | reg [3:0] filbuf_tag_evict_way_c3; |
| 1880 | |
| 1881 | |
| 1882 | ////////////////////////////////////////////////// |
| 1883 | // L1 clk header |
| 1884 | ////////////////////////////////////////////////// |
| 1885 | assign pce_ov = tcu_pce_ov; |
| 1886 | assign stop = 1'b0; |
| 1887 | assign siclk = tcu_aclk; |
| 1888 | assign soclk = tcu_bclk; |
| 1889 | assign se = tcu_scan_en; |
| 1890 | |
| 1891 | l2t_filbuf_ctl_l1clkhdr_ctl_macro clkgen ( |
| 1892 | .l2clk(l2clk), |
| 1893 | .l1en(1'b1 ), |
| 1894 | .l1clk(l1clk), |
| 1895 | .pce_ov(pce_ov), |
| 1896 | .stop(stop), |
| 1897 | .se(se)); |
| 1898 | |
| 1899 | ////////////////////////////////////////////////// |
| 1900 | |
| 1901 | ////////////////////////////////////////// |
| 1902 | // Spare gate insertion |
| 1903 | ////////////////////////////////////////// |
| 1904 | l2t_filbuf_ctl_spare_ctl_macro__num_6 spares ( |
| 1905 | .scan_in(spares_scanin), |
| 1906 | .scan_out(spares_scanout), |
| 1907 | .l1clk (l1clk), |
| 1908 | .siclk(siclk), |
| 1909 | .soclk(soclk) |
| 1910 | ); |
| 1911 | ////////////////////////////////////////// |
| 1912 | |
| 1913 | |
| 1914 | |
| 1915 | //////////////////////////////////////////////////////////////////////////////// |
| 1916 | // L2 OFF MODE : |
| 1917 | // |
| 1918 | // The RTL for filbuf contains the following exceptions to handle off mode operation. |
| 1919 | // |
| 1920 | // 1) A non Store, non LD64 entry is invalidated in C2 on a Fill Buffer hit. |
| 1921 | // stores have to be kept around to write to DRAM, LD64s turn the valid bit |
| 1922 | // of in C3( they can afford to do so due to the access bubbles following a ld64). |
| 1923 | // |
| 1924 | // 2) Fill Buffer is one deep only |
| 1925 | // |
| 1926 | // 3) fb_l2_ready is set only in the following case, |
| 1927 | // A non CAS1 instruction hitting an entry with fb_stinst =1 . |
| 1928 | // |
| 1929 | // 4) Fill does not wake up stores by default. It only wakes up |
| 1930 | // dependent instructions in the Miss Buffer. |
| 1931 | // |
| 1932 | // 5) dep wr enable is asserted only if an instruction( other than a CAS1) hits |
| 1933 | // a Fill Buffer entry with fb_stinst=1. |
| 1934 | // |
| 1935 | // 6) Fill Pipeline is skewed by one cycle. |
| 1936 | // |
| 1937 | // 7) In l2_bypass_mode, the way_vld bit is not required to be set. |
| 1938 | // for an l2_pick |
| 1939 | //////////////////////////////////////////////////////////////////////////////// |
| 1940 | //////////////////////////////////////////////////////////////////////////////// |
| 1941 | // L2 DIR MAP MODE ON |
| 1942 | // |
| 1943 | // This mode is different from the regular mode of operation in the following |
| 1944 | // ways |
| 1945 | // - Loads/Imisses are not readied by the second incoming packet of data from the |
| 1946 | // mcu. Check the expression for ready_miss_r1 |
| 1947 | // - Loads/Imisses are readied similar to stores, i.e. after a Fill. |
| 1948 | //////////////////////////////////////////////////////////////////////////////// |
| 1949 | |
| 1950 | /////////////////////////////////////////////////////////////////// |
| 1951 | // Reset flop |
| 1952 | /////////////////////////////////////////////////////////////////// |
| 1953 | |
| 1954 | l2t_filbuf_ctl_msff_ctl_macro__width_1 reset_flop |
| 1955 | (.dout(dbb_rst_l), |
| 1956 | .scan_in(reset_flop_scanin), |
| 1957 | .scan_out(reset_flop_scanout), |
| 1958 | .l1clk(l1clk), |
| 1959 | .din(wmr_l), |
| 1960 | .siclk(siclk), |
| 1961 | .soclk(soclk) |
| 1962 | |
| 1963 | ); |
| 1964 | |
| 1965 | |
| 1966 | //////////////////////////////////////////////////////////////////////////////// |
| 1967 | // Fill Buffer Insertion Pipeline. |
| 1968 | // The Fill Buffer (FB) is inserted when a Miss Buffer is read for making |
| 1969 | // a request to DRAM. The following pipeline is used for FB insertion |
| 1970 | // |
| 1971 | //------------------------------------------------------------------------------ |
| 1972 | // D0 D1 D2 |
| 1973 | //------------------------------------------------------------------------------ |
| 1974 | // mcu pick (misbuf) read mbtag write fbtag+ecc |
| 1975 | // |
| 1976 | // read mbdata |
| 1977 | // for rqtyp and tag ecc write "stinst" |
| 1978 | // write insert mbid |
| 1979 | // |
| 1980 | // xmit mcu pick generate wr ptr fb_entry_avail |
| 1981 | // to filbuf. xmit to fbtag. logic |
| 1982 | // |
| 1983 | // xmit mcu_pickd1 xmit inserting |
| 1984 | // as wen to fbtag. fbid to mbf |
| 1985 | // |
| 1986 | // set valid bit xmit addr(arbadr) |
| 1987 | // xmit req id (filbuf) |
| 1988 | // update fbcount xmit req ( misbuf). |
| 1989 | // |
| 1990 | // |
| 1991 | //------------------------------------------------------------------------------ |
| 1992 | //////////////////////////////////////////////////////////////////////////////// |
| 1993 | |
| 1994 | ////////////////// |
| 1995 | // 1. Generation of insertion ptr |
| 1996 | // and wen for fbtag. |
| 1997 | ////////////////// |
| 1998 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_mcu_pick_d1 |
| 1999 | (.din(misbuf_filbuf_mcu_pick), .l1clk(l1clk), |
| 2000 | .scan_in(ff_mcu_pick_d1_scanin), |
| 2001 | .scan_out(ff_mcu_pick_d1_scanout), |
| 2002 | .dout(mcu_pick_d1), |
| 2003 | .siclk(siclk), |
| 2004 | .soclk(soclk) |
| 2005 | ); |
| 2006 | |
| 2007 | assign fb_wr_ptr_d1[0] = ~fb_valid[0] ; |
| 2008 | assign fb_wr_ptr_d1[1] = fb_valid[0] & ~fb_valid[1]; |
| 2009 | assign fb_wr_ptr_d1[2] = &(fb_valid[1:0]) & ~fb_valid[2] ; |
| 2010 | assign fb_wr_ptr_d1[3] = &(fb_valid[2:0]) & ~fb_valid[3] ; |
| 2011 | assign fb_wr_ptr_d1[4] = &(fb_valid[3:0]) & ~fb_valid[4] ; |
| 2012 | assign fb_wr_ptr_d1[5] = &(fb_valid[4:0]) & ~fb_valid[5] ; |
| 2013 | assign fb_wr_ptr_d1[6] = &(fb_valid[5:0]) & ~fb_valid[6] ; |
| 2014 | assign fb_wr_ptr_d1[7] = &(fb_valid[6:0]) & ~fb_valid[7] ; |
| 2015 | |
| 2016 | |
| 2017 | assign mbist_fbtag_wr_ptr[0] = (l2t_mb2_addr_r3[2:0]==3'h0); |
| 2018 | assign mbist_fbtag_wr_ptr[1] = (l2t_mb2_addr_r3[2:0]==3'h1); |
| 2019 | assign mbist_fbtag_wr_ptr[2] = (l2t_mb2_addr_r3[2:0]==3'h2); |
| 2020 | assign mbist_fbtag_wr_ptr[3] = (l2t_mb2_addr_r3[2:0]==3'h3); |
| 2021 | assign mbist_fbtag_wr_ptr[4] = (l2t_mb2_addr_r3[2:0]==3'h4); |
| 2022 | assign mbist_fbtag_wr_ptr[5] = (l2t_mb2_addr_r3[2:0]==3'h5); |
| 2023 | assign mbist_fbtag_wr_ptr[6] = (l2t_mb2_addr_r3[2:0]==3'h6); |
| 2024 | assign mbist_fbtag_wr_ptr[7] = (l2t_mb2_addr_r3[2:0]==3'h7); |
| 2025 | |
| 2026 | |
| 2027 | l2t_filbuf_ctl_msff_ctl_macro__width_18 ff_l2t_mb2_run_r1 |
| 2028 | ( |
| 2029 | .scan_in(ff_l2t_mb2_run_r1_scanin), |
| 2030 | .scan_out(ff_l2t_mb2_run_r1_scanout), |
| 2031 | .din({mbist_run,l2t_mb2_fbtag_rd_en,l2t_mb2_fbtag_rd_en_r1,l2t_mb2_fbtag_rd_en_r2, |
| 2032 | fb_mbist_cam_sel,l2t_mb2_run,l2t_mb2_fbtag_wr_en, |
| 2033 | l2t_mb2_fbtag_wr_en_r1,l2t_mb2_fbtag_wr_en_r2,l2t_mb2_addr[2:0], |
| 2034 | l2t_mb2_addr_r1[2:0],l2t_mb2_addr_r2[2:0]}), |
| 2035 | .l1clk(l1clk), |
| 2036 | .dout({mbist_run_r1,l2t_mb2_fbtag_rd_en_r1,l2t_mb2_fbtag_rd_en_r2, |
| 2037 | l2t_mb2_fbtag_rd_en_r3,fb_mbist_cam_sel_r1,l2t_mb2_run_r1,l2t_mb2_fbtag_wr_en_r1, |
| 2038 | l2t_mb2_fbtag_wr_en_r2,l2t_mb2_fbtag_wr_en_r3,l2t_mb2_addr_r1[2:0], |
| 2039 | l2t_mb2_addr_r2[2:0],l2t_mb2_addr_r3[2:0]}), |
| 2040 | .siclk(siclk), |
| 2041 | .soclk(soclk) |
| 2042 | ); |
| 2043 | |
| 2044 | assign filbuf_fbtag_wr_ptr[7:0] = l2t_mb2_run_r1 ? mbist_fbtag_wr_ptr[7:0] : fb_wr_ptr_d1[7:0] ; |
| 2045 | assign filbuf_fbtag_wr_en = l2t_mb2_run_r1 ? l2t_mb2_fbtag_wr_en_r3 : mcu_pick_d1 ; |
| 2046 | |
| 2047 | ////////////////// |
| 2048 | // 2. xmit fbid to mbf |
| 2049 | // for misbuf tracking.THe fbid is later |
| 2050 | // re-transmitted to filbuf for writing the way |
| 2051 | // and way valid fields in filbuf. |
| 2052 | ////////////////// |
| 2053 | |
| 2054 | assign enc_wr_ptr_d1[0] = fb_wr_ptr_d1[1] | fb_wr_ptr_d1[3] | |
| 2055 | fb_wr_ptr_d1[5] | fb_wr_ptr_d1[7] ; |
| 2056 | assign enc_wr_ptr_d1[1] = fb_wr_ptr_d1[2] | fb_wr_ptr_d1[3] | |
| 2057 | fb_wr_ptr_d1[6] | fb_wr_ptr_d1[7] ; |
| 2058 | assign enc_wr_ptr_d1[2] = fb_wr_ptr_d1[4] | fb_wr_ptr_d1[5] | |
| 2059 | fb_wr_ptr_d1[6] | fb_wr_ptr_d1[7] ; |
| 2060 | |
| 2061 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_filbuf_misbuf_fbid_d2 |
| 2062 | (.din(enc_wr_ptr_d1[2:0]), .l1clk(l1clk), |
| 2063 | .scan_in(ff_filbuf_misbuf_fbid_d2_scanin), |
| 2064 | .scan_out(ff_filbuf_misbuf_fbid_d2_scanout), |
| 2065 | .dout(filbuf_misbuf_fbid_d2[2:0]), |
| 2066 | .siclk(siclk), |
| 2067 | .soclk(soclk) |
| 2068 | ); |
| 2069 | |
| 2070 | /////////////////////////////////////////////////////////////// |
| 2071 | // 3.The l2t-mcu interface for read requests consists of |
| 2072 | // req, req_id and addr signals all of which are |
| 2073 | // transmitted in the D2 stage |
| 2074 | /////////////////////////////////////////////////////////////// |
| 2075 | |
| 2076 | assign l2t_mcu_rd_req_id = filbuf_misbuf_fbid_d2 ; |
| 2077 | |
| 2078 | |
| 2079 | ////////////////////////////////////////////////////////// |
| 2080 | // VALID bit logic. |
| 2081 | // The Valid bit is set in cycle D1 of a miss insertion. |
| 2082 | // It is reset in the C3 cycle of a FIll. Since a Fill is |
| 2083 | // followed by 3 bubbles, the earliest operation following |
| 2084 | // a Fill will be in C1 when the fill is in C4. This means that |
| 2085 | // an operation following the fill ( to the same $ line) |
| 2086 | // will never hit the FB. |
| 2087 | // |
| 2088 | // Valid bit is also reset for a nofill entry if that entry |
| 2089 | // encounters a hit. Since ld64s are the only instructions that |
| 2090 | // will cause a no_fill entry, the reset operation can be |
| 2091 | // performed in C3 like that for a Fill operation. This is |
| 2092 | // because a ld64 is followed by two bubbles. |
| 2093 | // |
| 2094 | // Valid bit is reset for a fb hit to entry 0 in l2 off mode |
| 2095 | // if that entry has fb_stinst==0. In this case, the valid bit |
| 2096 | // will have to be reset in C2 since the following instruction |
| 2097 | // will have to see the effects of it.Hence this reset condition |
| 2098 | // is the most critical. |
| 2099 | ////////////////////////////////////////////////////////// |
| 2100 | |
| 2101 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_fill_vld_c3 |
| 2102 | (.din(arb_fill_vld_c2), .l1clk(l1clk), |
| 2103 | .scan_in(ff_fill_vld_c3_scanin), |
| 2104 | .scan_out(ff_fill_vld_c3_scanout), |
| 2105 | .dout(fill_vld_c3), |
| 2106 | .siclk(siclk), |
| 2107 | .soclk(soclk) |
| 2108 | ); |
| 2109 | |
| 2110 | |
| 2111 | assign no_fill_entry_dequeue_c3 = (fb_hit_vec_c3 & fb_nofill & |
| 2112 | {8{qual_hit_vec_c3}}); |
| 2113 | |
| 2114 | // In l2 off mode, any non-store entry is dequeued |
| 2115 | // when an inst hits the Fill Buffer. |
| 2116 | |
| 2117 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_l2_bypass_mode_on |
| 2118 | (.din(csr_l2_bypass_mode_on), .l1clk(l1clk), |
| 2119 | .scan_in(ff_l2_bypass_mode_on_scanin), |
| 2120 | .scan_out(ff_l2_bypass_mode_on_scanout), |
| 2121 | .dout(l2_bypass_mode_on_d1), |
| 2122 | .siclk(siclk), |
| 2123 | .soclk(soclk) |
| 2124 | ); |
| 2125 | |
| 2126 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_l2_dir_map_on_d1 |
| 2127 | (.din(csr_l2_dir_map_on), .l1clk(l1clk), |
| 2128 | .scan_in(ff_l2_dir_map_on_d1_scanin), |
| 2129 | .scan_out(ff_l2_dir_map_on_d1_scanout), |
| 2130 | .dout(l2_dir_map_on_d1), |
| 2131 | .siclk(siclk), |
| 2132 | .soclk(soclk) |
| 2133 | ); |
| 2134 | |
| 2135 | // In OFF mode, an instruction(B) may be in C1 when |
| 2136 | // a C2 instruction(A) hits the Fill Buffer. Hence the valid bit |
| 2137 | // reset condition should be flopped to C3 so that instruction B |
| 2138 | // can see the effects of instruction A on the Fill Buffer. |
| 2139 | // However, en_hit_dequeue_c2 had a critical component, tag_rdma_gate_off_c2 |
| 2140 | // This component has been removed and replaced with |
| 2141 | // rdma_inst_c2 & tag_misbuf_rdma_reg_vld_c2. |
| 2142 | |
| 2143 | |
| 2144 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_rdma_inst_c2 |
| 2145 | (.din(arbdec_arbdp_rdma_inst_c1), .l1clk(l1clk), |
| 2146 | .scan_in(ff_rdma_inst_c2_scanin), |
| 2147 | .scan_out(ff_rdma_inst_c2_scanout), |
| 2148 | .dout(rdma_inst_c2), |
| 2149 | .siclk(siclk), |
| 2150 | .soclk(soclk) |
| 2151 | ); |
| 2152 | |
| 2153 | |
| 2154 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_arb_filbuf_inst_vld_c2 |
| 2155 | ( |
| 2156 | .scan_in(ff_arb_filbuf_inst_vld_c2_scanin), |
| 2157 | .scan_out(ff_arb_filbuf_inst_vld_c2_scanout), |
| 2158 | .din(arb_inst_vld_c2_prev), |
| 2159 | .l1clk(l1clk), |
| 2160 | .dout(arb_filbuf_inst_vld_c2), |
| 2161 | .siclk(siclk), |
| 2162 | .soclk(soclk) |
| 2163 | ); |
| 2164 | |
| 2165 | |
| 2166 | assign en_hit_dequeue_c2 = arbdec_arbdp_inst_mb_c2 & |
| 2167 | arb_filbuf_inst_vld_c2 & |
| 2168 | ~(rdma_inst_c2 & tag_misbuf_rdma_reg_vld_c2) & |
| 2169 | fb_hit_vec_c2[0] & |
| 2170 | ~fb_stinst[0] & // not a store |
| 2171 | ~fb_nofill[0] & // not a ld64 |
| 2172 | l2_bypass_mode_on_d1 ; // OFF mode on. |
| 2173 | |
| 2174 | assign dec_fill_entry_c3[7:1] = fill_entry_num_c3[7:1] & {7{fill_vld_c3}} ; |
| 2175 | |
| 2176 | assign fill_complete_c3[7:1] = dec_fill_entry_c3[7:1] | |
| 2177 | no_fill_entry_dequeue_c3[7:1] ; |
| 2178 | |
| 2179 | assign dec_fill_entry_c3[0] = fill_entry_num_c3[0] & fill_vld_c3 ; |
| 2180 | |
| 2181 | assign fill_complete_c3[0] = dec_fill_entry_c3[0] | |
| 2182 | no_fill_entry_dequeue_c3[0] | |
| 2183 | en_hit_dequeue_c2 ; // off mode condition only. |
| 2184 | |
| 2185 | // COVERAGE: exercise all fill_complete_c3[7:0] conditions. |
| 2186 | // especially all en_hit_dequeue_c2 conditions. |
| 2187 | |
| 2188 | assign fb_set_valid = fb_wr_ptr_d1 |
| 2189 | & {8{mcu_pick_d1}} ; |
| 2190 | |
| 2191 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_fb_set_valid_d2 |
| 2192 | (.din(fb_set_valid[7:0]), .l1clk(l1clk), |
| 2193 | .scan_in(ff_fb_set_valid_d2_scanin), |
| 2194 | .scan_out(ff_fb_set_valid_d2_scanout), |
| 2195 | .dout(fb_set_valid_d2[7:0]), |
| 2196 | .siclk(siclk), |
| 2197 | .soclk(soclk) |
| 2198 | ); |
| 2199 | |
| 2200 | assign fb_valid_prev = ( fb_set_valid_d2 | fb_valid ) & |
| 2201 | ~fill_complete_c3; |
| 2202 | |
| 2203 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_valid_bit // sync reset active low |
| 2204 | (.din(fb_valid_prev[7:0]), .l1clk(l1clk), |
| 2205 | .scan_in(ff_valid_bit_scanin), |
| 2206 | .scan_out(ff_valid_bit_scanout), |
| 2207 | .clr(~dbb_rst_l), .dout(fb_valid[7:0]), |
| 2208 | .siclk(siclk), |
| 2209 | .soclk(soclk) |
| 2210 | ); |
| 2211 | |
| 2212 | ////////////////////////////////////////////////////////// |
| 2213 | // FB Counter |
| 2214 | // Increment and decrement conditions are the same as |
| 2215 | // set and reset conditions of the valid bit, respectively. |
| 2216 | // |
| 2217 | // filbuf_fb_count_eq_0 is required by misbuf to ready a csr write. |
| 2218 | // |
| 2219 | // filbuf_misbuf_entry_avail is required by misbuf as a condition |
| 2220 | // for mcu_pick. |
| 2221 | ////////////////////////////////////////////////////////// |
| 2222 | |
| 2223 | assign en_dequeue_c3 = (|( no_fill_entry_dequeue_c3 )) | |
| 2224 | fill_vld_c3 | |
| 2225 | en_hit_dequeue_c2 ; |
| 2226 | |
| 2227 | |
| 2228 | assign fb_count_en = ( mcu_pick_d1 | en_dequeue_c3 ) & |
| 2229 | ~( mcu_pick_d1 & en_dequeue_c3 ) ; |
| 2230 | |
| 2231 | assign fb_count_plus1 = fb_count + 4'b1 ; |
| 2232 | assign fb_count_minus1 = fb_count - 4'b1 ; |
| 2233 | |
| 2234 | assign fb_count_rst = (~dbb_rst_l ); |
| 2235 | |
| 2236 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_fb_count |
| 2237 | (.dout (fb_count_prev[3:0]), |
| 2238 | .din0(fb_count_plus1[3:0]), .din1(fb_count_minus1[3:0]), |
| 2239 | .sel0(mcu_pick_d1), .sel1(~mcu_pick_d1)); |
| 2240 | |
| 2241 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_4 ff_fb_count // sync reset active high |
| 2242 | (.din(fb_count_prev[3:0]), |
| 2243 | .scan_in(ff_fb_count_scanin), |
| 2244 | .scan_out(ff_fb_count_scanout), |
| 2245 | .l1clk(l1clk), .clr(fb_count_rst),.en(fb_count_en), |
| 2246 | .dout(fb_count[3:0]), |
| 2247 | .siclk(siclk), |
| 2248 | .soclk(soclk) |
| 2249 | ); |
| 2250 | |
| 2251 | assign filbuf_fb_count_eq_0 = ( fb_count == 4'b0 ) ; |
| 2252 | |
| 2253 | /////////////////////////////////////////// |
| 2254 | // in L2 off mode, Fb is only one deep. |
| 2255 | /////////////////////////////////////////// |
| 2256 | |
| 2257 | |
| 2258 | assign filbuf_misbuf_entry_avail = |
| 2259 | ( ~fb_count[3] & ~l2_bypass_mode_on_d1 ) | |
| 2260 | ( filbuf_fb_count_eq_0 & l2_bypass_mode_on_d1 ) ; |
| 2261 | |
| 2262 | |
| 2263 | |
| 2264 | ////////////////////////////////////////////////////////// |
| 2265 | // STINST: Set for any miss that requires a fill to happen |
| 2266 | // before it is processed out of the Miss Buffer. |
| 2267 | // |
| 2268 | // Lds , Imisses and Strloads are the only requests which bypass |
| 2269 | // data out of the fill buffer. All other instructions |
| 2270 | // will wait for a FIll to happen before they are readied |
| 2271 | // in the mIss Buffer. |
| 2272 | // |
| 2273 | // This bit is not valid unless fb_valid is set. |
| 2274 | ////////////////////////////////////////////////////////// |
| 2275 | |
| 2276 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_rqtyp_d2 |
| 2277 | (.din(mbdata_filbuf_rqtyp_d1[4:0]), .l1clk(l1clk), |
| 2278 | .scan_in(ff_rqtyp_d2_scanin), |
| 2279 | .scan_out(ff_rqtyp_d2_scanout), |
| 2280 | .dout(mbf_rqtyp_d2[4:0]), |
| 2281 | .siclk(siclk), |
| 2282 | .soclk(soclk) |
| 2283 | ); |
| 2284 | |
| 2285 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_snp_d2 |
| 2286 | (.din(mbdata_filbuf_rsvd_d1), .l1clk(l1clk), |
| 2287 | .scan_in(ff_snp_d2_scanin), |
| 2288 | .scan_out(ff_snp_d2_scanout), |
| 2289 | .dout(mbf_rsvd_d2), |
| 2290 | .siclk(siclk), |
| 2291 | .soclk(soclk) |
| 2292 | ); |
| 2293 | |
| 2294 | |
| 2295 | assign fb_stinst_d2 = (~( mbf_rqtyp_d2 == `IMISS_RQ ) & |
| 2296 | ~( mbf_rqtyp_d2 == `LOAD_RQ ) & |
| 2297 | ~( mbf_rqtyp_d2 == `STRLOAD_RQ ) & |
| 2298 | ~( mbf_rsvd_d2 & mbf_rqtyp_d2[0] ) ) ; |
| 2299 | |
| 2300 | // SR Changes for new MCU protocol 4/8/04 : decoding IMISS_RQ and LOAD_RQ also |
| 2301 | // for N2 as the MCU protocol has changed : mcu_data_vld's for chunks <0,1> and <2,3> |
| 2302 | // do not come back to back as in N1 but can come separated by arbitrary number of |
| 2303 | // cycles. Hence the fill buffer wakeup will happen after 1st packet for load, after |
| 2304 | // 2nd packet for imiss and after 4th packet for block loads and bypass cases. |
| 2305 | |
| 2306 | assign fb_imissinst_d2 = mbf_rqtyp_d2 == `IMISS_RQ ; |
| 2307 | assign ff_stinst_din_input = {fb_stinst_d2, fb_imissinst_d2}; |
| 2308 | |
| 2309 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_0 |
| 2310 | ( |
| 2311 | .scan_in(ff_stinst_0_scanin), |
| 2312 | .scan_out(ff_stinst_0_scanout), |
| 2313 | .din(ff_stinst_din_input), |
| 2314 | .en(fb_set_valid_d2[0]), |
| 2315 | .l1clk(l1clk), |
| 2316 | .dout({fb_stinst[0], fb_imissinst[0]}), |
| 2317 | .siclk(siclk), |
| 2318 | .soclk(soclk) |
| 2319 | ); |
| 2320 | |
| 2321 | |
| 2322 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_1 |
| 2323 | ( |
| 2324 | .scan_in(ff_stinst_1_scanin), |
| 2325 | .scan_out(ff_stinst_1_scanout), |
| 2326 | .din(ff_stinst_din_input), |
| 2327 | .en(fb_set_valid_d2[1]), |
| 2328 | .l1clk(l1clk), |
| 2329 | .dout({fb_stinst[1],fb_imissinst[1]}), |
| 2330 | .siclk(siclk), |
| 2331 | .soclk(soclk) |
| 2332 | ); |
| 2333 | |
| 2334 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_2 |
| 2335 | ( |
| 2336 | .scan_in(ff_stinst_2_scanin), |
| 2337 | .scan_out(ff_stinst_2_scanout), |
| 2338 | .din(ff_stinst_din_input), |
| 2339 | .en(fb_set_valid_d2[2]), |
| 2340 | .l1clk(l1clk), .dout({fb_stinst[2],fb_imissinst[2]}), |
| 2341 | .siclk(siclk), |
| 2342 | .soclk(soclk) |
| 2343 | ); |
| 2344 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_3 |
| 2345 | ( |
| 2346 | .scan_in(ff_stinst_3_scanin), |
| 2347 | .scan_out(ff_stinst_3_scanout), |
| 2348 | .din(ff_stinst_din_input), |
| 2349 | .en(fb_set_valid_d2[3]), |
| 2350 | .l1clk(l1clk), .dout({fb_stinst[3],fb_imissinst[3]}), |
| 2351 | .siclk(siclk), |
| 2352 | .soclk(soclk) |
| 2353 | ); |
| 2354 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_4 |
| 2355 | (.din(ff_stinst_din_input), |
| 2356 | .scan_in(ff_stinst_4_scanin), |
| 2357 | .scan_out(ff_stinst_4_scanout), |
| 2358 | .en(fb_set_valid_d2[4]), |
| 2359 | .l1clk(l1clk), |
| 2360 | .dout({fb_stinst[4],fb_imissinst[4]}), |
| 2361 | .siclk(siclk), |
| 2362 | .soclk(soclk) |
| 2363 | ); |
| 2364 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_5 |
| 2365 | ( |
| 2366 | .scan_in(ff_stinst_5_scanin), |
| 2367 | .scan_out(ff_stinst_5_scanout), |
| 2368 | .din(ff_stinst_din_input), |
| 2369 | .en(fb_set_valid_d2[5]), |
| 2370 | .l1clk(l1clk), .dout({fb_stinst[5],fb_imissinst[5]}), |
| 2371 | .siclk(siclk), |
| 2372 | .soclk(soclk) |
| 2373 | ); |
| 2374 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_6 |
| 2375 | (.din(ff_stinst_din_input), |
| 2376 | .scan_in(ff_stinst_6_scanin), |
| 2377 | .scan_out(ff_stinst_6_scanout), |
| 2378 | .en(fb_set_valid_d2[6]), |
| 2379 | .l1clk(l1clk), .dout({fb_stinst[6],fb_imissinst[6]}), |
| 2380 | .siclk(siclk), |
| 2381 | .soclk(soclk) |
| 2382 | ); |
| 2383 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ff_stinst_7 |
| 2384 | (.din(ff_stinst_din_input), |
| 2385 | .scan_in(ff_stinst_7_scanin), |
| 2386 | .scan_out(ff_stinst_7_scanout), |
| 2387 | .en(fb_set_valid_d2[7]), |
| 2388 | .l1clk(l1clk), .dout({fb_stinst[7],fb_imissinst[7]}), |
| 2389 | .siclk(siclk), |
| 2390 | .soclk(soclk) |
| 2391 | ); |
| 2392 | |
| 2393 | |
| 2394 | ////////////////////////////////////////////////////////// |
| 2395 | // NO_FILL: Set or reset when an entry is written into |
| 2396 | // the fbtags. |
| 2397 | // Set for a ld64 instruction and reset for any |
| 2398 | // other instruction. |
| 2399 | // Used in the valid bit setting and l2_ready logic. |
| 2400 | // |
| 2401 | // filbuf_misbuf_nofill_d2 is used to not turn on fbid_vld in |
| 2402 | // the miss buffer. |
| 2403 | ////////////////////////////////////////////////////////// |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | assign fb_nofill_d2 = mbf_rsvd_d2 & mbf_rqtyp_d2[0] ; |
| 2408 | assign filbuf_misbuf_nofill_d2 = fb_nofill_d2 ; |
| 2409 | assign fb_nofill_rst = ~dbb_rst_l; |
| 2410 | |
| 2411 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_0 // sync reset active high |
| 2412 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[0]), |
| 2413 | .scan_in(ff_nofill_0_scanin), |
| 2414 | .scan_out(ff_nofill_0_scanout), |
| 2415 | .clr(fb_nofill_rst), |
| 2416 | .l1clk(l1clk), .dout(fb_nofill[0]), |
| 2417 | .siclk(siclk), |
| 2418 | .soclk(soclk) |
| 2419 | ); |
| 2420 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_1 // sync reset active high |
| 2421 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[1]), |
| 2422 | .scan_in(ff_nofill_1_scanin), |
| 2423 | .scan_out(ff_nofill_1_scanout), |
| 2424 | .clr(fb_nofill_rst), |
| 2425 | .l1clk(l1clk), .dout(fb_nofill[1]), |
| 2426 | .siclk(siclk), |
| 2427 | .soclk(soclk) |
| 2428 | ); |
| 2429 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_2 // sync reset active high |
| 2430 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[2]), |
| 2431 | .scan_in(ff_nofill_2_scanin), |
| 2432 | .scan_out(ff_nofill_2_scanout), |
| 2433 | .clr(fb_nofill_rst), |
| 2434 | .l1clk(l1clk), .dout(fb_nofill[2]), |
| 2435 | .siclk(siclk), |
| 2436 | .soclk(soclk) |
| 2437 | ); |
| 2438 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_3 // sync reset active high |
| 2439 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[3]), |
| 2440 | .scan_in(ff_nofill_3_scanin), |
| 2441 | .scan_out(ff_nofill_3_scanout), |
| 2442 | .clr(fb_nofill_rst), |
| 2443 | .l1clk(l1clk), .dout(fb_nofill[3]), |
| 2444 | .siclk(siclk), |
| 2445 | .soclk(soclk) |
| 2446 | ); |
| 2447 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_4 // sync reset active high |
| 2448 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[4]), |
| 2449 | .scan_in(ff_nofill_4_scanin), |
| 2450 | .scan_out(ff_nofill_4_scanout), |
| 2451 | .clr(fb_nofill_rst), |
| 2452 | .l1clk(l1clk), .dout(fb_nofill[4]), |
| 2453 | .siclk(siclk), |
| 2454 | .soclk(soclk) |
| 2455 | ); |
| 2456 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_5 // sync reset active high |
| 2457 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[5]), |
| 2458 | .scan_in(ff_nofill_5_scanin), |
| 2459 | .scan_out(ff_nofill_5_scanout), |
| 2460 | .clr(fb_nofill_rst), |
| 2461 | .l1clk(l1clk), .dout(fb_nofill[5]), |
| 2462 | .siclk(siclk), |
| 2463 | .soclk(soclk) |
| 2464 | ); |
| 2465 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_6 // sync reset active high |
| 2466 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[6]), |
| 2467 | .scan_in(ff_nofill_6_scanin), |
| 2468 | .scan_out(ff_nofill_6_scanout), |
| 2469 | .clr(fb_nofill_rst), |
| 2470 | .l1clk(l1clk), .dout(fb_nofill[6]), |
| 2471 | .siclk(siclk), |
| 2472 | .soclk(soclk) |
| 2473 | ); |
| 2474 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_nofill_7 // sync reset active high |
| 2475 | (.din(fb_nofill_d2), .en(fb_set_valid_d2[7]), |
| 2476 | .scan_in(ff_nofill_7_scanin), |
| 2477 | .scan_out(ff_nofill_7_scanout), |
| 2478 | .clr(fb_nofill_rst), |
| 2479 | .l1clk(l1clk), .dout(fb_nofill[7]), |
| 2480 | .siclk(siclk), |
| 2481 | .soclk(soclk) |
| 2482 | ); |
| 2483 | |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | |
| 2488 | /////////////////////////////////////////////////////////////////////// |
| 2489 | // FB CAM EN: THe FB cam is enabled if arb_inst_vld_c1. |
| 2490 | // FB hit is enabled (in arb) . |
| 2491 | // |
| 2492 | // The Hit logic in C2 generates the following signals. |
| 2493 | // |
| 2494 | // filbuf_misbuf_match_c2 : used by misbuf to turn off eviction for |
| 2495 | // an insrtuction that misses the tag. Notice |
| 2496 | // that this signal is not qualified with |
| 2497 | // arb_inst_vld_c2. |
| 2498 | // |
| 2499 | // filbuf_misbuf_stinst_match_c2: fb hit entry corresponds to a store |
| 2500 | // |
| 2501 | // filbuf_tag_hit_frm_mb_c2 : Used in tag to generate tag_hit_l2orfb_c2. |
| 2502 | // This signal is high only if an instruction from |
| 2503 | // the miss buffer hits the FIll buffer.Not gated off when |
| 2504 | // the rdma register is vld. |
| 2505 | // |
| 2506 | /////////////////////////////////////////////////////////////////////// |
| 2507 | |
| 2508 | |
| 2509 | |
| 2510 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_fb_hit_off_c1_d1 |
| 2511 | (.din(arb_filbuf_hit_off_c1), .l1clk(l1clk), |
| 2512 | .scan_in(ff_fb_hit_off_c1_d1_scanin), |
| 2513 | .scan_out(ff_fb_hit_off_c1_d1_scanout), |
| 2514 | .dout(fb_hit_off_c1_d1), |
| 2515 | .siclk(siclk), |
| 2516 | .soclk(soclk) |
| 2517 | ); |
| 2518 | |
| 2519 | l2t_filbuf_ctl_msff_ctl_macro__width_9 ff_fb_cam_hit_vec |
| 2520 | (.din({fb_mbist_cam_hit_unreg,fb_cam_match[7:0]}), .l1clk(l1clk), |
| 2521 | .scan_in(ff_fb_cam_hit_vec_scanin), |
| 2522 | .scan_out(ff_fb_cam_hit_vec_scanout), |
| 2523 | .dout({fb_mbist_cam_hit,fb_cam_match_d1[7:0]}), |
| 2524 | .siclk(siclk), |
| 2525 | .soclk(soclk) |
| 2526 | ); |
| 2527 | |
| 2528 | assign fb_mbist_cam_hit_unreg = fb_mbist_cam_sel_r1 ? |(fb_cam_match_d1[7:0]) :1'b0; |
| 2529 | |
| 2530 | // fb_hit_vec_c2: |
| 2531 | // indicates that a valid instruction hits |
| 2532 | // the fill buffer. |
| 2533 | |
| 2534 | assign fb_hit_vec_c2 = fb_cam_match & fb_valid & |
| 2535 | {8{~fb_hit_off_c1_d1 }} ; |
| 2536 | |
| 2537 | // Above equation is cloned and sent to misbuf |
| 2538 | assign filbuf_arb_tag_hit_frm_mb_c2 = |( fb_hit_vec_c2 ) & // tag match in fb |
| 2539 | arbdec_arbdp_inst_mb_c2 & |
| 2540 | arb_filbuf_inst_vld_c2 ;// Miss buffer instruction |
| 2541 | |
| 2542 | |
| 2543 | assign filbuf_misbuf_tag_hit_frm_mb_c2 = |( fb_hit_vec_c2 ) & // tag match in fb |
| 2544 | arbdec_arbdp_inst_mb_c2 & |
| 2545 | arb_filbuf_inst_vld_c2 ;// Miss buffer instruction |
| 2546 | |
| 2547 | |
| 2548 | assign filbuf_tag_hit_frm_mb_c2 = filbuf_arb_tag_hit_frm_mb_c2 ; |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | |
| 2553 | |
| 2554 | |
| 2555 | assign filbuf_tag_hit_c2 = |( fb_hit_vec_c2 ) & // tag match in fb |
| 2556 | arb_filbuf_inst_vld_c2 ; // tag_rdma_gate_off_c2 qual mbist_done in tag. |
| 2557 | |
| 2558 | assign filbuf_misbuf_match_c2 = |( fb_hit_vec_c2 ) ; // not qualified with inst vld. |
| 2559 | |
| 2560 | |
| 2561 | assign filbuf_misbuf_stinst_match_c2 = ( fb_hit_vec_c2[0] & fb_stinst[0]) ; // matches a |
| 2562 | // store instruction. |
| 2563 | |
| 2564 | |
| 2565 | assign filbuf_hit_c2 = filbuf_tag_hit_frm_mb_c2 & ~tag_rdma_gate_off_c2 ; |
| 2566 | |
| 2567 | |
| 2568 | |
| 2569 | assign imiss_ld64_fb_hit_c2 = ( arb_decdp_imiss_inst_c2 | |
| 2570 | arb_decdp_ld64_inst_c2 ) & filbuf_hit_c2 ; |
| 2571 | |
| 2572 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_imiss_ld64_fb_hit_c3 |
| 2573 | (.din(imiss_ld64_fb_hit_c2), .l1clk(l1clk), |
| 2574 | .scan_in(ff_imiss_ld64_fb_hit_c3_scanin), |
| 2575 | .scan_out(ff_imiss_ld64_fb_hit_c3_scanout), |
| 2576 | .dout(imiss_ld64_fb_hit_c3), |
| 2577 | .siclk(siclk), |
| 2578 | .soclk(soclk) |
| 2579 | ); |
| 2580 | |
| 2581 | /////////////////////////////////////////////////////////////////////// |
| 2582 | // |
| 2583 | // filbuf_l2d_fb_hit_c3: Generated as a select for Fill Buffer data |
| 2584 | // over $ data. |
| 2585 | // C3 cycle of a regular load/imiss or |
| 2586 | // C4 cycle of an imiss hitting the Fill Buffer. |
| 2587 | // C4 cycle of a FIll in l2 off mode. |
| 2588 | // This signal is staged for two cycles and used |
| 2589 | // in l2d for the Fbdata vs L2data mux. |
| 2590 | // |
| 2591 | /////////////////////////////////////////////////////////////////////// |
| 2592 | |
| 2593 | assign l2t_l2d_fb_hit_c2 = mbist_run_r1 ? 1'b0 : (filbuf_hit_c2 | // ld or imiss 1st packet |
| 2594 | imiss_ld64_fb_hit_c3 | // imiss 2nd packet |
| 2595 | (fill_vld_c3 & l2_bypass_mode_on_d1 )); // fill in OFF mode |
| 2596 | |
| 2597 | |
| 2598 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_l2d_fb_hit_c3 |
| 2599 | (.din(l2t_l2d_fb_hit_c2), .l1clk(l1clk), |
| 2600 | .scan_in(ff_l2d_fb_hit_c3_scanin), |
| 2601 | .scan_out(ff_l2d_fb_hit_c3_scanout), |
| 2602 | .dout(filbuf_l2d_fb_hit_c3), |
| 2603 | .siclk(siclk), |
| 2604 | .soclk(soclk) |
| 2605 | ); |
| 2606 | |
| 2607 | |
| 2608 | |
| 2609 | |
| 2610 | assign qual_hit_vec_c2 = ~tag_rdma_gate_off_c2 & arbdec_arbdp_inst_mb_c2 & |
| 2611 | arb_filbuf_inst_vld_c2 ; |
| 2612 | |
| 2613 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_qual_hit_vec_c3 |
| 2614 | (.din(qual_hit_vec_c2), .l1clk(l1clk), |
| 2615 | .scan_in(ff_qual_hit_vec_c3_scanin), |
| 2616 | .scan_out(ff_qual_hit_vec_c3_scanout), |
| 2617 | .dout(qual_hit_vec_c3), |
| 2618 | .siclk(siclk), |
| 2619 | .soclk(soclk) |
| 2620 | ); |
| 2621 | |
| 2622 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_qual_hit_vec_c4 |
| 2623 | (.din(qual_hit_vec_c3), .l1clk(l1clk), |
| 2624 | .scan_in(ff_qual_hit_vec_c4_scanin), |
| 2625 | .scan_out(ff_qual_hit_vec_c4_scanout), |
| 2626 | .dout(qual_hit_vec_c4), |
| 2627 | .siclk(siclk), |
| 2628 | .soclk(soclk) |
| 2629 | ); |
| 2630 | |
| 2631 | |
| 2632 | /////////////////////////////////////////////////////////////////// |
| 2633 | // BYPASSED bit: The Bypassed bit is used to |
| 2634 | // tell if an instruction already |
| 2635 | // received bypassed data from the |
| 2636 | // Fill Buffer. If not, then the |
| 2637 | // ALLOC bit in vuad is not reset |
| 2638 | // by the FIll but rather by the |
| 2639 | // operation that hits the $. |
| 2640 | // |
| 2641 | // Set in the C3 cycle of a mbf instruction hitting |
| 2642 | // the fill buffer and reset in C3 cycle of a Fill |
| 2643 | // Bypassed bit is not set for a no fill Entry |
| 2644 | // or in the $ off mode. |
| 2645 | /////////////////////////////////////////////////////////////////// |
| 2646 | |
| 2647 | |
| 2648 | assign fb_bypassed_in = ( fb_bypassed | |
| 2649 | (fb_hit_vec_c3 & {8{qual_hit_vec_c3}} & |
| 2650 | ~fb_nofill & |
| 2651 | ~{8{l2_bypass_mode_on_d1}}) |
| 2652 | ) & ~fill_complete_c3; |
| 2653 | |
| 2654 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_bypassed // sync reset active low |
| 2655 | (.din(fb_bypassed_in[7:0]), .l1clk(l1clk), .clr(~dbb_rst_l), |
| 2656 | .scan_in(ff_bypassed_scanin), |
| 2657 | .scan_out(ff_bypassed_scanout), |
| 2658 | .dout(fb_bypassed[7:0]), |
| 2659 | .siclk(siclk), |
| 2660 | .soclk(soclk) |
| 2661 | ); |
| 2662 | |
| 2663 | assign fill_entry_num_c1[0] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd0 ); |
| 2664 | assign fill_entry_num_c1[1] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd1 ); |
| 2665 | assign fill_entry_num_c1[2] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd2 ); |
| 2666 | assign fill_entry_num_c1[3] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd3 ); |
| 2667 | assign fill_entry_num_c1[4] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd4 ); |
| 2668 | assign fill_entry_num_c1[5] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd5 ); |
| 2669 | assign fill_entry_num_c1[6] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd6 ); |
| 2670 | assign fill_entry_num_c1[7] = ( arbdec_arbdp_inst_mb_entry_c1[2:0] == 3'd7 ); |
| 2671 | |
| 2672 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_fill_entry_num_c2 |
| 2673 | (.din(fill_entry_num_c1[7:0]), .l1clk(l1clk), |
| 2674 | .scan_in(ff_fill_entry_num_c2_scanin), |
| 2675 | .scan_out(ff_fill_entry_num_c2_scanout), |
| 2676 | .dout(fill_entry_num_c2[7:0]), |
| 2677 | .siclk(siclk), |
| 2678 | .soclk(soclk) |
| 2679 | ); |
| 2680 | |
| 2681 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_fill_entry_num_c3 |
| 2682 | (.din(fill_entry_num_c2[7:0]), .l1clk(l1clk), |
| 2683 | .scan_in(ff_fill_entry_num_c3_scanin), |
| 2684 | .scan_out(ff_fill_entry_num_c3_scanout), |
| 2685 | .dout(fill_entry_num_c3[7:0]), |
| 2686 | .siclk(siclk), |
| 2687 | .soclk(soclk) |
| 2688 | ); |
| 2689 | |
| 2690 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_inst_vld_c3 |
| 2691 | (.din(arb_filbuf_inst_vld_c2), .l1clk(l1clk), |
| 2692 | .scan_in(ff_inst_vld_c3_scanin), |
| 2693 | .scan_out(ff_inst_vld_c3_scanout), |
| 2694 | .dout(inst_vld_c3), |
| 2695 | .siclk(siclk), |
| 2696 | .soclk(soclk) |
| 2697 | ); |
| 2698 | |
| 2699 | assign filbuf_vuad_bypassed_c3 = |( fb_bypassed & fill_entry_num_c3 ) & |
| 2700 | inst_vld_c3 ; |
| 2701 | |
| 2702 | |
| 2703 | ////////////////////////////////////////////////////////////////////// |
| 2704 | // MBF interface: Way, WAY_VLD bits in filbuf are written |
| 2705 | // by misbuf. |
| 2706 | //WAY and WAY_VLD are written when an instruction in the |
| 2707 | //miss buffer performs its "eviction" pass and gets a way allocated. |
| 2708 | // The above explanation assumes that an eviction pass will always |
| 2709 | // follow a request to mcu. However, in cases that the mcu request |
| 2710 | // happens after the eviction pass, the WAY and WAY_VLD bits |
| 2711 | // are written immediately after the DRAM request. |
| 2712 | // |
| 2713 | // Here is the pipeline for writing the way and evict_done bits. |
| 2714 | // if eviction happens after a request to DRAM is issued by the |
| 2715 | // miss buffer |
| 2716 | // --------------------------------------------------------------- |
| 2717 | // C4/ C5/ C6/ |
| 2718 | //---------------------------------------------------------------- |
| 2719 | // write pick |
| 2720 | // way vld bit. one mbf entry write |
| 2721 | // (misbuf) with wayvld and way into |
| 2722 | // fbid vld. entry pointed |
| 2723 | // by fbid. |
| 2724 | // muxout |
| 2725 | // way and |
| 2726 | // fbid. set evict_done |
| 2727 | // --------------------------------------------------------------- |
| 2728 | // |
| 2729 | /////////////////////////////////////////////////////////////////////// |
| 2730 | |
| 2731 | |
| 2732 | |
| 2733 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_misbuf_filbuf_fbid_d1 |
| 2734 | (.din(misbuf_filbuf_fbid[2:0]), .l1clk(l1clk), |
| 2735 | .scan_in(ff_misbuf_filbuf_fbid_d1_scanin), |
| 2736 | .scan_out(ff_misbuf_filbuf_fbid_d1_scanout), |
| 2737 | .dout(misbuf_filbuf_fbid_d1[2:0]), |
| 2738 | .siclk(siclk), |
| 2739 | .soclk(soclk) |
| 2740 | ); |
| 2741 | |
| 2742 | l2t_filbuf_ctl_msff_ctl_macro__width_4 ff_misbuf_filbuf_way_d1 |
| 2743 | (.din(misbuf_filbuf_way[3:0]), .l1clk(l1clk), |
| 2744 | .scan_in(ff_misbuf_filbuf_way_d1_scanin), |
| 2745 | .scan_out(ff_misbuf_filbuf_way_d1_scanout), |
| 2746 | .dout(misbuf_filbuf_way_d1[3:0]), |
| 2747 | .siclk(siclk), |
| 2748 | .soclk(soclk) |
| 2749 | ); |
| 2750 | |
| 2751 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_misbuf_filbuf_way_vld_d1 |
| 2752 | (.din(misbuf_filbuf_way_fbid_vld), .l1clk(l1clk), |
| 2753 | .scan_in(ff_misbuf_filbuf_way_vld_d1_scanin), |
| 2754 | .scan_out(ff_misbuf_filbuf_way_vld_d1_scanout), |
| 2755 | .dout(misbuf_filbuf_way_vld_d1), |
| 2756 | .siclk(siclk), |
| 2757 | .soclk(soclk) |
| 2758 | ); |
| 2759 | |
| 2760 | assign dec_mb_fb_id_d1[0] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd0 ) & |
| 2761 | misbuf_filbuf_way_vld_d1; |
| 2762 | assign dec_mb_fb_id_d1[1] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd1 ) & |
| 2763 | misbuf_filbuf_way_vld_d1; |
| 2764 | assign dec_mb_fb_id_d1[2] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd2 ) & |
| 2765 | misbuf_filbuf_way_vld_d1; |
| 2766 | assign dec_mb_fb_id_d1[3] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd3 ) & |
| 2767 | misbuf_filbuf_way_vld_d1; |
| 2768 | assign dec_mb_fb_id_d1[4] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd4 ) & |
| 2769 | misbuf_filbuf_way_vld_d1; |
| 2770 | assign dec_mb_fb_id_d1[5] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd5 ) & |
| 2771 | misbuf_filbuf_way_vld_d1; |
| 2772 | assign dec_mb_fb_id_d1[6] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd6 ) & |
| 2773 | misbuf_filbuf_way_vld_d1; |
| 2774 | assign dec_mb_fb_id_d1[7] = ( misbuf_filbuf_fbid_d1[2:0] == 3'd7 ) & |
| 2775 | misbuf_filbuf_way_vld_d1; |
| 2776 | |
| 2777 | |
| 2778 | /////////// |
| 2779 | // WAY<3:0> |
| 2780 | /////////// |
| 2781 | |
| 2782 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way0 |
| 2783 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[0]), |
| 2784 | .scan_in(ff_way0_scanin), |
| 2785 | .scan_out(ff_way0_scanout), |
| 2786 | .l1clk(l1clk), .dout(way0[3:0]), |
| 2787 | .siclk(siclk), |
| 2788 | .soclk(soclk) |
| 2789 | ); |
| 2790 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way1 |
| 2791 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[1]), |
| 2792 | .scan_in(ff_way1_scanin), |
| 2793 | .scan_out(ff_way1_scanout), |
| 2794 | .l1clk(l1clk), .dout(way1[3:0]), |
| 2795 | .siclk(siclk), |
| 2796 | .soclk(soclk) |
| 2797 | ); |
| 2798 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way2 |
| 2799 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[2]), |
| 2800 | .scan_in(ff_way2_scanin), |
| 2801 | .scan_out(ff_way2_scanout), |
| 2802 | .l1clk(l1clk), .dout(way2[3:0]), |
| 2803 | .siclk(siclk), |
| 2804 | .soclk(soclk) |
| 2805 | ); |
| 2806 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way3 |
| 2807 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[3]), |
| 2808 | .scan_in(ff_way3_scanin), |
| 2809 | .scan_out(ff_way3_scanout), |
| 2810 | .l1clk(l1clk), .dout(way3[3:0]), |
| 2811 | .siclk(siclk), |
| 2812 | .soclk(soclk) |
| 2813 | ); |
| 2814 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way4 |
| 2815 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[4]), |
| 2816 | .scan_in(ff_way4_scanin), |
| 2817 | .scan_out(ff_way4_scanout), |
| 2818 | .l1clk(l1clk), .dout(way4[3:0]), |
| 2819 | .siclk(siclk), |
| 2820 | .soclk(soclk) |
| 2821 | ); |
| 2822 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way5 |
| 2823 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[5]), |
| 2824 | .scan_in(ff_way5_scanin), |
| 2825 | .scan_out(ff_way5_scanout), |
| 2826 | .l1clk(l1clk), .dout(way5[3:0]), |
| 2827 | .siclk(siclk), |
| 2828 | .soclk(soclk) |
| 2829 | ); |
| 2830 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way6 |
| 2831 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[6]), |
| 2832 | .scan_in(ff_way6_scanin), |
| 2833 | .scan_out(ff_way6_scanout), |
| 2834 | .l1clk(l1clk), .dout(way6[3:0]), |
| 2835 | .siclk(siclk), |
| 2836 | .soclk(soclk) |
| 2837 | ); |
| 2838 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_way7 |
| 2839 | (.din(misbuf_filbuf_way_d1[3:0]), .en(dec_mb_fb_id_d1[7]), |
| 2840 | .scan_in(ff_way7_scanin), |
| 2841 | .scan_out(ff_way7_scanout), |
| 2842 | .l1clk(l1clk), .dout(way7[3:0]), |
| 2843 | .siclk(siclk), |
| 2844 | .soclk(soclk) |
| 2845 | ); |
| 2846 | |
| 2847 | /////////// |
| 2848 | // WAY_VLD |
| 2849 | // set at the time of an eviction "pass" ( or after a mcu pick ) |
| 2850 | // and reset at the time of fill |
| 2851 | // Can also be reset if picked by the L2_ARB picker. |
| 2852 | /////////// |
| 2853 | |
| 2854 | assign fb_way_vld_in = ( fb_way_vld | dec_mb_fb_id_d1 ) & ~fill_complete_c3 ; |
| 2855 | |
| 2856 | |
| 2857 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_way_vld // sync reset active low |
| 2858 | (.din(fb_way_vld_in[7:0]), .l1clk(l1clk), |
| 2859 | .scan_in(ff_way_vld_scanin), |
| 2860 | .scan_out(ff_way_vld_scanout), |
| 2861 | .clr(~dbb_rst_l), .dout(fb_way_vld[7:0]), |
| 2862 | .siclk(siclk), |
| 2863 | .soclk(soclk) |
| 2864 | ); |
| 2865 | |
| 2866 | |
| 2867 | //////////////////////////////////////////////////////////////////////////////// |
| 2868 | // DRAM interface.: |
| 2869 | // Data arriving from DRAM is written into the Fill Buffer |
| 2870 | // 128 bits at a time. Here is the pipeline. |
| 2871 | // |
| 2872 | //----------------------------------------------------------------------------- |
| 2873 | // R0 R1 R2 R3 R4 R5(PX2) |
| 2874 | //----------------------------------------------------------------------------- |
| 2875 | // -inc -data -write |
| 2876 | // -data_vld mcu_cnt from into |
| 2877 | // from mcu mcu FB |
| 2878 | // to in PH2 |
| 2879 | // l2b |
| 2880 | // |
| 2881 | // -if mcu_cnt_in -READY -PICK -READ -ISSUE |
| 2882 | // is 2, rdy miss logic |
| 2883 | // in mbf in misbuf |
| 2884 | //----------------------------------------------------------------------------- |
| 2885 | // |
| 2886 | // New addition; |
| 2887 | // Added a R0_d1 stage between R0 and R1 |
| 2888 | // |
| 2889 | //////////////////////////////////////////////////////////////////////////////// |
| 2890 | |
| 2891 | ////////////// |
| 2892 | // mcu packet |
| 2893 | // counter |
| 2894 | ////////////// |
| 2895 | |
| 2896 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_data_vld_r0_d1 |
| 2897 | (.din(mcu_l2t_data_vld_r0), .l1clk(l1clk), |
| 2898 | .scan_in(ff_data_vld_r0_d1_scanin), |
| 2899 | .scan_out(ff_data_vld_r0_d1_scanout), |
| 2900 | .dout(mcu_data_vld_r0_d1), |
| 2901 | .siclk(siclk), |
| 2902 | .soclk(soclk) |
| 2903 | ); |
| 2904 | |
| 2905 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_data_vld_r1 |
| 2906 | (.din(mcu_data_vld_r0_d1), .l1clk(l1clk), |
| 2907 | .scan_in(ff_data_vld_r1_scanin), |
| 2908 | .scan_out(ff_data_vld_r1_scanout), |
| 2909 | .dout(mcu_data_vld_r1), |
| 2910 | .siclk(siclk), |
| 2911 | .soclk(soclk) |
| 2912 | ); |
| 2913 | |
| 2914 | assign filbuf_mcu_l2t_data_vld_r1 = mcu_data_vld_r1; |
| 2915 | |
| 2916 | l2t_filbuf_ctl_msff_ctl_macro__width_2 ff_mcu_l2t_chunk_id_r0_d1 |
| 2917 | (.din(mcu_l2t_chunk_id_r0[1:0]), |
| 2918 | .scan_in(ff_mcu_l2t_chunk_id_r0_d1_scanin), |
| 2919 | .scan_out(ff_mcu_l2t_chunk_id_r0_d1_scanout), |
| 2920 | .l1clk(l1clk), |
| 2921 | .dout(mcu_l2t_chunk_id_r0_d1[1:0]), |
| 2922 | .siclk(siclk), |
| 2923 | .soclk(soclk) |
| 2924 | ); |
| 2925 | |
| 2926 | l2t_filbuf_ctl_msff_ctl_macro__width_2 ff_mcu_l2t_chunk_id_r1 |
| 2927 | (.din(mcu_l2t_chunk_id_r0_d1[1:0]), |
| 2928 | .scan_in(ff_mcu_l2t_chunk_id_r1_scanin), |
| 2929 | .scan_out(ff_mcu_l2t_chunk_id_r1_scanout), |
| 2930 | .l1clk(l1clk), |
| 2931 | .dout(filbuf_mcu_l2t_chunk_id_r1[1:0]), |
| 2932 | .siclk(siclk), |
| 2933 | .soclk(soclk) |
| 2934 | ); |
| 2935 | |
| 2936 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_l2t_req_id_r0_d1 |
| 2937 | (.din(mcu_l2t_rd_req_id_r0[2:0]), |
| 2938 | .scan_in(ff_l2t_req_id_r0_d1_scanin), |
| 2939 | .scan_out(ff_l2t_req_id_r0_d1_scanout), |
| 2940 | .l1clk(l1clk), |
| 2941 | .dout(mcu_rd_req_id_r0_d1[2:0]), |
| 2942 | .siclk(siclk), |
| 2943 | .soclk(soclk) |
| 2944 | ); |
| 2945 | |
| 2946 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_l2t_req_id_r1 |
| 2947 | (.din(mcu_rd_req_id_r0_d1[2:0]), |
| 2948 | .scan_in(ff_l2t_req_id_r1_scanin), |
| 2949 | .scan_out(ff_l2t_req_id_r1_scanout), |
| 2950 | .l1clk(l1clk), |
| 2951 | .dout(mcu_rd_req_id_r1[2:0]), |
| 2952 | .siclk(siclk), |
| 2953 | .soclk(soclk) |
| 2954 | ); |
| 2955 | |
| 2956 | |
| 2957 | |
| 2958 | // counter |
| 2959 | assign mcu_return_cnt_plus1 = mcu_return_cnt + 2'b1 ; |
| 2960 | |
| 2961 | assign mcu_cnt_reset = ~dbb_rst_l ; |
| 2962 | |
| 2963 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_2 ff_mcu_cnt // sync reset active high |
| 2964 | (.din(mcu_return_cnt_plus1[1:0]), .l1clk(l1clk), |
| 2965 | .scan_in(ff_mcu_cnt_scanin), |
| 2966 | .scan_out(ff_mcu_cnt_scanout), |
| 2967 | .clr(mcu_cnt_reset), .en(mcu_data_vld_r0_d1), |
| 2968 | .dout(mcu_return_cnt[1:0]), |
| 2969 | .siclk(siclk), |
| 2970 | .soclk(soclk) |
| 2971 | ); |
| 2972 | |
| 2973 | |
| 2974 | // SR Changes for new MCU protocol 4/8/04 : decoding IMISS_RQ and LOAD_RQ also |
| 2975 | // for N2 as the MCU protocol has changed : mcu_data_vld's for chunks <0,1> and <2,3> |
| 2976 | // do not come back to back as in N1 but can come separated by arbitrary number of |
| 2977 | // cycles. Hence the fill buffer wakeup will happen after 1st packet for load, after |
| 2978 | // 2nd packet for imiss and after 4th packet for block loads and bypass cases. |
| 2979 | |
| 2980 | |
| 2981 | //assign mcu_count_state0 = (mcu_return_cnt == 2'd0); |
| 2982 | assign mcu_count_state1 = (mcu_return_cnt == 2'd1); |
| 2983 | //assign mcu_count_state2 = (mcu_return_cnt == 2'd2); |
| 2984 | assign mcu_count_state3 = (mcu_return_cnt == 2'd3); |
| 2985 | |
| 2986 | |
| 2987 | |
| 2988 | //////////////// |
| 2989 | // Miss Buffer Ld/Imiss miss Ready |
| 2990 | // A load/Imiss instruction is readied if |
| 2991 | // mcu_count_state1 & mcu_data_vld_r1 implying |
| 2992 | // that the 2nd packet has arrived from DRAM. |
| 2993 | // |
| 2994 | // In off mode, an instruction is readied |
| 2995 | // when all packets arrive from DRAM |
| 2996 | //////////////// |
| 2997 | |
| 2998 | assign dec_rdreq_id_r0_d1[0] = ( mcu_rd_req_id_r0_d1 == 3'd0 ) ; |
| 2999 | assign dec_rdreq_id_r0_d1[1] = ( mcu_rd_req_id_r0_d1 == 3'd1 ) ; |
| 3000 | assign dec_rdreq_id_r0_d1[2] = ( mcu_rd_req_id_r0_d1 == 3'd2 ) ; |
| 3001 | assign dec_rdreq_id_r0_d1[3] = ( mcu_rd_req_id_r0_d1 == 3'd3 ) ; |
| 3002 | assign dec_rdreq_id_r0_d1[4] = ( mcu_rd_req_id_r0_d1 == 3'd4 ) ; |
| 3003 | assign dec_rdreq_id_r0_d1[5] = ( mcu_rd_req_id_r0_d1 == 3'd5 ) ; |
| 3004 | assign dec_rdreq_id_r0_d1[6] = ( mcu_rd_req_id_r0_d1 == 3'd6 ) ; |
| 3005 | assign dec_rdreq_id_r0_d1[7] = ( mcu_rd_req_id_r0_d1 == 3'd7 ) ; |
| 3006 | |
| 3007 | assign rdreq_0to3_def = ~(|dec_rdreq_id_r0_d1[2:0]); |
| 3008 | assign rdreq_4to7_def = ~(|dec_rdreq_id_r0_d1[6:4]); |
| 3009 | |
| 3010 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux1_rtn_mbid // BS & SR 11/04/03, MB grows to 32 |
| 3011 | (.dout(mux1_mbid_r1[4:0]), |
| 3012 | .din0(mbid0[4:0]), .din1(mbid1[4:0]), .din2(mbid2[4:0]), .din3(mbid3[4:0]), |
| 3013 | .sel0(dec_rdreq_id_r0_d1[0]), .sel1(dec_rdreq_id_r0_d1[1]), |
| 3014 | .sel2(dec_rdreq_id_r0_d1[2]), .sel3(rdreq_0to3_def)); |
| 3015 | |
| 3016 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux2_rtn_mbid |
| 3017 | (.dout(mux2_mbid_r1[4:0]), |
| 3018 | .din0(mbid4[4:0]), .din1(mbid5[4:0]), .din2(mbid6[4:0]), .din3(mbid7[4:0]), |
| 3019 | .sel0(dec_rdreq_id_r0_d1[4]), .sel1(dec_rdreq_id_r0_d1[5]), |
| 3020 | .sel2(dec_rdreq_id_r0_d1[6]), .sel3(rdreq_4to7_def)); |
| 3021 | |
| 3022 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux3_rtn_mbid // BS & SR 11/04/03, MB grows to 32 |
| 3023 | (.dout(filbuf_fbf_enc_ld_mbid_r1[4:0]), |
| 3024 | .din0(mux1_mbid_r1[4:0]), .din1(mux2_mbid_r1[4:0]), |
| 3025 | .sel0(~mcu_rd_req_id_r0_d1[2]), .sel1(mcu_rd_req_id_r0_d1[2])); |
| 3026 | |
| 3027 | |
| 3028 | |
| 3029 | assign ready_ld64_r0_d1 = |( dec_rdreq_id_r0_d1 & fb_nofill) ; // => ld64 instr. |
| 3030 | |
| 3031 | // SR Changes for new MCU protocol 4/8/04 : decoding IMISS_RQ and LOAD_RQ also |
| 3032 | // for N2 as the MCU protocol has changed : mcu_data_vld's for chunks <0,1> and <2,3> |
| 3033 | // do not come back to back as in N1 but can come separated by arbitrary number of |
| 3034 | // cycles. Hence the fill buffer wakeup will happen after 1st packet for load, after |
| 3035 | // 2nd packet for imiss and after 4th packet for block loads and bypass cases. |
| 3036 | |
| 3037 | assign ready_ld_r0_d1 = |( dec_rdreq_id_r0_d1 & ~fb_stinst & ~fb_imissinst & ~fb_nofill) ; // => everything otherr than store and imiss, |
| 3038 | // covers ld instr. |
| 3039 | assign ready_imiss_r0_d1 = |( dec_rdreq_id_r0_d1 & fb_imissinst & ~fb_nofill) ; // => imiss instr. |
| 3040 | |
| 3041 | assign filbuf_fbf_ready_miss_r1 = |
| 3042 | ( ( ( mcu_count_state1 & mcu_data_vld_r0_d1 & ready_ld_r0_d1 ) | // Load ready |
| 3043 | ( mcu_count_state1 & mcu_data_vld_r0_d1 & ready_imiss_r0_d1)) & // Imiss ready |
| 3044 | ~l2_bypass_mode_on_d1 & // L2 ON |
| 3045 | ~l2_dir_map_on_d1) | |
| 3046 | ( mcu_count_state3 & mcu_data_vld_r0_d1 & // 3 packets received |
| 3047 | ( l2_bypass_mode_on_d1 | ready_ld64_r0_d1 ) ) ; // L2 OFF and any instruction. |
| 3048 | |
| 3049 | /////////////////////////////////////////////////////////// |
| 3050 | // L2 ready: is set to indicate that all packets for this |
| 3051 | // miss request have arrived from DRAM. ALongwith WAY_VLD, |
| 3052 | // this bit is used as a pick condition for a FILL. |
| 3053 | // |
| 3054 | // Set when mcu_count_state2 and mcu_data_vld_r1 is high |
| 3055 | // in l2 ON mode. |
| 3056 | // |
| 3057 | // In cache OFF mode, L2 ready is set if an instruction |
| 3058 | // hits an FB entry with fb_stinst=1, implying that the |
| 3059 | // line is dirty in the FIll Buffer and needs to be written |
| 3060 | // back to DRAM , exception is a CAS1. IN the case of a cas1 |
| 3061 | // instruction, the ready bit is not set. |
| 3062 | /////////////////////////////////////////////////////////// |
| 3063 | |
| 3064 | |
| 3065 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_cas1_inst_c3 |
| 3066 | (.din(arb_decdp_cas1_inst_c2), .l1clk(l1clk), |
| 3067 | .scan_in(ff_cas1_inst_c3_scanin), |
| 3068 | .scan_out(ff_cas1_inst_c3_scanout), |
| 3069 | .dout(cas1_inst_c3), |
| 3070 | .siclk(siclk), |
| 3071 | .soclk(soclk) |
| 3072 | ); |
| 3073 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_cas1_inst_c4 |
| 3074 | (.din(cas1_inst_c3), .l1clk(l1clk), |
| 3075 | .scan_in(ff_cas1_inst_c4_scanin), |
| 3076 | .scan_out(ff_cas1_inst_c4_scanout), |
| 3077 | .dout(cas1_inst_c4), |
| 3078 | .siclk(siclk), |
| 3079 | .soclk(soclk) |
| 3080 | ); |
| 3081 | |
| 3082 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_fb_hit_vec_c3 |
| 3083 | (.din(fb_hit_vec_c2[7:0]), .l1clk(l1clk), |
| 3084 | .scan_in(ff_fb_hit_vec_c3_scanin), |
| 3085 | .scan_out(ff_fb_hit_vec_c3_scanout), |
| 3086 | .dout(fb_hit_vec_c3[7:0]), |
| 3087 | .siclk(siclk), |
| 3088 | .soclk(soclk) |
| 3089 | ); |
| 3090 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_fb_hit_vec_c4 |
| 3091 | (.din(fb_hit_vec_c3[7:0]), .l1clk(l1clk), |
| 3092 | .scan_in(ff_fb_hit_vec_c4_scanin), |
| 3093 | .scan_out(ff_fb_hit_vec_c4_scanout), |
| 3094 | .dout(fb_hit_vec_c4[7:0]), |
| 3095 | .siclk(siclk), |
| 3096 | .soclk(soclk) |
| 3097 | ); |
| 3098 | |
| 3099 | // SR Changes for new MCU protocol 4/8/04 : decoding IMISS_RQ and LOAD_RQ also |
| 3100 | // for N2 as the MCU protocol has changed : mcu_data_vld's for chunks <0,1> and <2,3> |
| 3101 | // do not come back to back as in N1 but can come separated by arbitrary number of |
| 3102 | // cycles. Hence the fill buffer wakeup will happen after 1st packet for load, after |
| 3103 | // 2nd packet for imiss and after 4th packet for block loads and bypass cases. |
| 3104 | |
| 3105 | |
| 3106 | assign fb_l2_ready_in[7:1] = ( ({7{mcu_count_state3 & |
| 3107 | mcu_data_vld_r0_d1 }} // last pckt from mcu |
| 3108 | & dec_rdreq_id_r0_d1[7:1] // id of incoming pckt |
| 3109 | & ~fb_nofill[7:1] )| // not a no fill req. |
| 3110 | fb_l2_ready[7:1] ) & |
| 3111 | ~fb_l2_rd_ptr[7:1] ; |
| 3112 | |
| 3113 | assign fb_l2_ready_in[0] = ( ( mcu_count_state3 & |
| 3114 | ~l2_bypass_mode_on_d1 & |
| 3115 | mcu_data_vld_r0_d1 |
| 3116 | & ~fb_nofill[0] |
| 3117 | & dec_rdreq_id_r0_d1[0] ) | |
| 3118 | ( l2_bypass_mode_on_d1 & // l2 off |
| 3119 | fb_stinst[0] & // ~imiss and ~ld & ~ld64 |
| 3120 | misbuf_mbf_delete_c4 & // mbf dequeue |
| 3121 | fb_hit_vec_c4[0] & // hit in fb |
| 3122 | qual_hit_vec_c4 & |
| 3123 | ~cas1_inst_c4 ) | // not a CAS1 |
| 3124 | fb_l2_ready[0] |
| 3125 | ) & ~fb_l2_rd_ptr[0] ; |
| 3126 | |
| 3127 | |
| 3128 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_fb_l2_ready // sync reset active low |
| 3129 | (.din(fb_l2_ready_in[7:0]), .l1clk(l1clk), |
| 3130 | .scan_in(ff_fb_l2_ready_scanin), |
| 3131 | .scan_out(ff_fb_l2_ready_scanout), |
| 3132 | .clr(~dbb_rst_l), |
| 3133 | .dout(fb_l2_ready[7:0]), |
| 3134 | .siclk(siclk), |
| 3135 | .soclk(soclk) |
| 3136 | ); |
| 3137 | |
| 3138 | |
| 3139 | /////////////////////////////////////////////////////////////////////////// |
| 3140 | // Interface with L2 ARB: |
| 3141 | // The Fill Buffer can issue instructions at the rate of 1 every 4 cycles. |
| 3142 | // and the issue pipeline is similar to that of the Miss Buffer. |
| 3143 | //-------------------------------------------------------------------------- |
| 3144 | // inst A PICK READ (PX1) ISSUE(PX2) |
| 3145 | //-------------------------------------------------------------------------- |
| 3146 | // -pick if |
| 3147 | // ~l2_wait |
| 3148 | // or fbsel_c1 -read fbtag |
| 3149 | // |
| 3150 | // -set l2_wait -enable px2 rd flop |
| 3151 | // if l2_pick_d1 - hold fbtag |
| 3152 | // until next l2_pick |
| 3153 | // |
| 3154 | // -way and fbid |
| 3155 | // to arbdec. |
| 3156 | //-------------------------------------------------------------------------- |
| 3157 | // ENtires that are l2_ready and way_vld are picked for FIlls. |
| 3158 | // However, in l2_bypass_mode, the way_vld bit is not required to be set. |
| 3159 | // |
| 3160 | /////////////////////////////////////////////////////////////////////////// |
| 3161 | |
| 3162 | |
| 3163 | assign l2_pick_vec[7:1] = ( fb_l2_ready[7:1] & fb_way_vld[7:1] ) & ~{7{l2_wait}} ; |
| 3164 | assign l2_pick_vec[0] = ( fb_l2_ready[0] & (fb_way_vld[0]| l2_bypass_mode_on_d1) ) & ~l2_wait ; |
| 3165 | |
| 3166 | assign l2_pick = |( l2_pick_vec ) ; |
| 3167 | |
| 3168 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_l2_pick_d1 |
| 3169 | (.din(l2_pick), .l1clk(l1clk), |
| 3170 | .scan_in(ff_l2_pick_d1_scanin), |
| 3171 | .scan_out(ff_l2_pick_d1_scanout), |
| 3172 | .dout(l2_pick_d1), |
| 3173 | .siclk(siclk), |
| 3174 | .soclk(soclk) |
| 3175 | ); |
| 3176 | |
| 3177 | |
| 3178 | assign l2_wait_in = ( l2_pick | l2_wait) |
| 3179 | & ~arb_filbuf_fbsel_c1 ; |
| 3180 | |
| 3181 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_l2_wait // sync reset active low |
| 3182 | (.din(l2_wait_in), .l1clk(l1clk), .clr(~dbb_rst_l), |
| 3183 | .scan_in(ff_l2_wait_scanin), |
| 3184 | .scan_out(ff_l2_wait_scanout), |
| 3185 | .dout(l2_wait), |
| 3186 | .siclk(siclk), |
| 3187 | .soclk(soclk) |
| 3188 | ); |
| 3189 | |
| 3190 | |
| 3191 | |
| 3192 | assign filbuf_buf_rd_en = l2t_mb2_run_r1 ? l2t_mb2_fbtag_rd_en_r3 : l2_pick ; |
| 3193 | |
| 3194 | assign filbuf_arb_l2rd_en = l2_pick_d1; |
| 3195 | |
| 3196 | assign filbuf_arb_vld_px1 = l2_wait ; |
| 3197 | |
| 3198 | |
| 3199 | ////////////////////////// |
| 3200 | // FBID field to L2 arbdec |
| 3201 | ////////////////////////// |
| 3202 | |
| 3203 | assign enc_l2_rd_ptr[0] = fb_l2_rd_ptr[1] | fb_l2_rd_ptr[3] | |
| 3204 | fb_l2_rd_ptr[5] | fb_l2_rd_ptr[7] ; |
| 3205 | |
| 3206 | assign enc_l2_rd_ptr[1] = fb_l2_rd_ptr[2] | fb_l2_rd_ptr[3] | |
| 3207 | fb_l2_rd_ptr[6] | fb_l2_rd_ptr[7] ; |
| 3208 | |
| 3209 | assign enc_l2_rd_ptr[2] = fb_l2_rd_ptr[4] | fb_l2_rd_ptr[5] | |
| 3210 | fb_l2_rd_ptr[6] | fb_l2_rd_ptr[7] ; |
| 3211 | |
| 3212 | |
| 3213 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_3 ff_l2_entry_px2 |
| 3214 | (.din(enc_l2_rd_ptr[2:0]), .en(l2_pick_d1), |
| 3215 | .scan_in(ff_l2_entry_px2_scanin), |
| 3216 | .scan_out(ff_l2_entry_px2_scanout), |
| 3217 | .l1clk(l1clk), .dout(filbuf_arbdp_entry_px2[2:0]), |
| 3218 | .siclk(siclk), |
| 3219 | .soclk(soclk) |
| 3220 | |
| 3221 | ); |
| 3222 | |
| 3223 | |
| 3224 | ////////////////////// |
| 3225 | // WAY field to L2 arbdec |
| 3226 | ////////////////////// |
| 3227 | |
| 3228 | assign way_mux1_def = ~(|fb_l2_rd_ptr[2:0]); |
| 3229 | assign way_mux2_def = ~(|fb_l2_rd_ptr[6:4]); |
| 3230 | |
| 3231 | assign fb_l2_rd_ptr_sel[0] = fb_l2_rd_ptr[0] ; |
| 3232 | assign fb_l2_rd_ptr_sel[1] = fb_l2_rd_ptr[1] ; |
| 3233 | assign fb_l2_rd_ptr_sel[2] = fb_l2_rd_ptr[2] ; |
| 3234 | assign fb_l2_rd_ptr_sel[3] = way_mux1_def ; |
| 3235 | |
| 3236 | assign fb_l2_rd_ptr_sel[4] = fb_l2_rd_ptr[4] ; |
| 3237 | assign fb_l2_rd_ptr_sel[5] = fb_l2_rd_ptr[5] ; |
| 3238 | assign fb_l2_rd_ptr_sel[6] = fb_l2_rd_ptr[6] ; |
| 3239 | assign fb_l2_rd_ptr_sel[7] = way_mux2_def ; |
| 3240 | |
| 3241 | |
| 3242 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 l2_way_mux1 |
| 3243 | (.dout (mux1_way[3:0]), |
| 3244 | .din0(way0[3:0]),.din1(way1[3:0]), |
| 3245 | .din2(way2[3:0]),.din3(way3[3:0]), |
| 3246 | .sel0(fb_l2_rd_ptr_sel[0]), .sel1(fb_l2_rd_ptr_sel[1]), |
| 3247 | .sel2(fb_l2_rd_ptr_sel[2]), .sel3(fb_l2_rd_ptr_sel[3])); |
| 3248 | |
| 3249 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 l2_way_mux2 |
| 3250 | (.dout (mux2_way[3:0]), |
| 3251 | .din0(way4[3:0]),.din1(way5[3:0]), |
| 3252 | .din2(way6[3:0]),.din3(way7[3:0]), |
| 3253 | .sel0(fb_l2_rd_ptr_sel[4]),.sel1(fb_l2_rd_ptr_sel[5]), |
| 3254 | .sel2(fb_l2_rd_ptr_sel[6]),.sel3(fb_l2_rd_ptr_sel[7])); |
| 3255 | |
| 3256 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 l2_way_mux |
| 3257 | (.dout (fill_way[3:0]), |
| 3258 | .din0(mux2_way[3:0]), .din1(mux1_way[3:0]), |
| 3259 | .sel0(enc_l2_rd_ptr[2]),.sel1(~enc_l2_rd_ptr[2])); |
| 3260 | |
| 3261 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ff_l2_way_px2 |
| 3262 | (.din(fill_way[3:0]), .en(l2_pick_d1), |
| 3263 | .scan_in(ff_l2_way_px2_scanin), |
| 3264 | .scan_out(ff_l2_way_px2_scanout), |
| 3265 | .l1clk(l1clk), .dout(filbuf_arbdp_way_px2[3:0]), |
| 3266 | .siclk(siclk), |
| 3267 | .soclk(soclk) |
| 3268 | |
| 3269 | ); |
| 3270 | |
| 3271 | |
| 3272 | |
| 3273 | /////////////////////////////////////////////////////////////////////////// |
| 3274 | // Writing MBID into the FIll Buffer. |
| 3275 | // There are 3 conditions under which the mbid of an instruction is written |
| 3276 | // into the Fill Buffer so that the fill buffer can ready that instruction |
| 3277 | // after a fill. They are as following: |
| 3278 | // 1. A miss buffer dependent's mbID is written into the fill Buffer when |
| 3279 | // the older instruction hits the fill buffer and completes ( dequeues from mb) |
| 3280 | // This is mbist_done in the C4 cycle of the older instruction. |
| 3281 | // 2. A non dependent instruction that issues from the IQ cannot receive data |
| 3282 | // from the FIll Buffer. The mbID of the instruction is written into the |
| 3283 | // Fill Buffer so that it can be readied when a fill is performed. |
| 3284 | // The mbID write into the Fill Buffer is performed in C4. |
| 3285 | // 3. The ID of a miss requesting to DRAM is writted into the Fill Buffer in |
| 3286 | // the D2 cycle of the l2-mcu request pipeline. |
| 3287 | // |
| 3288 | // |
| 3289 | // A next_link VALID bit is set when the mbid comes from either 1 or 2 above. |
| 3290 | // The next_link VALID bit is reset when a fill is complete. |
| 3291 | // |
| 3292 | /////////////////////////////////////////////////////////////////////////// |
| 3293 | |
| 3294 | |
| 3295 | |
| 3296 | assign dep_ptr_wr_en_c4 = misbuf_filbuf_next_vld_c4 & misbuf_mbf_delete_c4 & |
| 3297 | ~cas1_inst_c4; // cas1 dependents never woken up by the FBF |
| 3298 | |
| 3299 | |
| 3300 | assign dep_wr_qual_c4 = ( {8{~l2_bypass_mode_on_d1}} | // l2 $ ON |
| 3301 | fb_stinst ) ; // Fill Buffer instruction is a Store. |
| 3302 | |
| 3303 | assign dep_wr_ptr_c4 = fb_hit_vec_c4 & dep_wr_qual_c4 & |
| 3304 | {8{dep_ptr_wr_en_c4 }} ; |
| 3305 | |
| 3306 | |
| 3307 | |
| 3308 | assign non_dep_mbf_insert_c4 = misbuf_mbf_insert_c4 & ~misbuf_hit_c4; |
| 3309 | |
| 3310 | assign non_dep_wr_ptr_c4 = fb_hit_vec_c4 & |
| 3311 | {8{non_dep_mbf_insert_c4 }} ; |
| 3312 | |
| 3313 | |
| 3314 | assign non_dep_wr_ptr_c4_rst = non_dep_wr_ptr_c4 ; |
| 3315 | assign dep_wr_ptr_c4_rst = dep_wr_ptr_c4 ; |
| 3316 | assign fb_set_valid_d2_rst = fb_set_valid_d2 ; |
| 3317 | |
| 3318 | |
| 3319 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbf_entry_d2 // BS & SR 11/04/03, MB grows to 32 |
| 3320 | (.din(mbdata_filbuf_mbf_entry[4:0]), .l1clk(l1clk), |
| 3321 | .scan_in(ff_mbf_entry_d2_scanin), |
| 3322 | .scan_out(ff_mbf_entry_d2_scanout), |
| 3323 | .dout(mbf_entry_d2[4:0]), |
| 3324 | .siclk(siclk), |
| 3325 | .soclk(soclk) |
| 3326 | ); |
| 3327 | |
| 3328 | assign sel_def_mbid = ~( dep_wr_ptr_c4 | fb_set_valid_d2_rst | |
| 3329 | non_dep_wr_ptr_c4 ) ; |
| 3330 | |
| 3331 | //BS & SR 11/04/03, MB grows to 32 |
| 3332 | |
| 3333 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid0 |
| 3334 | (.dout(mbid0_in[4:0]), |
| 3335 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3336 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid0[4:0]), |
| 3337 | .sel0(dep_wr_ptr_c4_rst[0]), .sel1(fb_set_valid_d2_rst[0]), |
| 3338 | .sel2(non_dep_wr_ptr_c4_rst[0]), .sel3(sel_def_mbid[0])); |
| 3339 | |
| 3340 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid0 |
| 3341 | (.din(mbid0_in[4:0]), .l1clk(l1clk), |
| 3342 | .scan_in(ff_mbid0_scanin), |
| 3343 | .scan_out(ff_mbid0_scanout), |
| 3344 | .dout(mbid0[4:0]), |
| 3345 | .siclk(siclk), |
| 3346 | .soclk(soclk) |
| 3347 | ); |
| 3348 | |
| 3349 | |
| 3350 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid1 |
| 3351 | (.dout(mbid1_in[4:0]), |
| 3352 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3353 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid1[4:0]), |
| 3354 | .sel0(dep_wr_ptr_c4_rst[1]), .sel1(fb_set_valid_d2_rst[1]), |
| 3355 | .sel2(non_dep_wr_ptr_c4_rst[1]), .sel3(sel_def_mbid[1])); |
| 3356 | |
| 3357 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid1 |
| 3358 | (.din(mbid1_in[4:0]), .l1clk(l1clk), |
| 3359 | .scan_in(ff_mbid1_scanin), |
| 3360 | .scan_out(ff_mbid1_scanout), |
| 3361 | .dout(mbid1[4:0]), |
| 3362 | .siclk(siclk), |
| 3363 | .soclk(soclk) |
| 3364 | ); |
| 3365 | |
| 3366 | |
| 3367 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid2 |
| 3368 | (.dout(mbid2_in[4:0]), |
| 3369 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3370 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid2[4:0]), |
| 3371 | .sel0(dep_wr_ptr_c4_rst[2]), .sel1(fb_set_valid_d2_rst[2]), |
| 3372 | .sel2(non_dep_wr_ptr_c4_rst[2]), .sel3(sel_def_mbid[2])); |
| 3373 | |
| 3374 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid2 |
| 3375 | (.din(mbid2_in[4:0]), .l1clk(l1clk), |
| 3376 | .scan_in(ff_mbid2_scanin), |
| 3377 | .scan_out(ff_mbid2_scanout), |
| 3378 | .dout(mbid2[4:0]), |
| 3379 | .siclk(siclk), |
| 3380 | .soclk(soclk) |
| 3381 | ); |
| 3382 | |
| 3383 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid3 |
| 3384 | (.dout(mbid3_in[4:0]), |
| 3385 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3386 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid3[4:0]), |
| 3387 | .sel0(dep_wr_ptr_c4_rst[3]), .sel1(fb_set_valid_d2_rst[3]), |
| 3388 | .sel2(non_dep_wr_ptr_c4_rst[3]), .sel3(sel_def_mbid[3])); |
| 3389 | |
| 3390 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid3 |
| 3391 | (.din(mbid3_in[4:0]), .l1clk(l1clk), |
| 3392 | .scan_in(ff_mbid3_scanin), |
| 3393 | .scan_out(ff_mbid3_scanout), |
| 3394 | .dout(mbid3[4:0]), |
| 3395 | .siclk(siclk), |
| 3396 | .soclk(soclk) |
| 3397 | ); |
| 3398 | |
| 3399 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid4 |
| 3400 | (.dout(mbid4_in[4:0]), |
| 3401 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3402 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid4[4:0]), |
| 3403 | .sel0(dep_wr_ptr_c4_rst[4]), .sel1(fb_set_valid_d2_rst[4]), |
| 3404 | .sel2(non_dep_wr_ptr_c4_rst[4]), .sel3(sel_def_mbid[4])); |
| 3405 | |
| 3406 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid4 |
| 3407 | (.din(mbid4_in[4:0]), .l1clk(l1clk), |
| 3408 | .scan_in(ff_mbid4_scanin), |
| 3409 | .scan_out(ff_mbid4_scanout), |
| 3410 | .dout(mbid4[4:0]), |
| 3411 | .siclk(siclk), |
| 3412 | .soclk(soclk) |
| 3413 | ); |
| 3414 | |
| 3415 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid5 |
| 3416 | (.dout(mbid5_in[4:0]), |
| 3417 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3418 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid5[4:0]), |
| 3419 | .sel0(dep_wr_ptr_c4_rst[5]), .sel1(fb_set_valid_d2_rst[5]), |
| 3420 | .sel2(non_dep_wr_ptr_c4_rst[5]), .sel3(sel_def_mbid[5])); |
| 3421 | |
| 3422 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid5 |
| 3423 | (.din(mbid5_in[4:0]), .l1clk(l1clk), |
| 3424 | .scan_in(ff_mbid5_scanin), |
| 3425 | .scan_out(ff_mbid5_scanout), |
| 3426 | .dout(mbid5[4:0]), |
| 3427 | .siclk(siclk), |
| 3428 | .soclk(soclk) |
| 3429 | ); |
| 3430 | |
| 3431 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid6 |
| 3432 | (.dout(mbid6_in[4:0]), |
| 3433 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3434 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid6[4:0]), |
| 3435 | .sel0(dep_wr_ptr_c4_rst[6]), .sel1(fb_set_valid_d2_rst[6]), |
| 3436 | .sel2(non_dep_wr_ptr_c4_rst[6]), .sel3(sel_def_mbid[6])); |
| 3437 | |
| 3438 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid6 |
| 3439 | (.din(mbid6_in[4:0]), .l1clk(l1clk), |
| 3440 | .scan_in(ff_mbid6_scanin), |
| 3441 | .scan_out(ff_mbid6_scanout), |
| 3442 | .dout(mbid6[4:0]), |
| 3443 | .siclk(siclk), |
| 3444 | .soclk(soclk) |
| 3445 | ); |
| 3446 | |
| 3447 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux_mbid7 |
| 3448 | (.dout(mbid7_in[4:0]), |
| 3449 | .din0(misbuf_filbuf_next_link_c4[4:0]), .din1(mbf_entry_d2[4:0]), |
| 3450 | .din2(misbuf_mbf_insert_mbid_c4[4:0]), .din3(mbid7[4:0]), |
| 3451 | .sel0(dep_wr_ptr_c4_rst[7]), .sel1(fb_set_valid_d2_rst[7]), |
| 3452 | .sel2(non_dep_wr_ptr_c4_rst[7]), .sel3(sel_def_mbid[7])); |
| 3453 | |
| 3454 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_mbid7 |
| 3455 | (.din(mbid7_in[4:0]), .l1clk(l1clk), |
| 3456 | .scan_in(ff_mbid7_scanin), |
| 3457 | .scan_out(ff_mbid7_scanout), |
| 3458 | .dout(mbid7[4:0]), |
| 3459 | .siclk(siclk), |
| 3460 | .soclk(soclk) |
| 3461 | ); |
| 3462 | |
| 3463 | ////////////////////////////////////////////////////////////////////// |
| 3464 | // FB next link valid: |
| 3465 | // Set in the C4 cycle of an operation that writes mbid into |
| 3466 | // the Fill Buffer. REset in the C4 cycle of a Fill operation. |
| 3467 | // |
| 3468 | // NOTE: The resetting of next_link vld cannot be mbist_done before C4 |
| 3469 | // since it is only set in C4 of a miss buffer/IQ operation. |
| 3470 | ////////////////////////////////////////////////////////////////////// |
| 3471 | |
| 3472 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_fill_complete_c4 |
| 3473 | (.din(fill_complete_c3[7:0]), .l1clk(l1clk), |
| 3474 | .scan_in(ff_fill_complete_c4_scanin), |
| 3475 | .scan_out(ff_fill_complete_c4_scanout), |
| 3476 | .dout(fill_complete_c4[7:0]), |
| 3477 | .siclk(siclk), |
| 3478 | .soclk(soclk) |
| 3479 | ); |
| 3480 | |
| 3481 | |
| 3482 | assign fb_next_link_vld_in = ( fb_next_link_vld | |
| 3483 | dep_wr_ptr_c4 | |
| 3484 | non_dep_wr_ptr_c4 ) & |
| 3485 | ~fill_complete_c4 ; |
| 3486 | |
| 3487 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_fb_next_link_vld // sync reset active low |
| 3488 | (.din(fb_next_link_vld_in[7:0]), .l1clk(l1clk), |
| 3489 | .scan_in(ff_fb_next_link_vld_scanin), |
| 3490 | .scan_out(ff_fb_next_link_vld_scanout), |
| 3491 | .clr(~dbb_rst_l), .dout(fb_next_link_vld[7:0]), |
| 3492 | .siclk(siclk), |
| 3493 | .soclk(soclk) |
| 3494 | ); |
| 3495 | |
| 3496 | |
| 3497 | //////////////// |
| 3498 | // Ready logic for dependent instructions. |
| 3499 | // Dependents/Store instructions are readied on a Fill. |
| 3500 | // |
| 3501 | // In L2 off mode, stores are readied when the FB entry has |
| 3502 | // the complete 64Bytes. Hence, we do not ready stores on |
| 3503 | // a Fill in L2 OFF mode. |
| 3504 | ///////////////// |
| 3505 | |
| 3506 | assign fill_entry_0to3_c4 = |( fill_complete_c4[3:0]) ; |
| 3507 | |
| 3508 | |
| 3509 | // Added for one hot sel and scan protection. |
| 3510 | assign fill_complete_0to3_def = ~(|fill_complete_c4[2:0]); |
| 3511 | assign fill_complete_4to7_def = ~(|fill_complete_c4[6:4]); |
| 3512 | |
| 3513 | assign fill_complete_sel[0] = fill_complete_c4[0] ; |
| 3514 | assign fill_complete_sel[1] = fill_complete_c4[1] ; |
| 3515 | assign fill_complete_sel[2] = fill_complete_c4[2] ; |
| 3516 | assign fill_complete_sel[3] = fill_complete_0to3_def ; |
| 3517 | |
| 3518 | assign fill_complete_sel[4] = fill_complete_c4[4] ; |
| 3519 | assign fill_complete_sel[5] = fill_complete_c4[5] ; |
| 3520 | assign fill_complete_sel[6] = fill_complete_c4[6] ; |
| 3521 | assign fill_complete_sel[7] = fill_complete_4to7_def ; |
| 3522 | |
| 3523 | // BS & SR 11/04/03, MB grows to 32 |
| 3524 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux1_dep_mbid |
| 3525 | (.dout(mux1_dep_mbid_c4[4:0]), |
| 3526 | .din0(mbid0[4:0]), .din1(mbid1[4:0]), .din2(mbid2[4:0]), .din3(mbid3[4:0]), |
| 3527 | .sel0(fill_complete_sel[0]), .sel1(fill_complete_sel[1]), |
| 3528 | .sel2(fill_complete_sel[2]), .sel3(fill_complete_sel[3])); |
| 3529 | |
| 3530 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 mux2_dep_mbid |
| 3531 | (.dout(mux2_dep_mbid_c4[4:0]), |
| 3532 | .din0(mbid4[4:0]), .din1(mbid5[4:0]), .din2(mbid6[4:0]), .din3(mbid7[4:0]), |
| 3533 | .sel0(fill_complete_sel[4]), .sel1(fill_complete_sel[5]), |
| 3534 | .sel2(fill_complete_sel[6]), .sel3(fill_complete_sel[7])); |
| 3535 | |
| 3536 | |
| 3537 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 mux3_dep_mbid // BS & SR 11/04/03, MB grows to 32 |
| 3538 | (.dout(filbuf_fbf_enc_dep_mbid_c4[4:0]), |
| 3539 | .din0(mux1_dep_mbid_c4[4:0]), .din1(mux2_dep_mbid_c4[4:0]), |
| 3540 | .sel0(fill_entry_0to3_c4), .sel1(~fill_entry_0to3_c4)); |
| 3541 | |
| 3542 | |
| 3543 | assign filbuf_fbf_st_or_dep_rdy_c4 = |( fill_complete_c4 & |
| 3544 | ( fb_next_link_vld | // real dep. |
| 3545 | (fb_stinst & ~{8{l2_bypass_mode_on_d1}}) | // store inst |
| 3546 | (~fb_stinst & ~fb_nofill & {8{l2_dir_map_on_d1}} )) // any inst in dir map mode. |
| 3547 | // no FILLS have to be gated off because they |
| 3548 | // are invalidated in this cycle. |
| 3549 | ); |
| 3550 | |
| 3551 | |
| 3552 | |
| 3553 | ////////////////////////////////////////////////////////////////////// |
| 3554 | // FB data interface. |
| 3555 | // fbdata has two ports 1r and 1w. Read is performed in PH1 and write |
| 3556 | // in PH2. |
| 3557 | // |
| 3558 | // THe operations causing a read are as follows: |
| 3559 | // - Any operation that hits the FB in |
| 3560 | // - An Imiss operation hitting the FB accesses it for 2 cycles. |
| 3561 | // - A Fill operation |
| 3562 | // Here is the pipeline for read enable and read wl generation. |
| 3563 | // |
| 3564 | //------------------------------------------------------------------- |
| 3565 | // C2 C3 C4 |
| 3566 | //------------------------------------------------------------------- |
| 3567 | // generate flop read |
| 3568 | // hit in tag FB data. |
| 3569 | // and hit entry |
| 3570 | // |
| 3571 | // generate wen xmit |
| 3572 | // and wordline to fbdata |
| 3573 | // |
| 3574 | // xmit to |
| 3575 | // tag |
| 3576 | //------------------------------------------------------------------- |
| 3577 | // |
| 3578 | ////////////////////////////////////////////////////////////////////// |
| 3579 | |
| 3580 | ///////// |
| 3581 | // Wr en and wr wordline generation. |
| 3582 | ///////// |
| 3583 | |
| 3584 | |
| 3585 | // change r1 to r2 in the following equation. |
| 3586 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 mux_fbwr_entry_c2 |
| 3587 | (.dout(filbuf_fbd_wr_entry_r1[2:0]), |
| 3588 | .din0(enc_hit_vec_c2[2:0]), .din1(mcu_rd_req_id_r1[2:0]), |
| 3589 | .sel0(~filbuf_mcu_l2t_data_vld_r1), .sel1(filbuf_mcu_l2t_data_vld_r1)); |
| 3590 | |
| 3591 | |
| 3592 | ///////// |
| 3593 | // |
| 3594 | // Rd en and rd wordline generation. |
| 3595 | // |
| 3596 | ///////// |
| 3597 | |
| 3598 | assign sel_c2_fill_entry = arb_fill_vld_c2 & ~l2_bypass_mode_on_d1 ; |
| 3599 | assign sel_c3_fill_entry = fill_vld_c3 & l2_bypass_mode_on_d1 ; |
| 3600 | |
| 3601 | assign filbuf_fbd_rd_en_c2 = filbuf_tag_hit_frm_mb_c2 | // replaced from filbuf_hit_c2 |
| 3602 | imiss_ld64_fb_hit_c3 | |
| 3603 | sel_c2_fill_entry | |
| 3604 | sel_c3_fill_entry ; |
| 3605 | |
| 3606 | assign enc_hit_vec_c2[0] = fb_hit_vec_c2[1] | fb_hit_vec_c2[3] | |
| 3607 | fb_hit_vec_c2[5] | fb_hit_vec_c2[7] ; |
| 3608 | |
| 3609 | assign enc_hit_vec_c2[1] = fb_hit_vec_c2[2] | fb_hit_vec_c2[3] | |
| 3610 | fb_hit_vec_c2[6] | fb_hit_vec_c2[7] ; |
| 3611 | |
| 3612 | assign enc_hit_vec_c2[2] = fb_hit_vec_c2[4] | fb_hit_vec_c2[5] | |
| 3613 | fb_hit_vec_c2[6] | fb_hit_vec_c2[7] ; |
| 3614 | |
| 3615 | |
| 3616 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_enc_hit_vec_c3 |
| 3617 | (.din(enc_hit_vec_c2[2:0]), .l1clk(l1clk), |
| 3618 | .scan_in(ff_enc_hit_vec_c3_scanin), |
| 3619 | .scan_out(ff_enc_hit_vec_c3_scanout), |
| 3620 | .dout(enc_hit_vec_c3[2:0]), |
| 3621 | .siclk(siclk), |
| 3622 | .soclk(soclk) |
| 3623 | ); |
| 3624 | |
| 3625 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_fill_entry_c2 |
| 3626 | (.din(arbdec_arbdp_inst_mb_entry_c1[2:0]), .l1clk(l1clk), |
| 3627 | .scan_in(ff_fill_entry_c2_scanin), |
| 3628 | .scan_out(ff_fill_entry_c2_scanout), |
| 3629 | .dout(fill_entry_c2[2:0]), |
| 3630 | .siclk(siclk), |
| 3631 | .soclk(soclk) |
| 3632 | ); |
| 3633 | |
| 3634 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_fill_entry_c3 |
| 3635 | (.din(fill_entry_c2[2:0]), .l1clk(l1clk), |
| 3636 | .scan_in(ff_fill_entry_c3_scanin), |
| 3637 | .scan_out(ff_fill_entry_c3_scanout), |
| 3638 | .dout(fill_entry_c3[2:0]), |
| 3639 | .siclk(siclk), |
| 3640 | .soclk(soclk) |
| 3641 | ); |
| 3642 | |
| 3643 | |
| 3644 | // Pick C2 fill entry if Fill and $ ON |
| 3645 | // Pick C3 fill entry if Fill and $ OFF. |
| 3646 | // Else pick C3 hit entry. |
| 3647 | |
| 3648 | assign sel_def_hit_entry_mux1 = ~sel_c2_fill_entry & ~sel_c3_fill_entry ; |
| 3649 | |
| 3650 | |
| 3651 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_3 mux1_fb_entry_c2 |
| 3652 | (.dout(fb_rd_entry_c2[2:0]), |
| 3653 | .din0(fill_entry_c2[2:0]), |
| 3654 | .din1(fill_entry_c3[2:0]), |
| 3655 | .din2(enc_hit_vec_c3[2:0]), |
| 3656 | .sel0(sel_c2_fill_entry), |
| 3657 | .sel1(sel_c3_fill_entry), |
| 3658 | .sel2(sel_def_hit_entry_mux1)); |
| 3659 | |
| 3660 | assign sel_c2_entry = sel_def_hit_entry_mux1 & ~imiss_ld64_fb_hit_c3 ; |
| 3661 | |
| 3662 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 mux2_fb_entry_c2 |
| 3663 | (.dout(filbuf_fbd_rd_entry_c2[2:0]), |
| 3664 | .din0(enc_hit_vec_c2[2:0]), |
| 3665 | .din1(fb_rd_entry_c2[2:0]), |
| 3666 | .sel0(sel_c2_entry), |
| 3667 | .sel1(~sel_c2_entry)); |
| 3668 | |
| 3669 | |
| 3670 | /////////////// |
| 3671 | // PICKER |
| 3672 | /////////////// |
| 3673 | |
| 3674 | assign dbginit_l = 1'b1; |
| 3675 | |
| 3676 | // Pick from the FIll Buffer. |
| 3677 | assign init_pick_state = ~dbb_rst_l | ~dbginit_l ; |
| 3678 | |
| 3679 | // PICK STATE |
| 3680 | assign sel_l2st_lshift = arb_filbuf_fbsel_c1 & ~init_pick_state ; |
| 3681 | assign sel_l2st_same = ~arb_filbuf_fbsel_c1 & ~init_pick_state ; |
| 3682 | assign l2_rd_state_lshift = { l2_rd_state[2:0], l2_rd_state[3] } ; |
| 3683 | |
| 3684 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_rd_state |
| 3685 | (.dout(l2_rd_state_in[3:0]), |
| 3686 | .din0(4'b1), .din1(l2_rd_state_lshift[3:0]), |
| 3687 | .din2(l2_rd_state[3:0]), |
| 3688 | .sel0(init_pick_state), .sel1(sel_l2st_lshift), |
| 3689 | .sel2(sel_l2st_same)) ; |
| 3690 | l2t_filbuf_ctl_msff_ctl_macro__width_4 ff_l2_rd_state |
| 3691 | (.din(l2_rd_state_in[3:0]), .l1clk(l1clk), |
| 3692 | .scan_in(ff_l2_rd_state_scanin), |
| 3693 | .scan_out(ff_l2_rd_state_scanout), |
| 3694 | .dout(l2_rd_state[3:0]), |
| 3695 | .siclk(siclk), |
| 3696 | .soclk(soclk) |
| 3697 | ); |
| 3698 | |
| 3699 | // PICK STATE quad0 |
| 3700 | assign sel_l2st_lshift_quad0 = ( arb_filbuf_fbsel_c1 |
| 3701 | & (|(fb_l2_rd_ptr[3:0])) ) & ~init_pick_state ; |
| 3702 | assign sel_l2st_same_quad0 = ~( arb_filbuf_fbsel_c1 & |
| 3703 | (|(fb_l2_rd_ptr[3:0])) ) & ~init_pick_state ; |
| 3704 | assign l2_rd_state_lshift_quad0 = { l2_rd_state_quad0[2:0], l2_rd_state_quad0[3] } ; |
| 3705 | |
| 3706 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_rd_state_quad0 |
| 3707 | (.dout(l2_rd_state_in_quad0[3:0]), |
| 3708 | .din0(4'b1), .din1(l2_rd_state_lshift_quad0[3:0]), |
| 3709 | .din2(l2_rd_state_quad0[3:0]), |
| 3710 | .sel0(init_pick_state), .sel1(sel_l2st_lshift_quad0), |
| 3711 | .sel2(sel_l2st_same_quad0)) ; |
| 3712 | l2t_filbuf_ctl_msff_ctl_macro__width_4 ff_l2_rd_state_quad0 |
| 3713 | (.din(l2_rd_state_in_quad0[3:0]), .l1clk(l1clk), |
| 3714 | .scan_in(ff_l2_rd_state_quad0_scanin), |
| 3715 | .scan_out(ff_l2_rd_state_quad0_scanout), |
| 3716 | .dout(l2_rd_state_quad0[3:0]), |
| 3717 | .siclk(siclk), |
| 3718 | .soclk(soclk) |
| 3719 | ); |
| 3720 | // PICK STATE quad1 |
| 3721 | assign sel_l2st_lshift_quad1 = ( arb_filbuf_fbsel_c1 |
| 3722 | & (|(fb_l2_rd_ptr[3:0])) ) & ~init_pick_state ; |
| 3723 | assign sel_l2st_same_quad1 = ~( arb_filbuf_fbsel_c1 |
| 3724 | & (|(fb_l2_rd_ptr[3:0])) ) & ~init_pick_state ; |
| 3725 | assign l2_rd_state_lshift_quad1 = { l2_rd_state_quad1[2:0], l2_rd_state_quad1[3] } ; |
| 3726 | |
| 3727 | l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_l2_rd_state_quad1 |
| 3728 | (.dout(l2_rd_state_in_quad1[3:0]), |
| 3729 | .din0(4'b1), .din1(l2_rd_state_lshift_quad1[3:0]), |
| 3730 | .din2(l2_rd_state_quad1[3:0]), |
| 3731 | .sel0(init_pick_state), .sel1(sel_l2st_lshift_quad1), |
| 3732 | .sel2(sel_l2st_same_quad1)) ; |
| 3733 | l2t_filbuf_ctl_msff_ctl_macro__width_4 ff_l2_rd_state_quad1 |
| 3734 | (.din(l2_rd_state_in_quad1[3:0]), .l1clk(l1clk), |
| 3735 | .scan_in(ff_l2_rd_state_quad1_scanin), |
| 3736 | .scan_out(ff_l2_rd_state_quad1_scanout), |
| 3737 | .dout(l2_rd_state_quad1[3:0]), |
| 3738 | .siclk(siclk), |
| 3739 | .soclk(soclk) |
| 3740 | ); |
| 3741 | |
| 3742 | |
| 3743 | |
| 3744 | // anchor |
| 3745 | assign pick_s0 = l2_rd_state[0] ; |
| 3746 | assign pick_s1 = l2_rd_state[1] ; |
| 3747 | assign pick_s2 = l2_rd_state[2] ; |
| 3748 | assign pick_s3 = l2_rd_state[3] ; |
| 3749 | |
| 3750 | assign pick_s0_quad0 = l2_rd_state_quad0[0]; |
| 3751 | assign pick_s1_quad0 = l2_rd_state_quad0[1]; |
| 3752 | assign pick_s2_quad0 = l2_rd_state_quad0[2]; |
| 3753 | assign pick_s3_quad0 = l2_rd_state_quad0[3]; |
| 3754 | |
| 3755 | assign pick_s0_quad1 = l2_rd_state_quad1[0]; |
| 3756 | assign pick_s1_quad1 = l2_rd_state_quad1[1]; |
| 3757 | assign pick_s2_quad1 = l2_rd_state_quad1[2]; |
| 3758 | assign pick_s3_quad1 = l2_rd_state_quad1[3]; |
| 3759 | |
| 3760 | |
| 3761 | // anchor quads |
| 3762 | assign pick_quad_s0 = ( pick_s0 | pick_s2 ) ; |
| 3763 | assign pick_quad_s1 = ( pick_s1 | pick_s3 ) ; |
| 3764 | |
| 3765 | // sel vector |
| 3766 | assign pick_quad0_in = ( l2_pick_vec[3:0] ); |
| 3767 | assign pick_quad1_in = ( l2_pick_vec[7:4] ) ; |
| 3768 | |
| 3769 | // sel vector quad |
| 3770 | assign pick_quad_in[0] = |( pick_quad0_in ) ; |
| 3771 | assign pick_quad_in[1] = |( pick_quad1_in ) ; |
| 3772 | |
| 3773 | |
| 3774 | // QUAD0 bits. |
| 3775 | assign pick_quad0_sel[0] = pick_quad0_in[0] & ( pick_s0_quad0 | |
| 3776 | ( pick_s1_quad0 & ~( pick_quad0_in[1] | |
| 3777 | pick_quad0_in[2] | pick_quad0_in[3] ) ) | |
| 3778 | ( pick_s2_quad0 & ~(pick_quad0_in[2] | pick_quad0_in[3] )) | |
| 3779 | ( pick_s3_quad0 & ~(pick_quad0_in[3] ) ) ) ; |
| 3780 | |
| 3781 | assign pick_quad0_sel[1] = pick_quad0_in[1] & ( pick_s1_quad0 | |
| 3782 | ( pick_s2_quad0 & ~( pick_quad0_in[2] | |
| 3783 | pick_quad0_in[3] | pick_quad0_in[0] ) ) | |
| 3784 | ( pick_s3_quad0 & ~(pick_quad0_in[3] | pick_quad0_in[0] )) | |
| 3785 | ( pick_s0_quad0 & ~(pick_quad0_in[0] ) ) ) ; |
| 3786 | |
| 3787 | |
| 3788 | assign pick_quad0_sel[2] = pick_quad0_in[2] & ( pick_s2_quad0 | |
| 3789 | ( pick_s3_quad0 & ~( pick_quad0_in[3] | |
| 3790 | pick_quad0_in[0] | pick_quad0_in[1] ) ) | |
| 3791 | ( pick_s0_quad0 & ~(pick_quad0_in[0] | pick_quad0_in[1] )) | |
| 3792 | ( pick_s1_quad0 & ~(pick_quad0_in[1] ) ) ) ; |
| 3793 | |
| 3794 | assign pick_quad0_sel[3] = pick_quad0_in[3] & ( pick_s3_quad0 | |
| 3795 | ( pick_s0_quad0 & ~( pick_quad0_in[0] | |
| 3796 | pick_quad0_in[1] | pick_quad0_in[2] ) ) | |
| 3797 | ( pick_s1_quad0 & ~(pick_quad0_in[1] | pick_quad0_in[2] )) | |
| 3798 | ( pick_s2_quad0 & ~(pick_quad0_in[2] ) ) ) ; |
| 3799 | |
| 3800 | |
| 3801 | // QUAD1 bits. |
| 3802 | assign pick_quad1_sel[0] = pick_quad1_in[0] & ( pick_s0_quad1 | |
| 3803 | ( pick_s1_quad1 & ~( pick_quad1_in[1] | |
| 3804 | pick_quad1_in[2] | pick_quad1_in[3] ) ) | |
| 3805 | ( pick_s2_quad1 & ~(pick_quad1_in[2] | pick_quad1_in[3] )) | |
| 3806 | ( pick_s3_quad1 & ~(pick_quad1_in[3] ) ) ) ; |
| 3807 | |
| 3808 | |
| 3809 | assign pick_quad1_sel[1] = pick_quad1_in[1] & ( pick_s1_quad1 | |
| 3810 | ( pick_s2_quad1 & ~( pick_quad1_in[2] | |
| 3811 | pick_quad1_in[3] | pick_quad1_in[0] ) ) | |
| 3812 | ( pick_s3_quad1 & ~(pick_quad1_in[3] | pick_quad1_in[0] )) | |
| 3813 | ( pick_s0_quad1 & ~(pick_quad1_in[0] ) ) ) ; |
| 3814 | |
| 3815 | |
| 3816 | assign pick_quad1_sel[2] = pick_quad1_in[2] & ( pick_s2_quad1 | |
| 3817 | ( pick_s3_quad1 & ~( pick_quad1_in[3] | |
| 3818 | pick_quad1_in[0] | pick_quad1_in[1] ) ) | |
| 3819 | ( pick_s0_quad1 & ~(pick_quad1_in[0] | pick_quad1_in[1] )) | |
| 3820 | ( pick_s1_quad1 & ~(pick_quad1_in[1] ) ) ) ; |
| 3821 | |
| 3822 | assign pick_quad1_sel[3] = pick_quad1_in[3] & ( pick_s3_quad1 | |
| 3823 | ( pick_s0_quad1 & ~( pick_quad1_in[0] | |
| 3824 | pick_quad1_in[1] | pick_quad1_in[2] ) ) | |
| 3825 | ( pick_s1_quad1 & ~(pick_quad1_in[1] | pick_quad1_in[2] )) | |
| 3826 | ( pick_s2_quad1 & ~(pick_quad1_in[2] ) ) ) ; |
| 3827 | |
| 3828 | // QUAD |
| 3829 | |
| 3830 | assign pick_quad_sel[0] = pick_quad_in[0] & ( pick_quad_s0 | |
| 3831 | ( pick_quad_s1 & ~pick_quad_in[1] ) ) ; |
| 3832 | |
| 3833 | assign pick_quad_sel[1] = pick_quad_in[1] & ( pick_quad_s1 | |
| 3834 | ( pick_quad_s0 & ~pick_quad_in[0] ) ) ; |
| 3835 | |
| 3836 | assign fb_l2_rd_ptr_in[3:0] = ( pick_quad0_sel[3:0] & {4{pick_quad_sel[0]}} ) ; |
| 3837 | assign fb_l2_rd_ptr_in[7:4] = ( pick_quad1_sel[3:0] & {4{pick_quad_sel[1]}} ) ; |
| 3838 | |
| 3839 | assign filbuf_fbtag_rd_ptr[7:0] = l2t_mb2_run_r1 ? mbist_fbtag_wr_ptr[7:0] : fb_l2_rd_ptr_in[7:0] ; |
| 3840 | |
| 3841 | l2t_filbuf_ctl_msff_ctl_macro__width_8 ff_l2_rd_ptr |
| 3842 | (.din(fb_l2_rd_ptr_in[7:0]), .l1clk(l1clk), |
| 3843 | .scan_in(ff_l2_rd_ptr_scanin), |
| 3844 | .scan_out(ff_l2_rd_ptr_scanout), |
| 3845 | .dout(fb_l2_rd_ptr[7:0]), |
| 3846 | .siclk(siclk), |
| 3847 | .soclk(soclk) |
| 3848 | ); |
| 3849 | |
| 3850 | |
| 3851 | ////////////////////////////////////////////////////////////////////////////////// |
| 3852 | // DRAM related ERRORs |
| 3853 | // fb_Cerr and fb_uerr: |
| 3854 | // |
| 3855 | // When a DRAM read access encounters an error, an error indication is sent |
| 3856 | // to the L2$. The L2 uses this indication to set DAC/DAU bits in the Error |
| 3857 | // Status register. |
| 3858 | // fb_cerr or fb_uerr bits are set synchronous with any data xfer from mcu. |
| 3859 | // |
| 3860 | // If an instruction issued from the Miss Buffer hits an entry in the Fill Buffer |
| 3861 | // with fb_cerr or fb_uerr, an error indication is reported to the sparcs |
| 3862 | // and the err bits are reset in filbuf. |
| 3863 | // AN error is not cleared in the case of a wr8 hitting the fill buffer in |
| 3864 | // OFF mode. In this case, we wait for the fill to clear the ERROR |
| 3865 | // after causing a DAU to be reported.This is because a WR8 instruction will |
| 3866 | // not be sending a st_ack but an evict_ack to the sparcs. The ERR field of |
| 3867 | // a CPX evict_ack is ignored. |
| 3868 | // |
| 3869 | // Note: Set condition has a higher priority than the reset condition. |
| 3870 | // |
| 3871 | // If a fill happens before the bypass operation, an error indication is sent( to the cores) |
| 3872 | // synchronous with the fill oepration and the error bits are reset in filbuf. |
| 3873 | // |
| 3874 | // The following signals are generated in l2t_filbuf for logging and |
| 3875 | // reporting. |
| 3876 | // |
| 3877 | // Logging |
| 3878 | // filbuf_spc_uncorr_err_c7; // |
| 3879 | // filbuf_spc_corr_err_c7; // |
| 3880 | // filbuf_spc_rd_vld_c7; // |
| 3881 | // filbuf_bsc_corr_err_c12; // |
| 3882 | // filbuf_ld64_fb_hit_c12; // |
| 3883 | // |
| 3884 | // Reporting. |
| 3885 | // filbuf_dis_cerr_c3; |
| 3886 | // filbuf_dis_uerr_c3; |
| 3887 | // |
| 3888 | // |
| 3889 | // |
| 3890 | // filbuf_corr_err_c8, filbuf_uncorr_err_c8: Used only for logging of |
| 3891 | // errors DAC/DAU in l2t_csr_ctl.sv. Generated during a Fill. |
| 3892 | // |
| 3893 | // filbuf_spc_corr_err_c7, filbuf_spc_uncorr_err_c7: Used for logging |
| 3894 | // of DAC/DAU hits during sparc reads hitting the FIll buffer. |
| 3895 | // Also used to report errors to the issuing sparcs for |
| 3896 | // Load/imiss/pst_read hits. |
| 3897 | // |
| 3898 | // filbuf_spc_rd_vld_c7: Used for reporting errors to the issuing sparc. |
| 3899 | // This bit will be used to detect any bit flips in the data that |
| 3900 | // is in the Fill Buffer. Any errors coming from DRAM will already |
| 3901 | // be detected by the above two signals filbuf_spc_corr_err_c7 & |
| 3902 | // filbuf_spc_uncorr_err_c7. |
| 3903 | // |
| 3904 | // filbuf_bsc_corr_err_c12: Used to detect correctable errors in |
| 3905 | // an RDMA read instruction when it misses the L2. Used |
| 3906 | // for logging |
| 3907 | // |
| 3908 | // filbuf_ld64_fbhit_c12: Used for differentiating between an LDRU |
| 3909 | // and a DRU error while logging. |
| 3910 | // |
| 3911 | // |
| 3912 | // |
| 3913 | // |
| 3914 | // |
| 3915 | ////////////////////////////////////////////////////////////////////////////////// |
| 3916 | |
| 3917 | |
| 3918 | |
| 3919 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_secc_err_r3 |
| 3920 | (.din(mcu_l2t_secc_err_r2), .l1clk(l1clk), |
| 3921 | .scan_in(ff_secc_err_r3_scanin), |
| 3922 | .scan_out(ff_secc_err_r3_scanout), |
| 3923 | .dout(secc_err_r3), |
| 3924 | .siclk(siclk), |
| 3925 | .soclk(soclk) |
| 3926 | ); |
| 3927 | |
| 3928 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_mecc_err_r3 |
| 3929 | (.din(mcu_l2t_mecc_err_r2), .l1clk(l1clk), |
| 3930 | .scan_in(ff_mecc_err_r3_scanin), |
| 3931 | .scan_out(ff_mecc_err_r3_scanout), |
| 3932 | .dout(mecc_err_r3), |
| 3933 | .siclk(siclk), |
| 3934 | .soclk(soclk) |
| 3935 | ); |
| 3936 | |
| 3937 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_data_vld_r2 |
| 3938 | (.din(mcu_data_vld_r1), .l1clk(l1clk), |
| 3939 | .scan_in(ff_data_vld_r2_scanin), |
| 3940 | .scan_out(ff_data_vld_r2_scanout), |
| 3941 | .dout(mcu_data_vld_r2), |
| 3942 | .siclk(siclk), |
| 3943 | .soclk(soclk) |
| 3944 | ); |
| 3945 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_data_vld_r3 |
| 3946 | (.din(mcu_data_vld_r2), .l1clk(l1clk), |
| 3947 | .scan_in(ff_data_vld_r3_scanin), |
| 3948 | .scan_out(ff_data_vld_r3_scanout), |
| 3949 | .dout(mcu_data_vld_r3), |
| 3950 | .siclk(siclk), |
| 3951 | .soclk(soclk) |
| 3952 | ); |
| 3953 | |
| 3954 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_mcu_rd_req_id_r2 |
| 3955 | (.din(mcu_rd_req_id_r1[2:0]), .l1clk(l1clk), |
| 3956 | .scan_in(ff_mcu_rd_req_id_r2_scanin), |
| 3957 | .scan_out(ff_mcu_rd_req_id_r2_scanout), |
| 3958 | .dout(mcu_rd_req_id_r2[2:0]), |
| 3959 | .siclk(siclk), |
| 3960 | .soclk(soclk) |
| 3961 | ); |
| 3962 | |
| 3963 | l2t_filbuf_ctl_msff_ctl_macro__width_3 ff_mcu_rd_req_id_r3 |
| 3964 | (.din(mcu_rd_req_id_r2[2:0]), .l1clk(l1clk), |
| 3965 | .scan_in(ff_mcu_rd_req_id_r3_scanin), |
| 3966 | .scan_out(ff_mcu_rd_req_id_r3_scanout), |
| 3967 | .dout(mcu_rd_req_id_r3[2:0]), |
| 3968 | .siclk(siclk), |
| 3969 | .soclk(soclk) |
| 3970 | ); |
| 3971 | |
| 3972 | |
| 3973 | assign fb_cerr_in[0] = ( mcu_rd_req_id_r3 == 3'd0 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3974 | assign fb_cerr_in[1] = ( mcu_rd_req_id_r3 == 3'd1 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3975 | assign fb_cerr_in[2] = ( mcu_rd_req_id_r3 == 3'd2 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3976 | assign fb_cerr_in[3] = ( mcu_rd_req_id_r3 == 3'd3 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3977 | assign fb_cerr_in[4] = ( mcu_rd_req_id_r3 == 3'd4 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3978 | assign fb_cerr_in[5] = ( mcu_rd_req_id_r3 == 3'd5 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3979 | assign fb_cerr_in[6] = ( mcu_rd_req_id_r3 == 3'd6 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3980 | assign fb_cerr_in[7] = ( mcu_rd_req_id_r3 == 3'd7 ) & secc_err_r3 & mcu_data_vld_r3; |
| 3981 | |
| 3982 | assign fb_uerr_in[0] = ( mcu_rd_req_id_r3 == 3'd0 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3983 | assign fb_uerr_in[1] = ( mcu_rd_req_id_r3 == 3'd1 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3984 | assign fb_uerr_in[2] = ( mcu_rd_req_id_r3 == 3'd2 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3985 | assign fb_uerr_in[3] = ( mcu_rd_req_id_r3 == 3'd3 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3986 | assign fb_uerr_in[4] = ( mcu_rd_req_id_r3 == 3'd4 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3987 | assign fb_uerr_in[5] = ( mcu_rd_req_id_r3 == 3'd5 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3988 | assign fb_uerr_in[6] = ( mcu_rd_req_id_r3 == 3'd6 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3989 | assign fb_uerr_in[7] = ( mcu_rd_req_id_r3 == 3'd7 ) & mecc_err_r3 & mcu_data_vld_r3; |
| 3990 | |
| 3991 | |
| 3992 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_wr8_inst_c3 |
| 3993 | (.din(arb_decdp_wr8_inst_c2), .l1clk(l1clk), |
| 3994 | .scan_in(ff_wr8_inst_c3_scanin), |
| 3995 | .scan_out(ff_wr8_inst_c3_scanout), |
| 3996 | .dout(wr8_inst_c3), |
| 3997 | .siclk(siclk), |
| 3998 | .soclk(soclk) |
| 3999 | ); |
| 4000 | |
| 4001 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_wr8_inst_c4 |
| 4002 | (.din(wr8_inst_c3), .l1clk(l1clk), |
| 4003 | .scan_in(ff_wr8_inst_c4_scanin), |
| 4004 | .scan_out(ff_wr8_inst_c4_scanout), |
| 4005 | .dout(wr8_inst_c4), |
| 4006 | .siclk(siclk), |
| 4007 | .soclk(soclk) |
| 4008 | ); |
| 4009 | |
| 4010 | assign clear_err_c3 = fb_hit_vec_c3 & {8{filbuf_hit_c3 & ~wr8_inst_c3}} ; |
| 4011 | |
| 4012 | assign fb_cerr_prev = ( fb_cerr & ~( fill_complete_c3 | clear_err_c3 ) ) |
| 4013 | | fb_cerr_in ; |
| 4014 | assign fb_uerr_prev = ( fb_uerr & ~( fill_complete_c3 | clear_err_c3 ) ) |
| 4015 | | fb_uerr_in ; |
| 4016 | |
| 4017 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_fb_cerr // sync reset active low |
| 4018 | (.din(fb_cerr_prev[7:0]), .l1clk(l1clk), .dout(fb_cerr[7:0]), |
| 4019 | .scan_in(ff_fb_cerr_scanin), |
| 4020 | .scan_out(ff_fb_cerr_scanout), |
| 4021 | .clr(~dbb_rst_l), |
| 4022 | .siclk(siclk), |
| 4023 | .soclk(soclk) |
| 4024 | |
| 4025 | ); |
| 4026 | |
| 4027 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ff_fb_uerr // sync reset active low |
| 4028 | (.din(fb_uerr_prev[7:0]), .l1clk(l1clk), .dout(fb_uerr[7:0]), |
| 4029 | .scan_in(ff_fb_uerr_scanin), |
| 4030 | .scan_out(ff_fb_uerr_scanout), |
| 4031 | .clr(~dbb_rst_l), |
| 4032 | .siclk(siclk), |
| 4033 | .soclk(soclk) |
| 4034 | |
| 4035 | ); |
| 4036 | |
| 4037 | // in case CAS1 or SWAP/ldstub 1st pass detects a UE or CE in the FIll Buffer |
| 4038 | // in off_mode , need to log the error bit in the miss buffer (mb_corr,mb_uncorr_err bits) |
| 4039 | // so that the CAS2 pass and SWAP/LDSTUB second pass also reports error in the |
| 4040 | // Store ack packet. |
| 4041 | |
| 4042 | assign filbuf_misbuf_ue_offmode_c3 = (|(fb_uerr & clear_err_c3)) & l2_bypass_mode_on_d1; |
| 4043 | assign filbuf_misbuf_ce_offmode_c3 = (|(fb_cerr & clear_err_c3)) & l2_bypass_mode_on_d1; |
| 4044 | |
| 4045 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_filbuf_misbuf_ue_offmode |
| 4046 | (.din({filbuf_misbuf_ue_offmode_c3,filbuf_misbuf_ue_offmode_c4, |
| 4047 | filbuf_misbuf_ue_offmode_c5,filbuf_misbuf_ue_offmode_c52, |
| 4048 | filbuf_misbuf_ue_offmode_c6}), |
| 4049 | .scan_in(ff_filbuf_misbuf_ue_offmode_scanin), |
| 4050 | .scan_out(ff_filbuf_misbuf_ue_offmode_scanout), |
| 4051 | .l1clk(l1clk), |
| 4052 | .dout({filbuf_misbuf_ue_offmode_c4,filbuf_misbuf_ue_offmode_c5, |
| 4053 | filbuf_misbuf_ue_offmode_c52,filbuf_misbuf_ue_offmode_c6, |
| 4054 | filbuf_misbuf_ue_offmode_c7}), |
| 4055 | .siclk(siclk), |
| 4056 | .soclk(soclk)); |
| 4057 | |
| 4058 | l2t_filbuf_ctl_msff_ctl_macro__width_5 ff_filbuf_misbuf_ce_offmode |
| 4059 | (.din({filbuf_misbuf_ce_offmode_c3,filbuf_misbuf_ce_offmode_c4, |
| 4060 | filbuf_misbuf_ce_offmode_c5,filbuf_misbuf_ce_offmode_c52, |
| 4061 | filbuf_misbuf_ce_offmode_c6}), |
| 4062 | .scan_in(ff_filbuf_misbuf_ce_offmode_scanin), |
| 4063 | .scan_out(ff_filbuf_misbuf_ce_offmode_scanout), |
| 4064 | .l1clk(l1clk), |
| 4065 | .dout({filbuf_misbuf_ce_offmode_c4,filbuf_misbuf_ce_offmode_c5, |
| 4066 | filbuf_misbuf_ce_offmode_c52,filbuf_misbuf_ce_offmode_c6, |
| 4067 | filbuf_misbuf_ce_offmode_c7}), |
| 4068 | .siclk(siclk), |
| 4069 | .soclk(soclk)); |
| 4070 | |
| 4071 | |
| 4072 | ////////////////////////// |
| 4073 | // Error during a FIll: |
| 4074 | // Reported to the CSR block. |
| 4075 | // |
| 4076 | // The fb_cerr/fb_uerr bits are |
| 4077 | // cleared by a fill or a HIT |
| 4078 | // except for a wr8 hit. |
| 4079 | // |
| 4080 | // However, a filbuf_corr err |
| 4081 | // or filbuf_uncorr_err is |
| 4082 | // signalled only for a fill. |
| 4083 | // |
| 4084 | ////////////////////////// |
| 4085 | |
| 4086 | |
| 4087 | assign filbuf_corr_err_c3 = |( dec_fill_entry_c3 & fb_cerr ) ; |
| 4088 | assign filbuf_uncorr_err_c3 = |( dec_fill_entry_c3 & fb_uerr ) ; |
| 4089 | |
| 4090 | |
| 4091 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_corr_err_c4 |
| 4092 | (.din(filbuf_corr_err_c3), .l1clk(l1clk), |
| 4093 | .scan_in(ff_filbuf_corr_err_c4_scanin), |
| 4094 | .scan_out(ff_filbuf_corr_err_c4_scanout), |
| 4095 | .dout(filbuf_corr_err_c4), |
| 4096 | .siclk(siclk), |
| 4097 | .soclk(soclk) |
| 4098 | ); |
| 4099 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_corr_err_c5 |
| 4100 | (.din(filbuf_corr_err_c4), .l1clk(l1clk), |
| 4101 | .scan_in(ff_filbuf_corr_err_c5_scanin), |
| 4102 | .scan_out(ff_filbuf_corr_err_c5_scanout), |
| 4103 | .dout(filbuf_corr_err_c5), |
| 4104 | .siclk(siclk), |
| 4105 | .soclk(soclk) |
| 4106 | ); |
| 4107 | // BS 03/11/04 extra cycle for mem access |
| 4108 | |
| 4109 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_corr_err_c52 |
| 4110 | (.din(filbuf_corr_err_c5), .l1clk(l1clk), |
| 4111 | .scan_in(ff_filbuf_corr_err_c52_scanin), |
| 4112 | .scan_out(ff_filbuf_corr_err_c52_scanout), |
| 4113 | .dout(filbuf_corr_err_c52), |
| 4114 | .siclk(siclk), |
| 4115 | .soclk(soclk) |
| 4116 | ); |
| 4117 | |
| 4118 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_corr_err_c6 |
| 4119 | (.din(filbuf_corr_err_c52), .l1clk(l1clk), |
| 4120 | .scan_in(ff_filbuf_corr_err_c6_scanin), |
| 4121 | .scan_out(ff_filbuf_corr_err_c6_scanout), |
| 4122 | .dout(filbuf_corr_err_c6), |
| 4123 | .siclk(siclk), |
| 4124 | .soclk(soclk) |
| 4125 | ); |
| 4126 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_corr_err_c7 |
| 4127 | (.din(filbuf_corr_err_c6), .l1clk(l1clk), |
| 4128 | .scan_in(ff_filbuf_corr_err_c7_scanin), |
| 4129 | .scan_out(ff_filbuf_corr_err_c7_scanout), |
| 4130 | .dout(filbuf_corr_err_c7), |
| 4131 | .siclk(siclk), |
| 4132 | .soclk(soclk) |
| 4133 | ); |
| 4134 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_corr_err_c8 |
| 4135 | (.din(filbuf_corr_err_c7), .l1clk(l1clk), |
| 4136 | .scan_in(ff_filbuf_corr_err_c8_scanin), |
| 4137 | .scan_out(ff_filbuf_corr_err_c8_scanout), |
| 4138 | .dout(filbuf_corr_err_c8), |
| 4139 | .siclk(siclk), |
| 4140 | .soclk(soclk) |
| 4141 | ); |
| 4142 | |
| 4143 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_uncorr_err_c4 |
| 4144 | (.din(filbuf_uncorr_err_c3), .l1clk(l1clk), |
| 4145 | .scan_in(ff_filbuf_uncorr_err_c4_scanin), |
| 4146 | .scan_out(ff_filbuf_uncorr_err_c4_scanout), |
| 4147 | .dout(filbuf_uncorr_err_c4), |
| 4148 | .siclk(siclk), |
| 4149 | .soclk(soclk) |
| 4150 | ); |
| 4151 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_uncorr_err_c5 |
| 4152 | (.din(filbuf_uncorr_err_c4), .l1clk(l1clk), |
| 4153 | .scan_in(ff_filbuf_uncorr_err_c5_scanin), |
| 4154 | .scan_out(ff_filbuf_uncorr_err_c5_scanout), |
| 4155 | .dout(filbuf_uncorr_err_c5), |
| 4156 | .siclk(siclk), |
| 4157 | .soclk(soclk) |
| 4158 | ); |
| 4159 | |
| 4160 | // BS 03/11/04 extra cycle for mem access |
| 4161 | |
| 4162 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_uncorr_err_c52 |
| 4163 | (.din(filbuf_uncorr_err_c5), .l1clk(l1clk), |
| 4164 | .scan_in(ff_filbuf_uncorr_err_c52_scanin), |
| 4165 | .scan_out(ff_filbuf_uncorr_err_c52_scanout), |
| 4166 | .dout(filbuf_uncorr_err_c52), |
| 4167 | .siclk(siclk), |
| 4168 | .soclk(soclk) |
| 4169 | ); |
| 4170 | |
| 4171 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_uncorr_err_c6 |
| 4172 | (.din(filbuf_uncorr_err_c52), .l1clk(l1clk), |
| 4173 | .scan_in(ff_filbuf_uncorr_err_c6_scanin), |
| 4174 | .scan_out(ff_filbuf_uncorr_err_c6_scanout), |
| 4175 | .dout(filbuf_uncorr_err_c6), |
| 4176 | .siclk(siclk), |
| 4177 | .soclk(soclk) |
| 4178 | ); |
| 4179 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_uncorr_err_c7 |
| 4180 | (.din(filbuf_uncorr_err_c6), .l1clk(l1clk), |
| 4181 | .scan_in(ff_filbuf_uncorr_err_c7_scanin), |
| 4182 | .scan_out(ff_filbuf_uncorr_err_c7_scanout), |
| 4183 | .dout(filbuf_uncorr_err_c7), |
| 4184 | .siclk(siclk), |
| 4185 | .soclk(soclk) |
| 4186 | ); |
| 4187 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_uncorr_err_c8 |
| 4188 | (.din(filbuf_uncorr_err_c7), .l1clk(l1clk), |
| 4189 | .scan_in(ff_filbuf_uncorr_err_c8_scanin), |
| 4190 | .scan_out(ff_filbuf_uncorr_err_c8_scanout), |
| 4191 | .dout(filbuf_uncorr_err_c8), |
| 4192 | .siclk(siclk), |
| 4193 | .soclk(soclk) |
| 4194 | ); |
| 4195 | |
| 4196 | |
| 4197 | |
| 4198 | /////////////////////////// |
| 4199 | // Error During a Hit. |
| 4200 | // Sent to the decc block |
| 4201 | /////////////////////////// |
| 4202 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_hit_c3 |
| 4203 | (.din(filbuf_hit_c2), .l1clk(l1clk), |
| 4204 | .scan_in(ff_filbuf_hit_c3_scanin), |
| 4205 | .scan_out(ff_filbuf_hit_c3_scanout), |
| 4206 | .dout(filbuf_hit_c3), |
| 4207 | .siclk(siclk), |
| 4208 | .soclk(soclk) |
| 4209 | ); |
| 4210 | |
| 4211 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_filbuf_hit_c4 |
| 4212 | (.din(filbuf_hit_c3), .l1clk(l1clk), |
| 4213 | .scan_in(ff_filbuf_hit_c4_scanin), |
| 4214 | .scan_out(ff_filbuf_hit_c4_scanout), |
| 4215 | .dout(filbuf_hit_c4), |
| 4216 | .siclk(siclk), |
| 4217 | .soclk(soclk) |
| 4218 | ); |
| 4219 | |
| 4220 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_imiss_inst_c3 |
| 4221 | (.din(arb_decdp_imiss_inst_c2), .l1clk(l1clk), |
| 4222 | .scan_in(ff_imiss_inst_c3_scanin), |
| 4223 | .scan_out(ff_imiss_inst_c3_scanout), |
| 4224 | .dout(imiss_inst_c3), |
| 4225 | .siclk(siclk), |
| 4226 | .soclk(soclk) |
| 4227 | ); |
| 4228 | |
| 4229 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_imiss_inst_c4 |
| 4230 | (.din(imiss_inst_c3), .l1clk(l1clk), |
| 4231 | .scan_in(ff_imiss_inst_c4_scanin), |
| 4232 | .scan_out(ff_imiss_inst_c4_scanout), |
| 4233 | .dout(imiss_inst_c4), |
| 4234 | .siclk(siclk), |
| 4235 | .soclk(soclk) |
| 4236 | ); |
| 4237 | |
| 4238 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_inst_c3 |
| 4239 | (.din(arb_decdp_ld64_inst_c2), .l1clk(l1clk), |
| 4240 | .scan_in(ff_ld64_inst_c3_scanin), |
| 4241 | .scan_out(ff_ld64_inst_c3_scanout), |
| 4242 | .dout(ld64_inst_c3), |
| 4243 | .siclk(siclk), |
| 4244 | .soclk(soclk) |
| 4245 | ); |
| 4246 | |
| 4247 | assign spc_rd_vld_c3 = (filbuf_hit_c3 & tag_spc_rd_cond_c3) | // any read of the Fill buffer.( other than rdma inst) |
| 4248 | // should cause spc_rd_vld_c3 to go high. |
| 4249 | ( filbuf_hit_c4 & imiss_inst_c4 ) ; |
| 4250 | |
| 4251 | |
| 4252 | |
| 4253 | |
| 4254 | //////////////////////////// |
| 4255 | // sparc read |
| 4256 | //////////////////////////// |
| 4257 | |
| 4258 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_rd_vld_c4 |
| 4259 | (.din(spc_rd_vld_c3), .l1clk(l1clk), |
| 4260 | .scan_in(ff_spc_rd_vld_c4_scanin), |
| 4261 | .scan_out(ff_spc_rd_vld_c4_scanout), |
| 4262 | .dout(spc_rd_vld_c4), |
| 4263 | .siclk(siclk), |
| 4264 | .soclk(soclk) |
| 4265 | ); |
| 4266 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_rd_vld_c5 |
| 4267 | (.din(spc_rd_vld_c4), .l1clk(l1clk), |
| 4268 | .scan_in(ff_spc_rd_vld_c5_scanin), |
| 4269 | .scan_out(ff_spc_rd_vld_c5_scanout), |
| 4270 | .dout(spc_rd_vld_c5), |
| 4271 | .siclk(siclk), |
| 4272 | .soclk(soclk) |
| 4273 | ); |
| 4274 | |
| 4275 | // BS 03/11/04 extra cycle for mem access |
| 4276 | |
| 4277 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_rd_vld_c52 |
| 4278 | (.din(spc_rd_vld_c5), .l1clk(l1clk), |
| 4279 | .scan_in(ff_spc_rd_vld_c52_scanin), |
| 4280 | .scan_out(ff_spc_rd_vld_c52_scanout), |
| 4281 | .dout(spc_rd_vld_c52), |
| 4282 | .siclk(siclk), |
| 4283 | .soclk(soclk) |
| 4284 | ); |
| 4285 | |
| 4286 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_rd_vld_c6 |
| 4287 | (.din(spc_rd_vld_c52), .l1clk(l1clk), |
| 4288 | .scan_in(ff_spc_rd_vld_c6_scanin), |
| 4289 | .scan_out(ff_spc_rd_vld_c6_scanout), |
| 4290 | .dout(spc_rd_vld_c6), |
| 4291 | .siclk(siclk), |
| 4292 | .soclk(soclk) |
| 4293 | ); |
| 4294 | //msff_ctl_macro ff_spc_rd_vld_c7 (width=1) |
| 4295 | // (.din(spc_rd_vld_c6), .l1clk(l1clk), |
| 4296 | // .scan_in(ff_spc_rd_vld_c7_scanin), |
| 4297 | // .scan_out(ff_spc_rd_vld_c7_scanout), |
| 4298 | // .dout(spc_rd_vld_c7), |
| 4299 | //); |
| 4300 | |
| 4301 | assign filbuf_spc_rd_vld_c6 = spc_rd_vld_c6 ; |
| 4302 | |
| 4303 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_fbcerr0_d1 |
| 4304 | (.din(fb_cerr[0]), .l1clk(l1clk), |
| 4305 | .scan_in(ff_fbcerr0_d1_scanin), |
| 4306 | .scan_out(ff_fbcerr0_d1_scanout), |
| 4307 | .dout(fbcerr0_d1), |
| 4308 | .siclk(siclk), |
| 4309 | .soclk(soclk) |
| 4310 | ); |
| 4311 | |
| 4312 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_fbuerr0_d1 |
| 4313 | (.din(fb_uerr[0]), .l1clk(l1clk), |
| 4314 | .scan_in(ff_fbuerr0_d1_scanin), |
| 4315 | .scan_out(ff_fbuerr0_d1_scanout), |
| 4316 | .dout(fbuerr0_d1), |
| 4317 | .siclk(siclk), |
| 4318 | .soclk(soclk) |
| 4319 | ); |
| 4320 | |
| 4321 | // In the OFF mode, fb_cerr & fb_uerr are reset in the C2 cycle of |
| 4322 | // a hit. Hence they are unavailable for setting fbhit_cerr_err_c3 & |
| 4323 | // fbhit_uerr_err_c3. This problem can be solved by flopping fb_cerr_0 and |
| 4324 | // fb_uerr_0 and using them in the L2 off mode for flagging errors. |
| 4325 | // |
| 4326 | |
| 4327 | assign fbhit_cerr_err_c3 = (|( fb_hit_vec_c3 & fb_cerr ) | |
| 4328 | (fb_hit_vec_c3[0] & fbcerr0_d1 & l2_bypass_mode_on_d1)) |
| 4329 | & qual_hit_vec_c3 ; |
| 4330 | assign fbhit_uerr_err_c3 = (|( fb_hit_vec_c3 & fb_uerr ) | |
| 4331 | (fb_hit_vec_c3[0] & fbuerr0_d1 & l2_bypass_mode_on_d1)) |
| 4332 | & qual_hit_vec_c3 ; |
| 4333 | |
| 4334 | |
| 4335 | assign spc_corr_err_c3 = fbhit_cerr_err_c3 & |
| 4336 | spc_rd_vld_c3 ; // the first packet of |
| 4337 | // an imiss will clear |
| 4338 | // the cerr bit. |
| 4339 | |
| 4340 | assign spc_uncorr_err_c3 = fbhit_uerr_err_c3 & |
| 4341 | spc_rd_vld_c3 ; // the first packet of |
| 4342 | // an imiss will clear |
| 4343 | // the uerr bit. |
| 4344 | //////////////////////////// |
| 4345 | // sparc corr err |
| 4346 | //////////////////////////// |
| 4347 | |
| 4348 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_corr_err_c4 |
| 4349 | (.din(spc_corr_err_c3), .l1clk(l1clk), |
| 4350 | .scan_in(ff_spc_corr_err_c4_scanin), |
| 4351 | .scan_out(ff_spc_corr_err_c4_scanout), |
| 4352 | .dout(spc_corr_err_c4), |
| 4353 | .siclk(siclk), |
| 4354 | .soclk(soclk) |
| 4355 | ); |
| 4356 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_corr_err_c5 |
| 4357 | (.din(spc_corr_err_c4), .l1clk(l1clk), |
| 4358 | .scan_in(ff_spc_corr_err_c5_scanin), |
| 4359 | .scan_out(ff_spc_corr_err_c5_scanout), |
| 4360 | .dout(spc_corr_err_c5), |
| 4361 | .siclk(siclk), |
| 4362 | .soclk(soclk) |
| 4363 | ); |
| 4364 | // BS 03/11/04 extra cycle for mem access |
| 4365 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_corr_err_c52 |
| 4366 | (.din(spc_corr_err_c5), .l1clk(l1clk), |
| 4367 | .scan_in(ff_spc_corr_err_c52_scanin), |
| 4368 | .scan_out(ff_spc_corr_err_c52_scanout), |
| 4369 | .dout(spc_corr_err_c52), |
| 4370 | .siclk(siclk), |
| 4371 | .soclk(soclk) |
| 4372 | ); |
| 4373 | |
| 4374 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_corr_err_c6 |
| 4375 | (.din(spc_corr_err_c52), .l1clk(l1clk), |
| 4376 | .scan_in(ff_spc_corr_err_c6_scanin), |
| 4377 | .scan_out(ff_spc_corr_err_c6_scanout), |
| 4378 | .dout(spc_corr_err_c6), |
| 4379 | .siclk(siclk), |
| 4380 | .soclk(soclk) |
| 4381 | ); |
| 4382 | //msff_ctl_macro ff_spc_corr_err_c7 (width=1) |
| 4383 | // (.din(spc_corr_err_c6), .l1clk(l1clk), |
| 4384 | // .scan_in(ff_spc_corr_err_c7_scanin), |
| 4385 | // .scan_out(ff_spc_corr_err_c7_scanout), |
| 4386 | // .dout(spc_corr_err_c7), |
| 4387 | //); |
| 4388 | |
| 4389 | assign filbuf_spc_corr_err_c6 = spc_corr_err_c6 ; |
| 4390 | |
| 4391 | //////////////////////////// |
| 4392 | // sparc uncorr err |
| 4393 | //////////////////////////// |
| 4394 | |
| 4395 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_uncorr_err_c4 |
| 4396 | (.din(spc_uncorr_err_c3), .l1clk(l1clk), |
| 4397 | .scan_in(ff_spc_uncorr_err_c4_scanin), |
| 4398 | .scan_out(ff_spc_uncorr_err_c4_scanout), |
| 4399 | .dout(spc_uncorr_err_c4), |
| 4400 | .siclk(siclk), |
| 4401 | .soclk(soclk) |
| 4402 | ); |
| 4403 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_uncorr_err_c5 |
| 4404 | (.din(spc_uncorr_err_c4), .l1clk(l1clk), |
| 4405 | .scan_in(ff_spc_uncorr_err_c5_scanin), |
| 4406 | .scan_out(ff_spc_uncorr_err_c5_scanout), |
| 4407 | .dout(spc_uncorr_err_c5), |
| 4408 | .siclk(siclk), |
| 4409 | .soclk(soclk) |
| 4410 | ); |
| 4411 | // BS 03/11/04 extra cycle for mem access |
| 4412 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_uncorr_err_c52 |
| 4413 | (.din(spc_uncorr_err_c5), .l1clk(l1clk), |
| 4414 | .scan_in(ff_spc_uncorr_err_c52_scanin), |
| 4415 | .scan_out(ff_spc_uncorr_err_c52_scanout), |
| 4416 | .dout(spc_uncorr_err_c52), |
| 4417 | .siclk(siclk), |
| 4418 | .soclk(soclk) |
| 4419 | ); |
| 4420 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_spc_uncorr_err_c6 |
| 4421 | (.din(spc_uncorr_err_c52), .l1clk(l1clk), |
| 4422 | .scan_in(ff_spc_uncorr_err_c6_scanin), |
| 4423 | .scan_out(ff_spc_uncorr_err_c6_scanout), |
| 4424 | .dout(spc_uncorr_err_c6), |
| 4425 | .siclk(siclk), |
| 4426 | .soclk(soclk) |
| 4427 | ); |
| 4428 | //msff_ctl_macro ff_spc_uncorr_err_c7 (width=1) |
| 4429 | // (.din(spc_uncorr_err_c6), .l1clk(l1clk), |
| 4430 | // .scan_in(ff_spc_uncorr_err_c7_scanin), |
| 4431 | // .scan_out(ff_spc_uncorr_err_c7_scanout), |
| 4432 | // .dout(spc_uncorr_err_c7), |
| 4433 | //); |
| 4434 | |
| 4435 | assign filbuf_spc_uncorr_err_c6 = spc_uncorr_err_c6 ; |
| 4436 | |
| 4437 | //////////////////////////// |
| 4438 | // bsc corr err |
| 4439 | //////////////////////////// |
| 4440 | |
| 4441 | assign bsc_corr_err_c3 = ( filbuf_hit_c3 & ld64_inst_c3 ) & |
| 4442 | fbhit_cerr_err_c3 ; |
| 4443 | |
| 4444 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c4 |
| 4445 | (.din(bsc_corr_err_c3), .l1clk(l1clk), |
| 4446 | .scan_in(ff_bsc_corr_err_c4_scanin), |
| 4447 | .scan_out(ff_bsc_corr_err_c4_scanout), |
| 4448 | .dout(bsc_corr_err_c4), |
| 4449 | .siclk(siclk), |
| 4450 | .soclk(soclk) |
| 4451 | ); |
| 4452 | |
| 4453 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c5 |
| 4454 | (.din(bsc_corr_err_c4), .l1clk(l1clk), |
| 4455 | .scan_in(ff_bsc_corr_err_c5_scanin), |
| 4456 | .scan_out(ff_bsc_corr_err_c5_scanout), |
| 4457 | .dout(bsc_corr_err_c5), |
| 4458 | .siclk(siclk), |
| 4459 | .soclk(soclk) |
| 4460 | ); |
| 4461 | // BS 03/11/04 extra cycle for mem access |
| 4462 | |
| 4463 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c52 |
| 4464 | (.din(bsc_corr_err_c5), .l1clk(l1clk), |
| 4465 | .scan_in(ff_bsc_corr_err_c52_scanin), |
| 4466 | .scan_out(ff_bsc_corr_err_c52_scanout), |
| 4467 | .dout(bsc_corr_err_c52), |
| 4468 | .siclk(siclk), |
| 4469 | .soclk(soclk) |
| 4470 | ); |
| 4471 | |
| 4472 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c6 |
| 4473 | (.din(bsc_corr_err_c52), .l1clk(l1clk), |
| 4474 | .scan_in(ff_bsc_corr_err_c6_scanin), |
| 4475 | .scan_out(ff_bsc_corr_err_c6_scanout), |
| 4476 | .dout(bsc_corr_err_c6), |
| 4477 | .siclk(siclk), |
| 4478 | .soclk(soclk) |
| 4479 | ); |
| 4480 | |
| 4481 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c7 |
| 4482 | (.din(bsc_corr_err_c6), .l1clk(l1clk), |
| 4483 | .scan_in(ff_bsc_corr_err_c7_scanin), |
| 4484 | .scan_out(ff_bsc_corr_err_c7_scanout), |
| 4485 | .dout(bsc_corr_err_c7), |
| 4486 | .siclk(siclk), |
| 4487 | .soclk(soclk) |
| 4488 | ); |
| 4489 | |
| 4490 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c8 |
| 4491 | (.din(bsc_corr_err_c7), .l1clk(l1clk), |
| 4492 | .scan_in(ff_bsc_corr_err_c8_scanin), |
| 4493 | .scan_out(ff_bsc_corr_err_c8_scanout), |
| 4494 | .dout(bsc_corr_err_c8), |
| 4495 | .siclk(siclk), |
| 4496 | .soclk(soclk) |
| 4497 | ); |
| 4498 | |
| 4499 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c9 |
| 4500 | (.din(bsc_corr_err_c8), .l1clk(l1clk), |
| 4501 | .scan_in(ff_bsc_corr_err_c9_scanin), |
| 4502 | .scan_out(ff_bsc_corr_err_c9_scanout), |
| 4503 | .dout(bsc_corr_err_c9), |
| 4504 | .siclk(siclk), |
| 4505 | .soclk(soclk) |
| 4506 | ); |
| 4507 | |
| 4508 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c10 |
| 4509 | (.din(bsc_corr_err_c9), .l1clk(l1clk), |
| 4510 | .scan_in(ff_bsc_corr_err_c10_scanin), |
| 4511 | .scan_out(ff_bsc_corr_err_c10_scanout), |
| 4512 | .dout(bsc_corr_err_c10), |
| 4513 | .siclk(siclk), |
| 4514 | .soclk(soclk) |
| 4515 | ); |
| 4516 | |
| 4517 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c11 |
| 4518 | (.din(bsc_corr_err_c10), .l1clk(l1clk), |
| 4519 | .scan_in(ff_bsc_corr_err_c11_scanin), |
| 4520 | .scan_out(ff_bsc_corr_err_c11_scanout), |
| 4521 | .dout(bsc_corr_err_c11), |
| 4522 | .siclk(siclk), |
| 4523 | .soclk(soclk) |
| 4524 | ); |
| 4525 | |
| 4526 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_bsc_corr_err_c12 |
| 4527 | (.din(bsc_corr_err_c11), .l1clk(l1clk), |
| 4528 | .scan_in(ff_bsc_corr_err_c12_scanin), |
| 4529 | .scan_out(ff_bsc_corr_err_c12_scanout), |
| 4530 | .dout(bsc_corr_err_c12), |
| 4531 | .siclk(siclk), |
| 4532 | .soclk(soclk) |
| 4533 | ); |
| 4534 | |
| 4535 | assign filbuf_bsc_corr_err_c12 = bsc_corr_err_c12 ; |
| 4536 | |
| 4537 | |
| 4538 | //////////////////////////// |
| 4539 | // ld64 fb hit c12 |
| 4540 | //////////////////////////// |
| 4541 | |
| 4542 | |
| 4543 | assign ld64_fb_hit_c3 = (filbuf_hit_c3 & ld64_inst_c3) ; |
| 4544 | |
| 4545 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c4 |
| 4546 | (.din(ld64_fb_hit_c3), .l1clk(l1clk), |
| 4547 | .scan_in(ff_ld64_fb_hit_c4_scanin), |
| 4548 | .scan_out(ff_ld64_fb_hit_c4_scanout), |
| 4549 | .dout(ld64_fb_hit_c4), |
| 4550 | .siclk(siclk), |
| 4551 | .soclk(soclk) |
| 4552 | ); |
| 4553 | |
| 4554 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c5 |
| 4555 | (.din(ld64_fb_hit_c4), .l1clk(l1clk), |
| 4556 | .scan_in(ff_ld64_fb_hit_c5_scanin), |
| 4557 | .scan_out(ff_ld64_fb_hit_c5_scanout), |
| 4558 | .dout(ld64_fb_hit_c5), |
| 4559 | .siclk(siclk), |
| 4560 | .soclk(soclk) |
| 4561 | ); |
| 4562 | // BS 03/11/04 extra cycle for mem access |
| 4563 | |
| 4564 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c52 |
| 4565 | (.din(ld64_fb_hit_c5), .l1clk(l1clk), |
| 4566 | .scan_in(ff_ld64_fb_hit_c52_scanin), |
| 4567 | .scan_out(ff_ld64_fb_hit_c52_scanout), |
| 4568 | .dout(ld64_fb_hit_c52), |
| 4569 | .siclk(siclk), |
| 4570 | .soclk(soclk) |
| 4571 | ); |
| 4572 | |
| 4573 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c6 |
| 4574 | (.din(ld64_fb_hit_c52), .l1clk(l1clk), |
| 4575 | .scan_in(ff_ld64_fb_hit_c6_scanin), |
| 4576 | .scan_out(ff_ld64_fb_hit_c6_scanout), |
| 4577 | .dout(ld64_fb_hit_c6), |
| 4578 | .siclk(siclk), |
| 4579 | .soclk(soclk) |
| 4580 | ); |
| 4581 | |
| 4582 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c7 |
| 4583 | (.din(ld64_fb_hit_c6), .l1clk(l1clk), |
| 4584 | .scan_in(ff_ld64_fb_hit_c7_scanin), |
| 4585 | .scan_out(ff_ld64_fb_hit_c7_scanout), |
| 4586 | .dout(ld64_fb_hit_c7), |
| 4587 | .siclk(siclk), |
| 4588 | .soclk(soclk) |
| 4589 | ); |
| 4590 | |
| 4591 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c8 |
| 4592 | (.din(ld64_fb_hit_c7), .l1clk(l1clk), |
| 4593 | .scan_in(ff_ld64_fb_hit_c8_scanin), |
| 4594 | .scan_out(ff_ld64_fb_hit_c8_scanout), |
| 4595 | .dout(ld64_fb_hit_c8), |
| 4596 | .siclk(siclk), |
| 4597 | .soclk(soclk) |
| 4598 | ); |
| 4599 | |
| 4600 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c9 |
| 4601 | (.din(ld64_fb_hit_c8), .l1clk(l1clk), |
| 4602 | .scan_in(ff_ld64_fb_hit_c9_scanin), |
| 4603 | .scan_out(ff_ld64_fb_hit_c9_scanout), |
| 4604 | .dout(ld64_fb_hit_c9), |
| 4605 | .siclk(siclk), |
| 4606 | .soclk(soclk) |
| 4607 | ); |
| 4608 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c10 |
| 4609 | (.din(ld64_fb_hit_c9), .l1clk(l1clk), |
| 4610 | .scan_in(ff_ld64_fb_hit_c10_scanin), |
| 4611 | .scan_out(ff_ld64_fb_hit_c10_scanout), |
| 4612 | .dout(ld64_fb_hit_c10), |
| 4613 | .siclk(siclk), |
| 4614 | .soclk(soclk) |
| 4615 | ); |
| 4616 | |
| 4617 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_ld64_fb_hit_c11 |
| 4618 | (.din(ld64_fb_hit_c10), .l1clk(l1clk), |
| 4619 | .scan_in(ff_ld64_fb_hit_c11_scanin), |
| 4620 | .scan_out(ff_ld64_fb_hit_c11_scanout), |
| 4621 | .dout(ld64_fb_hit_c11), |
| 4622 | .siclk(siclk), |
| 4623 | .soclk(soclk) |
| 4624 | ); |
| 4625 | |
| 4626 | l2t_filbuf_ctl_msff_ctl_macro__en_1__width_1 ff_ld64_fb_hit_c12 |
| 4627 | (.din(ld64_fb_hit_c11), .l1clk(l1clk), |
| 4628 | .scan_in(ff_ld64_fb_hit_c12_scanin), |
| 4629 | .scan_out(ff_ld64_fb_hit_c12_scanout), |
| 4630 | .en(tag_rd64_complete_c11), |
| 4631 | .dout(ld64_fb_hit_c12), |
| 4632 | .siclk(siclk), |
| 4633 | .soclk(soclk) |
| 4634 | ); |
| 4635 | |
| 4636 | assign filbuf_ld64_fb_hit_c12 = ld64_fb_hit_c12; |
| 4637 | |
| 4638 | |
| 4639 | |
| 4640 | |
| 4641 | |
| 4642 | ////////////////////////////////////////////////////////////////////////////////// |
| 4643 | // Asynchronous errors : |
| 4644 | // Errors due to the following cases are reported as disrupting erross |
| 4645 | // * eviction C and U |
| 4646 | // * l2 scrub. C and U |
| 4647 | // * mcu scrub C and U |
| 4648 | // * tag error. C only |
| 4649 | // * vuad error. C only |
| 4650 | // |
| 4651 | ////////////////////////////////////////////////////////////////////////////////// |
| 4652 | |
| 4653 | |
| 4654 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_mcu_scb_mecc_err_d1 |
| 4655 | (.din(mcu_l2t_scb_mecc_err), .l1clk(l1clk), |
| 4656 | .scan_in(ff_mcu_scb_mecc_err_d1_scanin), |
| 4657 | .scan_out(ff_mcu_scb_mecc_err_d1_scanout), |
| 4658 | .dout(filbuf_mcu_scb_mecc_err_d1), |
| 4659 | .siclk(siclk), |
| 4660 | .soclk(soclk) |
| 4661 | ); |
| 4662 | |
| 4663 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_mcu_scb_secc_err_d1 |
| 4664 | (.din(mcu_l2t_scb_secc_err), .l1clk(l1clk), |
| 4665 | .scan_in(ff_mcu_scb_secc_err_d1_scanin), |
| 4666 | .scan_out(ff_mcu_scb_secc_err_d1_scanout), |
| 4667 | .dout(filbuf_mcu_scb_secc_err_d1), |
| 4668 | .siclk(siclk), |
| 4669 | .soclk(soclk) |
| 4670 | ); |
| 4671 | |
| 4672 | |
| 4673 | |
| 4674 | ////////////// |
| 4675 | // UERR PEND |
| 4676 | // |
| 4677 | // POST_2.0 conditions: |
| 4678 | // |
| 4679 | // If an error is encountered while performing |
| 4680 | // the read part of a partial wr8. the error is |
| 4681 | // recorded in the miss buffer and then registered |
| 4682 | // as a pending error in filbuf . An ERROR indication |
| 4683 | // is sent to the "steering sparc" on a FILL. |
| 4684 | // |
| 4685 | ////////////////////////////////////////////////////////// |
| 4686 | |
| 4687 | |
| 4688 | assign uerr_ack_c4 = tag_uerr_ack_tmp_c4 & wr8_inst_c4 ; |
| 4689 | |
| 4690 | assign fb_uerr_pend_set = rdmat_ev_uerr_r6 | // eviction |
| 4691 | uerr_ack_c4 | |
| 4692 | filbuf_mcu_scb_mecc_err_d1 | // mcu scrub err |
| 4693 | deccck_scrd_uncorr_err_c8 | // l2 scrub err. |
| 4694 | rdmat_rdmard_uerr_c12 | // Ld64 error |
| 4695 | (rdmat_rdmard_notdata_c12 & filbuf_ld64_fb_hit_c12) | // Ld64 Notdata error |
| 4696 | (deccck_bscd_uncorr_err_c8 & misbuf_vuad_ce_err_c8); // WR8 uncorr error in ON mode only if VUAD CE detected. |
| 4697 | |
| 4698 | |
| 4699 | assign fb_uerr_pend_reset = (~fb_uerr_pend_set & fill_vld_c3 ); |
| 4700 | |
| 4701 | assign fb_uerr_pend_in = ( fb_uerr_pend_set | fb_uerr_pend ) |
| 4702 | & ~fb_uerr_pend_reset ; |
| 4703 | |
| 4704 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_fb_uerr_pend // sync reset active low |
| 4705 | (.din(fb_uerr_pend_in), .l1clk(l1clk),.clr(~dbb_rst_l), |
| 4706 | .scan_in(ff_fb_uerr_pend_scanin), |
| 4707 | .scan_out(ff_fb_uerr_pend_scanout), |
| 4708 | .dout(fb_uerr_pend), |
| 4709 | .siclk(siclk), |
| 4710 | .soclk(soclk) |
| 4711 | ); |
| 4712 | /////////////////////////////////////////////////////////////////////////////////////////////// |
| 4713 | // Not data pending ueerr bit |
| 4714 | /////////////////////////////////////////////////////////////////////////////////////////////// |
| 4715 | |
| 4716 | |
| 4717 | assign fb_nduerr_pend_set = (rdmat_rdmard_notdata_c12 & ~l2_bypass_mode_on_d1 & ~filbuf_ld64_fb_hit_c12) |
| 4718 | | // Ld64 Notdata error |
| 4719 | deccck_bscd_notdata_err_c8 ; // WR8 notdata error in ON mode only |
| 4720 | |
| 4721 | assign fb_nduerr_pend_reset = (~fb_nduerr_pend_set & fill_vld_c3 ); |
| 4722 | |
| 4723 | assign fb_nduerr_pend_in = ( fb_nduerr_pend_set | fb_nduerr_pend ) |
| 4724 | & ~fb_nduerr_pend_reset ; |
| 4725 | |
| 4726 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_fb_nduerr_pend // sync reset active low |
| 4727 | ( |
| 4728 | .scan_in(ff_fb_nduerr_pend_scanin), |
| 4729 | .scan_out(ff_fb_nduerr_pend_scanout), |
| 4730 | .din(fb_nduerr_pend_in), |
| 4731 | .l1clk(l1clk), |
| 4732 | .clr(~dbb_rst_l), |
| 4733 | .dout(fb_nduerr_pend), |
| 4734 | .siclk(siclk), |
| 4735 | .soclk(soclk) |
| 4736 | ); |
| 4737 | |
| 4738 | |
| 4739 | |
| 4740 | |
| 4741 | |
| 4742 | |
| 4743 | |
| 4744 | |
| 4745 | ////////////// |
| 4746 | // CERR PEND |
| 4747 | ////////////// |
| 4748 | assign cerr_ack_c4 = tag_cerr_ack_tmp_c4 & wr8_inst_c4 ; |
| 4749 | ///////////////////////////////////// |
| 4750 | // Bud id 93653 fix |
| 4751 | //assign fb_cerr_pend_set = rdmat_ev_cerr_r6 | // eviction |
| 4752 | // cerr_ack_c4 | |
| 4753 | // filbuf_mcu_scb_secc_err_d1 | // mcu scrub err |
| 4754 | // tagdp_tag_error_c8 | // Tag parity Error |
| 4755 | // misbuf_vuad_ce_err_c8 | // vuad SBE |
| 4756 | // deccck_scrd_corr_err_c8 | // l2 scrub err. |
| 4757 | // rdmat_rdmard_cerr_c12 | // Ld 64 error. for LDRC |
| 4758 | // rdmat_rdmard_notdata_c12 | // Ld64 Notdata error |
| 4759 | // filbuf_bsc_corr_err_c12 | // ld 64 error for DRC |
| 4760 | // deccck_bscd_notdata_err_c8 | // WR8 notdata error in ON mode only |
| 4761 | // deccck_bscd_corr_err_c8 ; // Wr8 corr error in L2 ON mode only |
| 4762 | // If the rdma load 64 hits filbuf means that this was a miss and hence should |
| 4763 | // not report notdata but should report UE. |
| 4764 | |
| 4765 | assign fb_cerr_pend_set = rdmat_ev_cerr_r6 | // eviction |
| 4766 | cerr_ack_c4 | |
| 4767 | filbuf_mcu_scb_secc_err_d1 | // mcu scrub err |
| 4768 | tagdp_tag_error_c8 | // Tag parity Error |
| 4769 | misbuf_vuad_ce_err_c8 | // vuad SBE |
| 4770 | deccck_scrd_corr_err_c8 | // l2 scrub err. |
| 4771 | rdmat_rdmard_cerr_c12 | // Ld 64 error. for LDRC |
| 4772 | filbuf_bsc_corr_err_c12 | // ld 64 error for DRC |
| 4773 | deccck_bscd_corr_err_c8 ; // Wr8 corr error in L2 ON mode only |
| 4774 | |
| 4775 | assign fb_cerr_pend_reset = (~fb_cerr_pend_set & fill_vld_c3 ); |
| 4776 | assign fb_cerr_pend_in = ( fb_cerr_pend_set | fb_cerr_pend ) & ~fb_cerr_pend_reset ; |
| 4777 | |
| 4778 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_fb_cerr_pend // sync reset active low |
| 4779 | ( |
| 4780 | .scan_in(ff_fb_cerr_pend_scanin), |
| 4781 | .scan_out(ff_fb_cerr_pend_scanout), |
| 4782 | .din(fb_cerr_pend_in), |
| 4783 | .l1clk(l1clk), |
| 4784 | .clr(~dbb_rst_l), |
| 4785 | .dout(fb_cerr_pend), |
| 4786 | .siclk(siclk), |
| 4787 | .soclk(soclk) |
| 4788 | ); |
| 4789 | /////////////////////////////////////////////////////////////////////////////////////////////// |
| 4790 | // Not data cerr err bit reported |
| 4791 | /////////////////////////////////////////////////////////////////////////////////////////////// |
| 4792 | assign fb_ndcerr_pend_set = deccck_bscd_notdata_err_c8 | // WR8 notdata error in ON mode only |
| 4793 | (rdmat_rdmard_notdata_c12 & ~l2_bypass_mode_on_d1 & ~filbuf_ld64_fb_hit_c12); // Ld64 Notdata error |
| 4794 | |
| 4795 | assign fb_ndcerr_pend_reset = ~fb_ndcerr_pend_set & fill_vld_c3; |
| 4796 | |
| 4797 | assign fb_ndcerr_pend_in = (fb_ndcerr_pend_set | fb_ndcerr_pend) & ~fb_ndcerr_pend_reset; |
| 4798 | |
| 4799 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_fb_ndcerr_pend // sync reset active low |
| 4800 | ( |
| 4801 | .scan_in(ff_fb_ndcerr_pend_scanin), |
| 4802 | .scan_out(ff_fb_ndcerr_pend_scanout), |
| 4803 | .din( fb_ndcerr_pend_in), |
| 4804 | .l1clk(l1clk), |
| 4805 | .clr(~dbb_rst_l), |
| 4806 | .dout( fb_ndcerr_pend), |
| 4807 | .siclk(siclk), |
| 4808 | .soclk(soclk) |
| 4809 | ); |
| 4810 | |
| 4811 | /////////////////////////////////////////////////////////////////////////////////////////////// |
| 4812 | |
| 4813 | /////////////// |
| 4814 | // |
| 4815 | // A Disrupting error is sent to the Thread and |
| 4816 | // Core pointed to by the steering control fields in the |
| 4817 | // L2 control register. |
| 4818 | // |
| 4819 | // A disrupting error is sent under the following conditions. |
| 4820 | // - A fill when the fb_?err bit is still set. |
| 4821 | // - A Fill occurring after any of the following errors happen |
| 4822 | // 1. eviction |
| 4823 | // 2. scrub err from mcu. |
| 4824 | // 3. l2 scrub error. |
| 4825 | // 4. rdma rd error. |
| 4826 | // 5. err while performing the rd part of a Wr8 inst. |
| 4827 | // 6. Tag ecc error. |
| 4828 | // 7. VUAD SBE |
| 4829 | // |
| 4830 | /////////////// |
| 4831 | |
| 4832 | assign filbuf_dis_cerr_c3 = filbuf_corr_err_c3 | // bypass operation |
| 4833 | ( fill_vld_c3 & fb_cerr_pend ) ; // Fill operation |
| 4834 | |
| 4835 | assign filbuf_dis_uerr_c3 = filbuf_uncorr_err_c3 | |
| 4836 | ( fill_vld_c3 & fb_uerr_pend ) ; |
| 4837 | |
| 4838 | assign filbuf_dis_nderr_c3[1] = (fill_vld_c3 & fb_nduerr_pend); |
| 4839 | assign filbuf_dis_nderr_c3[0] = (fill_vld_c3 & fb_ndcerr_pend); |
| 4840 | |
| 4841 | |
| 4842 | ////////////////////////////////////////////////////////////// |
| 4843 | // SCRUB / TECC: |
| 4844 | // The tecc bit |
| 4845 | // in filbuf is used to get a scrub started. |
| 4846 | // Reset in the C1 cycle of a FILL. |
| 4847 | /////////////////////////////////////////////////////////////// |
| 4848 | |
| 4849 | |
| 4850 | assign fb_tecc_pend_set = csr_filbuf_scrub_ready ; |
| 4851 | |
| 4852 | assign fb_tecc_pend_reset = ( ~csr_filbuf_scrub_ready & fb_tecc_pend_d1 & arb_filbuf_fbsel_c1 ); |
| 4853 | |
| 4854 | assign fb_tecc_pend_in = ( fb_tecc_pend_set | fb_tecc_pend ) & ~fb_tecc_pend_reset ; |
| 4855 | |
| 4856 | l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ff_fb_tecc_pend // sync reset active low |
| 4857 | (.din(fb_tecc_pend_in), .l1clk(l1clk),.clr(~dbb_rst_l), |
| 4858 | .scan_in(ff_fb_tecc_pend_scanin), |
| 4859 | .scan_out(ff_fb_tecc_pend_scanout), |
| 4860 | .dout(fb_tecc_pend), |
| 4861 | .siclk(siclk), |
| 4862 | .soclk(soclk) |
| 4863 | ); |
| 4864 | |
| 4865 | l2t_filbuf_ctl_msff_ctl_macro__width_1 ff_fb_tecc_pend_d1 |
| 4866 | (.din(fb_tecc_pend), .l1clk(l1clk), |
| 4867 | .scan_in(ff_fb_tecc_pend_d1_scanin), |
| 4868 | .scan_out(ff_fb_tecc_pend_d1_scanout), |
| 4869 | .dout(fb_tecc_pend_d1), |
| 4870 | .siclk(siclk), |
| 4871 | .soclk(soclk) |
| 4872 | ); |
| 4873 | |
| 4874 | |
| 4875 | assign filbuf_arbdp_tecc_px2 = fb_tecc_pend ; |
| 4876 | |
| 4877 | // BS and SR 12/18/03, LRU way from Filbuf needs to be written to Dir on a Load Miss |
| 4878 | // during the replay phase of the load . |
| 4879 | // We pick the way based on fb_hit_vec_c3 |
| 4880 | // |
| 4881 | //mux_ctl_macro mux_filbuf_tag_evict_way_c3 (width=4,ports=8,mux=pgnpe) |
| 4882 | // ( |
| 4883 | // .dout (filbuf_tag_evict_way_c3[3:0]), |
| 4884 | // .din0(way0[3:0]),.din1(way1[3:0]), |
| 4885 | // .din2(way2[3:0]),.din3(way3[3:0]), |
| 4886 | // .din4(way4[3:0]),.din5(way5[3:0]), |
| 4887 | // .din6(way6[3:0]),.din7(way7[3:0]), |
| 4888 | // .sel0(fb_hit_vec_c3[0]), |
| 4889 | // .sel1(fb_hit_vec_c3[1]), |
| 4890 | // .sel2(fb_hit_vec_c3[2]), |
| 4891 | // .sel3(fb_hit_vec_c3[3]), |
| 4892 | // .sel4(fb_hit_vec_c3[4]), |
| 4893 | // .sel5(fb_hit_vec_c3[5]), |
| 4894 | // .sel6(fb_hit_vec_c3[6]), |
| 4895 | // .sel7(fb_hit_vec_c3[7]) |
| 4896 | // ); |
| 4897 | // |
| 4898 | |
| 4899 | |
| 4900 | always@(way0 or way1 or way2 or way3 or way4 or way5 or way6 or way7 or fb_hit_vec_c3) |
| 4901 | begin |
| 4902 | case(fb_hit_vec_c3) // synopsys parallel_case full_case |
| 4903 | 8'b00000001 : filbuf_tag_evict_way_c3[3:0] = way0[3:0]; |
| 4904 | 8'b00000010 : filbuf_tag_evict_way_c3[3:0] = way1[3:0]; |
| 4905 | 8'b00000100 : filbuf_tag_evict_way_c3[3:0] = way2[3:0]; |
| 4906 | 8'b00001000 : filbuf_tag_evict_way_c3[3:0] = way3[3:0]; |
| 4907 | 8'b00010000 : filbuf_tag_evict_way_c3[3:0] = way4[3:0]; |
| 4908 | 8'b00100000 : filbuf_tag_evict_way_c3[3:0] = way5[3:0]; |
| 4909 | 8'b01000000 : filbuf_tag_evict_way_c3[3:0] = way6[3:0]; |
| 4910 | 8'b10000000 : filbuf_tag_evict_way_c3[3:0] = way7[3:0]; |
| 4911 | default : filbuf_tag_evict_way_c3[3:0] = 4'b0; |
| 4912 | endcase |
| 4913 | end |
| 4914 | |
| 4915 | |
| 4916 | |
| 4917 | // fixscan start: |
| 4918 | assign spares_scanin = scan_in ; |
| 4919 | assign reset_flop_scanin = spares_scanout ; |
| 4920 | assign ff_mcu_pick_d1_scanin = reset_flop_scanout ; |
| 4921 | assign ff_l2t_mb2_run_r1_scanin = ff_mcu_pick_d1_scanout ; |
| 4922 | assign ff_filbuf_misbuf_fbid_d2_scanin = ff_l2t_mb2_run_r1_scanout; |
| 4923 | assign ff_fill_vld_c3_scanin = ff_filbuf_misbuf_fbid_d2_scanout; |
| 4924 | assign ff_l2_bypass_mode_on_scanin = ff_fill_vld_c3_scanout ; |
| 4925 | assign ff_l2_dir_map_on_d1_scanin = ff_l2_bypass_mode_on_scanout; |
| 4926 | assign ff_rdma_inst_c2_scanin = ff_l2_dir_map_on_d1_scanout; |
| 4927 | assign ff_arb_filbuf_inst_vld_c2_scanin = ff_rdma_inst_c2_scanout ; |
| 4928 | assign ff_fb_set_valid_d2_scanin = ff_arb_filbuf_inst_vld_c2_scanout; |
| 4929 | assign ff_valid_bit_scanin = ff_fb_set_valid_d2_scanout; |
| 4930 | assign ff_fb_count_scanin = ff_valid_bit_scanout ; |
| 4931 | assign ff_rqtyp_d2_scanin = ff_fb_count_scanout ; |
| 4932 | assign ff_snp_d2_scanin = ff_rqtyp_d2_scanout ; |
| 4933 | assign ff_stinst_0_scanin = ff_snp_d2_scanout ; |
| 4934 | assign ff_stinst_1_scanin = ff_stinst_0_scanout ; |
| 4935 | assign ff_stinst_2_scanin = ff_stinst_1_scanout ; |
| 4936 | assign ff_stinst_3_scanin = ff_stinst_2_scanout ; |
| 4937 | assign ff_stinst_4_scanin = ff_stinst_3_scanout ; |
| 4938 | assign ff_stinst_5_scanin = ff_stinst_4_scanout ; |
| 4939 | assign ff_stinst_6_scanin = ff_stinst_5_scanout ; |
| 4940 | assign ff_stinst_7_scanin = ff_stinst_6_scanout ; |
| 4941 | assign ff_nofill_0_scanin = ff_stinst_7_scanout ; |
| 4942 | assign ff_nofill_1_scanin = ff_nofill_0_scanout ; |
| 4943 | assign ff_nofill_2_scanin = ff_nofill_1_scanout ; |
| 4944 | assign ff_nofill_3_scanin = ff_nofill_2_scanout ; |
| 4945 | assign ff_nofill_4_scanin = ff_nofill_3_scanout ; |
| 4946 | assign ff_nofill_5_scanin = ff_nofill_4_scanout ; |
| 4947 | assign ff_nofill_6_scanin = ff_nofill_5_scanout ; |
| 4948 | assign ff_nofill_7_scanin = ff_nofill_6_scanout ; |
| 4949 | assign ff_fb_hit_off_c1_d1_scanin = ff_nofill_7_scanout ; |
| 4950 | assign ff_fb_cam_hit_vec_scanin = ff_fb_hit_off_c1_d1_scanout; |
| 4951 | assign ff_imiss_ld64_fb_hit_c3_scanin = ff_fb_cam_hit_vec_scanout; |
| 4952 | assign ff_l2d_fb_hit_c3_scanin = ff_imiss_ld64_fb_hit_c3_scanout; |
| 4953 | assign ff_qual_hit_vec_c3_scanin = ff_l2d_fb_hit_c3_scanout ; |
| 4954 | assign ff_qual_hit_vec_c4_scanin = ff_qual_hit_vec_c3_scanout; |
| 4955 | assign ff_bypassed_scanin = ff_qual_hit_vec_c4_scanout; |
| 4956 | assign ff_fill_entry_num_c2_scanin = ff_bypassed_scanout ; |
| 4957 | assign ff_fill_entry_num_c3_scanin = ff_fill_entry_num_c2_scanout; |
| 4958 | assign ff_inst_vld_c3_scanin = ff_fill_entry_num_c3_scanout; |
| 4959 | assign ff_misbuf_filbuf_fbid_d1_scanin = ff_inst_vld_c3_scanout ; |
| 4960 | assign ff_misbuf_filbuf_way_d1_scanin = ff_misbuf_filbuf_fbid_d1_scanout; |
| 4961 | assign ff_misbuf_filbuf_way_vld_d1_scanin = ff_misbuf_filbuf_way_d1_scanout; |
| 4962 | assign ff_way0_scanin = ff_misbuf_filbuf_way_vld_d1_scanout; |
| 4963 | assign ff_way1_scanin = ff_way0_scanout ; |
| 4964 | assign ff_way2_scanin = ff_way1_scanout ; |
| 4965 | assign ff_way3_scanin = ff_way2_scanout ; |
| 4966 | assign ff_way4_scanin = ff_way3_scanout ; |
| 4967 | assign ff_way5_scanin = ff_way4_scanout ; |
| 4968 | assign ff_way6_scanin = ff_way5_scanout ; |
| 4969 | assign ff_way7_scanin = ff_way6_scanout ; |
| 4970 | assign ff_way_vld_scanin = ff_way7_scanout ; |
| 4971 | assign ff_data_vld_r0_d1_scanin = ff_way_vld_scanout ; |
| 4972 | assign ff_data_vld_r1_scanin = ff_data_vld_r0_d1_scanout; |
| 4973 | assign ff_mcu_l2t_chunk_id_r0_d1_scanin = ff_data_vld_r1_scanout ; |
| 4974 | assign ff_mcu_l2t_chunk_id_r1_scanin = ff_mcu_l2t_chunk_id_r0_d1_scanout; |
| 4975 | assign ff_l2t_req_id_r0_d1_scanin = ff_mcu_l2t_chunk_id_r1_scanout; |
| 4976 | assign ff_l2t_req_id_r1_scanin = ff_l2t_req_id_r0_d1_scanout; |
| 4977 | assign ff_mcu_cnt_scanin = ff_l2t_req_id_r1_scanout ; |
| 4978 | assign ff_cas1_inst_c3_scanin = ff_mcu_cnt_scanout ; |
| 4979 | assign ff_cas1_inst_c4_scanin = ff_cas1_inst_c3_scanout ; |
| 4980 | assign ff_fb_hit_vec_c3_scanin = ff_cas1_inst_c4_scanout ; |
| 4981 | assign ff_fb_hit_vec_c4_scanin = ff_fb_hit_vec_c3_scanout ; |
| 4982 | assign ff_fb_l2_ready_scanin = ff_fb_hit_vec_c4_scanout ; |
| 4983 | assign ff_l2_pick_d1_scanin = ff_fb_l2_ready_scanout ; |
| 4984 | assign ff_l2_wait_scanin = ff_l2_pick_d1_scanout ; |
| 4985 | assign ff_l2_entry_px2_scanin = ff_l2_wait_scanout ; |
| 4986 | assign ff_l2_way_px2_scanin = ff_l2_entry_px2_scanout ; |
| 4987 | assign ff_mbf_entry_d2_scanin = ff_l2_way_px2_scanout ; |
| 4988 | assign ff_mbid0_scanin = ff_mbf_entry_d2_scanout ; |
| 4989 | assign ff_mbid1_scanin = ff_mbid0_scanout ; |
| 4990 | assign ff_mbid2_scanin = ff_mbid1_scanout ; |
| 4991 | assign ff_mbid3_scanin = ff_mbid2_scanout ; |
| 4992 | assign ff_mbid4_scanin = ff_mbid3_scanout ; |
| 4993 | assign ff_mbid5_scanin = ff_mbid4_scanout ; |
| 4994 | assign ff_mbid6_scanin = ff_mbid5_scanout ; |
| 4995 | assign ff_mbid7_scanin = ff_mbid6_scanout ; |
| 4996 | assign ff_fill_complete_c4_scanin = ff_mbid7_scanout ; |
| 4997 | assign ff_fb_next_link_vld_scanin = ff_fill_complete_c4_scanout; |
| 4998 | assign ff_enc_hit_vec_c3_scanin = ff_fb_next_link_vld_scanout; |
| 4999 | assign ff_fill_entry_c2_scanin = ff_enc_hit_vec_c3_scanout; |
| 5000 | assign ff_fill_entry_c3_scanin = ff_fill_entry_c2_scanout ; |
| 5001 | assign ff_l2_rd_state_scanin = ff_fill_entry_c3_scanout ; |
| 5002 | assign ff_l2_rd_state_quad0_scanin = ff_l2_rd_state_scanout ; |
| 5003 | assign ff_l2_rd_state_quad1_scanin = ff_l2_rd_state_quad0_scanout; |
| 5004 | assign ff_l2_rd_ptr_scanin = ff_l2_rd_state_quad1_scanout; |
| 5005 | assign ff_secc_err_r3_scanin = ff_l2_rd_ptr_scanout ; |
| 5006 | assign ff_mecc_err_r3_scanin = ff_secc_err_r3_scanout ; |
| 5007 | assign ff_data_vld_r2_scanin = ff_mecc_err_r3_scanout ; |
| 5008 | assign ff_data_vld_r3_scanin = ff_data_vld_r2_scanout ; |
| 5009 | assign ff_mcu_rd_req_id_r2_scanin = ff_data_vld_r3_scanout ; |
| 5010 | assign ff_mcu_rd_req_id_r3_scanin = ff_mcu_rd_req_id_r2_scanout; |
| 5011 | assign ff_wr8_inst_c3_scanin = ff_mcu_rd_req_id_r3_scanout; |
| 5012 | assign ff_wr8_inst_c4_scanin = ff_wr8_inst_c3_scanout ; |
| 5013 | assign ff_fb_cerr_scanin = ff_wr8_inst_c4_scanout ; |
| 5014 | assign ff_fb_uerr_scanin = ff_fb_cerr_scanout ; |
| 5015 | assign ff_filbuf_misbuf_ue_offmode_scanin = ff_fb_uerr_scanout ; |
| 5016 | assign ff_filbuf_misbuf_ce_offmode_scanin = ff_filbuf_misbuf_ue_offmode_scanout; |
| 5017 | assign ff_filbuf_corr_err_c4_scanin = ff_filbuf_misbuf_ce_offmode_scanout; |
| 5018 | assign ff_filbuf_corr_err_c5_scanin = ff_filbuf_corr_err_c4_scanout; |
| 5019 | assign ff_filbuf_corr_err_c52_scanin = ff_filbuf_corr_err_c5_scanout; |
| 5020 | assign ff_filbuf_corr_err_c6_scanin = ff_filbuf_corr_err_c52_scanout; |
| 5021 | assign ff_filbuf_corr_err_c7_scanin = ff_filbuf_corr_err_c6_scanout; |
| 5022 | assign ff_filbuf_corr_err_c8_scanin = ff_filbuf_corr_err_c7_scanout; |
| 5023 | assign ff_filbuf_uncorr_err_c4_scanin = ff_filbuf_corr_err_c8_scanout; |
| 5024 | assign ff_filbuf_uncorr_err_c5_scanin = ff_filbuf_uncorr_err_c4_scanout; |
| 5025 | assign ff_filbuf_uncorr_err_c52_scanin = ff_filbuf_uncorr_err_c5_scanout; |
| 5026 | assign ff_filbuf_uncorr_err_c6_scanin = ff_filbuf_uncorr_err_c52_scanout; |
| 5027 | assign ff_filbuf_uncorr_err_c7_scanin = ff_filbuf_uncorr_err_c6_scanout; |
| 5028 | assign ff_filbuf_uncorr_err_c8_scanin = ff_filbuf_uncorr_err_c7_scanout; |
| 5029 | assign ff_filbuf_hit_c3_scanin = ff_filbuf_uncorr_err_c8_scanout; |
| 5030 | assign ff_filbuf_hit_c4_scanin = ff_filbuf_hit_c3_scanout ; |
| 5031 | assign ff_imiss_inst_c3_scanin = ff_filbuf_hit_c4_scanout ; |
| 5032 | assign ff_imiss_inst_c4_scanin = ff_imiss_inst_c3_scanout ; |
| 5033 | assign ff_ld64_inst_c3_scanin = ff_imiss_inst_c4_scanout ; |
| 5034 | assign ff_spc_rd_vld_c4_scanin = ff_ld64_inst_c3_scanout ; |
| 5035 | assign ff_spc_rd_vld_c5_scanin = ff_spc_rd_vld_c4_scanout ; |
| 5036 | assign ff_spc_rd_vld_c52_scanin = ff_spc_rd_vld_c5_scanout ; |
| 5037 | assign ff_spc_rd_vld_c6_scanin = ff_spc_rd_vld_c52_scanout; |
| 5038 | assign ff_fbcerr0_d1_scanin = ff_spc_rd_vld_c6_scanout ; |
| 5039 | assign ff_fbuerr0_d1_scanin = ff_fbcerr0_d1_scanout ; |
| 5040 | assign ff_spc_corr_err_c4_scanin = ff_fbuerr0_d1_scanout ; |
| 5041 | assign ff_spc_corr_err_c5_scanin = ff_spc_corr_err_c4_scanout; |
| 5042 | assign ff_spc_corr_err_c52_scanin = ff_spc_corr_err_c5_scanout; |
| 5043 | assign ff_spc_corr_err_c6_scanin = ff_spc_corr_err_c52_scanout; |
| 5044 | assign ff_spc_uncorr_err_c4_scanin = ff_spc_corr_err_c6_scanout; |
| 5045 | assign ff_spc_uncorr_err_c5_scanin = ff_spc_uncorr_err_c4_scanout; |
| 5046 | assign ff_spc_uncorr_err_c52_scanin = ff_spc_uncorr_err_c5_scanout; |
| 5047 | assign ff_spc_uncorr_err_c6_scanin = ff_spc_uncorr_err_c52_scanout; |
| 5048 | assign ff_bsc_corr_err_c4_scanin = ff_spc_uncorr_err_c6_scanout; |
| 5049 | assign ff_bsc_corr_err_c5_scanin = ff_bsc_corr_err_c4_scanout; |
| 5050 | assign ff_bsc_corr_err_c52_scanin = ff_bsc_corr_err_c5_scanout; |
| 5051 | assign ff_bsc_corr_err_c6_scanin = ff_bsc_corr_err_c52_scanout; |
| 5052 | assign ff_bsc_corr_err_c7_scanin = ff_bsc_corr_err_c6_scanout; |
| 5053 | assign ff_bsc_corr_err_c8_scanin = ff_bsc_corr_err_c7_scanout; |
| 5054 | assign ff_bsc_corr_err_c9_scanin = ff_bsc_corr_err_c8_scanout; |
| 5055 | assign ff_bsc_corr_err_c10_scanin = ff_bsc_corr_err_c9_scanout; |
| 5056 | assign ff_bsc_corr_err_c11_scanin = ff_bsc_corr_err_c10_scanout; |
| 5057 | assign ff_bsc_corr_err_c12_scanin = ff_bsc_corr_err_c11_scanout; |
| 5058 | assign ff_ld64_fb_hit_c4_scanin = ff_bsc_corr_err_c12_scanout; |
| 5059 | assign ff_ld64_fb_hit_c5_scanin = ff_ld64_fb_hit_c4_scanout; |
| 5060 | assign ff_ld64_fb_hit_c52_scanin = ff_ld64_fb_hit_c5_scanout; |
| 5061 | assign ff_ld64_fb_hit_c6_scanin = ff_ld64_fb_hit_c52_scanout; |
| 5062 | assign ff_ld64_fb_hit_c7_scanin = ff_ld64_fb_hit_c6_scanout; |
| 5063 | assign ff_ld64_fb_hit_c8_scanin = ff_ld64_fb_hit_c7_scanout; |
| 5064 | assign ff_ld64_fb_hit_c9_scanin = ff_ld64_fb_hit_c8_scanout; |
| 5065 | assign ff_ld64_fb_hit_c10_scanin = ff_ld64_fb_hit_c9_scanout; |
| 5066 | assign ff_ld64_fb_hit_c11_scanin = ff_ld64_fb_hit_c10_scanout; |
| 5067 | assign ff_ld64_fb_hit_c12_scanin = ff_ld64_fb_hit_c11_scanout; |
| 5068 | assign ff_mcu_scb_mecc_err_d1_scanin = ff_ld64_fb_hit_c12_scanout; |
| 5069 | assign ff_mcu_scb_secc_err_d1_scanin = ff_mcu_scb_mecc_err_d1_scanout; |
| 5070 | assign ff_fb_uerr_pend_scanin = ff_mcu_scb_secc_err_d1_scanout; |
| 5071 | assign ff_fb_nduerr_pend_scanin = ff_fb_uerr_pend_scanout ; |
| 5072 | assign ff_fb_cerr_pend_scanin = ff_fb_nduerr_pend_scanout; |
| 5073 | assign ff_fb_ndcerr_pend_scanin = ff_fb_cerr_pend_scanout ; |
| 5074 | assign ff_fb_tecc_pend_scanin = ff_fb_ndcerr_pend_scanout; |
| 5075 | assign ff_fb_tecc_pend_d1_scanin = ff_fb_tecc_pend_scanout ; |
| 5076 | assign scan_out = ff_fb_tecc_pend_d1_scanout; |
| 5077 | // fixscan end: |
| 5078 | endmodule |
| 5079 | |
| 5080 | |
| 5081 | |
| 5082 | |
| 5083 | |
| 5084 | |
| 5085 | |
| 5086 | // any PARAMS parms go into naming of macro |
| 5087 | |
| 5088 | module l2t_filbuf_ctl_l1clkhdr_ctl_macro ( |
| 5089 | l2clk, |
| 5090 | l1en, |
| 5091 | pce_ov, |
| 5092 | stop, |
| 5093 | se, |
| 5094 | l1clk); |
| 5095 | |
| 5096 | |
| 5097 | input l2clk; |
| 5098 | input l1en; |
| 5099 | input pce_ov; |
| 5100 | input stop; |
| 5101 | input se; |
| 5102 | output l1clk; |
| 5103 | |
| 5104 | |
| 5105 | |
| 5106 | |
| 5107 | |
| 5108 | cl_sc1_l1hdr_8x c_0 ( |
| 5109 | |
| 5110 | |
| 5111 | .l2clk(l2clk), |
| 5112 | .pce(l1en), |
| 5113 | .l1clk(l1clk), |
| 5114 | .se(se), |
| 5115 | .pce_ov(pce_ov), |
| 5116 | .stop(stop) |
| 5117 | ); |
| 5118 | |
| 5119 | |
| 5120 | |
| 5121 | endmodule |
| 5122 | |
| 5123 | |
| 5124 | |
| 5125 | |
| 5126 | |
| 5127 | |
| 5128 | |
| 5129 | |
| 5130 | |
| 5131 | // Description: Spare gate macro for control blocks |
| 5132 | // |
| 5133 | // Param num controls the number of times the macro is added |
| 5134 | // flops=0 can be used to use only combination spare logic |
| 5135 | |
| 5136 | |
| 5137 | module l2t_filbuf_ctl_spare_ctl_macro__num_6 ( |
| 5138 | l1clk, |
| 5139 | scan_in, |
| 5140 | siclk, |
| 5141 | soclk, |
| 5142 | scan_out); |
| 5143 | wire si_0; |
| 5144 | wire so_0; |
| 5145 | wire spare0_flop_unused; |
| 5146 | wire spare0_buf_32x_unused; |
| 5147 | wire spare0_nand3_8x_unused; |
| 5148 | wire spare0_inv_8x_unused; |
| 5149 | wire spare0_aoi22_4x_unused; |
| 5150 | wire spare0_buf_8x_unused; |
| 5151 | wire spare0_oai22_4x_unused; |
| 5152 | wire spare0_inv_16x_unused; |
| 5153 | wire spare0_nand2_16x_unused; |
| 5154 | wire spare0_nor3_4x_unused; |
| 5155 | wire spare0_nand2_8x_unused; |
| 5156 | wire spare0_buf_16x_unused; |
| 5157 | wire spare0_nor2_16x_unused; |
| 5158 | wire spare0_inv_32x_unused; |
| 5159 | wire si_1; |
| 5160 | wire so_1; |
| 5161 | wire spare1_flop_unused; |
| 5162 | wire spare1_buf_32x_unused; |
| 5163 | wire spare1_nand3_8x_unused; |
| 5164 | wire spare1_inv_8x_unused; |
| 5165 | wire spare1_aoi22_4x_unused; |
| 5166 | wire spare1_buf_8x_unused; |
| 5167 | wire spare1_oai22_4x_unused; |
| 5168 | wire spare1_inv_16x_unused; |
| 5169 | wire spare1_nand2_16x_unused; |
| 5170 | wire spare1_nor3_4x_unused; |
| 5171 | wire spare1_nand2_8x_unused; |
| 5172 | wire spare1_buf_16x_unused; |
| 5173 | wire spare1_nor2_16x_unused; |
| 5174 | wire spare1_inv_32x_unused; |
| 5175 | wire si_2; |
| 5176 | wire so_2; |
| 5177 | wire spare2_flop_unused; |
| 5178 | wire spare2_buf_32x_unused; |
| 5179 | wire spare2_nand3_8x_unused; |
| 5180 | wire spare2_inv_8x_unused; |
| 5181 | wire spare2_aoi22_4x_unused; |
| 5182 | wire spare2_buf_8x_unused; |
| 5183 | wire spare2_oai22_4x_unused; |
| 5184 | wire spare2_inv_16x_unused; |
| 5185 | wire spare2_nand2_16x_unused; |
| 5186 | wire spare2_nor3_4x_unused; |
| 5187 | wire spare2_nand2_8x_unused; |
| 5188 | wire spare2_buf_16x_unused; |
| 5189 | wire spare2_nor2_16x_unused; |
| 5190 | wire spare2_inv_32x_unused; |
| 5191 | wire si_3; |
| 5192 | wire so_3; |
| 5193 | wire spare3_flop_unused; |
| 5194 | wire spare3_buf_32x_unused; |
| 5195 | wire spare3_nand3_8x_unused; |
| 5196 | wire spare3_inv_8x_unused; |
| 5197 | wire spare3_aoi22_4x_unused; |
| 5198 | wire spare3_buf_8x_unused; |
| 5199 | wire spare3_oai22_4x_unused; |
| 5200 | wire spare3_inv_16x_unused; |
| 5201 | wire spare3_nand2_16x_unused; |
| 5202 | wire spare3_nor3_4x_unused; |
| 5203 | wire spare3_nand2_8x_unused; |
| 5204 | wire spare3_buf_16x_unused; |
| 5205 | wire spare3_nor2_16x_unused; |
| 5206 | wire spare3_inv_32x_unused; |
| 5207 | wire si_4; |
| 5208 | wire so_4; |
| 5209 | wire spare4_flop_unused; |
| 5210 | wire spare4_buf_32x_unused; |
| 5211 | wire spare4_nand3_8x_unused; |
| 5212 | wire spare4_inv_8x_unused; |
| 5213 | wire spare4_aoi22_4x_unused; |
| 5214 | wire spare4_buf_8x_unused; |
| 5215 | wire spare4_oai22_4x_unused; |
| 5216 | wire spare4_inv_16x_unused; |
| 5217 | wire spare4_nand2_16x_unused; |
| 5218 | wire spare4_nor3_4x_unused; |
| 5219 | wire spare4_nand2_8x_unused; |
| 5220 | wire spare4_buf_16x_unused; |
| 5221 | wire spare4_nor2_16x_unused; |
| 5222 | wire spare4_inv_32x_unused; |
| 5223 | wire si_5; |
| 5224 | wire so_5; |
| 5225 | wire spare5_flop_unused; |
| 5226 | wire spare5_buf_32x_unused; |
| 5227 | wire spare5_nand3_8x_unused; |
| 5228 | wire spare5_inv_8x_unused; |
| 5229 | wire spare5_aoi22_4x_unused; |
| 5230 | wire spare5_buf_8x_unused; |
| 5231 | wire spare5_oai22_4x_unused; |
| 5232 | wire spare5_inv_16x_unused; |
| 5233 | wire spare5_nand2_16x_unused; |
| 5234 | wire spare5_nor3_4x_unused; |
| 5235 | wire spare5_nand2_8x_unused; |
| 5236 | wire spare5_buf_16x_unused; |
| 5237 | wire spare5_nor2_16x_unused; |
| 5238 | wire spare5_inv_32x_unused; |
| 5239 | |
| 5240 | |
| 5241 | input l1clk; |
| 5242 | input scan_in; |
| 5243 | input siclk; |
| 5244 | input soclk; |
| 5245 | output scan_out; |
| 5246 | |
| 5247 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 5248 | .siclk(siclk), |
| 5249 | .soclk(soclk), |
| 5250 | .si(si_0), |
| 5251 | .so(so_0), |
| 5252 | .d(1'b0), |
| 5253 | .q(spare0_flop_unused)); |
| 5254 | assign si_0 = scan_in; |
| 5255 | |
| 5256 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 5257 | .out(spare0_buf_32x_unused)); |
| 5258 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 5259 | .in1(1'b1), |
| 5260 | .in2(1'b1), |
| 5261 | .out(spare0_nand3_8x_unused)); |
| 5262 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 5263 | .out(spare0_inv_8x_unused)); |
| 5264 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 5265 | .in01(1'b1), |
| 5266 | .in10(1'b1), |
| 5267 | .in11(1'b1), |
| 5268 | .out(spare0_aoi22_4x_unused)); |
| 5269 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 5270 | .out(spare0_buf_8x_unused)); |
| 5271 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 5272 | .in01(1'b1), |
| 5273 | .in10(1'b1), |
| 5274 | .in11(1'b1), |
| 5275 | .out(spare0_oai22_4x_unused)); |
| 5276 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 5277 | .out(spare0_inv_16x_unused)); |
| 5278 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 5279 | .in1(1'b1), |
| 5280 | .out(spare0_nand2_16x_unused)); |
| 5281 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 5282 | .in1(1'b0), |
| 5283 | .in2(1'b0), |
| 5284 | .out(spare0_nor3_4x_unused)); |
| 5285 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 5286 | .in1(1'b1), |
| 5287 | .out(spare0_nand2_8x_unused)); |
| 5288 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 5289 | .out(spare0_buf_16x_unused)); |
| 5290 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 5291 | .in1(1'b0), |
| 5292 | .out(spare0_nor2_16x_unused)); |
| 5293 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 5294 | .out(spare0_inv_32x_unused)); |
| 5295 | |
| 5296 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 5297 | .siclk(siclk), |
| 5298 | .soclk(soclk), |
| 5299 | .si(si_1), |
| 5300 | .so(so_1), |
| 5301 | .d(1'b0), |
| 5302 | .q(spare1_flop_unused)); |
| 5303 | assign si_1 = so_0; |
| 5304 | |
| 5305 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 5306 | .out(spare1_buf_32x_unused)); |
| 5307 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 5308 | .in1(1'b1), |
| 5309 | .in2(1'b1), |
| 5310 | .out(spare1_nand3_8x_unused)); |
| 5311 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 5312 | .out(spare1_inv_8x_unused)); |
| 5313 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 5314 | .in01(1'b1), |
| 5315 | .in10(1'b1), |
| 5316 | .in11(1'b1), |
| 5317 | .out(spare1_aoi22_4x_unused)); |
| 5318 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 5319 | .out(spare1_buf_8x_unused)); |
| 5320 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 5321 | .in01(1'b1), |
| 5322 | .in10(1'b1), |
| 5323 | .in11(1'b1), |
| 5324 | .out(spare1_oai22_4x_unused)); |
| 5325 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 5326 | .out(spare1_inv_16x_unused)); |
| 5327 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 5328 | .in1(1'b1), |
| 5329 | .out(spare1_nand2_16x_unused)); |
| 5330 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 5331 | .in1(1'b0), |
| 5332 | .in2(1'b0), |
| 5333 | .out(spare1_nor3_4x_unused)); |
| 5334 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 5335 | .in1(1'b1), |
| 5336 | .out(spare1_nand2_8x_unused)); |
| 5337 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 5338 | .out(spare1_buf_16x_unused)); |
| 5339 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 5340 | .in1(1'b0), |
| 5341 | .out(spare1_nor2_16x_unused)); |
| 5342 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 5343 | .out(spare1_inv_32x_unused)); |
| 5344 | |
| 5345 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 5346 | .siclk(siclk), |
| 5347 | .soclk(soclk), |
| 5348 | .si(si_2), |
| 5349 | .so(so_2), |
| 5350 | .d(1'b0), |
| 5351 | .q(spare2_flop_unused)); |
| 5352 | assign si_2 = so_1; |
| 5353 | |
| 5354 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 5355 | .out(spare2_buf_32x_unused)); |
| 5356 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 5357 | .in1(1'b1), |
| 5358 | .in2(1'b1), |
| 5359 | .out(spare2_nand3_8x_unused)); |
| 5360 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 5361 | .out(spare2_inv_8x_unused)); |
| 5362 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 5363 | .in01(1'b1), |
| 5364 | .in10(1'b1), |
| 5365 | .in11(1'b1), |
| 5366 | .out(spare2_aoi22_4x_unused)); |
| 5367 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 5368 | .out(spare2_buf_8x_unused)); |
| 5369 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 5370 | .in01(1'b1), |
| 5371 | .in10(1'b1), |
| 5372 | .in11(1'b1), |
| 5373 | .out(spare2_oai22_4x_unused)); |
| 5374 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 5375 | .out(spare2_inv_16x_unused)); |
| 5376 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 5377 | .in1(1'b1), |
| 5378 | .out(spare2_nand2_16x_unused)); |
| 5379 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 5380 | .in1(1'b0), |
| 5381 | .in2(1'b0), |
| 5382 | .out(spare2_nor3_4x_unused)); |
| 5383 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 5384 | .in1(1'b1), |
| 5385 | .out(spare2_nand2_8x_unused)); |
| 5386 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 5387 | .out(spare2_buf_16x_unused)); |
| 5388 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 5389 | .in1(1'b0), |
| 5390 | .out(spare2_nor2_16x_unused)); |
| 5391 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 5392 | .out(spare2_inv_32x_unused)); |
| 5393 | |
| 5394 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 5395 | .siclk(siclk), |
| 5396 | .soclk(soclk), |
| 5397 | .si(si_3), |
| 5398 | .so(so_3), |
| 5399 | .d(1'b0), |
| 5400 | .q(spare3_flop_unused)); |
| 5401 | assign si_3 = so_2; |
| 5402 | |
| 5403 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 5404 | .out(spare3_buf_32x_unused)); |
| 5405 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 5406 | .in1(1'b1), |
| 5407 | .in2(1'b1), |
| 5408 | .out(spare3_nand3_8x_unused)); |
| 5409 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 5410 | .out(spare3_inv_8x_unused)); |
| 5411 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 5412 | .in01(1'b1), |
| 5413 | .in10(1'b1), |
| 5414 | .in11(1'b1), |
| 5415 | .out(spare3_aoi22_4x_unused)); |
| 5416 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 5417 | .out(spare3_buf_8x_unused)); |
| 5418 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 5419 | .in01(1'b1), |
| 5420 | .in10(1'b1), |
| 5421 | .in11(1'b1), |
| 5422 | .out(spare3_oai22_4x_unused)); |
| 5423 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 5424 | .out(spare3_inv_16x_unused)); |
| 5425 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 5426 | .in1(1'b1), |
| 5427 | .out(spare3_nand2_16x_unused)); |
| 5428 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 5429 | .in1(1'b0), |
| 5430 | .in2(1'b0), |
| 5431 | .out(spare3_nor3_4x_unused)); |
| 5432 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 5433 | .in1(1'b1), |
| 5434 | .out(spare3_nand2_8x_unused)); |
| 5435 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 5436 | .out(spare3_buf_16x_unused)); |
| 5437 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 5438 | .in1(1'b0), |
| 5439 | .out(spare3_nor2_16x_unused)); |
| 5440 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 5441 | .out(spare3_inv_32x_unused)); |
| 5442 | |
| 5443 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 5444 | .siclk(siclk), |
| 5445 | .soclk(soclk), |
| 5446 | .si(si_4), |
| 5447 | .so(so_4), |
| 5448 | .d(1'b0), |
| 5449 | .q(spare4_flop_unused)); |
| 5450 | assign si_4 = so_3; |
| 5451 | |
| 5452 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 5453 | .out(spare4_buf_32x_unused)); |
| 5454 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 5455 | .in1(1'b1), |
| 5456 | .in2(1'b1), |
| 5457 | .out(spare4_nand3_8x_unused)); |
| 5458 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 5459 | .out(spare4_inv_8x_unused)); |
| 5460 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 5461 | .in01(1'b1), |
| 5462 | .in10(1'b1), |
| 5463 | .in11(1'b1), |
| 5464 | .out(spare4_aoi22_4x_unused)); |
| 5465 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 5466 | .out(spare4_buf_8x_unused)); |
| 5467 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 5468 | .in01(1'b1), |
| 5469 | .in10(1'b1), |
| 5470 | .in11(1'b1), |
| 5471 | .out(spare4_oai22_4x_unused)); |
| 5472 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 5473 | .out(spare4_inv_16x_unused)); |
| 5474 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 5475 | .in1(1'b1), |
| 5476 | .out(spare4_nand2_16x_unused)); |
| 5477 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 5478 | .in1(1'b0), |
| 5479 | .in2(1'b0), |
| 5480 | .out(spare4_nor3_4x_unused)); |
| 5481 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 5482 | .in1(1'b1), |
| 5483 | .out(spare4_nand2_8x_unused)); |
| 5484 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 5485 | .out(spare4_buf_16x_unused)); |
| 5486 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 5487 | .in1(1'b0), |
| 5488 | .out(spare4_nor2_16x_unused)); |
| 5489 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 5490 | .out(spare4_inv_32x_unused)); |
| 5491 | |
| 5492 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), |
| 5493 | .siclk(siclk), |
| 5494 | .soclk(soclk), |
| 5495 | .si(si_5), |
| 5496 | .so(so_5), |
| 5497 | .d(1'b0), |
| 5498 | .q(spare5_flop_unused)); |
| 5499 | assign si_5 = so_4; |
| 5500 | |
| 5501 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), |
| 5502 | .out(spare5_buf_32x_unused)); |
| 5503 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), |
| 5504 | .in1(1'b1), |
| 5505 | .in2(1'b1), |
| 5506 | .out(spare5_nand3_8x_unused)); |
| 5507 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), |
| 5508 | .out(spare5_inv_8x_unused)); |
| 5509 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), |
| 5510 | .in01(1'b1), |
| 5511 | .in10(1'b1), |
| 5512 | .in11(1'b1), |
| 5513 | .out(spare5_aoi22_4x_unused)); |
| 5514 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), |
| 5515 | .out(spare5_buf_8x_unused)); |
| 5516 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), |
| 5517 | .in01(1'b1), |
| 5518 | .in10(1'b1), |
| 5519 | .in11(1'b1), |
| 5520 | .out(spare5_oai22_4x_unused)); |
| 5521 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), |
| 5522 | .out(spare5_inv_16x_unused)); |
| 5523 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), |
| 5524 | .in1(1'b1), |
| 5525 | .out(spare5_nand2_16x_unused)); |
| 5526 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), |
| 5527 | .in1(1'b0), |
| 5528 | .in2(1'b0), |
| 5529 | .out(spare5_nor3_4x_unused)); |
| 5530 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), |
| 5531 | .in1(1'b1), |
| 5532 | .out(spare5_nand2_8x_unused)); |
| 5533 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), |
| 5534 | .out(spare5_buf_16x_unused)); |
| 5535 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), |
| 5536 | .in1(1'b0), |
| 5537 | .out(spare5_nor2_16x_unused)); |
| 5538 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), |
| 5539 | .out(spare5_inv_32x_unused)); |
| 5540 | assign scan_out = so_5; |
| 5541 | |
| 5542 | |
| 5543 | |
| 5544 | endmodule |
| 5545 | |
| 5546 | |
| 5547 | |
| 5548 | |
| 5549 | |
| 5550 | |
| 5551 | // any PARAMS parms go into naming of macro |
| 5552 | |
| 5553 | module l2t_filbuf_ctl_msff_ctl_macro__width_1 ( |
| 5554 | din, |
| 5555 | l1clk, |
| 5556 | scan_in, |
| 5557 | siclk, |
| 5558 | soclk, |
| 5559 | dout, |
| 5560 | scan_out); |
| 5561 | wire [0:0] fdin; |
| 5562 | |
| 5563 | input [0:0] din; |
| 5564 | input l1clk; |
| 5565 | input scan_in; |
| 5566 | |
| 5567 | |
| 5568 | input siclk; |
| 5569 | input soclk; |
| 5570 | |
| 5571 | output [0:0] dout; |
| 5572 | output scan_out; |
| 5573 | assign fdin[0:0] = din[0:0]; |
| 5574 | |
| 5575 | |
| 5576 | |
| 5577 | |
| 5578 | |
| 5579 | |
| 5580 | dff #(1) d0_0 ( |
| 5581 | .l1clk(l1clk), |
| 5582 | .siclk(siclk), |
| 5583 | .soclk(soclk), |
| 5584 | .d(fdin[0:0]), |
| 5585 | .si(scan_in), |
| 5586 | .so(scan_out), |
| 5587 | .q(dout[0:0]) |
| 5588 | ); |
| 5589 | |
| 5590 | |
| 5591 | |
| 5592 | |
| 5593 | |
| 5594 | |
| 5595 | |
| 5596 | |
| 5597 | |
| 5598 | |
| 5599 | |
| 5600 | |
| 5601 | endmodule |
| 5602 | |
| 5603 | |
| 5604 | |
| 5605 | |
| 5606 | |
| 5607 | |
| 5608 | |
| 5609 | |
| 5610 | |
| 5611 | |
| 5612 | |
| 5613 | |
| 5614 | |
| 5615 | // any PARAMS parms go into naming of macro |
| 5616 | |
| 5617 | module l2t_filbuf_ctl_msff_ctl_macro__width_18 ( |
| 5618 | din, |
| 5619 | l1clk, |
| 5620 | scan_in, |
| 5621 | siclk, |
| 5622 | soclk, |
| 5623 | dout, |
| 5624 | scan_out); |
| 5625 | wire [17:0] fdin; |
| 5626 | wire [16:0] so; |
| 5627 | |
| 5628 | input [17:0] din; |
| 5629 | input l1clk; |
| 5630 | input scan_in; |
| 5631 | |
| 5632 | |
| 5633 | input siclk; |
| 5634 | input soclk; |
| 5635 | |
| 5636 | output [17:0] dout; |
| 5637 | output scan_out; |
| 5638 | assign fdin[17:0] = din[17:0]; |
| 5639 | |
| 5640 | |
| 5641 | |
| 5642 | |
| 5643 | |
| 5644 | |
| 5645 | dff #(18) d0_0 ( |
| 5646 | .l1clk(l1clk), |
| 5647 | .siclk(siclk), |
| 5648 | .soclk(soclk), |
| 5649 | .d(fdin[17:0]), |
| 5650 | .si({scan_in,so[16:0]}), |
| 5651 | .so({so[16:0],scan_out}), |
| 5652 | .q(dout[17:0]) |
| 5653 | ); |
| 5654 | |
| 5655 | |
| 5656 | |
| 5657 | |
| 5658 | |
| 5659 | |
| 5660 | |
| 5661 | |
| 5662 | |
| 5663 | |
| 5664 | |
| 5665 | |
| 5666 | endmodule |
| 5667 | |
| 5668 | |
| 5669 | |
| 5670 | |
| 5671 | |
| 5672 | |
| 5673 | |
| 5674 | |
| 5675 | |
| 5676 | |
| 5677 | |
| 5678 | |
| 5679 | |
| 5680 | // any PARAMS parms go into naming of macro |
| 5681 | |
| 5682 | module l2t_filbuf_ctl_msff_ctl_macro__width_3 ( |
| 5683 | din, |
| 5684 | l1clk, |
| 5685 | scan_in, |
| 5686 | siclk, |
| 5687 | soclk, |
| 5688 | dout, |
| 5689 | scan_out); |
| 5690 | wire [2:0] fdin; |
| 5691 | wire [1:0] so; |
| 5692 | |
| 5693 | input [2:0] din; |
| 5694 | input l1clk; |
| 5695 | input scan_in; |
| 5696 | |
| 5697 | |
| 5698 | input siclk; |
| 5699 | input soclk; |
| 5700 | |
| 5701 | output [2:0] dout; |
| 5702 | output scan_out; |
| 5703 | assign fdin[2:0] = din[2:0]; |
| 5704 | |
| 5705 | |
| 5706 | |
| 5707 | |
| 5708 | |
| 5709 | |
| 5710 | dff #(3) d0_0 ( |
| 5711 | .l1clk(l1clk), |
| 5712 | .siclk(siclk), |
| 5713 | .soclk(soclk), |
| 5714 | .d(fdin[2:0]), |
| 5715 | .si({scan_in,so[1:0]}), |
| 5716 | .so({so[1:0],scan_out}), |
| 5717 | .q(dout[2:0]) |
| 5718 | ); |
| 5719 | |
| 5720 | |
| 5721 | |
| 5722 | |
| 5723 | |
| 5724 | |
| 5725 | |
| 5726 | |
| 5727 | |
| 5728 | |
| 5729 | |
| 5730 | |
| 5731 | endmodule |
| 5732 | |
| 5733 | |
| 5734 | |
| 5735 | |
| 5736 | |
| 5737 | |
| 5738 | |
| 5739 | |
| 5740 | |
| 5741 | |
| 5742 | |
| 5743 | |
| 5744 | |
| 5745 | // any PARAMS parms go into naming of macro |
| 5746 | |
| 5747 | module l2t_filbuf_ctl_msff_ctl_macro__width_8 ( |
| 5748 | din, |
| 5749 | l1clk, |
| 5750 | scan_in, |
| 5751 | siclk, |
| 5752 | soclk, |
| 5753 | dout, |
| 5754 | scan_out); |
| 5755 | wire [7:0] fdin; |
| 5756 | wire [6:0] so; |
| 5757 | |
| 5758 | input [7:0] din; |
| 5759 | input l1clk; |
| 5760 | input scan_in; |
| 5761 | |
| 5762 | |
| 5763 | input siclk; |
| 5764 | input soclk; |
| 5765 | |
| 5766 | output [7:0] dout; |
| 5767 | output scan_out; |
| 5768 | assign fdin[7:0] = din[7:0]; |
| 5769 | |
| 5770 | |
| 5771 | |
| 5772 | |
| 5773 | |
| 5774 | |
| 5775 | dff #(8) d0_0 ( |
| 5776 | .l1clk(l1clk), |
| 5777 | .siclk(siclk), |
| 5778 | .soclk(soclk), |
| 5779 | .d(fdin[7:0]), |
| 5780 | .si({scan_in,so[6:0]}), |
| 5781 | .so({so[6:0],scan_out}), |
| 5782 | .q(dout[7:0]) |
| 5783 | ); |
| 5784 | |
| 5785 | |
| 5786 | |
| 5787 | |
| 5788 | |
| 5789 | |
| 5790 | |
| 5791 | |
| 5792 | |
| 5793 | |
| 5794 | |
| 5795 | |
| 5796 | endmodule |
| 5797 | |
| 5798 | |
| 5799 | |
| 5800 | |
| 5801 | |
| 5802 | |
| 5803 | |
| 5804 | |
| 5805 | |
| 5806 | |
| 5807 | |
| 5808 | |
| 5809 | |
| 5810 | // any PARAMS parms go into naming of macro |
| 5811 | |
| 5812 | module l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_8 ( |
| 5813 | din, |
| 5814 | clr, |
| 5815 | l1clk, |
| 5816 | scan_in, |
| 5817 | siclk, |
| 5818 | soclk, |
| 5819 | dout, |
| 5820 | scan_out); |
| 5821 | wire [7:0] fdin; |
| 5822 | wire [6:0] so; |
| 5823 | |
| 5824 | input [7:0] din; |
| 5825 | input clr; |
| 5826 | input l1clk; |
| 5827 | input scan_in; |
| 5828 | |
| 5829 | |
| 5830 | input siclk; |
| 5831 | input soclk; |
| 5832 | |
| 5833 | output [7:0] dout; |
| 5834 | output scan_out; |
| 5835 | assign fdin[7:0] = din[7:0] & ~{8{clr}}; |
| 5836 | |
| 5837 | |
| 5838 | |
| 5839 | |
| 5840 | |
| 5841 | |
| 5842 | dff #(8) d0_0 ( |
| 5843 | .l1clk(l1clk), |
| 5844 | .siclk(siclk), |
| 5845 | .soclk(soclk), |
| 5846 | .d(fdin[7:0]), |
| 5847 | .si({scan_in,so[6:0]}), |
| 5848 | .so({so[6:0],scan_out}), |
| 5849 | .q(dout[7:0]) |
| 5850 | ); |
| 5851 | |
| 5852 | |
| 5853 | |
| 5854 | |
| 5855 | |
| 5856 | |
| 5857 | |
| 5858 | |
| 5859 | |
| 5860 | |
| 5861 | |
| 5862 | |
| 5863 | endmodule |
| 5864 | |
| 5865 | |
| 5866 | |
| 5867 | |
| 5868 | |
| 5869 | |
| 5870 | |
| 5871 | |
| 5872 | |
| 5873 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 5874 | // also for pass-gate with decoder |
| 5875 | |
| 5876 | |
| 5877 | |
| 5878 | |
| 5879 | |
| 5880 | // any PARAMS parms go into naming of macro |
| 5881 | |
| 5882 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 ( |
| 5883 | din0, |
| 5884 | sel0, |
| 5885 | din1, |
| 5886 | sel1, |
| 5887 | dout); |
| 5888 | input [3:0] din0; |
| 5889 | input sel0; |
| 5890 | input [3:0] din1; |
| 5891 | input sel1; |
| 5892 | output [3:0] dout; |
| 5893 | |
| 5894 | |
| 5895 | |
| 5896 | |
| 5897 | |
| 5898 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 5899 | ( {4{sel1}} & din1[3:0]); |
| 5900 | |
| 5901 | |
| 5902 | |
| 5903 | |
| 5904 | |
| 5905 | endmodule |
| 5906 | |
| 5907 | |
| 5908 | |
| 5909 | |
| 5910 | |
| 5911 | |
| 5912 | // any PARAMS parms go into naming of macro |
| 5913 | |
| 5914 | module l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_4 ( |
| 5915 | din, |
| 5916 | en, |
| 5917 | clr, |
| 5918 | l1clk, |
| 5919 | scan_in, |
| 5920 | siclk, |
| 5921 | soclk, |
| 5922 | dout, |
| 5923 | scan_out); |
| 5924 | wire [3:0] fdin; |
| 5925 | wire [2:0] so; |
| 5926 | |
| 5927 | input [3:0] din; |
| 5928 | input en; |
| 5929 | input clr; |
| 5930 | input l1clk; |
| 5931 | input scan_in; |
| 5932 | |
| 5933 | |
| 5934 | input siclk; |
| 5935 | input soclk; |
| 5936 | |
| 5937 | output [3:0] dout; |
| 5938 | output scan_out; |
| 5939 | assign fdin[3:0] = (din[3:0] & {4{en}} & ~{4{clr}}) | (dout[3:0] & ~{4{en}} & ~{4{clr}}); |
| 5940 | |
| 5941 | |
| 5942 | |
| 5943 | |
| 5944 | |
| 5945 | |
| 5946 | dff #(4) d0_0 ( |
| 5947 | .l1clk(l1clk), |
| 5948 | .siclk(siclk), |
| 5949 | .soclk(soclk), |
| 5950 | .d(fdin[3:0]), |
| 5951 | .si({scan_in,so[2:0]}), |
| 5952 | .so({so[2:0],scan_out}), |
| 5953 | .q(dout[3:0]) |
| 5954 | ); |
| 5955 | |
| 5956 | |
| 5957 | |
| 5958 | |
| 5959 | |
| 5960 | |
| 5961 | |
| 5962 | |
| 5963 | |
| 5964 | |
| 5965 | |
| 5966 | |
| 5967 | endmodule |
| 5968 | |
| 5969 | |
| 5970 | |
| 5971 | |
| 5972 | |
| 5973 | |
| 5974 | |
| 5975 | |
| 5976 | |
| 5977 | |
| 5978 | |
| 5979 | |
| 5980 | |
| 5981 | // any PARAMS parms go into naming of macro |
| 5982 | |
| 5983 | module l2t_filbuf_ctl_msff_ctl_macro__width_5 ( |
| 5984 | din, |
| 5985 | l1clk, |
| 5986 | scan_in, |
| 5987 | siclk, |
| 5988 | soclk, |
| 5989 | dout, |
| 5990 | scan_out); |
| 5991 | wire [4:0] fdin; |
| 5992 | wire [3:0] so; |
| 5993 | |
| 5994 | input [4:0] din; |
| 5995 | input l1clk; |
| 5996 | input scan_in; |
| 5997 | |
| 5998 | |
| 5999 | input siclk; |
| 6000 | input soclk; |
| 6001 | |
| 6002 | output [4:0] dout; |
| 6003 | output scan_out; |
| 6004 | assign fdin[4:0] = din[4:0]; |
| 6005 | |
| 6006 | |
| 6007 | |
| 6008 | |
| 6009 | |
| 6010 | |
| 6011 | dff #(5) d0_0 ( |
| 6012 | .l1clk(l1clk), |
| 6013 | .siclk(siclk), |
| 6014 | .soclk(soclk), |
| 6015 | .d(fdin[4:0]), |
| 6016 | .si({scan_in,so[3:0]}), |
| 6017 | .so({so[3:0],scan_out}), |
| 6018 | .q(dout[4:0]) |
| 6019 | ); |
| 6020 | |
| 6021 | |
| 6022 | |
| 6023 | |
| 6024 | |
| 6025 | |
| 6026 | |
| 6027 | |
| 6028 | |
| 6029 | |
| 6030 | |
| 6031 | |
| 6032 | endmodule |
| 6033 | |
| 6034 | |
| 6035 | |
| 6036 | |
| 6037 | |
| 6038 | |
| 6039 | |
| 6040 | |
| 6041 | |
| 6042 | |
| 6043 | |
| 6044 | |
| 6045 | |
| 6046 | // any PARAMS parms go into naming of macro |
| 6047 | |
| 6048 | module l2t_filbuf_ctl_msff_ctl_macro__en_1__width_2 ( |
| 6049 | din, |
| 6050 | en, |
| 6051 | l1clk, |
| 6052 | scan_in, |
| 6053 | siclk, |
| 6054 | soclk, |
| 6055 | dout, |
| 6056 | scan_out); |
| 6057 | wire [1:0] fdin; |
| 6058 | wire [0:0] so; |
| 6059 | |
| 6060 | input [1:0] din; |
| 6061 | input en; |
| 6062 | input l1clk; |
| 6063 | input scan_in; |
| 6064 | |
| 6065 | |
| 6066 | input siclk; |
| 6067 | input soclk; |
| 6068 | |
| 6069 | output [1:0] dout; |
| 6070 | output scan_out; |
| 6071 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); |
| 6072 | |
| 6073 | |
| 6074 | |
| 6075 | |
| 6076 | |
| 6077 | |
| 6078 | dff #(2) d0_0 ( |
| 6079 | .l1clk(l1clk), |
| 6080 | .siclk(siclk), |
| 6081 | .soclk(soclk), |
| 6082 | .d(fdin[1:0]), |
| 6083 | .si({scan_in,so[0:0]}), |
| 6084 | .so({so[0:0],scan_out}), |
| 6085 | .q(dout[1:0]) |
| 6086 | ); |
| 6087 | |
| 6088 | |
| 6089 | |
| 6090 | |
| 6091 | |
| 6092 | |
| 6093 | |
| 6094 | |
| 6095 | |
| 6096 | |
| 6097 | |
| 6098 | |
| 6099 | endmodule |
| 6100 | |
| 6101 | |
| 6102 | |
| 6103 | |
| 6104 | |
| 6105 | |
| 6106 | |
| 6107 | |
| 6108 | |
| 6109 | |
| 6110 | |
| 6111 | |
| 6112 | |
| 6113 | // any PARAMS parms go into naming of macro |
| 6114 | |
| 6115 | module l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_1 ( |
| 6116 | din, |
| 6117 | en, |
| 6118 | clr, |
| 6119 | l1clk, |
| 6120 | scan_in, |
| 6121 | siclk, |
| 6122 | soclk, |
| 6123 | dout, |
| 6124 | scan_out); |
| 6125 | wire [0:0] fdin; |
| 6126 | |
| 6127 | input [0:0] din; |
| 6128 | input en; |
| 6129 | input clr; |
| 6130 | input l1clk; |
| 6131 | input scan_in; |
| 6132 | |
| 6133 | |
| 6134 | input siclk; |
| 6135 | input soclk; |
| 6136 | |
| 6137 | output [0:0] dout; |
| 6138 | output scan_out; |
| 6139 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}}); |
| 6140 | |
| 6141 | |
| 6142 | |
| 6143 | |
| 6144 | |
| 6145 | |
| 6146 | dff #(1) d0_0 ( |
| 6147 | .l1clk(l1clk), |
| 6148 | .siclk(siclk), |
| 6149 | .soclk(soclk), |
| 6150 | .d(fdin[0:0]), |
| 6151 | .si(scan_in), |
| 6152 | .so(scan_out), |
| 6153 | .q(dout[0:0]) |
| 6154 | ); |
| 6155 | |
| 6156 | |
| 6157 | |
| 6158 | |
| 6159 | |
| 6160 | |
| 6161 | |
| 6162 | |
| 6163 | |
| 6164 | |
| 6165 | |
| 6166 | |
| 6167 | endmodule |
| 6168 | |
| 6169 | |
| 6170 | |
| 6171 | |
| 6172 | |
| 6173 | |
| 6174 | |
| 6175 | |
| 6176 | |
| 6177 | |
| 6178 | |
| 6179 | |
| 6180 | |
| 6181 | // any PARAMS parms go into naming of macro |
| 6182 | |
| 6183 | module l2t_filbuf_ctl_msff_ctl_macro__width_9 ( |
| 6184 | din, |
| 6185 | l1clk, |
| 6186 | scan_in, |
| 6187 | siclk, |
| 6188 | soclk, |
| 6189 | dout, |
| 6190 | scan_out); |
| 6191 | wire [8:0] fdin; |
| 6192 | wire [7:0] so; |
| 6193 | |
| 6194 | input [8:0] din; |
| 6195 | input l1clk; |
| 6196 | input scan_in; |
| 6197 | |
| 6198 | |
| 6199 | input siclk; |
| 6200 | input soclk; |
| 6201 | |
| 6202 | output [8:0] dout; |
| 6203 | output scan_out; |
| 6204 | assign fdin[8:0] = din[8:0]; |
| 6205 | |
| 6206 | |
| 6207 | |
| 6208 | |
| 6209 | |
| 6210 | |
| 6211 | dff #(9) d0_0 ( |
| 6212 | .l1clk(l1clk), |
| 6213 | .siclk(siclk), |
| 6214 | .soclk(soclk), |
| 6215 | .d(fdin[8:0]), |
| 6216 | .si({scan_in,so[7:0]}), |
| 6217 | .so({so[7:0],scan_out}), |
| 6218 | .q(dout[8:0]) |
| 6219 | ); |
| 6220 | |
| 6221 | |
| 6222 | |
| 6223 | |
| 6224 | |
| 6225 | |
| 6226 | |
| 6227 | |
| 6228 | |
| 6229 | |
| 6230 | |
| 6231 | |
| 6232 | endmodule |
| 6233 | |
| 6234 | |
| 6235 | |
| 6236 | |
| 6237 | |
| 6238 | |
| 6239 | |
| 6240 | |
| 6241 | |
| 6242 | |
| 6243 | |
| 6244 | |
| 6245 | |
| 6246 | // any PARAMS parms go into naming of macro |
| 6247 | |
| 6248 | module l2t_filbuf_ctl_msff_ctl_macro__width_4 ( |
| 6249 | din, |
| 6250 | l1clk, |
| 6251 | scan_in, |
| 6252 | siclk, |
| 6253 | soclk, |
| 6254 | dout, |
| 6255 | scan_out); |
| 6256 | wire [3:0] fdin; |
| 6257 | wire [2:0] so; |
| 6258 | |
| 6259 | input [3:0] din; |
| 6260 | input l1clk; |
| 6261 | input scan_in; |
| 6262 | |
| 6263 | |
| 6264 | input siclk; |
| 6265 | input soclk; |
| 6266 | |
| 6267 | output [3:0] dout; |
| 6268 | output scan_out; |
| 6269 | assign fdin[3:0] = din[3:0]; |
| 6270 | |
| 6271 | |
| 6272 | |
| 6273 | |
| 6274 | |
| 6275 | |
| 6276 | dff #(4) d0_0 ( |
| 6277 | .l1clk(l1clk), |
| 6278 | .siclk(siclk), |
| 6279 | .soclk(soclk), |
| 6280 | .d(fdin[3:0]), |
| 6281 | .si({scan_in,so[2:0]}), |
| 6282 | .so({so[2:0],scan_out}), |
| 6283 | .q(dout[3:0]) |
| 6284 | ); |
| 6285 | |
| 6286 | |
| 6287 | |
| 6288 | |
| 6289 | |
| 6290 | |
| 6291 | |
| 6292 | |
| 6293 | |
| 6294 | |
| 6295 | |
| 6296 | |
| 6297 | endmodule |
| 6298 | |
| 6299 | |
| 6300 | |
| 6301 | |
| 6302 | |
| 6303 | |
| 6304 | |
| 6305 | |
| 6306 | |
| 6307 | |
| 6308 | |
| 6309 | |
| 6310 | |
| 6311 | // any PARAMS parms go into naming of macro |
| 6312 | |
| 6313 | module l2t_filbuf_ctl_msff_ctl_macro__en_1__width_4 ( |
| 6314 | din, |
| 6315 | en, |
| 6316 | l1clk, |
| 6317 | scan_in, |
| 6318 | siclk, |
| 6319 | soclk, |
| 6320 | dout, |
| 6321 | scan_out); |
| 6322 | wire [3:0] fdin; |
| 6323 | wire [2:0] so; |
| 6324 | |
| 6325 | input [3:0] din; |
| 6326 | input en; |
| 6327 | input l1clk; |
| 6328 | input scan_in; |
| 6329 | |
| 6330 | |
| 6331 | input siclk; |
| 6332 | input soclk; |
| 6333 | |
| 6334 | output [3:0] dout; |
| 6335 | output scan_out; |
| 6336 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); |
| 6337 | |
| 6338 | |
| 6339 | |
| 6340 | |
| 6341 | |
| 6342 | |
| 6343 | dff #(4) d0_0 ( |
| 6344 | .l1clk(l1clk), |
| 6345 | .siclk(siclk), |
| 6346 | .soclk(soclk), |
| 6347 | .d(fdin[3:0]), |
| 6348 | .si({scan_in,so[2:0]}), |
| 6349 | .so({so[2:0],scan_out}), |
| 6350 | .q(dout[3:0]) |
| 6351 | ); |
| 6352 | |
| 6353 | |
| 6354 | |
| 6355 | |
| 6356 | |
| 6357 | |
| 6358 | |
| 6359 | |
| 6360 | |
| 6361 | |
| 6362 | |
| 6363 | |
| 6364 | endmodule |
| 6365 | |
| 6366 | |
| 6367 | |
| 6368 | |
| 6369 | |
| 6370 | |
| 6371 | |
| 6372 | |
| 6373 | |
| 6374 | |
| 6375 | |
| 6376 | |
| 6377 | |
| 6378 | // any PARAMS parms go into naming of macro |
| 6379 | |
| 6380 | module l2t_filbuf_ctl_msff_ctl_macro__width_2 ( |
| 6381 | din, |
| 6382 | l1clk, |
| 6383 | scan_in, |
| 6384 | siclk, |
| 6385 | soclk, |
| 6386 | dout, |
| 6387 | scan_out); |
| 6388 | wire [1:0] fdin; |
| 6389 | wire [0:0] so; |
| 6390 | |
| 6391 | input [1:0] din; |
| 6392 | input l1clk; |
| 6393 | input scan_in; |
| 6394 | |
| 6395 | |
| 6396 | input siclk; |
| 6397 | input soclk; |
| 6398 | |
| 6399 | output [1:0] dout; |
| 6400 | output scan_out; |
| 6401 | assign fdin[1:0] = din[1:0]; |
| 6402 | |
| 6403 | |
| 6404 | |
| 6405 | |
| 6406 | |
| 6407 | |
| 6408 | dff #(2) d0_0 ( |
| 6409 | .l1clk(l1clk), |
| 6410 | .siclk(siclk), |
| 6411 | .soclk(soclk), |
| 6412 | .d(fdin[1:0]), |
| 6413 | .si({scan_in,so[0:0]}), |
| 6414 | .so({so[0:0],scan_out}), |
| 6415 | .q(dout[1:0]) |
| 6416 | ); |
| 6417 | |
| 6418 | |
| 6419 | |
| 6420 | |
| 6421 | |
| 6422 | |
| 6423 | |
| 6424 | |
| 6425 | |
| 6426 | |
| 6427 | |
| 6428 | |
| 6429 | endmodule |
| 6430 | |
| 6431 | |
| 6432 | |
| 6433 | |
| 6434 | |
| 6435 | |
| 6436 | |
| 6437 | |
| 6438 | |
| 6439 | |
| 6440 | |
| 6441 | |
| 6442 | |
| 6443 | // any PARAMS parms go into naming of macro |
| 6444 | |
| 6445 | module l2t_filbuf_ctl_msff_ctl_macro__clr_1__en_1__width_2 ( |
| 6446 | din, |
| 6447 | en, |
| 6448 | clr, |
| 6449 | l1clk, |
| 6450 | scan_in, |
| 6451 | siclk, |
| 6452 | soclk, |
| 6453 | dout, |
| 6454 | scan_out); |
| 6455 | wire [1:0] fdin; |
| 6456 | wire [0:0] so; |
| 6457 | |
| 6458 | input [1:0] din; |
| 6459 | input en; |
| 6460 | input clr; |
| 6461 | input l1clk; |
| 6462 | input scan_in; |
| 6463 | |
| 6464 | |
| 6465 | input siclk; |
| 6466 | input soclk; |
| 6467 | |
| 6468 | output [1:0] dout; |
| 6469 | output scan_out; |
| 6470 | assign fdin[1:0] = (din[1:0] & {2{en}} & ~{2{clr}}) | (dout[1:0] & ~{2{en}} & ~{2{clr}}); |
| 6471 | |
| 6472 | |
| 6473 | |
| 6474 | |
| 6475 | |
| 6476 | |
| 6477 | dff #(2) d0_0 ( |
| 6478 | .l1clk(l1clk), |
| 6479 | .siclk(siclk), |
| 6480 | .soclk(soclk), |
| 6481 | .d(fdin[1:0]), |
| 6482 | .si({scan_in,so[0:0]}), |
| 6483 | .so({so[0:0],scan_out}), |
| 6484 | .q(dout[1:0]) |
| 6485 | ); |
| 6486 | |
| 6487 | |
| 6488 | |
| 6489 | |
| 6490 | |
| 6491 | |
| 6492 | |
| 6493 | |
| 6494 | |
| 6495 | |
| 6496 | |
| 6497 | |
| 6498 | endmodule |
| 6499 | |
| 6500 | |
| 6501 | |
| 6502 | |
| 6503 | |
| 6504 | |
| 6505 | |
| 6506 | |
| 6507 | |
| 6508 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 6509 | // also for pass-gate with decoder |
| 6510 | |
| 6511 | |
| 6512 | |
| 6513 | |
| 6514 | |
| 6515 | // any PARAMS parms go into naming of macro |
| 6516 | |
| 6517 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_5 ( |
| 6518 | din0, |
| 6519 | sel0, |
| 6520 | din1, |
| 6521 | sel1, |
| 6522 | din2, |
| 6523 | sel2, |
| 6524 | din3, |
| 6525 | sel3, |
| 6526 | dout); |
| 6527 | input [4:0] din0; |
| 6528 | input sel0; |
| 6529 | input [4:0] din1; |
| 6530 | input sel1; |
| 6531 | input [4:0] din2; |
| 6532 | input sel2; |
| 6533 | input [4:0] din3; |
| 6534 | input sel3; |
| 6535 | output [4:0] dout; |
| 6536 | |
| 6537 | |
| 6538 | |
| 6539 | |
| 6540 | |
| 6541 | assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) | |
| 6542 | ( {5{sel1}} & din1[4:0]) | |
| 6543 | ( {5{sel2}} & din2[4:0]) | |
| 6544 | ( {5{sel3}} & din3[4:0]); |
| 6545 | |
| 6546 | |
| 6547 | |
| 6548 | |
| 6549 | |
| 6550 | endmodule |
| 6551 | |
| 6552 | |
| 6553 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 6554 | // also for pass-gate with decoder |
| 6555 | |
| 6556 | |
| 6557 | |
| 6558 | |
| 6559 | |
| 6560 | // any PARAMS parms go into naming of macro |
| 6561 | |
| 6562 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_5 ( |
| 6563 | din0, |
| 6564 | sel0, |
| 6565 | din1, |
| 6566 | sel1, |
| 6567 | dout); |
| 6568 | input [4:0] din0; |
| 6569 | input sel0; |
| 6570 | input [4:0] din1; |
| 6571 | input sel1; |
| 6572 | output [4:0] dout; |
| 6573 | |
| 6574 | |
| 6575 | |
| 6576 | |
| 6577 | |
| 6578 | assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) | |
| 6579 | ( {5{sel1}} & din1[4:0]); |
| 6580 | |
| 6581 | |
| 6582 | |
| 6583 | |
| 6584 | |
| 6585 | endmodule |
| 6586 | |
| 6587 | |
| 6588 | |
| 6589 | |
| 6590 | |
| 6591 | |
| 6592 | // any PARAMS parms go into naming of macro |
| 6593 | |
| 6594 | module l2t_filbuf_ctl_msff_ctl_macro__clr_1__width_1 ( |
| 6595 | din, |
| 6596 | clr, |
| 6597 | l1clk, |
| 6598 | scan_in, |
| 6599 | siclk, |
| 6600 | soclk, |
| 6601 | dout, |
| 6602 | scan_out); |
| 6603 | wire [0:0] fdin; |
| 6604 | |
| 6605 | input [0:0] din; |
| 6606 | input clr; |
| 6607 | input l1clk; |
| 6608 | input scan_in; |
| 6609 | |
| 6610 | |
| 6611 | input siclk; |
| 6612 | input soclk; |
| 6613 | |
| 6614 | output [0:0] dout; |
| 6615 | output scan_out; |
| 6616 | assign fdin[0:0] = din[0:0] & ~{1{clr}}; |
| 6617 | |
| 6618 | |
| 6619 | |
| 6620 | |
| 6621 | |
| 6622 | |
| 6623 | dff #(1) d0_0 ( |
| 6624 | .l1clk(l1clk), |
| 6625 | .siclk(siclk), |
| 6626 | .soclk(soclk), |
| 6627 | .d(fdin[0:0]), |
| 6628 | .si(scan_in), |
| 6629 | .so(scan_out), |
| 6630 | .q(dout[0:0]) |
| 6631 | ); |
| 6632 | |
| 6633 | |
| 6634 | |
| 6635 | |
| 6636 | |
| 6637 | |
| 6638 | |
| 6639 | |
| 6640 | |
| 6641 | |
| 6642 | |
| 6643 | |
| 6644 | endmodule |
| 6645 | |
| 6646 | |
| 6647 | |
| 6648 | |
| 6649 | |
| 6650 | |
| 6651 | |
| 6652 | |
| 6653 | |
| 6654 | |
| 6655 | |
| 6656 | |
| 6657 | |
| 6658 | // any PARAMS parms go into naming of macro |
| 6659 | |
| 6660 | module l2t_filbuf_ctl_msff_ctl_macro__en_1__width_3 ( |
| 6661 | din, |
| 6662 | en, |
| 6663 | l1clk, |
| 6664 | scan_in, |
| 6665 | siclk, |
| 6666 | soclk, |
| 6667 | dout, |
| 6668 | scan_out); |
| 6669 | wire [2:0] fdin; |
| 6670 | wire [1:0] so; |
| 6671 | |
| 6672 | input [2:0] din; |
| 6673 | input en; |
| 6674 | input l1clk; |
| 6675 | input scan_in; |
| 6676 | |
| 6677 | |
| 6678 | input siclk; |
| 6679 | input soclk; |
| 6680 | |
| 6681 | output [2:0] dout; |
| 6682 | output scan_out; |
| 6683 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); |
| 6684 | |
| 6685 | |
| 6686 | |
| 6687 | |
| 6688 | |
| 6689 | |
| 6690 | dff #(3) d0_0 ( |
| 6691 | .l1clk(l1clk), |
| 6692 | .siclk(siclk), |
| 6693 | .soclk(soclk), |
| 6694 | .d(fdin[2:0]), |
| 6695 | .si({scan_in,so[1:0]}), |
| 6696 | .so({so[1:0],scan_out}), |
| 6697 | .q(dout[2:0]) |
| 6698 | ); |
| 6699 | |
| 6700 | |
| 6701 | |
| 6702 | |
| 6703 | |
| 6704 | |
| 6705 | |
| 6706 | |
| 6707 | |
| 6708 | |
| 6709 | |
| 6710 | |
| 6711 | endmodule |
| 6712 | |
| 6713 | |
| 6714 | |
| 6715 | |
| 6716 | |
| 6717 | |
| 6718 | |
| 6719 | |
| 6720 | |
| 6721 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 6722 | // also for pass-gate with decoder |
| 6723 | |
| 6724 | |
| 6725 | |
| 6726 | |
| 6727 | |
| 6728 | // any PARAMS parms go into naming of macro |
| 6729 | |
| 6730 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_4 ( |
| 6731 | din0, |
| 6732 | sel0, |
| 6733 | din1, |
| 6734 | sel1, |
| 6735 | din2, |
| 6736 | sel2, |
| 6737 | din3, |
| 6738 | sel3, |
| 6739 | dout); |
| 6740 | input [3:0] din0; |
| 6741 | input sel0; |
| 6742 | input [3:0] din1; |
| 6743 | input sel1; |
| 6744 | input [3:0] din2; |
| 6745 | input sel2; |
| 6746 | input [3:0] din3; |
| 6747 | input sel3; |
| 6748 | output [3:0] dout; |
| 6749 | |
| 6750 | |
| 6751 | |
| 6752 | |
| 6753 | |
| 6754 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 6755 | ( {4{sel1}} & din1[3:0]) | |
| 6756 | ( {4{sel2}} & din2[3:0]) | |
| 6757 | ( {4{sel3}} & din3[3:0]); |
| 6758 | |
| 6759 | |
| 6760 | |
| 6761 | |
| 6762 | |
| 6763 | endmodule |
| 6764 | |
| 6765 | |
| 6766 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 6767 | // also for pass-gate with decoder |
| 6768 | |
| 6769 | |
| 6770 | |
| 6771 | |
| 6772 | |
| 6773 | // any PARAMS parms go into naming of macro |
| 6774 | |
| 6775 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_3 ( |
| 6776 | din0, |
| 6777 | sel0, |
| 6778 | din1, |
| 6779 | sel1, |
| 6780 | dout); |
| 6781 | input [2:0] din0; |
| 6782 | input sel0; |
| 6783 | input [2:0] din1; |
| 6784 | input sel1; |
| 6785 | output [2:0] dout; |
| 6786 | |
| 6787 | |
| 6788 | |
| 6789 | |
| 6790 | |
| 6791 | assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) | |
| 6792 | ( {3{sel1}} & din1[2:0]); |
| 6793 | |
| 6794 | |
| 6795 | |
| 6796 | |
| 6797 | |
| 6798 | endmodule |
| 6799 | |
| 6800 | |
| 6801 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 6802 | // also for pass-gate with decoder |
| 6803 | |
| 6804 | |
| 6805 | |
| 6806 | |
| 6807 | |
| 6808 | // any PARAMS parms go into naming of macro |
| 6809 | |
| 6810 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_3 ( |
| 6811 | din0, |
| 6812 | sel0, |
| 6813 | din1, |
| 6814 | sel1, |
| 6815 | din2, |
| 6816 | sel2, |
| 6817 | dout); |
| 6818 | input [2:0] din0; |
| 6819 | input sel0; |
| 6820 | input [2:0] din1; |
| 6821 | input sel1; |
| 6822 | input [2:0] din2; |
| 6823 | input sel2; |
| 6824 | output [2:0] dout; |
| 6825 | |
| 6826 | |
| 6827 | |
| 6828 | |
| 6829 | |
| 6830 | assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) | |
| 6831 | ( {3{sel1}} & din1[2:0]) | |
| 6832 | ( {3{sel2}} & din2[2:0]); |
| 6833 | |
| 6834 | |
| 6835 | |
| 6836 | |
| 6837 | |
| 6838 | endmodule |
| 6839 | |
| 6840 | |
| 6841 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 6842 | // also for pass-gate with decoder |
| 6843 | |
| 6844 | |
| 6845 | |
| 6846 | |
| 6847 | |
| 6848 | // any PARAMS parms go into naming of macro |
| 6849 | |
| 6850 | module l2t_filbuf_ctl_mux_ctl_macro__mux_aonpe__ports_3__width_4 ( |
| 6851 | din0, |
| 6852 | sel0, |
| 6853 | din1, |
| 6854 | sel1, |
| 6855 | din2, |
| 6856 | sel2, |
| 6857 | dout); |
| 6858 | input [3:0] din0; |
| 6859 | input sel0; |
| 6860 | input [3:0] din1; |
| 6861 | input sel1; |
| 6862 | input [3:0] din2; |
| 6863 | input sel2; |
| 6864 | output [3:0] dout; |
| 6865 | |
| 6866 | |
| 6867 | |
| 6868 | |
| 6869 | |
| 6870 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 6871 | ( {4{sel1}} & din1[3:0]) | |
| 6872 | ( {4{sel2}} & din2[3:0]); |
| 6873 | |
| 6874 | |
| 6875 | |
| 6876 | |
| 6877 | |
| 6878 | endmodule |
| 6879 | |
| 6880 | |
| 6881 | |
| 6882 | |
| 6883 | |
| 6884 | |
| 6885 | // any PARAMS parms go into naming of macro |
| 6886 | |
| 6887 | module l2t_filbuf_ctl_msff_ctl_macro__en_1__width_1 ( |
| 6888 | din, |
| 6889 | en, |
| 6890 | l1clk, |
| 6891 | scan_in, |
| 6892 | siclk, |
| 6893 | soclk, |
| 6894 | dout, |
| 6895 | scan_out); |
| 6896 | wire [0:0] fdin; |
| 6897 | |
| 6898 | input [0:0] din; |
| 6899 | input en; |
| 6900 | input l1clk; |
| 6901 | input scan_in; |
| 6902 | |
| 6903 | |
| 6904 | input siclk; |
| 6905 | input soclk; |
| 6906 | |
| 6907 | output [0:0] dout; |
| 6908 | output scan_out; |
| 6909 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 6910 | |
| 6911 | |
| 6912 | |
| 6913 | |
| 6914 | |
| 6915 | |
| 6916 | dff #(1) d0_0 ( |
| 6917 | .l1clk(l1clk), |
| 6918 | .siclk(siclk), |
| 6919 | .soclk(soclk), |
| 6920 | .d(fdin[0:0]), |
| 6921 | .si(scan_in), |
| 6922 | .so(scan_out), |
| 6923 | .q(dout[0:0]) |
| 6924 | ); |
| 6925 | |
| 6926 | |
| 6927 | |
| 6928 | |
| 6929 | |
| 6930 | |
| 6931 | |
| 6932 | |
| 6933 | |
| 6934 | |
| 6935 | |
| 6936 | |
| 6937 | endmodule |
| 6938 | |
| 6939 | |
| 6940 | |
| 6941 | |
| 6942 | |
| 6943 | |
| 6944 | |
| 6945 | |