| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_oqu_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define ACK_IDLE 0 |
| 36 | `define ACK_WAIT 1 |
| 37 | `define ACK_CCX_REQ 2 |
| 38 | |
| 39 | |
| 40 | |
| 41 | |
| 42 | // Address Map Defines |
| 43 | // =================== |
| 44 | `define ADDR_MAP_HI 39 |
| 45 | `define ADDR_MAP_LO 32 |
| 46 | `define IO_ADDR_BIT 39 |
| 47 | |
| 48 | // CMP space |
| 49 | `define DRAM_DATA_LO 8'h00 |
| 50 | `define DRAM_DATA_HI 8'h7f |
| 51 | |
| 52 | // IOP space |
| 53 | `define JBUS1 8'h80 |
| 54 | `define HASH_TBL_NRAM_CSR 8'h81 |
| 55 | `define RESERVED_1 8'h82 |
| 56 | `define ENET_MAC_CSR 8'h83 |
| 57 | `define ENET_ING_CSR 8'h84 |
| 58 | `define ENET_EGR_CMD_CSR 8'h85 |
| 59 | `define ENET_EGR_DP_CSR 8'h86 |
| 60 | `define RESERVED_2_LO 8'h87 |
| 61 | `define RESERVED_2_HI 8'h92 |
| 62 | `define BSC_CSR 8'h93 |
| 63 | `define RESERVED_3 8'h94 |
| 64 | `define RAND_GEN_CSR 8'h95 |
| 65 | `define CLOCK_UNIT_CSR 8'h96 |
| 66 | `define DRAM_CSR 8'h97 |
| 67 | `define IOB_MAN_CSR 8'h98 |
| 68 | `define TAP_CSR 8'h99 |
| 69 | `define RESERVED_4_L0 8'h9a |
| 70 | `define RESERVED_4_HI 8'h9d |
| 71 | `define CPU_ASI 8'h9e |
| 72 | `define IOB_INT_CSR 8'h9f |
| 73 | |
| 74 | // L2 space |
| 75 | `define L2C_CSR_LO 8'ha0 |
| 76 | `define L2C_CSR_HI 8'hbf |
| 77 | |
| 78 | // More IOP space |
| 79 | `define JBUS2_LO 8'hc0 |
| 80 | `define JBUS2_HI 8'hfe |
| 81 | `define SPI_CSR 8'hff |
| 82 | |
| 83 | |
| 84 | //Cache Crossbar Width and Field Defines |
| 85 | //====================================== |
| 86 | `define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change |
| 87 | `define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change |
| 88 | `define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change |
| 89 | `define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change |
| 90 | `define CPX_WIDTH11 134 |
| 91 | `define CPX_WIDTH11c 134c |
| 92 | `define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change |
| 93 | |
| 94 | `define PCX_VLD 123 //PCX packet valid |
| 95 | `define PCX_RQ_HI 122 //PCX request type field |
| 96 | `define PCX_RQ_LO 118 |
| 97 | `define PCX_NC 117 //PCX non-cacheable bit |
| 98 | `define PCX_R 117 //PCX read/!write bit |
| 99 | `define PCX_CP_HI 116 //PCX cpu_id field |
| 100 | `define PCX_CP_LO 114 |
| 101 | `define PCX_TH_HI 113 //PCX Thread field |
| 102 | `define PCX_TH_LO 112 |
| 103 | `define PCX_BF_HI 111 //PCX buffer id field |
| 104 | `define PCX_INVALL 111 |
| 105 | `define PCX_BF_LO 109 |
| 106 | `define PCX_WY_HI 108 //PCX replaced L1 way field |
| 107 | `define PCX_WY_LO 107 |
| 108 | `define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01 |
| 109 | `define PCX_P_LO 107 |
| 110 | `define PCX_SZ_HI 106 //PCX load/store size field |
| 111 | `define PCX_SZ_LO 104 |
| 112 | `define PCX_ERR_HI 106 //PCX error field |
| 113 | `define PCX_ERR_LO 104 |
| 114 | `define PCX_AD_HI 103 //PCX address field |
| 115 | `define PCX_AD_LO 64 |
| 116 | `define PCX_DA_HI 63 //PCX Store data |
| 117 | `define PCX_DA_LO 0 |
| 118 | |
| 119 | `define PCX_SZ_1B 3'b000 // encoding for 1B access |
| 120 | `define PCX_SZ_2B 3'b001 // encoding for 2B access |
| 121 | `define PCX_SZ_4B 3'b010 // encoding for 4B access |
| 122 | `define PCX_SZ_8B 3'b011 // encoding for 8B access |
| 123 | `define PCX_SZ_16B 3'b100 // encoding for 16B access |
| 124 | |
| 125 | `define CPX_VLD 145 //CPX payload packet valid |
| 126 | |
| 127 | `define CPX_RQ_HI 144 //CPX Request type |
| 128 | `define CPX_RQ_LO 141 |
| 129 | `define CPX_L2MISS 140 |
| 130 | `define CPX_ERR_HI 140 //CPX error field |
| 131 | `define CPX_ERR_LO 138 |
| 132 | `define CPX_NC 137 //CPX non-cacheable |
| 133 | `define CPX_R 137 //CPX read/!write bit |
| 134 | `define CPX_TH_HI 136 //CPX thread ID field |
| 135 | `define CPX_TH_LO 134 |
| 136 | |
| 137 | //bits 133:128 are shared by different fields |
| 138 | //for different packet types. |
| 139 | |
| 140 | `define CPX_IN_HI 133 //CPX Interrupt source |
| 141 | `define CPX_IN_LO 128 |
| 142 | |
| 143 | `define CPX_WYVLD 133 //CPX replaced way valid |
| 144 | `define CPX_WY_HI 132 //CPX replaced I$/D$ way |
| 145 | `define CPX_WY_LO 131 |
| 146 | `define CPX_BF_HI 130 //CPX buffer ID field - 3 bits |
| 147 | `define CPX_BF_LO 128 |
| 148 | |
| 149 | `define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits |
| 150 | `define CPX_SI_LO 128 //used for invalidates |
| 151 | |
| 152 | `define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01 |
| 153 | `define CPX_P_LO 130 |
| 154 | |
| 155 | `define CPX_ASI 130 //CPX forward request to ASI |
| 156 | `define CPX_IF4B 130 |
| 157 | `define CPX_IINV 124 |
| 158 | `define CPX_DINV 123 |
| 159 | `define CPX_INVPA5 122 |
| 160 | `define CPX_INVPA4 121 |
| 161 | `define CPX_CPUID_HI 120 |
| 162 | `define CPX_CPUID_LO 118 |
| 163 | `define CPX_INV_PA_HI 116 |
| 164 | `define CPX_INV_PA_LO 112 |
| 165 | `define CPX_INV_IDX_HI 117 |
| 166 | `define CPX_INV_IDX_LO 112 |
| 167 | |
| 168 | `define CPX_DA_HI 127 //CPX data payload |
| 169 | `define CPX_DA_LO 0 |
| 170 | |
| 171 | `define LOAD_RQ 5'b00000 |
| 172 | `define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 173 | `define IMISS_RQ 5'b10000 |
| 174 | `define STORE_RQ 5'b00001 |
| 175 | `define CAS1_RQ 5'b00010 |
| 176 | `define CAS2_RQ 5'b00011 |
| 177 | `define SWAP_RQ 5'b00111 |
| 178 | `define STRLOAD_RQ 5'b00100 |
| 179 | `define STRST_RQ 5'b00101 |
| 180 | `define STQ_RQ 5'b00111 |
| 181 | `define INT_RQ 5'b01001 |
| 182 | `define FWD_RQ 5'b01101 |
| 183 | `define FWD_RPY 5'b01110 |
| 184 | `define RSVD_RQ 5'b11111 |
| 185 | |
| 186 | `define LOAD_RET 4'b0000 |
| 187 | `define INV_RET 4'b0011 |
| 188 | `define ST_ACK 4'b0100 |
| 189 | `define AT_ACK 4'b0011 |
| 190 | `define INT_RET 4'b0111 |
| 191 | `define TEST_RET 4'b0101 |
| 192 | `define FP_RET 4'b1000 |
| 193 | `define IFILL_RET 4'b0001 |
| 194 | `define EVICT_REQ 4'b0011 |
| 195 | //`define INVAL_ACK 4'b1000 |
| 196 | `define INVAL_ACK 4'b0100 |
| 197 | `define ERR_RET 4'b1100 |
| 198 | `define STRLOAD_RET 4'b0010 |
| 199 | `define STRST_ACK 4'b0110 |
| 200 | `define FWD_RQ_RET 4'b1010 |
| 201 | `define FWD_RPY_RET 4'b1011 |
| 202 | `define RSVD_RET 4'b1111 |
| 203 | |
| 204 | //End cache crossbar defines |
| 205 | |
| 206 | |
| 207 | // Number of COS supported by EECU |
| 208 | `define EECU_COS_NUM 2 |
| 209 | |
| 210 | |
| 211 | // |
| 212 | // BSC bus sizes |
| 213 | // ============= |
| 214 | // |
| 215 | |
| 216 | // General |
| 217 | `define BSC_ADDRESS 40 |
| 218 | `define MAX_XFER_LEN 7'b0 |
| 219 | `define XFER_LEN_WIDTH 6 |
| 220 | |
| 221 | // CTags |
| 222 | `define BSC_CTAG_SZ 12 |
| 223 | `define EICU_CTAG_PRE 5'b11101 |
| 224 | `define EICU_CTAG_REM 7 |
| 225 | `define EIPU_CTAG_PRE 3'b011 |
| 226 | `define EIPU_CTAG_REM 9 |
| 227 | `define EECU_CTAG_PRE 8'b11010000 |
| 228 | `define EECU_CTAG_REM 4 |
| 229 | `define EEPU_CTAG_PRE 6'b010000 |
| 230 | `define EEPU_CTAG_REM 6 |
| 231 | `define L2C_CTAG_PRE 2'b00 |
| 232 | `define L2C_CTAG_REM 10 |
| 233 | `define JBI_CTAG_PRE 2'b10 |
| 234 | `define JBI_CTAG_REM 10 |
| 235 | // reinstated temporarily |
| 236 | `define PCI_CTAG_PRE 7'b1101100 |
| 237 | `define PCI_CTAG_REM 5 |
| 238 | |
| 239 | |
| 240 | // CoS |
| 241 | `define EICU_COS 1'b0 |
| 242 | `define EIPU_COS 1'b1 |
| 243 | `define EECU_COS 1'b0 |
| 244 | `define EEPU_COS 1'b1 |
| 245 | `define PCI_COS 1'b0 |
| 246 | |
| 247 | // L2$ Bank |
| 248 | `define BSC_L2_BNK_HI 8 |
| 249 | `define BSC_L2_BNK_LO 6 |
| 250 | |
| 251 | // L2$ Req |
| 252 | `define BSC_L2_REQ_SZ 62 |
| 253 | `define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code |
| 254 | `define BSC_L2_BUS 64 |
| 255 | `define BSC_L2_CTAG_HI 61 |
| 256 | `define BSC_L2_CTAG_LO 50 |
| 257 | `define BSC_L2_ADD_HI 49 |
| 258 | `define BSC_L2_ADD_LO 10 |
| 259 | `define BSC_L2_LEN_HI 9 |
| 260 | `define BSC_L2_LEN_LO 3 |
| 261 | `define BSC_L2_ALLOC 2 |
| 262 | `define BSC_L2_COS 1 |
| 263 | `define BSC_L2_READ 0 |
| 264 | |
| 265 | // L2$ Ack |
| 266 | `define L2_BSC_ACK_SZ 16 |
| 267 | `define L2_BSC_BUS 64 |
| 268 | `define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address |
| 269 | `define L2_BSC_CBA_LO 13 |
| 270 | `define L2_BSC_READ 12 |
| 271 | `define L2_BSC_CTAG_HI 11 |
| 272 | `define L2_BSC_CTAG_LO 0 |
| 273 | |
| 274 | // Enet Egress Command Unit |
| 275 | `define EECU_REQ_BUS 44 |
| 276 | `define EECU_REQ_SZ 44 |
| 277 | `define EECU_R_QID_HI 43 |
| 278 | `define EECU_R_QID_LO 40 |
| 279 | `define EECU_R_ADD_HI 39 |
| 280 | `define EECU_R_ADD_LO 0 |
| 281 | |
| 282 | `define EECU_ACK_BUS 64 |
| 283 | `define EECU_ACK_SZ 5 |
| 284 | `define EECU_A_NACK 4 |
| 285 | `define EECU_A_QID_HI 3 |
| 286 | `define EECU_A_QID_LO 0 |
| 287 | |
| 288 | |
| 289 | // Enet Egress Packet Unit |
| 290 | `define EEPU_REQ_BUS 55 |
| 291 | `define EEPU_REQ_SZ 55 |
| 292 | `define EEPU_R_TLEN_HI 54 |
| 293 | `define EEPU_R_TLEN_LO 48 |
| 294 | `define EEPU_R_SOF 47 |
| 295 | `define EEPU_R_EOF 46 |
| 296 | `define EEPU_R_PORT_HI 45 |
| 297 | `define EEPU_R_PORT_LO 44 |
| 298 | `define EEPU_R_QID_HI 43 |
| 299 | `define EEPU_R_QID_LO 40 |
| 300 | `define EEPU_R_ADD_HI 39 |
| 301 | `define EEPU_R_ADD_LO 0 |
| 302 | |
| 303 | // This is cleaved in between Egress Datapath Ack's |
| 304 | `define EEPU_ACK_BUS 6 |
| 305 | `define EEPU_ACK_SZ 6 |
| 306 | `define EEPU_A_EOF 5 |
| 307 | `define EEPU_A_NACK 4 |
| 308 | `define EEPU_A_QID_HI 3 |
| 309 | `define EEPU_A_QID_LO 0 |
| 310 | |
| 311 | |
| 312 | // Enet Egress Datapath |
| 313 | `define EEDP_ACK_BUS 128 |
| 314 | `define EEDP_ACK_SZ 28 |
| 315 | `define EEDP_A_NACK 27 |
| 316 | `define EEDP_A_QID_HI 26 |
| 317 | `define EEDP_A_QID_LO 21 |
| 318 | `define EEDP_A_SOF 20 |
| 319 | `define EEDP_A_EOF 19 |
| 320 | `define EEDP_A_LEN_HI 18 |
| 321 | `define EEDP_A_LEN_LO 12 |
| 322 | `define EEDP_A_TAG_HI 11 |
| 323 | `define EEDP_A_TAG_LO 0 |
| 324 | `define EEDP_A_PORT_HI 5 |
| 325 | `define EEDP_A_PORT_LO 4 |
| 326 | `define EEDP_A_PORT_WIDTH 2 |
| 327 | |
| 328 | |
| 329 | // In-Order / Ordered Queue: EEPU |
| 330 | // Tag is: TLEN, SOF, EOF, QID = 15 |
| 331 | `define EEPU_TAG_ARY (7+1+1+6) |
| 332 | `define EEPU_ENTRIES 16 |
| 333 | `define EEPU_E_IDX 4 |
| 334 | `define EEPU_PORTS 4 |
| 335 | `define EEPU_P_IDX 2 |
| 336 | |
| 337 | // Nack + Tag Info + CTag |
| 338 | `define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12) |
| 339 | `define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX) |
| 340 | |
| 341 | |
| 342 | // ENET Ingress Queue Management Req |
| 343 | `define EICU_REQ_BUS 64 |
| 344 | `define EICU_REQ_SZ 62 |
| 345 | `define EICU_R_CTAG_HI 61 |
| 346 | `define EICU_R_CTAG_LO 50 |
| 347 | `define EICU_R_ADD_HI 49 |
| 348 | `define EICU_R_ADD_LO 10 |
| 349 | `define EICU_R_LEN_HI 9 |
| 350 | `define EICU_R_LEN_LO 3 |
| 351 | `define EICU_R_COS 1 |
| 352 | `define EICU_R_READ 0 |
| 353 | |
| 354 | |
| 355 | // ENET Ingress Queue Management Ack |
| 356 | `define EICU_ACK_BUS 64 |
| 357 | `define EICU_ACK_SZ 14 |
| 358 | `define EICU_A_NACK 13 |
| 359 | `define EICU_A_READ 12 |
| 360 | `define EICU_A_CTAG_HI 11 |
| 361 | `define EICU_A_CTAG_LO 0 |
| 362 | |
| 363 | |
| 364 | // Enet Ingress Packet Unit |
| 365 | `define EIPU_REQ_BUS 128 |
| 366 | `define EIPU_REQ_SZ 59 |
| 367 | `define EIPU_R_CTAG_HI 58 |
| 368 | `define EIPU_R_CTAG_LO 50 |
| 369 | `define EIPU_R_ADD_HI 49 |
| 370 | `define EIPU_R_ADD_LO 10 |
| 371 | `define EIPU_R_LEN_HI 9 |
| 372 | `define EIPU_R_LEN_LO 3 |
| 373 | `define EIPU_R_COS 1 |
| 374 | `define EIPU_R_READ 0 |
| 375 | |
| 376 | |
| 377 | // ENET Ingress Packet Unit Ack |
| 378 | `define EIPU_ACK_BUS 10 |
| 379 | `define EIPU_ACK_SZ 10 |
| 380 | `define EIPU_A_NACK 9 |
| 381 | `define EIPU_A_CTAG_HI 8 |
| 382 | `define EIPU_A_CTAG_LO 0 |
| 383 | |
| 384 | |
| 385 | // In-Order / Ordered Queue: PCI |
| 386 | // Tag is: CTAG |
| 387 | `define PCI_TAG_ARY 12 |
| 388 | `define PCI_ENTRIES 16 |
| 389 | `define PCI_E_IDX 4 |
| 390 | `define PCI_PORTS 2 |
| 391 | |
| 392 | // PCI-X Request |
| 393 | `define PCI_REQ_BUS 64 |
| 394 | `define PCI_REQ_SZ 62 |
| 395 | `define PCI_R_CTAG_HI 61 |
| 396 | `define PCI_R_CTAG_LO 50 |
| 397 | `define PCI_R_ADD_HI 49 |
| 398 | `define PCI_R_ADD_LO 10 |
| 399 | `define PCI_R_LEN_HI 9 |
| 400 | `define PCI_R_LEN_LO 3 |
| 401 | `define PCI_R_COS 1 |
| 402 | `define PCI_R_READ 0 |
| 403 | |
| 404 | // PCI_X Acknowledge |
| 405 | `define PCI_ACK_BUS 64 |
| 406 | `define PCI_ACK_SZ 14 |
| 407 | `define PCI_A_NACK 13 |
| 408 | `define PCI_A_READ 12 |
| 409 | `define PCI_A_CTAG_HI 11 |
| 410 | `define PCI_A_CTAG_LO 0 |
| 411 | |
| 412 | |
| 413 | `define BSC_MAX_REQ_SZ 62 |
| 414 | |
| 415 | |
| 416 | // |
| 417 | // BSC array sizes |
| 418 | //================ |
| 419 | // |
| 420 | `define BSC_REQ_ARY_INDEX 6 |
| 421 | `define BSC_REQ_ARY_DEPTH 64 |
| 422 | `define BSC_REQ_ARY_WIDTH 62 |
| 423 | `define BSC_REQ_NXT_WIDTH 12 |
| 424 | `define BSC_ACK_ARY_INDEX 6 |
| 425 | `define BSC_ACK_ARY_DEPTH 64 |
| 426 | `define BSC_ACK_ARY_WIDTH 14 |
| 427 | `define BSC_ACK_NXT_WIDTH 12 |
| 428 | `define BSC_PAY_ARY_INDEX 6 |
| 429 | `define BSC_PAY_ARY_DEPTH 64 |
| 430 | `define BSC_PAY_ARY_WIDTH 256 |
| 431 | |
| 432 | // ECC syndrome bits per memory element |
| 433 | `define BSC_PAY_ECC 10 |
| 434 | `define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH) |
| 435 | |
| 436 | |
| 437 | // |
| 438 | // BSC Port Definitions |
| 439 | // ==================== |
| 440 | // |
| 441 | // Bits 7 to 4 of curr_port_id |
| 442 | `define BSC_PORT_NULL 4'h0 |
| 443 | `define BSC_PORT_SC 4'h1 |
| 444 | `define BSC_PORT_EICU 4'h2 |
| 445 | `define BSC_PORT_EIPU 4'h3 |
| 446 | `define BSC_PORT_EECU 4'h4 |
| 447 | `define BSC_PORT_EEPU 4'h8 |
| 448 | `define BSC_PORT_PCI 4'h9 |
| 449 | |
| 450 | // Number of ports of each type |
| 451 | `define BSC_PORT_SC_CNT 8 |
| 452 | |
| 453 | // Bits needed to represent above |
| 454 | `define BSC_PORT_SC_IDX 3 |
| 455 | |
| 456 | // How wide the linked list pointers are |
| 457 | // 60b for no payload (2CoS) |
| 458 | // 80b for payload (2CoS) |
| 459 | |
| 460 | //`define BSC_OBJ_PTR 80 |
| 461 | //`define BSC_HD1_HI 69 |
| 462 | //`define BSC_HD1_LO 60 |
| 463 | //`define BSC_TL1_HI 59 |
| 464 | //`define BSC_TL1_LO 50 |
| 465 | //`define BSC_CT1_HI 49 |
| 466 | //`define BSC_CT1_LO 40 |
| 467 | //`define BSC_HD0_HI 29 |
| 468 | //`define BSC_HD0_LO 20 |
| 469 | //`define BSC_TL0_HI 19 |
| 470 | //`define BSC_TL0_LO 10 |
| 471 | //`define BSC_CT0_HI 9 |
| 472 | //`define BSC_CT0_LO 0 |
| 473 | |
| 474 | `define BSC_OBJP_PTR 48 |
| 475 | `define BSC_PYP1_HI 47 |
| 476 | `define BSC_PYP1_LO 42 |
| 477 | `define BSC_HDP1_HI 41 |
| 478 | `define BSC_HDP1_LO 36 |
| 479 | `define BSC_TLP1_HI 35 |
| 480 | `define BSC_TLP1_LO 30 |
| 481 | `define BSC_CTP1_HI 29 |
| 482 | `define BSC_CTP1_LO 24 |
| 483 | `define BSC_PYP0_HI 23 |
| 484 | `define BSC_PYP0_LO 18 |
| 485 | `define BSC_HDP0_HI 17 |
| 486 | `define BSC_HDP0_LO 12 |
| 487 | `define BSC_TLP0_HI 11 |
| 488 | `define BSC_TLP0_LO 6 |
| 489 | `define BSC_CTP0_HI 5 |
| 490 | `define BSC_CTP0_LO 0 |
| 491 | |
| 492 | `define BSC_PTR_WIDTH 192 |
| 493 | `define BSC_PTR_REQ_HI 191 |
| 494 | `define BSC_PTR_REQ_LO 144 |
| 495 | `define BSC_PTR_REQP_HI 143 |
| 496 | `define BSC_PTR_REQP_LO 96 |
| 497 | `define BSC_PTR_ACK_HI 95 |
| 498 | `define BSC_PTR_ACK_LO 48 |
| 499 | `define BSC_PTR_ACKP_HI 47 |
| 500 | `define BSC_PTR_ACKP_LO 0 |
| 501 | |
| 502 | `define BSC_PORT_SC_PTR 96 // R, R+P |
| 503 | `define BSC_PORT_EECU_PTR 48 // A+P |
| 504 | `define BSC_PORT_EICU_PTR 96 // A, A+P |
| 505 | `define BSC_PORT_EIPU_PTR 48 // A |
| 506 | |
| 507 | // I2C STATES in DRAMctl |
| 508 | `define I2C_CMD_NOP 4'b0000 |
| 509 | `define I2C_CMD_START 4'b0001 |
| 510 | `define I2C_CMD_STOP 4'b0010 |
| 511 | `define I2C_CMD_WRITE 4'b0100 |
| 512 | `define I2C_CMD_READ 4'b1000 |
| 513 | |
| 514 | |
| 515 | // |
| 516 | // IOB defines |
| 517 | // =========== |
| 518 | // |
| 519 | `define IOB_ADDR_WIDTH 40 |
| 520 | `define IOB_LOCAL_ADDR_WIDTH 32 |
| 521 | |
| 522 | `define IOB_CPU_INDEX 3 |
| 523 | `define IOB_CPU_WIDTH 8 |
| 524 | `define IOB_THR_INDEX 2 |
| 525 | `define IOB_THR_WIDTH 4 |
| 526 | `define IOB_CPUTHR_INDEX 5 |
| 527 | `define IOB_CPUTHR_WIDTH 32 |
| 528 | |
| 529 | `define IOB_MONDO_DATA_INDEX 5 |
| 530 | `define IOB_MONDO_DATA_DEPTH 32 |
| 531 | `define IOB_MONDO_DATA_WIDTH 64 |
| 532 | `define IOB_MONDO_SRC_WIDTH 5 |
| 533 | `define IOB_MONDO_BUSY 5 |
| 534 | |
| 535 | `define IOB_INT_TAB_INDEX 6 |
| 536 | `define IOB_INT_TAB_DEPTH 64 |
| 537 | |
| 538 | `define IOB_INT_STAT_WIDTH 32 |
| 539 | `define IOB_INT_STAT_HI 31 |
| 540 | `define IOB_INT_STAT_LO 0 |
| 541 | |
| 542 | `define IOB_INT_VEC_WIDTH 6 |
| 543 | `define IOB_INT_VEC_HI 5 |
| 544 | `define IOB_INT_VEC_LO 0 |
| 545 | |
| 546 | `define IOB_INT_CPU_WIDTH 5 |
| 547 | `define IOB_INT_CPU_HI 12 |
| 548 | `define IOB_INT_CPU_LO 8 |
| 549 | |
| 550 | `define IOB_INT_MASK 2 |
| 551 | `define IOB_INT_CLEAR 1 |
| 552 | `define IOB_INT_PEND 0 |
| 553 | |
| 554 | `define IOB_DISP_TYPE_HI 17 |
| 555 | `define IOB_DISP_TYPE_LO 16 |
| 556 | `define IOB_DISP_THR_HI 12 |
| 557 | `define IOB_DISP_THR_LO 8 |
| 558 | `define IOB_DISP_VEC_HI 5 |
| 559 | `define IOB_DISP_VEC_LO 0 |
| 560 | |
| 561 | `define IOB_JBI_RESET 1 |
| 562 | `define IOB_ENET_RESET 0 |
| 563 | |
| 564 | `define IOB_RESET_STAT_WIDTH 3 |
| 565 | `define IOB_RESET_STAT_HI 3 |
| 566 | `define IOB_RESET_STAT_LO 1 |
| 567 | |
| 568 | `define IOB_SERNUM_WIDTH 64 |
| 569 | |
| 570 | `define IOB_FUSE_WIDTH 22 |
| 571 | |
| 572 | `define IOB_TMSTAT_THERM 63 |
| 573 | |
| 574 | `define IOB_POR_TT 6'b01 // power-on-reset trap type |
| 575 | |
| 576 | `define IOB_CPU_BUF_INDEX 4 |
| 577 | |
| 578 | `define IOB_INT_BUF_INDEX 4 |
| 579 | `define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width |
| 580 | |
| 581 | `define IOB_IO_BUF_INDEX 4 |
| 582 | `define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width |
| 583 | |
| 584 | `define IOB_L2_VIS_BUF_INDEX 5 |
| 585 | `define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width |
| 586 | |
| 587 | `define IOB_INT_AVEC_WIDTH 16 // availibility vector width |
| 588 | `define IOB_ACK_AVEC_WIDTH 16 // availibility vector width |
| 589 | |
| 590 | // fixme - double check address mapping |
| 591 | // CREG in `IOB_INT_CSR space |
| 592 | `define IOB_DEV_ADDR_MASK 32'hfffffe07 |
| 593 | `define IOB_CREG_INTSTAT 32'h00000000 |
| 594 | `define IOB_CREG_MDATA0 32'h00000400 |
| 595 | `define IOB_CREG_MDATA1 32'h00000500 |
| 596 | `define IOB_CREG_MBUSY 32'h00000900 |
| 597 | `define IOB_THR_ADDR_MASK 32'hffffff07 |
| 598 | `define IOB_CREG_MDATA0_ALIAS 32'h00000600 |
| 599 | `define IOB_CREG_MDATA1_ALIAS 32'h00000700 |
| 600 | `define IOB_CREG_MBUSY_ALIAS 32'h00000b00 |
| 601 | |
| 602 | // CREG in `IOB_MAN_CSR space |
| 603 | `define IOB_CREG_INTMAN 32'h00000000 |
| 604 | `define IOB_CREG_INTCTL 32'h00000400 |
| 605 | `define IOB_CREG_INTVECDISP 32'h00000800 |
| 606 | `define IOB_CREG_RESETSTAT 32'h00000810 |
| 607 | `define IOB_CREG_SERNUM 32'h00000820 |
| 608 | `define IOB_CREG_TMSTATCTRL 32'h00000828 |
| 609 | `define IOB_CREG_COREAVAIL 32'h00000830 |
| 610 | `define IOB_CREG_SSYSRESET 32'h00000838 |
| 611 | `define IOB_CREG_FUSESTAT 32'h00000840 |
| 612 | `define IOB_CREG_JINTV 32'h00000a00 |
| 613 | |
| 614 | `define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 |
| 615 | `define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 |
| 616 | `define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 |
| 617 | `define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 |
| 618 | `define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 |
| 619 | `define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 |
| 620 | `define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 |
| 621 | `define IOB_CREG_DBG_ENET_CTRL 32'h00002000 |
| 622 | `define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 |
| 623 | `define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 |
| 624 | `define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 |
| 625 | `define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 |
| 626 | `define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 |
| 627 | `define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 |
| 628 | `define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 |
| 629 | `define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 |
| 630 | `define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 |
| 631 | `define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 |
| 632 | `define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 |
| 633 | `define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 |
| 634 | `define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 |
| 635 | `define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 |
| 636 | |
| 637 | `define IOB_CREG_TESTSTUB 32'h80000000 |
| 638 | |
| 639 | // Address map for TAP access of SPARC ASI |
| 640 | `define IOB_ASI_PC 4'b0000 |
| 641 | `define IOB_ASI_BIST 4'b0001 |
| 642 | `define IOB_ASI_MARGIN 4'b0010 |
| 643 | `define IOB_ASI_DEFEATURE 4'b0011 |
| 644 | `define IOB_ASI_L1DD 4'b0100 |
| 645 | `define IOB_ASI_L1ID 4'b0101 |
| 646 | `define IOB_ASI_L1DT 4'b0110 |
| 647 | |
| 648 | `define IOB_INT 2'b00 |
| 649 | `define IOB_RESET 2'b01 |
| 650 | `define IOB_IDLE 2'b10 |
| 651 | `define IOB_RESUME 2'b11 |
| 652 | |
| 653 | // |
| 654 | // CIOP UCB Bus Width |
| 655 | // ================== |
| 656 | // |
| 657 | `define IOB_EECU_WIDTH 16 // ethernet egress command |
| 658 | `define EECU_IOB_WIDTH 16 |
| 659 | |
| 660 | `define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously) |
| 661 | `define NRAM_IOB_WIDTH 4 |
| 662 | |
| 663 | `define IOB_JBI_WIDTH 16 // JBI |
| 664 | `define JBI_IOB_WIDTH 16 |
| 665 | |
| 666 | `define IOB_ENET_ING_WIDTH 32 // ethernet ingress |
| 667 | `define ENET_ING_IOB_WIDTH 8 |
| 668 | |
| 669 | `define IOB_ENET_EGR_WIDTH 4 // ethernet egress |
| 670 | `define ENET_EGR_IOB_WIDTH 4 |
| 671 | |
| 672 | `define IOB_ENET_MAC_WIDTH 4 // ethernet MAC |
| 673 | `define ENET_MAC_IOB_WIDTH 4 |
| 674 | |
| 675 | `define IOB_DRAM_WIDTH 4 // DRAM controller |
| 676 | `define DRAM_IOB_WIDTH 4 |
| 677 | |
| 678 | `define IOB_BSC_WIDTH 4 // BSC |
| 679 | `define BSC_IOB_WIDTH 4 |
| 680 | |
| 681 | `define IOB_SPI_WIDTH 4 // SPI (Boot ROM) |
| 682 | `define SPI_IOB_WIDTH 4 |
| 683 | |
| 684 | `define IOB_CLK_WIDTH 4 // clk unit |
| 685 | `define CLK_IOB_WIDTH 4 |
| 686 | |
| 687 | `define IOB_CLSP_WIDTH 4 // clk spine unit |
| 688 | `define CLSP_IOB_WIDTH 4 |
| 689 | |
| 690 | `define IOB_TAP_WIDTH 8 // TAP |
| 691 | `define TAP_IOB_WIDTH 8 |
| 692 | |
| 693 | |
| 694 | // |
| 695 | // CIOP UCB Buf ID Type |
| 696 | // ==================== |
| 697 | // |
| 698 | `define UCB_BID_CMP 2'b00 |
| 699 | `define UCB_BID_TAP 2'b01 |
| 700 | |
| 701 | // |
| 702 | // Interrupt Device ID |
| 703 | // =================== |
| 704 | // |
| 705 | // Caution: DUMMY_DEV_ID has to be 9 bit wide |
| 706 | // for fields to line up properly in the IOB. |
| 707 | `define DUMMY_DEV_ID 9'h10 // 16 |
| 708 | `define UNCOR_ECC_DEV_ID 7'd17 // 17 |
| 709 | |
| 710 | // |
| 711 | // Soft Error related definitions |
| 712 | // ============================== |
| 713 | // |
| 714 | `define COR_ECC_CNT_WIDTH 16 |
| 715 | |
| 716 | |
| 717 | // |
| 718 | // CMP clock |
| 719 | // ========= |
| 720 | // |
| 721 | |
| 722 | `define CMP_CLK_PERIOD 1333 |
| 723 | |
| 724 | |
| 725 | // |
| 726 | // NRAM/IO Interface |
| 727 | // ================= |
| 728 | // |
| 729 | |
| 730 | `define DRAM_CLK_PERIOD 6000 |
| 731 | |
| 732 | `define NRAM_IO_DQ_WIDTH 32 |
| 733 | `define IO_NRAM_DQ_WIDTH 32 |
| 734 | |
| 735 | `define NRAM_IO_ADDR_WIDTH 15 |
| 736 | `define NRAM_IO_BA_WIDTH 2 |
| 737 | |
| 738 | |
| 739 | // |
| 740 | // NRAM/ENET Interface |
| 741 | // =================== |
| 742 | // |
| 743 | |
| 744 | `define NRAM_ENET_DATA_WIDTH 64 |
| 745 | `define ENET_NRAM_ADDR_WIDTH 20 |
| 746 | |
| 747 | `define NRAM_DBG_DATA_WIDTH 40 |
| 748 | |
| 749 | |
| 750 | // |
| 751 | // IO/FCRAM Interface |
| 752 | // ================== |
| 753 | // |
| 754 | |
| 755 | `define FCRAM_DATA1_HI 63 |
| 756 | `define FCRAM_DATA1_LO 32 |
| 757 | `define FCRAM_DATA0_HI 31 |
| 758 | `define FCRAM_DATA0_LO 0 |
| 759 | |
| 760 | // |
| 761 | // PCI Interface |
| 762 | // ================== |
| 763 | // Load/store size encodings |
| 764 | // ------------------------- |
| 765 | // Size encoding |
| 766 | // 000 - byte |
| 767 | // 001 - half-word |
| 768 | // 010 - word |
| 769 | // 011 - double-word |
| 770 | // 100 - quad |
| 771 | `define LDST_SZ_BYTE 3'b000 |
| 772 | `define LDST_SZ_HALF_WORD 3'b001 |
| 773 | `define LDST_SZ_WORD 3'b010 |
| 774 | `define LDST_SZ_DOUBLE_WORD 3'b011 |
| 775 | `define LDST_SZ_QUAD 3'b100 |
| 776 | |
| 777 | // |
| 778 | // JBI<->SCTAG Interface |
| 779 | // ======================= |
| 780 | // Outbound Header Format |
| 781 | `define JBI_BTU_OUT_ADDR_LO 0 |
| 782 | `define JBI_BTU_OUT_ADDR_HI 42 |
| 783 | `define JBI_BTU_OUT_RSV0_LO 43 |
| 784 | `define JBI_BTU_OUT_RSV0_HI 43 |
| 785 | `define JBI_BTU_OUT_TYPE_LO 44 |
| 786 | `define JBI_BTU_OUT_TYPE_HI 48 |
| 787 | `define JBI_BTU_OUT_RSV1_LO 49 |
| 788 | `define JBI_BTU_OUT_RSV1_HI 51 |
| 789 | `define JBI_BTU_OUT_REPLACE_LO 52 |
| 790 | `define JBI_BTU_OUT_REPLACE_HI 56 |
| 791 | `define JBI_BTU_OUT_RSV2_LO 57 |
| 792 | `define JBI_BTU_OUT_RSV2_HI 59 |
| 793 | `define JBI_BTU_OUT_BTU_ID_LO 60 |
| 794 | `define JBI_BTU_OUT_BTU_ID_HI 71 |
| 795 | `define JBI_BTU_OUT_DATA_RTN 72 |
| 796 | `define JBI_BTU_OUT_RSV3_LO 73 |
| 797 | `define JBI_BTU_OUT_RSV3_HI 75 |
| 798 | `define JBI_BTU_OUT_CE 76 |
| 799 | `define JBI_BTU_OUT_RSV4_LO 77 |
| 800 | `define JBI_BTU_OUT_RSV4_HI 79 |
| 801 | `define JBI_BTU_OUT_UE 80 |
| 802 | `define JBI_BTU_OUT_RSV5_LO 81 |
| 803 | `define JBI_BTU_OUT_RSV5_HI 83 |
| 804 | `define JBI_BTU_OUT_DRAM 84 |
| 805 | `define JBI_BTU_OUT_RSV6_LO 85 |
| 806 | `define JBI_BTU_OUT_RSV6_HI 127 |
| 807 | |
| 808 | // Inbound Header Format |
| 809 | `define JBI_SCTAG_IN_ADDR_LO 0 |
| 810 | `define JBI_SCTAG_IN_ADDR_HI 39 |
| 811 | `define JBI_SCTAG_IN_SZ_LO 40 |
| 812 | `define JBI_SCTAG_IN_SZ_HI 42 |
| 813 | `define JBI_SCTAG_IN_RSV0 43 |
| 814 | `define JBI_SCTAG_IN_TAG_LO 44 |
| 815 | `define JBI_SCTAG_IN_TAG_HI 55 |
| 816 | `define JBI_SCTAG_IN_REQ_LO 56 |
| 817 | `define JBI_SCTAG_IN_REQ_HI 58 |
| 818 | `define JBI_SCTAG_IN_POISON 59 |
| 819 | `define JBI_SCTAG_IN_RSV1_LO 60 |
| 820 | `define JBI_SCTAG_IN_RSV1_HI 63 |
| 821 | |
| 822 | `define JBI_SCTAG_REQ_WRI 3'b100 |
| 823 | `define JBI_SCTAG_REQ_WR8 3'b010 |
| 824 | `define JBI_SCTAG_REQ_RDD 3'b001 |
| 825 | `define JBI_SCTAG_REQ_WRI_BIT 2 |
| 826 | `define JBI_SCTAG_REQ_WR8_BIT 1 |
| 827 | `define JBI_SCTAG_REQ_RDD_BIT 0 |
| 828 | |
| 829 | // |
| 830 | // JBI->IOB Mondo Header Format |
| 831 | // ============================ |
| 832 | // |
| 833 | `define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1 |
| 834 | `define JBI_IOB_MONDO_RSV1_LO 13 |
| 835 | `define JBI_IOB_MONDO_TRG_HI 12 // interrupt target |
| 836 | `define JBI_IOB_MONDO_TRG_LO 8 |
| 837 | `define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0 |
| 838 | `define JBI_IOB_MONDO_RSV0_LO 5 |
| 839 | `define JBI_IOB_MONDO_SRC_HI 4 // interrupt source |
| 840 | `define JBI_IOB_MONDO_SRC_LO 0 |
| 841 | |
| 842 | `define JBI_IOB_MONDO_RSV1_WIDTH 3 |
| 843 | `define JBI_IOB_MONDO_TRG_WIDTH 5 |
| 844 | `define JBI_IOB_MONDO_RSV0_WIDTH 3 |
| 845 | `define JBI_IOB_MONDO_SRC_WIDTH 5 |
| 846 | |
| 847 | // JBI->IOB Mondo Bus Width/Cycle |
| 848 | // ============================== |
| 849 | // Cycle 1 Header[15:8] |
| 850 | // Cycle 2 Header[ 7:0] |
| 851 | // Cycle 3 J_AD[127:120] |
| 852 | // Cycle 4 J_AD[119:112] |
| 853 | // ..... |
| 854 | // Cycle 18 J_AD[ 7: 0] |
| 855 | `define JBI_IOB_MONDO_BUS_WIDTH 8 |
| 856 | `define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data |
| 857 | |
| 858 | |
| 859 | |
| 860 | |
| 861 | |
| 862 | `define IQ_SIZE 8 |
| 863 | `define OQ_SIZE 12 |
| 864 | `define TAG_WIDTH 28 |
| 865 | `define TAG_WIDTH_LESS1 27 |
| 866 | `define TAG_WIDTHr 28r |
| 867 | `define TAG_WIDTHc 28c |
| 868 | `define TAG_WIDTH6 22 |
| 869 | `define TAG_WIDTH6r 22r |
| 870 | `define TAG_WIDTH6c 22c |
| 871 | |
| 872 | |
| 873 | `define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 874 | |
| 875 | // BS and SR 11/12/03 N2 Xbar Packet format change |
| 876 | |
| 877 | `define MBD_ECC_HI 105 |
| 878 | `define MBD_ECC_HI_PLUS1 106 |
| 879 | `define MBD_ECC_HI_PLUS5 110 |
| 880 | `define MBD_ECC_LO 100 |
| 881 | `define MBD_EVICT 99 |
| 882 | `define MBD_DEP 98 |
| 883 | `define MBD_TECC 97 |
| 884 | `define MBD_ENTRY_HI 96 |
| 885 | `define MBD_ENTRY_LO 93 |
| 886 | |
| 887 | `define MBD_POISON 92 |
| 888 | `define MBD_RDMA_HI 91 |
| 889 | `define MBD_RDMA_LO 90 |
| 890 | `define MBD_RQ_HI 89 |
| 891 | `define MBD_RQ_LO 85 |
| 892 | `define MBD_NC 84 |
| 893 | `define MBD_RSVD 83 |
| 894 | `define MBD_CP_HI 82 |
| 895 | `define MBD_CP_LO 80 |
| 896 | `define MBD_TH_HI 79 |
| 897 | `define MBD_TH_LO 77 |
| 898 | `define MBD_BF_HI 76 |
| 899 | `define MBD_BF_LO 74 |
| 900 | `define MBD_WY_HI 73 |
| 901 | `define MBD_WY_LO 72 |
| 902 | `define MBD_SZ_HI 71 |
| 903 | `define MBD_SZ_LO 64 |
| 904 | `define MBD_DATA_HI 63 |
| 905 | `define MBD_DATA_LO 0 |
| 906 | |
| 907 | // BS and SR 11/12/03 N2 Xbar Packet format change |
| 908 | `define L2_FBF 40 |
| 909 | `define L2_MBF 39 |
| 910 | `define L2_SNP 38 |
| 911 | `define L2_CTRUE 37 |
| 912 | `define L2_EVICT 36 |
| 913 | `define L2_DEP 35 |
| 914 | `define L2_TECC 34 |
| 915 | `define L2_ENTRY_HI 33 |
| 916 | `define L2_ENTRY_LO 29 |
| 917 | |
| 918 | `define L2_POISON 28 |
| 919 | `define L2_RDMA_HI 27 |
| 920 | `define L2_RDMA_LO 26 |
| 921 | // BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit |
| 922 | `define L2_RQTYP_HI 25 |
| 923 | `define L2_RQTYP_LO 21 |
| 924 | `define L2_NC 20 |
| 925 | `define L2_RSVD 19 |
| 926 | `define L2_CPUID_HI 18 |
| 927 | `define L2_CPUID_LO 16 |
| 928 | `define L2_TID_HI 15 |
| 929 | `define L2_TID_LO 13 |
| 930 | `define L2_BUFID_HI 12 |
| 931 | `define L2_BUFID_LO 10 |
| 932 | `define L2_L1WY_HI 9 |
| 933 | `define L2_L1WY_LO 8 |
| 934 | `define L2_SZ_HI 7 |
| 935 | `define L2_SZ_LO 0 |
| 936 | |
| 937 | |
| 938 | `define ERR_MEU 63 |
| 939 | `define ERR_MEC 62 |
| 940 | `define ERR_RW 61 |
| 941 | `define ERR_ASYNC 60 |
| 942 | `define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54] |
| 943 | `define ERR_TID_LO 54 |
| 944 | `define ERR_LDAC 53 |
| 945 | `define ERR_LDAU 52 |
| 946 | `define ERR_LDWC 51 |
| 947 | `define ERR_LDWU 50 |
| 948 | `define ERR_LDRC 49 |
| 949 | `define ERR_LDRU 48 |
| 950 | `define ERR_LDSC 47 |
| 951 | `define ERR_LDSU 46 |
| 952 | `define ERR_LTC 45 |
| 953 | `define ERR_LRU 44 |
| 954 | `define ERR_LVU 43 |
| 955 | `define ERR_DAC 42 |
| 956 | `define ERR_DAU 41 |
| 957 | `define ERR_DRC 40 |
| 958 | `define ERR_DRU 39 |
| 959 | `define ERR_DSC 38 |
| 960 | `define ERR_DSU 37 |
| 961 | `define ERR_VEC 36 |
| 962 | `define ERR_VEU 35 |
| 963 | `define ERR_LVC 34 |
| 964 | `define ERR_SYN_HI 31 |
| 965 | `define ERR_SYN_LO 0 |
| 966 | |
| 967 | |
| 968 | |
| 969 | `define ERR_MEND 51 |
| 970 | `define ERR_NDRW 50 |
| 971 | `define ERR_NDSP 49 |
| 972 | `define ERR_NDDM 48 |
| 973 | `define ERR_NDVCID_HI 45 |
| 974 | `define ERR_NDVCID_LO 40 |
| 975 | `define ERR_NDADR_HI 39 |
| 976 | `define ERR_NDADR_LO 4 |
| 977 | |
| 978 | |
| 979 | // Phase 2 : SIU Inteface and format change |
| 980 | |
| 981 | `define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 982 | `define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 983 | `define JBI_HDR_SZ4 23 |
| 984 | `define JBI_HDR_SZc 27c |
| 985 | `define JBI_HDR_SZ4c 23c |
| 986 | |
| 987 | `define JBI_ADDR_LO 0 |
| 988 | `define JBI_ADDR_HI 7 |
| 989 | `define JBI_SZ_LO 8 |
| 990 | `define JBI_SZ_HI 15 |
| 991 | // `define JBI_RSVD 16 NOt used |
| 992 | `define JBI_CTAG_LO 16 |
| 993 | `define JBI_CTAG_HI 23 |
| 994 | `define JBI_RQ_RD 24 |
| 995 | `define JBI_RQ_WR8 25 |
| 996 | `define JBI_RQ_WR64 26 |
| 997 | `define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27 |
| 998 | `define JBI_OPES_HI 30 |
| 999 | `define JBI_RQ_POISON 31 |
| 1000 | `define JBI_ENTRY_LO 32 |
| 1001 | `define JBI_ENTRY_HI 33 |
| 1002 | |
| 1003 | // Phase 2 : SIU Inteface and format change |
| 1004 | // BS and SR 11/12/03 N2 Xbar Packet format change : |
| 1005 | `define JBINST_SZ_LO 0 |
| 1006 | `define JBINST_SZ_HI 7 |
| 1007 | // `define JBINST_RSVD 8 NOT used |
| 1008 | `define JBINST_CTAG_LO 8 |
| 1009 | `define JBINST_CTAG_HI 15 |
| 1010 | `define JBINST_RQ_RD 16 |
| 1011 | `define JBINST_RQ_WR8 17 |
| 1012 | `define JBINST_RQ_WR64 18 |
| 1013 | `define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19 |
| 1014 | `define JBINST_OPES_HI 22 |
| 1015 | `define JBINST_ENTRY_LO 23 |
| 1016 | `define JBINST_ENTRY_HI 24 |
| 1017 | `define JBINST_POISON 25 |
| 1018 | |
| 1019 | |
| 1020 | `define ST_REQ_ST 1 |
| 1021 | `define LD_REQ_ST 2 |
| 1022 | `define IDLE 0 |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | module l2t_oqu_ctl ( |
| 1028 | tcu_pce_ov, |
| 1029 | tcu_aclk, |
| 1030 | tcu_bclk, |
| 1031 | tcu_scan_en, |
| 1032 | arbdec_arbdp_cpuid_c5, |
| 1033 | arbdec_arbdp_int_bcast_c5, |
| 1034 | arb_decdp_strld_inst_c6, |
| 1035 | arb_decdp_atm_inst_c6, |
| 1036 | arb_decdp_pf_inst_c5, |
| 1037 | arb_evict_c5, |
| 1038 | arb_cpuid_c5, |
| 1039 | arb_oqu_swap_cas2_req_c2, |
| 1040 | dirvec_dirdp_req_vec_c6, |
| 1041 | tag_imiss_hit_c5, |
| 1042 | tag_ld_hit_c5, |
| 1043 | tag_nonmem_comp_c6, |
| 1044 | tag_st_ack_c5, |
| 1045 | tag_strst_ack_c5, |
| 1046 | tag_uerr_ack_c5, |
| 1047 | tag_cerr_ack_c5, |
| 1048 | tag_int_ack_c5, |
| 1049 | tag_st_req_c5, |
| 1050 | arb_decdp_mmuld_inst_c6, |
| 1051 | tag_inval_req_c5, |
| 1052 | tag_fwd_req_ret_c5, |
| 1053 | tag_sel_rdma_inval_vec_c5, |
| 1054 | tag_rdma_wr_comp_c4, |
| 1055 | tag_store_inst_c5, |
| 1056 | tag_fwd_req_ld_c6, |
| 1057 | tag_rmo_st_ack_c5, |
| 1058 | tag_inst_mb_c5, |
| 1059 | tag_hit_c5, |
| 1060 | arb_inst_l2data_vld_c6, |
| 1061 | arb_inst_l2tag_vld_c6, |
| 1062 | arb_inst_l2vuad_vld_c6, |
| 1063 | arb_csr_rd_en_c7, |
| 1064 | lkup_bank_ena_dcd_c4, |
| 1065 | lkup_bank_ena_icd_c4, |
| 1066 | cpx_l2t_grant_cx, |
| 1067 | wmr_l, |
| 1068 | scan_in, |
| 1069 | l2clk, |
| 1070 | scan_out, |
| 1071 | l2t_cpx_req_cq, |
| 1072 | l2t_cpx_atom_cq, |
| 1073 | oqu_diag_acc_c8, |
| 1074 | oqu_rqtyp_rtn_c7, |
| 1075 | oqu_cerr_ack_c7, |
| 1076 | oqu_uerr_ack_c7, |
| 1077 | oqu_str_ld_hit_c7, |
| 1078 | oqu_fwd_req_ret_c7, |
| 1079 | oqu_atm_inst_ack_c7, |
| 1080 | oqu_strst_ack_c7, |
| 1081 | oqu_int_ack_c7, |
| 1082 | oqu_imiss_hit_c8, |
| 1083 | oqu_pf_ack_c7, |
| 1084 | oqu_rmo_st_c7, |
| 1085 | oqu_l2_miss_c7, |
| 1086 | oqu_mux1_sel_data_c7, |
| 1087 | oqu_mux_csr_sel_c7, |
| 1088 | oqu_sel_inval_c7, |
| 1089 | oqu_out_mux1_sel_c7, |
| 1090 | oqu_out_mux2_sel_c7, |
| 1091 | oqu_sel_array_out_l, |
| 1092 | oqu_sel_mux1_c6, |
| 1093 | oqu_sel_mux2_c6, |
| 1094 | oqu_sel_mux3_c6, |
| 1095 | oqu_mux_vec_sel_c6, |
| 1096 | oqu_oqarray_wr_en, |
| 1097 | oqu_oqarray_rd_en, |
| 1098 | oqu_oqarray_wr_ptr, |
| 1099 | oqu_oqarray_rd_ptr, |
| 1100 | oqu_arb_full_px2, |
| 1101 | oqu_st_complete_c7, |
| 1102 | sel_st_ack_c7, |
| 1103 | oqu_mmu_ld_hit_c7, |
| 1104 | misbuf_vuad_ce_err_c6, |
| 1105 | l2t_mb0_run, |
| 1106 | l2t_mb0_oqarray_rd_en, |
| 1107 | l2t_mb0_oqarray_wr_en, |
| 1108 | l2t_mb0_addr); |
| 1109 | wire pce_ov; |
| 1110 | wire stop; |
| 1111 | wire siclk; |
| 1112 | wire soclk; |
| 1113 | wire se; |
| 1114 | wire l1clk; |
| 1115 | wire spares_scanin; |
| 1116 | wire spares_scanout; |
| 1117 | wire reset_flop_scanin; |
| 1118 | wire reset_flop_scanout; |
| 1119 | wire ff_int_bcast_c52_scanin; |
| 1120 | wire ff_int_bcast_c52_scanout; |
| 1121 | wire int_bcast_c52; |
| 1122 | wire ff_int_bcast_c6_scanin; |
| 1123 | wire ff_int_bcast_c6_scanout; |
| 1124 | wire ff_dec_cpu_c52_scanin; |
| 1125 | wire ff_dec_cpu_c52_scanout; |
| 1126 | wire [7:0] dec_cpu_c52; |
| 1127 | wire ff_dec_cpu_c6_scanin; |
| 1128 | wire ff_dec_cpu_c6_scanout; |
| 1129 | wire ff_dec_cpu_c7_scanin; |
| 1130 | wire ff_dec_cpu_c7_scanout; |
| 1131 | wire ff_sel_dec_vec_c7_scanin; |
| 1132 | wire ff_sel_dec_vec_c7_scanout; |
| 1133 | wire ff_diag_acc_c8_scanin; |
| 1134 | wire ff_diag_acc_c8_scanout; |
| 1135 | wire ff_sel_stinv_req_c52_scanin; |
| 1136 | wire ff_sel_stinv_req_c52_scanout; |
| 1137 | wire sel_stinv_req_c52; |
| 1138 | wire ff_sel_stinv_req_c6_scanin; |
| 1139 | wire ff_sel_stinv_req_c6_scanout; |
| 1140 | wire ff_sel_inv_vec_c52_scanin; |
| 1141 | wire ff_sel_inv_vec_c52_scanout; |
| 1142 | wire sel_inv_vec_c52; |
| 1143 | wire ff_sel_inv_vec_c6_scanin; |
| 1144 | wire ff_sel_inv_vec_c6_scanout; |
| 1145 | wire arb_oqu_swap_cas2_req_c5; |
| 1146 | wire ff_sel_dec_vec_c52_scanin; |
| 1147 | wire ff_sel_dec_vec_c52_scanout; |
| 1148 | wire sel_dec_vec_c52; |
| 1149 | wire ff_sel_dec_vec_c5_d1_scanin; |
| 1150 | wire ff_sel_dec_vec_c5_d1_scanout; |
| 1151 | wire ff_req_out_c7_scanin; |
| 1152 | wire ff_req_out_c7_scanout; |
| 1153 | wire ff_imiss1_out_c52_scanin; |
| 1154 | wire ff_imiss1_out_c52_scanout; |
| 1155 | wire imiss1_out_c52; |
| 1156 | wire ff_imiss1_out_c6_scanin; |
| 1157 | wire ff_imiss1_out_c6_scanout; |
| 1158 | wire ff_imiss1_out_c7_scanin; |
| 1159 | wire ff_imiss1_out_c7_scanout; |
| 1160 | wire ff_imiss1_out_c8_scanin; |
| 1161 | wire ff_imiss1_out_c8_scanout; |
| 1162 | wire ff_imiss2_req_vec_c7_scanin; |
| 1163 | wire ff_imiss2_req_vec_c7_scanout; |
| 1164 | wire ff_c6_req_vld_scanin; |
| 1165 | wire ff_c6_req_vld_scanout; |
| 1166 | wire ff_sel_c7_req_d1_scanin; |
| 1167 | wire ff_sel_c7_req_d1_scanout; |
| 1168 | wire misbuf_vuad_ce_err_c7; |
| 1169 | wire imiss1_out_gated_vuad_c6; |
| 1170 | wire imiss1_out_gated_vuad_c7; |
| 1171 | wire ff_rdma_inv_c7_scanin; |
| 1172 | wire ff_rdma_inv_c7_scanout; |
| 1173 | wire ff_xbar_req_c7_scanin; |
| 1174 | wire ff_xbar_req_c7_scanout; |
| 1175 | wire ff_imiss1_to_xbarq_c7_scanin; |
| 1176 | wire ff_imiss1_to_xbarq_c7_scanout; |
| 1177 | wire ff_rdma_to_xbarq_c7_scanin; |
| 1178 | wire ff_rdma_to_xbarq_c7_scanout; |
| 1179 | wire ff_imiss2_to_xbarq_c7_scanin; |
| 1180 | wire ff_imiss2_to_xbarq_c7_scanout; |
| 1181 | wire ff_bcast_req_c6_scanin; |
| 1182 | wire ff_bcast_req_c6_scanout; |
| 1183 | wire ff_bcast_to_xbar_c7_scanin; |
| 1184 | wire ff_bcast_to_xbar_c7_scanout; |
| 1185 | wire allow_req_c6_qual; |
| 1186 | wire ff_allow_req_c7_scanin; |
| 1187 | wire ff_allow_req_c7_scanout; |
| 1188 | wire [7:0] l2t_cpx_req_cq_c6; |
| 1189 | wire l2t_cpx_atom_cq_c6; |
| 1190 | wire ff_l2t_cpx_req_cq_c7_scanin; |
| 1191 | wire ff_l2t_cpx_req_cq_c7_scanout; |
| 1192 | wire ff_l2t_cpx_atom_cq_c7_scanin; |
| 1193 | wire ff_l2t_cpx_atom_cq_c7_scanout; |
| 1194 | wire ff_l2t_cpx_req_cq_c7_dup_scanin; |
| 1195 | wire ff_l2t_cpx_req_cq_c7_dup_scanout; |
| 1196 | wire [7:0] l2t_cpx_req_cq_dup; |
| 1197 | wire ff_fwd_req_ret_c52_scanin; |
| 1198 | wire ff_fwd_req_ret_c52_scanout; |
| 1199 | wire fwd_req_ret_c52; |
| 1200 | wire ff_fwd_req_ret_c6_scanin; |
| 1201 | wire ff_fwd_req_ret_c6_scanout; |
| 1202 | wire ff_fwd_req_ret_c7_scanin; |
| 1203 | wire ff_fwd_req_ret_c7_scanout; |
| 1204 | wire ff_int_ack_c52_scanin; |
| 1205 | wire ff_int_ack_c52_scanout; |
| 1206 | wire int_ack_c52; |
| 1207 | wire ff_int_ack_c6_scanin; |
| 1208 | wire ff_int_ack_c6_scanout; |
| 1209 | wire ff_int_ack_c7_scanin; |
| 1210 | wire ff_int_ack_c7_scanout; |
| 1211 | wire ff_ld_hit_c52_scanin; |
| 1212 | wire ff_ld_hit_c52_scanout; |
| 1213 | wire ld_hit_c52; |
| 1214 | wire ff_ld_hit_c6_scanin; |
| 1215 | wire ff_ld_hit_c6_scanout; |
| 1216 | wire ff_ld_hit_c7_scanin; |
| 1217 | wire ff_ld_hit_c7_scanout; |
| 1218 | wire ff_st_req_c52_scanin; |
| 1219 | wire ff_st_req_c52_scanout; |
| 1220 | wire st_req_c52; |
| 1221 | wire ff_st_req_c6_scanin; |
| 1222 | wire ff_st_req_c6_scanout; |
| 1223 | wire ff_st_req_c7_scanin; |
| 1224 | wire ff_st_req_c7_scanout; |
| 1225 | wire ff_inval_req_c52_scanin; |
| 1226 | wire ff_inval_req_c52_scanout; |
| 1227 | wire inval_req_c52; |
| 1228 | wire ff_inval_req_c6_scanin; |
| 1229 | wire ff_inval_req_c6_scanout; |
| 1230 | wire inval_req_c6; |
| 1231 | wire ff_inval_req_c7_scanin; |
| 1232 | wire ff_inval_req_c7_scanout; |
| 1233 | wire inval_req_c7; |
| 1234 | wire ff_strst_ack_c52_scanin; |
| 1235 | wire ff_strst_ack_c52_scanout; |
| 1236 | wire strst_ack_c52; |
| 1237 | wire ff_strst_ack_c6_scanin; |
| 1238 | wire ff_strst_ack_c6_scanout; |
| 1239 | wire ff_strst_ack_c7_scanin; |
| 1240 | wire ff_strst_ack_c7_scanout; |
| 1241 | wire ff_rmo_st_c52_scanin; |
| 1242 | wire ff_rmo_st_c52_scanout; |
| 1243 | wire rmo_st_c52; |
| 1244 | wire ff_rmo_st_c6_scanin; |
| 1245 | wire ff_rmo_st_c6_scanout; |
| 1246 | wire ff_rmo_st_c7_scanin; |
| 1247 | wire ff_rmo_st_c7_scanout; |
| 1248 | wire ff_sel_inv_vec_c7_scanin; |
| 1249 | wire ff_sel_inv_vec_c7_scanout; |
| 1250 | wire ff_uerr_ack_c52_scanin; |
| 1251 | wire ff_uerr_ack_c52_scanout; |
| 1252 | wire uerr_ack_c52; |
| 1253 | wire ff_uerr_ack_c6_scanin; |
| 1254 | wire ff_uerr_ack_c6_scanout; |
| 1255 | wire ff_uerr_ack_c7_scanin; |
| 1256 | wire ff_uerr_ack_c7_scanout; |
| 1257 | wire ff_st_ack_c52_scanin; |
| 1258 | wire ff_st_ack_c52_scanout; |
| 1259 | wire st_ack_c52; |
| 1260 | wire ff_st_ack_c6_scanin; |
| 1261 | wire ff_st_ack_c6_scanout; |
| 1262 | wire ff_st_ack_c7_scanin; |
| 1263 | wire ff_st_ack_c7_scanout; |
| 1264 | wire ff_cerr_ack_c52_scanin; |
| 1265 | wire ff_cerr_ack_c52_scanout; |
| 1266 | wire cerr_ack_c52; |
| 1267 | wire ff_cerr_ack_c6_scanin; |
| 1268 | wire ff_cerr_ack_c6_scanout; |
| 1269 | wire ff_cerr_ack_c7_scanin; |
| 1270 | wire ff_cerr_ack_c7_scanout; |
| 1271 | wire ff_strld_inst_c7_scanin; |
| 1272 | wire ff_strld_inst_c7_scanout; |
| 1273 | wire ff_mmuld_inst_c7_scanin; |
| 1274 | wire ff_mmuld_inst_c7_scanout; |
| 1275 | wire ff_atm_inst_c7_scanin; |
| 1276 | wire ff_atm_inst_c7_scanout; |
| 1277 | wire ff_l2_miss_c52_scanin; |
| 1278 | wire ff_l2_miss_c52_scanout; |
| 1279 | wire l2_miss_c52; |
| 1280 | wire ff_l2_miss_c6_scanin; |
| 1281 | wire ff_l2_miss_c6_scanout; |
| 1282 | wire ff_l2_miss_c7_scanin; |
| 1283 | wire ff_l2_miss_c7_scanout; |
| 1284 | wire ff_pf_inst_c52_scanin; |
| 1285 | wire ff_pf_inst_c52_scanout; |
| 1286 | wire pf_inst_c52; |
| 1287 | wire ff_pf_inst_c6_scanin; |
| 1288 | wire ff_pf_inst_c6_scanout; |
| 1289 | wire ff_pf_inst_c7_scanin; |
| 1290 | wire ff_pf_inst_c7_scanout; |
| 1291 | wire arb_oqu_swap_cas2_req_c3; |
| 1292 | wire arb_oqu_swap_cas2_req_c4; |
| 1293 | wire arb_oqu_swap_cas2_req_c52; |
| 1294 | wire arb_oqu_swap_cas2_req_c6; |
| 1295 | wire ff_arb_oqu_swap_cas2_req_scanin; |
| 1296 | wire ff_arb_oqu_swap_cas2_req_scanout; |
| 1297 | wire arb_oqu_swap_cas2_req_c7; |
| 1298 | wire sel_inval_ack_c7; |
| 1299 | wire sel_st_ack_true_c7; |
| 1300 | wire ff_inc_wr_ptr_d1_scanin; |
| 1301 | wire ff_inc_wr_ptr_d1_scanout; |
| 1302 | wire ff_inc_wr_ptr_d1_1_scanin; |
| 1303 | wire ff_inc_wr_ptr_d1_1_scanout; |
| 1304 | wire ff_inc_wr_ptr_d1_2_scanin; |
| 1305 | wire ff_inc_wr_ptr_d1_2_scanout; |
| 1306 | wire ff_l2t_mb0_run_r1_scanin; |
| 1307 | wire ff_l2t_mb0_run_r1_scanout; |
| 1308 | wire l2t_mb0_run_r1; |
| 1309 | wire ff_enc_wr_ptr_d1_scanin; |
| 1310 | wire ff_enc_wr_ptr_d1_scanout; |
| 1311 | wire ff_wr_ptr15to1_d1_scanin; |
| 1312 | wire ff_wr_ptr15to1_d1_scanout; |
| 1313 | wire ff_wr_ptr0_d1_scanin; |
| 1314 | wire ff_wr_ptr0_d1_scanout; |
| 1315 | wire ff_inc_rd_ptr_d1_scanin; |
| 1316 | wire ff_inc_rd_ptr_d1_scanout; |
| 1317 | wire ff_inc_rd_ptr_d1_1_scanin; |
| 1318 | wire ff_inc_rd_ptr_d1_1_scanout; |
| 1319 | wire ff_inc_rd_ptr_d1_2_scanin; |
| 1320 | wire ff_inc_rd_ptr_d1_2_scanout; |
| 1321 | wire ff_rd_ptr15to1_d1_scanin; |
| 1322 | wire ff_rd_ptr15to1_d1_scanout; |
| 1323 | wire ff_rd_ptr0_d1_scanin; |
| 1324 | wire ff_rd_ptr0_d1_scanout; |
| 1325 | wire ff_enc_wr_ptr_d2_scanin; |
| 1326 | wire ff_enc_wr_ptr_d2_scanout; |
| 1327 | wire ff_enc_rd_ptr_d1_scanin; |
| 1328 | wire ff_enc_rd_ptr_d1_scanout; |
| 1329 | wire ff_inc_wr_ptr_d2_scanin; |
| 1330 | wire ff_inc_wr_ptr_d2_scanout; |
| 1331 | wire ff_oq_cnt_d1_scanin; |
| 1332 | wire ff_oq_cnt_d1_scanout; |
| 1333 | wire ff_oq_cnt_plus1_d1_scanin; |
| 1334 | wire ff_oq_cnt_plus1_d1_scanout; |
| 1335 | wire ff_oq_cnt_minus1_d1_scanin; |
| 1336 | wire ff_oq_cnt_minus1_d1_scanout; |
| 1337 | wire ff_oq_count_15_d1_scanin; |
| 1338 | wire ff_oq_count_15_d1_scanout; |
| 1339 | wire ff_oq_count_16_d1_scanin; |
| 1340 | wire ff_oq_count_16_d1_scanout; |
| 1341 | wire ff_oqu_arb_full_px2_scanin; |
| 1342 | wire ff_oqu_arb_full_px2_scanout; |
| 1343 | wire ff_oq_count_nonzero_d1_scanin; |
| 1344 | wire ff_oq_count_nonzero_d1_scanout; |
| 1345 | wire ff_old_req_vld_d1_scanin; |
| 1346 | wire ff_old_req_vld_d1_scanout; |
| 1347 | wire ff_oq0_out_scanin; |
| 1348 | wire ff_oq0_out_scanout; |
| 1349 | wire ff_oq1_out_scanin; |
| 1350 | wire ff_oq1_out_scanout; |
| 1351 | wire ff_oq2_out_scanin; |
| 1352 | wire ff_oq2_out_scanout; |
| 1353 | wire ff_oq3_out_scanin; |
| 1354 | wire ff_oq3_out_scanout; |
| 1355 | wire ff_oq4_out_scanin; |
| 1356 | wire ff_oq4_out_scanout; |
| 1357 | wire ff_oq5_out_scanin; |
| 1358 | wire ff_oq5_out_scanout; |
| 1359 | wire ff_oq6_out_scanin; |
| 1360 | wire ff_oq6_out_scanout; |
| 1361 | wire ff_oq7_out_scanin; |
| 1362 | wire ff_oq7_out_scanout; |
| 1363 | wire ff_oq8_out_scanin; |
| 1364 | wire ff_oq8_out_scanout; |
| 1365 | wire ff_oq9_out_scanin; |
| 1366 | wire ff_oq9_out_scanout; |
| 1367 | wire ff_oq10_out_scanin; |
| 1368 | wire ff_oq10_out_scanout; |
| 1369 | wire ff_oq11_out_scanin; |
| 1370 | wire ff_oq11_out_scanout; |
| 1371 | wire ff_oq12_out_scanin; |
| 1372 | wire ff_oq12_out_scanout; |
| 1373 | wire ff_oq13_out_scanin; |
| 1374 | wire ff_oq13_out_scanout; |
| 1375 | wire ff_oq14_out_scanin; |
| 1376 | wire ff_oq14_out_scanout; |
| 1377 | wire ff_oq15_out_scanin; |
| 1378 | wire ff_oq15_out_scanout; |
| 1379 | wire ff_xbar0_scanin; |
| 1380 | wire ff_xbar0_scanout; |
| 1381 | wire ff_xbar1_scanin; |
| 1382 | wire ff_xbar1_scanout; |
| 1383 | wire ff_xbar2_scanin; |
| 1384 | wire ff_xbar2_scanout; |
| 1385 | wire ff_xbar3_scanin; |
| 1386 | wire ff_xbar3_scanout; |
| 1387 | wire ff_xbar4_scanin; |
| 1388 | wire ff_xbar4_scanout; |
| 1389 | wire ff_xbar5_scanin; |
| 1390 | wire ff_xbar5_scanout; |
| 1391 | wire ff_xbar6_scanin; |
| 1392 | wire ff_xbar6_scanout; |
| 1393 | wire ff_xbar7_scanin; |
| 1394 | wire ff_xbar7_scanout; |
| 1395 | wire ff_rdma_wr_comp_c5_scanin; |
| 1396 | wire ff_rdma_wr_comp_c5_scanout; |
| 1397 | wire ff_rdma_wr_comp_c52_scanin; |
| 1398 | wire ff_rdma_wr_comp_c52_scanout; |
| 1399 | wire ff_rdma_req_state_0_scanin; |
| 1400 | wire ff_rdma_req_state_0_scanout; |
| 1401 | wire ff_rdma_state_scanin; |
| 1402 | wire ff_rdma_state_scanout; |
| 1403 | wire ff_oqu_st_complete_c6_scanin; |
| 1404 | wire ff_oqu_st_complete_c6_scanout; |
| 1405 | wire store_inst_c52; |
| 1406 | wire ff_store_inst_c52_scanin; |
| 1407 | wire ff_store_inst_c52_scanout; |
| 1408 | wire ff_store_inst_c6_scanin; |
| 1409 | wire ff_store_inst_c6_scanout; |
| 1410 | wire ff_store_inst_c7_scanin; |
| 1411 | wire ff_store_inst_c7_scanout; |
| 1412 | wire ff_csr_reg_rd_en_c8_scanin; |
| 1413 | wire ff_csr_reg_rd_en_c8_scanout; |
| 1414 | wire ff_sel_inval_c7_scanin; |
| 1415 | wire ff_sel_inval_c7_scanout; |
| 1416 | wire ff_fwd_req_vld_ld_c7_scanin; |
| 1417 | wire ff_fwd_req_vld_ld_c7_scanout; |
| 1418 | wire ff_diag_data_sel_c7_scanin; |
| 1419 | wire ff_diag_data_sel_c7_scanout; |
| 1420 | wire ff_diag_lddata_sel_c8_scanin; |
| 1421 | wire ff_diag_lddata_sel_c8_scanout; |
| 1422 | wire ff_diag_tag_sel_c7_scanin; |
| 1423 | wire ff_diag_tag_sel_c7_scanout; |
| 1424 | wire ff_diag_ldtag_sel_c8_scanin; |
| 1425 | wire ff_diag_ldtag_sel_c8_scanout; |
| 1426 | wire ff_diag_vuad_sel_c7_scanin; |
| 1427 | wire ff_diag_vuad_sel_c7_scanout; |
| 1428 | wire ff_diag_ldvuad_sel_c8_scanin; |
| 1429 | wire ff_diag_ldvuad_sel_c8_scanout; |
| 1430 | wire ff_diag_def_sel_c8_scanin; |
| 1431 | wire ff_diag_def_sel_c8_scanout; |
| 1432 | wire [2:0] inst_cpuid_c52; |
| 1433 | wire ff_dirvec_cpuid_c52_scanin; |
| 1434 | wire ff_dirvec_cpuid_c52_scanout; |
| 1435 | wire ff_dirvec_cpuid_c6_scanin; |
| 1436 | wire ff_dirvec_cpuid_c6_scanout; |
| 1437 | wire [2:0] cpuid_c52; |
| 1438 | wire [6:0] dec_cpuid_c52; |
| 1439 | wire ff_dec_cpuid_c6_scanin; |
| 1440 | wire ff_dec_cpuid_c6_scanout; |
| 1441 | wire ff_lkup_bank_ena_icd_c5_scanin; |
| 1442 | wire ff_lkup_bank_ena_icd_c5_scanout; |
| 1443 | wire ff_lkup_bank_ena_dcd_c5_scanin; |
| 1444 | wire ff_lkup_bank_ena_dcd_c5_scanout; |
| 1445 | wire [3:0] mux_vec_sel_c52; |
| 1446 | wire ff_mux_vec_sel_c52_scanin; |
| 1447 | wire ff_mux_vec_sel_c52_scanout; |
| 1448 | wire ff_mux_vec_sel_c6_scanin; |
| 1449 | wire ff_mux_vec_sel_c6_scanout; |
| 1450 | |
| 1451 | |
| 1452 | input tcu_pce_ov; |
| 1453 | input tcu_aclk; |
| 1454 | input tcu_bclk; |
| 1455 | input tcu_scan_en; |
| 1456 | |
| 1457 | // from arbdec |
| 1458 | input [2:0] arbdec_arbdp_cpuid_c5; // account for fwd_req cpuid |
| 1459 | input arbdec_arbdp_int_bcast_c5; |
| 1460 | input arb_decdp_strld_inst_c6; |
| 1461 | input arb_decdp_atm_inst_c6; |
| 1462 | input arb_decdp_pf_inst_c5; // NEW_PIN from arbdec |
| 1463 | |
| 1464 | // from arb. |
| 1465 | input arb_evict_c5; |
| 1466 | input [2:0] arb_cpuid_c5; |
| 1467 | // BS,SR 12/07/04 : taking out arb_swap_cas2_req_c2 to l2t_oqu_ctl.sv to disable ERROR |
| 1468 | // Indication packet on a CE,UE, or Notdata on the store part of the swap or CAS2. |
| 1469 | // Instead , regular store ack packet will get sent. |
| 1470 | |
| 1471 | input arb_oqu_swap_cas2_req_c2; |
| 1472 | |
| 1473 | input [7:0] dirvec_dirdp_req_vec_c6; |
| 1474 | |
| 1475 | // from tag. |
| 1476 | input tag_imiss_hit_c5; |
| 1477 | input tag_ld_hit_c5; |
| 1478 | input tag_nonmem_comp_c6; |
| 1479 | input tag_st_ack_c5; |
| 1480 | input tag_strst_ack_c5; |
| 1481 | input tag_uerr_ack_c5; |
| 1482 | input tag_cerr_ack_c5; |
| 1483 | input tag_int_ack_c5; |
| 1484 | input tag_st_req_c5; |
| 1485 | input arb_decdp_mmuld_inst_c6; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1486 | input tag_inval_req_c5; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1487 | input tag_fwd_req_ret_c5; // tells oqu to send a req 2 cycles later. |
| 1488 | //input tag_fwd_req_in_c5; |
| 1489 | input tag_sel_rdma_inval_vec_c5; |
| 1490 | input tag_rdma_wr_comp_c4; |
| 1491 | input tag_store_inst_c5; |
| 1492 | input tag_fwd_req_ld_c6; |
| 1493 | input tag_rmo_st_ack_c5; // NEW_PIN from tag |
| 1494 | input tag_inst_mb_c5; // NEW_PIN from tag. |
| 1495 | input tag_hit_c5; // NEW_PIN from tag. |
| 1496 | |
| 1497 | // from arb. |
| 1498 | input arb_inst_l2data_vld_c6; |
| 1499 | input arb_inst_l2tag_vld_c6; |
| 1500 | input arb_inst_l2vuad_vld_c6; |
| 1501 | input arb_csr_rd_en_c7; |
| 1502 | |
| 1503 | input [3:0] lkup_bank_ena_dcd_c4; |
| 1504 | input [3:0] lkup_bank_ena_icd_c4; |
| 1505 | |
| 1506 | // from cpx |
| 1507 | input [7:0] cpx_l2t_grant_cx; |
| 1508 | |
| 1509 | input wmr_l; |
| 1510 | input scan_in; |
| 1511 | input l2clk; |
| 1512 | |
| 1513 | output scan_out; |
| 1514 | |
| 1515 | // cpx |
| 1516 | output [7:0] l2t_cpx_req_cq ; |
| 1517 | output l2t_cpx_atom_cq; |
| 1518 | |
| 1519 | // to oque. |
| 1520 | output oqu_diag_acc_c8; |
| 1521 | output [3:0] oqu_rqtyp_rtn_c7; |
| 1522 | output oqu_cerr_ack_c7 ; |
| 1523 | output oqu_uerr_ack_c7 ; |
| 1524 | output oqu_str_ld_hit_c7; |
| 1525 | output oqu_fwd_req_ret_c7; |
| 1526 | output oqu_atm_inst_ack_c7; |
| 1527 | output oqu_strst_ack_c7; |
| 1528 | output oqu_int_ack_c7; |
| 1529 | output oqu_imiss_hit_c8; |
| 1530 | output oqu_pf_ack_c7; // NEW_PIN to oque. |
| 1531 | output oqu_rmo_st_c7; // NEW_PIN to oque |
| 1532 | output oqu_l2_miss_c7; // NEW_PIN to oque |
| 1533 | |
| 1534 | |
| 1535 | // mux selects to oque |
| 1536 | output [3:0] oqu_mux1_sel_data_c7; |
| 1537 | output oqu_mux_csr_sel_c7; |
| 1538 | output oqu_sel_inval_c7; |
| 1539 | output [2:0] oqu_out_mux1_sel_c7; // sel for mux1 // new_pin POST_3.3 advanced to C7 |
| 1540 | output [2:0] oqu_out_mux2_sel_c7; // sel for mux2 // new_pin POST_3.3 advanced to C7 |
| 1541 | output oqu_sel_array_out_l; // NEW_PIN |
| 1542 | |
| 1543 | // outputs going to dirvec |
| 1544 | output [3:0] oqu_sel_mux1_c6; |
| 1545 | output [3:0] oqu_sel_mux2_c6; |
| 1546 | output oqu_sel_mux3_c6; |
| 1547 | output [3:0] oqu_mux_vec_sel_c6; |
| 1548 | |
| 1549 | |
| 1550 | |
| 1551 | // to oq array. |
| 1552 | output oqu_oqarray_wr_en; |
| 1553 | output oqu_oqarray_rd_en; |
| 1554 | output [3:0] oqu_oqarray_wr_ptr; |
| 1555 | output [3:0] oqu_oqarray_rd_ptr; |
| 1556 | |
| 1557 | // to arb |
| 1558 | output oqu_arb_full_px2; |
| 1559 | |
| 1560 | // to tag |
| 1561 | output oqu_st_complete_c7; |
| 1562 | |
| 1563 | output sel_st_ack_c7; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1564 | output oqu_mmu_ld_hit_c7; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1565 | |
| 1566 | // from misbuf |
| 1567 | input misbuf_vuad_ce_err_c6; // vuad ecc change |
| 1568 | |
| 1569 | // mbist |
| 1570 | |
| 1571 | input l2t_mb0_run; |
| 1572 | input l2t_mb0_oqarray_rd_en; |
| 1573 | input l2t_mb0_oqarray_wr_en; |
| 1574 | input [3:0] l2t_mb0_addr; |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | ////////////////////////////////////////////////// |
| 1580 | // L1 clk header |
| 1581 | ////////////////////////////////////////////////// |
| 1582 | assign pce_ov = tcu_pce_ov; |
| 1583 | assign stop = 1'b0; |
| 1584 | assign siclk = tcu_aclk; |
| 1585 | assign soclk = tcu_bclk; |
| 1586 | assign se = tcu_scan_en; |
| 1587 | |
| 1588 | l2t_l1clkhdr_ctl_macro clkgen ( |
| 1589 | .l2clk(l2clk), |
| 1590 | .l1en(1'b1 ), |
| 1591 | .l1clk(l1clk), |
| 1592 | .pce_ov(pce_ov), |
| 1593 | .stop(stop), |
| 1594 | .se(se)); |
| 1595 | |
| 1596 | ////////////////////////////////////////////////// |
| 1597 | |
| 1598 | ////////////////////////////////////////// |
| 1599 | // Spare gate insertion |
| 1600 | ////////////////////////////////////////// |
| 1601 | l2t_spare_ctl_macro__num_4 spares ( |
| 1602 | .scan_in(spares_scanin), |
| 1603 | .scan_out(spares_scanout), |
| 1604 | .l1clk (l1clk), |
| 1605 | .siclk(siclk), |
| 1606 | .soclk(soclk) |
| 1607 | ); |
| 1608 | ////////////////////////////////////////// |
| 1609 | |
| 1610 | |
| 1611 | wire [7:0] dec_cpu_gated_vuad_c6,dec_cpu_gated_vuad_c7,inval_vec_gated_vuad_c6; |
| 1612 | |
| 1613 | wire oqu_mmu_ld_hit_c7; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1614 | wire int_bcast_c5, int_bcast_c6; |
| 1615 | wire [7:0] dec_cpu_c5, dec_cpu_c6, dec_cpu_c7; |
| 1616 | wire sel_stinv_req_c5, sel_stinv_req_c6; |
| 1617 | wire sel_inv_vec_c5, sel_inv_vec_c6 ; |
| 1618 | wire sel_dec_vec_c5, sel_dec_vec_c5_d1; |
| 1619 | wire sel_dec_vec_c6, sel_dec_vec_c6_d1; |
| 1620 | wire [7:0] inval_vec_c6; |
| 1621 | wire [3:0] sel_req_out_c6; |
| 1622 | wire [7:0] req_out_c6, req_out_c7; |
| 1623 | wire imiss1_out_c6, imiss1_out_c7, imiss1_out_c8; |
| 1624 | wire imiss2_out_c6, imiss2_out_c7; |
| 1625 | wire [7:0] imiss2_req_vec_c6, imiss2_req_vec_c7; |
| 1626 | wire c6_req_vld, c7_req_vld; |
| 1627 | wire sel_c7_req, sel_c7_req_d1 ; |
| 1628 | wire old_req_vld_d1, oq_count_nonzero_d1; |
| 1629 | wire mux1_sel_c7_req, mux1_sel_dec_vec_c6; |
| 1630 | wire mux1_sel_def_c6, mux1_sel_dec_vec_c7; |
| 1631 | wire imiss1_to_xbar_tmp_c6; |
| 1632 | wire [7:0] imiss2_to_xbar_tmp_c6; |
| 1633 | |
| 1634 | wire mux2_sel_inv_vec_c6; |
| 1635 | wire oq_count_nonzero; |
| 1636 | wire mux3_sel_oq_req; |
| 1637 | wire imiss1_oq_or_pipe; |
| 1638 | wire sel_old_req; |
| 1639 | wire imiss1_to_xbarq_c6, imiss1_to_xbarq_c7; |
| 1640 | |
| 1641 | |
| 1642 | wire [7:0] imiss2_from_oq, imiss2_oq_or_pipe; |
| 1643 | wire [7:0] req_to_xbarq_c6, req_to_xbarq_c7; |
| 1644 | wire [7:0] imiss2_to_xbarq_c6, imiss2_to_xbarq_c7; |
| 1645 | wire [7:0] mux2_req_vec_c6, mux3_req_vec_c6; |
| 1646 | wire [7:0] mux1_req_vec_c6; |
| 1647 | |
| 1648 | wire [4:0] oq_count_p; |
| 1649 | |
| 1650 | wire [7:0] bcast_st_req_c6, bcast_inval_req_c6; |
| 1651 | wire bcast_req_c6,bcast_req_c7 ; |
| 1652 | wire bcast_req_pipe; |
| 1653 | wire bcast_req_oq_or_pipe, bcast_to_xbar_c6, bcast_to_xbar_c7; |
| 1654 | wire [7:0] bcast_req_xbarqfull_c6, req_to_que_in_xbarq_c7; |
| 1655 | wire allow_new_req_bcast, allow_old_req_bcast ; |
| 1656 | wire allow_req_c6, allow_req_c7 ; |
| 1657 | wire [7:0] que_in_xbarq_c7; |
| 1658 | wire old_req_vld ; |
| 1659 | |
| 1660 | wire [3:0] load_ret, stack_ret, imiss_err_or_int_rqtyp_c7 ; |
| 1661 | wire st_req_c6, st_req_c7, int_req_sel_c7 ; |
| 1662 | wire fwd_req_ret_c6 ; |
| 1663 | wire int_ack_c6, int_ack_c7 ; |
| 1664 | wire ld_hit_c6, ld_hit_c7 ; |
| 1665 | wire strld_inst_c7; |
| 1666 | wire mmuld_inst_c7; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1667 | wire atm_inst_c7; |
| 1668 | wire strst_ack_c6 ; |
| 1669 | wire uerr_ack_c6, uerr_ack_c7 ; |
| 1670 | wire cerr_ack_c6, cerr_ack_c7 ; |
| 1671 | wire imiss_req_sel_c7, err_req_sel_c7 ; |
| 1672 | wire sel_evict_vec_c7; |
| 1673 | wire imiss_err_or_int_sel_c7, sel_st_ack_c7, sel_ld_ret_c7; |
| 1674 | wire [3:0] rqtyp_rtn_c7; |
| 1675 | wire [3:0] rqtyp_rtn_c7_tmp; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 1676 | |
| 1677 | wire inc_wr_ptr, inc_wr_ptr_d1, inc_rd_ptr, inc_rd_ptr_d1; |
| 1678 | wire [15:0] wr_word_line, rd_word_line; |
| 1679 | wire [3:0] enc_wr_ptr, enc_rd_ptr; |
| 1680 | wire [3:0] enc_wr_ptr_d1, enc_rd_ptr_d1; |
| 1681 | wire [15:0] wr_ptr, wr_ptr_d1, wr_ptr_lsby1; |
| 1682 | wire wr_ptr0_n, wr_ptr0_n_d1 ; |
| 1683 | wire [15:0] rd_ptr, rd_ptr_d1, rd_ptr_lsby1; |
| 1684 | wire rd_ptr0_n, rd_ptr0_n_d1 ; |
| 1685 | |
| 1686 | wire sel_count_inc, sel_count_dec, sel_count_def; |
| 1687 | wire [4:0] oq_count_plus_1,oq_count_minus_1, oq_count_reset_p ; |
| 1688 | wire [4:0] oq_count_d1, oq_count_plus_1_d1, oq_count_minus_1_d1; |
| 1689 | wire oqu_full_px1; |
| 1690 | |
| 1691 | |
| 1692 | wire [11:0] oq0_out; |
| 1693 | wire [11:0] oq1_out; |
| 1694 | wire [11:0] oq2_out; |
| 1695 | wire [11:0] oq3_out; |
| 1696 | wire [11:0] oq4_out; |
| 1697 | wire [11:0] oq5_out; |
| 1698 | wire [11:0] oq6_out; |
| 1699 | wire [11:0] oq7_out; |
| 1700 | wire [11:0] oq8_out; |
| 1701 | wire [11:0] oq9_out; |
| 1702 | wire [11:0] oq10_out; |
| 1703 | wire [11:0] oq11_out; |
| 1704 | wire [11:0] oq12_out; |
| 1705 | wire [11:0] oq13_out; |
| 1706 | wire [11:0] oq14_out; |
| 1707 | wire [11:0] oq15_out; |
| 1708 | |
| 1709 | wire [7:0] oq_rd_out; |
| 1710 | wire imiss1_rd_out, imiss2_rd_out; |
| 1711 | wire oq_bcast_out; |
| 1712 | |
| 1713 | wire [1:0] xbar0_cnt, xbar0_cnt_p, xbar0_cnt_plus1, xbar0_cnt_minus1; |
| 1714 | wire [1:0] xbar1_cnt, xbar1_cnt_p, xbar1_cnt_plus1, xbar1_cnt_minus1; |
| 1715 | wire [1:0] xbar2_cnt, xbar2_cnt_p, xbar2_cnt_plus1, xbar2_cnt_minus1; |
| 1716 | wire [1:0] xbar3_cnt, xbar3_cnt_p, xbar3_cnt_plus1, xbar3_cnt_minus1; |
| 1717 | wire [1:0] xbar4_cnt, xbar4_cnt_p, xbar4_cnt_plus1, xbar4_cnt_minus1; |
| 1718 | wire [1:0] xbar5_cnt, xbar5_cnt_p, xbar5_cnt_plus1, xbar5_cnt_minus1; |
| 1719 | wire [1:0] xbar6_cnt, xbar6_cnt_p, xbar6_cnt_plus1, xbar6_cnt_minus1; |
| 1720 | wire [1:0] xbar7_cnt, xbar7_cnt_p, xbar7_cnt_plus1, xbar7_cnt_minus1; |
| 1721 | wire [7:0] xbarq_full, xbarq_cnt1; |
| 1722 | |
| 1723 | wire [7:0] inc_xbar_cnt; |
| 1724 | wire [7:0] dec_xbar_cnt; |
| 1725 | wire [7:0] nochange_xbar_cnt; |
| 1726 | wire [7:0] change_xbar_cnt; |
| 1727 | |
| 1728 | |
| 1729 | wire [15:0] oq_out_bit7,oq_out_bit6,oq_out_bit5,oq_out_bit4; |
| 1730 | wire [15:0] oq_out_bit3,oq_out_bit2,oq_out_bit1,oq_out_bit0; |
| 1731 | wire [15:0] imiss1_oq_out; |
| 1732 | wire [15:0] imiss2_oq_out; |
| 1733 | wire [15:0] bcast_oq_out ; |
| 1734 | wire [7:0] evict_inv_vec; |
| 1735 | |
| 1736 | wire [15:0] rdma_oq_out; |
| 1737 | wire oq_rdma_out; |
| 1738 | wire rdma_inv_c6, rdma_inv_c7; |
| 1739 | wire rdma_to_xbar_tmp_c6, rdma_oq_or_pipe; |
| 1740 | wire rdma_to_xbarq_c6, rdma_to_xbarq_c7 ; |
| 1741 | |
| 1742 | wire rdma_wr_comp_c5; |
| 1743 | wire rdma_wr_comp_c52; // BS 03/11/04 extra cycle for mem access |
| 1744 | wire dir_hit_c6 ; |
| 1745 | wire ack_idle_state_in_l, ack_idle_state_l ; |
| 1746 | wire oqu_st_complete_c6 ; |
| 1747 | wire [2:0] rdma_state_in, rdma_state; |
| 1748 | wire rdma_req_sent_c7; |
| 1749 | |
| 1750 | wire oqu_prev_data_c7; |
| 1751 | wire oqu_sel_oq_c7; |
| 1752 | wire oqu_sel_old_req_c7; |
| 1753 | wire oqu_sel_inval_c6; |
| 1754 | |
| 1755 | wire store_inst_c6; |
| 1756 | wire store_inst_c7; |
| 1757 | |
| 1758 | wire diag_data_sel_c7; |
| 1759 | wire diag_tag_sel_c7; |
| 1760 | wire diag_vuad_sel_c7; |
| 1761 | wire diag_lddata_sel_c7; |
| 1762 | wire diag_ldtag_sel_c7; |
| 1763 | wire diag_ldvuad_sel_c7; |
| 1764 | wire diag_lddata_sel_c8; |
| 1765 | wire diag_ldtag_sel_c8; |
| 1766 | wire diag_ldvuad_sel_c8; |
| 1767 | wire diag_def_sel_c7; |
| 1768 | wire diag_def_sel_c8; |
| 1769 | |
| 1770 | wire fwd_req_vld_ld_c7; |
| 1771 | |
| 1772 | wire oqctl_sel_inval_c7; |
| 1773 | |
| 1774 | wire csr_reg_rd_en_c8; |
| 1775 | |
| 1776 | |
| 1777 | wire sel_old_data_c7; |
| 1778 | |
| 1779 | |
| 1780 | wire [2:0] cpuid_c5; |
| 1781 | wire [2:0] inst_cpuid_c6; |
| 1782 | wire [6:0] dec_cpuid_c6 ; |
| 1783 | wire [6:0] dec_cpuid_c5; |
| 1784 | |
| 1785 | wire [3:0] lkup_bank_ena_dcd_c5; |
| 1786 | wire [3:0] lkup_bank_ena_icd_c5; |
| 1787 | |
| 1788 | wire [3:0] mux_vec_sel_c5; |
| 1789 | wire [3:0] mux_vec_sel_c6_unqual ; |
| 1790 | wire pf_inst_c6, pf_inst_c7 ; |
| 1791 | wire rmo_st_c6, rmo_st_c7 ; |
| 1792 | wire l2_miss_c5, l2_miss_c6, l2_miss_c7 ; |
| 1793 | |
| 1794 | |
| 1795 | wire [3:0] enc_wr_ptr_d2 ; |
| 1796 | wire inc_wr_ptr_d2; |
| 1797 | |
| 1798 | wire dbb_rst_l; |
| 1799 | wire inc_rd_ptr_d1_1, inc_rd_ptr_d1_2, inc_rd_ptr_d1_3; |
| 1800 | wire inc_wr_ptr_d1_1, inc_wr_ptr_d1_2; |
| 1801 | wire st_ack_c6, st_ack_c7; |
| 1802 | wire oq_count_15_p, oq_count_15_d1; |
| 1803 | wire oq_count_16_p, oq_count_16_d1; |
| 1804 | wire wr_wl_disable; |
| 1805 | |
| 1806 | /////////////////////////////////////////////////////////////////// |
| 1807 | // Reset flop |
| 1808 | /////////////////////////////////////////////////////////////////// |
| 1809 | |
| 1810 | l2t_msff_ctl_macro__width_1 reset_flop |
| 1811 | (.dout(dbb_rst_l), |
| 1812 | .scan_in(reset_flop_scanin), |
| 1813 | .scan_out(reset_flop_scanout), |
| 1814 | .l1clk(l1clk), |
| 1815 | .din(wmr_l), |
| 1816 | .siclk(siclk), |
| 1817 | .soclk(soclk) |
| 1818 | |
| 1819 | ); |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | /////////////////////////////////////////////////////////////////////////// |
| 1824 | // Request vector generation. |
| 1825 | // The CPUs need to be either invalidated or acknowledged for actions that |
| 1826 | // happen in the L2 $. Most of these actions are caused by cpu requests to |
| 1827 | // the L2. However, evictions and disrupting errors are independent of |
| 1828 | // requests coming from the CPU and form a portion of the requests going |
| 1829 | // to the CPUs |
| 1830 | // |
| 1831 | // All requests are sent to the CPUs in C7 except requests in response |
| 1832 | // to diagnostic accesses which are sent a cycle later. |
| 1833 | // |
| 1834 | // Request can be generated from an instruction in the pipe or an older |
| 1835 | // request. The request vector is generated in C6 The request vector is generated in C6. |
| 1836 | // The 4 sources of requests in the following logic are as follows: |
| 1837 | // * Request in pipe |
| 1838 | // * delayed ( 1cycle ) Request in pipe |
| 1839 | // * Request from the OQ. |
| 1840 | // * Request that was selected from the above 3 sources but |
| 1841 | // was not able to send to the xbar because of a xbar fulll condition |
| 1842 | // |
| 1843 | /////////////////////////////////////////////////////////////////////////// |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | |
| 1848 | assign int_bcast_c5 = tag_int_ack_c5 & arbdec_arbdp_int_bcast_c5 ; |
| 1849 | |
| 1850 | // BS 03/11/04 extra cycle for mem access |
| 1851 | |
| 1852 | l2t_msff_ctl_macro__width_1 ff_int_bcast_c52 |
| 1853 | (.din(int_bcast_c5), .l1clk(l1clk), |
| 1854 | .scan_in(ff_int_bcast_c52_scanin), |
| 1855 | .scan_out(ff_int_bcast_c52_scanout), |
| 1856 | .dout(int_bcast_c52), |
| 1857 | .siclk(siclk), |
| 1858 | .soclk(soclk) |
| 1859 | ); |
| 1860 | |
| 1861 | |
| 1862 | l2t_msff_ctl_macro__width_1 ff_int_bcast_c6 |
| 1863 | (.din(int_bcast_c52), .l1clk(l1clk), |
| 1864 | .scan_in(ff_int_bcast_c6_scanin), |
| 1865 | .scan_out(ff_int_bcast_c6_scanout), |
| 1866 | .dout(int_bcast_c6), |
| 1867 | .siclk(siclk), |
| 1868 | .soclk(soclk) |
| 1869 | ); |
| 1870 | |
| 1871 | |
| 1872 | /////////////// |
| 1873 | // FWD req responses are now forwarded to the |
| 1874 | // cpu that made the request. |
| 1875 | ////////// |
| 1876 | // |
| 1877 | //mux_ctl_macro mux_cpuid_c5 (width=3,ports=2,mux=aonpe) |
| 1878 | // (.dout(cpu_c5[2:0]), |
| 1879 | // .din0(arbdec_arbdp_cpuid_c5[2:0]), // instr cpu id |
| 1880 | // .din1(3'b0), // fwd req response alwaya to cpu0 |
| 1881 | // .sel0(~tag_fwd_req_in_c5), // no fwd req |
| 1882 | // .sel1(tag_fwd_req_in_c5)); // fwd req |
| 1883 | ////////////// |
| 1884 | |
| 1885 | assign dec_cpu_c5[0] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd0 ) | int_bcast_c5 ; |
| 1886 | assign dec_cpu_c5[1] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd1 ) | int_bcast_c5 ; |
| 1887 | assign dec_cpu_c5[2] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd2 ) | int_bcast_c5 ; |
| 1888 | assign dec_cpu_c5[3] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd3 ) | int_bcast_c5 ; |
| 1889 | assign dec_cpu_c5[4] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd4 ) | int_bcast_c5 ; |
| 1890 | assign dec_cpu_c5[5] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd5 ) | int_bcast_c5 ; |
| 1891 | assign dec_cpu_c5[6] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd6 ) | int_bcast_c5 ; |
| 1892 | assign dec_cpu_c5[7] = ( arbdec_arbdp_cpuid_c5[2:0] == 3'd7 ) | int_bcast_c5 ; |
| 1893 | |
| 1894 | // BS 03/11/04 extra cycle for mem access |
| 1895 | |
| 1896 | l2t_msff_ctl_macro__width_8 ff_dec_cpu_c52 |
| 1897 | (.din(dec_cpu_c5[7:0]), .l1clk(l1clk), |
| 1898 | .scan_in(ff_dec_cpu_c52_scanin), |
| 1899 | .scan_out(ff_dec_cpu_c52_scanout), |
| 1900 | .dout(dec_cpu_c52[7:0]), |
| 1901 | .siclk(siclk), |
| 1902 | .soclk(soclk) |
| 1903 | ); |
| 1904 | l2t_msff_ctl_macro__width_8 ff_dec_cpu_c6 |
| 1905 | (.din(dec_cpu_c52[7:0]), .l1clk(l1clk), |
| 1906 | .scan_in(ff_dec_cpu_c6_scanin), |
| 1907 | .scan_out(ff_dec_cpu_c6_scanout), |
| 1908 | .dout(dec_cpu_c6[7:0]), |
| 1909 | .siclk(siclk), |
| 1910 | .soclk(soclk) |
| 1911 | ); |
| 1912 | l2t_msff_ctl_macro__width_8 ff_dec_cpu_c7 |
| 1913 | (.din(dec_cpu_c6[7:0]), .l1clk(l1clk), |
| 1914 | .scan_in(ff_dec_cpu_c7_scanin), |
| 1915 | .scan_out(ff_dec_cpu_c7_scanout), |
| 1916 | .dout(dec_cpu_c7[7:0]), |
| 1917 | .siclk(siclk), |
| 1918 | .soclk(soclk) |
| 1919 | ); |
| 1920 | |
| 1921 | |
| 1922 | // select the req vec for the instruction in C6 for a diagnostic |
| 1923 | // access or a CSR instruction store completion. |
| 1924 | |
| 1925 | assign sel_dec_vec_c6 = tag_nonmem_comp_c6; |
| 1926 | |
| 1927 | l2t_msff_ctl_macro__width_1 ff_sel_dec_vec_c7 |
| 1928 | (.din(sel_dec_vec_c6), .l1clk(l1clk), |
| 1929 | .scan_in(ff_sel_dec_vec_c7_scanin), |
| 1930 | .scan_out(ff_sel_dec_vec_c7_scanout), |
| 1931 | .dout(sel_dec_vec_c6_d1), |
| 1932 | .siclk(siclk), |
| 1933 | .soclk(soclk) |
| 1934 | ); |
| 1935 | |
| 1936 | l2t_msff_ctl_macro__width_1 ff_diag_acc_c8 |
| 1937 | (.din(sel_dec_vec_c6_d1), .l1clk(l1clk), |
| 1938 | .scan_in(ff_diag_acc_c8_scanin), |
| 1939 | .scan_out(ff_diag_acc_c8_scanout), |
| 1940 | .dout(oqu_diag_acc_c8), |
| 1941 | .siclk(siclk), |
| 1942 | .soclk(soclk) |
| 1943 | ); |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | assign sel_stinv_req_c5 = ( tag_st_ack_c5 |
| 1948 | | tag_strst_ack_c5 ) ; |
| 1949 | |
| 1950 | // BS 03/11/04 extra cycle for mem access |
| 1951 | |
| 1952 | l2t_msff_ctl_macro__width_1 ff_sel_stinv_req_c52 |
| 1953 | (.din(sel_stinv_req_c5), .l1clk(l1clk), |
| 1954 | .scan_in(ff_sel_stinv_req_c52_scanin), |
| 1955 | .scan_out(ff_sel_stinv_req_c52_scanout), |
| 1956 | .dout(sel_stinv_req_c52), |
| 1957 | .siclk(siclk), |
| 1958 | .soclk(soclk) |
| 1959 | ); |
| 1960 | |
| 1961 | |
| 1962 | l2t_msff_ctl_macro__width_1 ff_sel_stinv_req_c6 |
| 1963 | (.din(sel_stinv_req_c52), .l1clk(l1clk), |
| 1964 | .scan_in(ff_sel_stinv_req_c6_scanin), |
| 1965 | .scan_out(ff_sel_stinv_req_c6_scanout), |
| 1966 | .dout(sel_stinv_req_c6), |
| 1967 | .siclk(siclk), |
| 1968 | .soclk(soclk) |
| 1969 | ); |
| 1970 | |
| 1971 | assign sel_inv_vec_c5 = ( arb_evict_c5 | tag_sel_rdma_inval_vec_c5 ) ; |
| 1972 | |
| 1973 | // BS 03/11/04 extra cycle for mem access |
| 1974 | l2t_msff_ctl_macro__width_1 ff_sel_inv_vec_c52 |
| 1975 | (.din(sel_inv_vec_c5), .l1clk(l1clk), |
| 1976 | .scan_in(ff_sel_inv_vec_c52_scanin), |
| 1977 | .scan_out(ff_sel_inv_vec_c52_scanout), |
| 1978 | .dout(sel_inv_vec_c52), |
| 1979 | .siclk(siclk), |
| 1980 | .soclk(soclk) |
| 1981 | ); |
| 1982 | |
| 1983 | |
| 1984 | l2t_msff_ctl_macro__width_1 ff_sel_inv_vec_c6 |
| 1985 | (.din(sel_inv_vec_c52), .l1clk(l1clk), |
| 1986 | .scan_in(ff_sel_inv_vec_c6_scanin), |
| 1987 | .scan_out(ff_sel_inv_vec_c6_scanout), |
| 1988 | .dout(sel_inv_vec_c6), |
| 1989 | .siclk(siclk), |
| 1990 | .soclk(soclk) |
| 1991 | ); |
| 1992 | |
| 1993 | assign sel_dec_vec_c5 = ( tag_imiss_hit_c5 | |
| 1994 | tag_ld_hit_c5 | |
| 1995 | (tag_uerr_ack_c5 & ~arb_oqu_swap_cas2_req_c5) | |
| 1996 | (tag_cerr_ack_c5 & ~arb_oqu_swap_cas2_req_c5) | |
| 1997 | tag_int_ack_c5 ) ; |
| 1998 | |
| 1999 | // fix for bug 92808, l2 should |
| 2000 | // let inval happen to other sparcs if it has UE/CE in cas2 or swap |
| 2001 | // as it will send regular store ack packet for such cases |
| 2002 | // and not ERROR indication packet. |
| 2003 | |
| 2004 | // BS 03/11/04 extra cycle for mem access |
| 2005 | l2t_msff_ctl_macro__width_1 ff_sel_dec_vec_c52 |
| 2006 | (.din(sel_dec_vec_c5), .l1clk(l1clk), |
| 2007 | .scan_in(ff_sel_dec_vec_c52_scanin), |
| 2008 | .scan_out(ff_sel_dec_vec_c52_scanout), |
| 2009 | .dout(sel_dec_vec_c52), |
| 2010 | .siclk(siclk), |
| 2011 | .soclk(soclk) |
| 2012 | ); |
| 2013 | |
| 2014 | |
| 2015 | l2t_msff_ctl_macro__width_1 ff_sel_dec_vec_c5_d1 |
| 2016 | (.din(sel_dec_vec_c52), .l1clk(l1clk), |
| 2017 | .scan_in(ff_sel_dec_vec_c5_d1_scanin), |
| 2018 | .scan_out(ff_sel_dec_vec_c5_d1_scanout), |
| 2019 | .dout(sel_dec_vec_c5_d1), |
| 2020 | .siclk(siclk), |
| 2021 | .soclk(soclk) |
| 2022 | ); |
| 2023 | |
| 2024 | |
| 2025 | // invalidate/stack vector |
| 2026 | assign inval_vec_c6 = ( dirvec_dirdp_req_vec_c6 | |
| 2027 | ( dec_cpu_c6 & |
| 2028 | {8{sel_stinv_req_c6}} ) ) ; |
| 2029 | |
| 2030 | |
| 2031 | assign sel_req_out_c6[0] = sel_dec_vec_c5_d1 ; |
| 2032 | assign sel_req_out_c6[1] = sel_dec_vec_c6_d1 & ~sel_dec_vec_c5_d1 ; |
| 2033 | assign sel_req_out_c6[2] = ( sel_stinv_req_c6 | sel_inv_vec_c6 ) & ~sel_dec_vec_c5_d1 & |
| 2034 | ~sel_dec_vec_c6_d1 ; |
| 2035 | assign sel_req_out_c6[3] = ~( sel_stinv_req_c6 | |
| 2036 | sel_inv_vec_c6 | |
| 2037 | sel_dec_vec_c5_d1 | |
| 2038 | sel_dec_vec_c6_d1 ) ; |
| 2039 | |
| 2040 | |
| 2041 | // pipeline request C6 |
| 2042 | l2t_mux_ctl_macro__mux_aonpe__ports_4__width_8 mux_req_out_c6 |
| 2043 | ( .dout (req_out_c6[7:0]), |
| 2044 | .din0(dec_cpu_gated_vuad_c6[7:0]), |
| 2045 | .din1(dec_cpu_gated_vuad_c7[7:0]), |
| 2046 | .din2(inval_vec_gated_vuad_c6[7:0]), |
| 2047 | .din3(8'b0), |
| 2048 | .sel0(sel_req_out_c6[0]), |
| 2049 | .sel1(sel_req_out_c6[1]), |
| 2050 | .sel2(sel_req_out_c6[2]), |
| 2051 | .sel3(sel_req_out_c6[3])); |
| 2052 | |
| 2053 | l2t_msff_ctl_macro__width_8 ff_req_out_c7 |
| 2054 | (.din(req_out_c6[7:0]), .l1clk(l1clk), |
| 2055 | .scan_in(ff_req_out_c7_scanin), |
| 2056 | .scan_out(ff_req_out_c7_scanout), |
| 2057 | .dout(req_out_c7[7:0]), |
| 2058 | .siclk(siclk), |
| 2059 | .soclk(soclk) |
| 2060 | ); |
| 2061 | |
| 2062 | |
| 2063 | // imiss 1 request C6. |
| 2064 | |
| 2065 | l2t_msff_ctl_macro__width_1 ff_imiss1_out_c52 |
| 2066 | (.din(tag_imiss_hit_c5), .l1clk(l1clk), |
| 2067 | .scan_in(ff_imiss1_out_c52_scanin), |
| 2068 | .scan_out(ff_imiss1_out_c52_scanout), |
| 2069 | .dout(imiss1_out_c52), |
| 2070 | .siclk(siclk), |
| 2071 | .soclk(soclk) |
| 2072 | ); |
| 2073 | |
| 2074 | // BS 03/11/04 extra cycle for mem access |
| 2075 | |
| 2076 | l2t_msff_ctl_macro__width_1 ff_imiss1_out_c6 |
| 2077 | (.din(imiss1_out_c52), .l1clk(l1clk), |
| 2078 | .scan_in(ff_imiss1_out_c6_scanin), |
| 2079 | .scan_out(ff_imiss1_out_c6_scanout), |
| 2080 | .dout(imiss1_out_c6), |
| 2081 | .siclk(siclk), |
| 2082 | .soclk(soclk) |
| 2083 | ); |
| 2084 | |
| 2085 | |
| 2086 | l2t_msff_ctl_macro__width_1 ff_imiss1_out_c7 |
| 2087 | (.din(imiss1_out_c6), .l1clk(l1clk), |
| 2088 | .scan_in(ff_imiss1_out_c7_scanin), |
| 2089 | .scan_out(ff_imiss1_out_c7_scanout), |
| 2090 | .dout(imiss1_out_c7), |
| 2091 | .siclk(siclk), |
| 2092 | .soclk(soclk) |
| 2093 | ); |
| 2094 | |
| 2095 | l2t_msff_ctl_macro__width_1 ff_imiss1_out_c8 |
| 2096 | (.din(imiss1_out_c7), .l1clk(l1clk), |
| 2097 | .scan_in(ff_imiss1_out_c8_scanin), |
| 2098 | .scan_out(ff_imiss1_out_c8_scanout), |
| 2099 | .dout(imiss1_out_c8), |
| 2100 | .siclk(siclk), |
| 2101 | .soclk(soclk) |
| 2102 | ); |
| 2103 | |
| 2104 | assign oqu_imiss_hit_c8 = imiss1_out_c8 ; |
| 2105 | |
| 2106 | assign imiss2_out_c6 = imiss1_out_c7; |
| 2107 | assign imiss2_out_c7 = imiss1_out_c8; |
| 2108 | |
| 2109 | assign imiss2_req_vec_c6 = {8{imiss2_out_c6}} & req_out_c7 ; |
| 2110 | |
| 2111 | l2t_msff_ctl_macro__width_8 ff_imiss2_req_vec_c7 |
| 2112 | (.din(imiss2_req_vec_c6[7:0]), .l1clk(l1clk), |
| 2113 | .scan_in(ff_imiss2_req_vec_c7_scanin), |
| 2114 | .scan_out(ff_imiss2_req_vec_c7_scanout), |
| 2115 | .dout(imiss2_req_vec_c7[7:0]), |
| 2116 | .siclk(siclk), |
| 2117 | .soclk(soclk) |
| 2118 | ); |
| 2119 | |
| 2120 | |
| 2121 | ////////////////////// |
| 2122 | // A request in the pipe is valid under the following conditions. |
| 2123 | // -dir inval vec is non-zero for an eviction |
| 2124 | // -an imiss 2nd packet is in C7 |
| 2125 | // -all conditions that cause assertion of sel_dec_vec_c5_d1 |
| 2126 | // -all conditions that cause the assertion of sel_dec_vec_c6_d1 |
| 2127 | // |
| 2128 | // A delayed pipe( by 1 cycle ) request is selected |
| 2129 | // over an incomping pipe request in Cycle T |
| 2130 | // if the pipe request is cycle T-1 was overruled due |
| 2131 | // to higher priority requests. |
| 2132 | ////////////////////// |
| 2133 | |
| 2134 | assign evict_inv_vec = {8{sel_inv_vec_c6}} & dirvec_dirdp_req_vec_c6 ; |
| 2135 | |
| 2136 | assign c6_req_vld = |( evict_inv_vec | imiss2_req_vec_c6 ) | |
| 2137 | sel_dec_vec_c5_d1 | |
| 2138 | sel_stinv_req_c6 | |
| 2139 | sel_dec_vec_c6_d1 ; |
| 2140 | |
| 2141 | l2t_msff_ctl_macro__width_1 ff_c6_req_vld |
| 2142 | (.din(c6_req_vld), .l1clk(l1clk), |
| 2143 | .scan_in(ff_c6_req_vld_scanin), |
| 2144 | .scan_out(ff_c6_req_vld_scanout), |
| 2145 | .dout(c7_req_vld), |
| 2146 | .siclk(siclk), |
| 2147 | .soclk(soclk) |
| 2148 | ); |
| 2149 | |
| 2150 | assign sel_c7_req = c7_req_vld & ( sel_c7_req_d1 |// selected delayed pipe req |
| 2151 | old_req_vld_d1 | // selected existing req to xbar |
| 2152 | oq_count_nonzero_d1) ; // selected from OQ. |
| 2153 | |
| 2154 | l2t_msff_ctl_macro__width_1 ff_sel_c7_req_d1 |
| 2155 | (.din(sel_c7_req), .l1clk(l1clk), |
| 2156 | .scan_in(ff_sel_c7_req_d1_scanin), |
| 2157 | .scan_out(ff_sel_c7_req_d1_scanout), |
| 2158 | .dout(sel_c7_req_d1), |
| 2159 | .siclk(siclk), |
| 2160 | .soclk(soclk) |
| 2161 | ); |
| 2162 | |
| 2163 | |
| 2164 | |
| 2165 | |
| 2166 | ////////////////////////// |
| 2167 | // request Mux1. |
| 2168 | // Select between the following |
| 2169 | // request sources - |
| 2170 | // - delayed pipe req |
| 2171 | // - c6 pipe req |
| 2172 | // - c7 pipe req |
| 2173 | // - default. |
| 2174 | // |
| 2175 | // A delayed pipe request has the |
| 2176 | // highest priority. |
| 2177 | ////////////////////////// |
| 2178 | assign mux1_sel_c7_req = sel_c7_req ; |
| 2179 | |
| 2180 | assign mux1_sel_dec_vec_c6 = sel_dec_vec_c5_d1 & ~sel_c7_req; |
| 2181 | assign mux1_sel_dec_vec_c7 = sel_dec_vec_c6_d1 & |
| 2182 | ~sel_dec_vec_c5_d1 & |
| 2183 | ~sel_c7_req ; |
| 2184 | |
| 2185 | assign mux1_sel_def_c6 = ~( sel_dec_vec_c5_d1 | |
| 2186 | sel_dec_vec_c6_d1 ) & |
| 2187 | ~sel_c7_req ; |
| 2188 | |
| 2189 | assign dec_cpu_gated_vuad_c6 = dec_cpu_c6 & {8{~misbuf_vuad_ce_err_c6}}; |
| 2190 | assign dec_cpu_gated_vuad_c7 = dec_cpu_c7 & {8{~misbuf_vuad_ce_err_c7}}; |
| 2191 | |
| 2192 | |
| 2193 | l2t_mux_ctl_macro__mux_aonpe__ports_4__width_8 mux_mux1_req_vec_c6 |
| 2194 | ( .dout (mux1_req_vec_c6[7:0]), |
| 2195 | .din0(req_out_c7[7:0]), |
| 2196 | .din1(dec_cpu_gated_vuad_c6[7:0]), |
| 2197 | .din2(dec_cpu_gated_vuad_c7[7:0]), |
| 2198 | .din3(8'b0), |
| 2199 | .sel0(mux1_sel_c7_req), |
| 2200 | .sel1(mux1_sel_dec_vec_c6), |
| 2201 | .sel2(mux1_sel_dec_vec_c7), |
| 2202 | .sel3(mux1_sel_def_c6)); |
| 2203 | |
| 2204 | assign imiss1_out_gated_vuad_c6 = imiss1_out_c6 & ~misbuf_vuad_ce_err_c6; |
| 2205 | assign imiss1_out_gated_vuad_c7 = imiss1_out_c7 & ~misbuf_vuad_ce_err_c7; |
| 2206 | |
| 2207 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_mux1_imiss1_c6 |
| 2208 | (.dout(imiss1_to_xbar_tmp_c6), |
| 2209 | .din0(imiss1_out_gated_vuad_c6), |
| 2210 | .din1(imiss1_out_gated_vuad_c7), |
| 2211 | .sel0(~sel_c7_req), |
| 2212 | .sel1(sel_c7_req)); |
| 2213 | |
| 2214 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_mux1_imiss2_c6 |
| 2215 | (.dout(imiss2_to_xbar_tmp_c6[7:0]), |
| 2216 | .din0(imiss2_req_vec_c6[7:0]), |
| 2217 | .din1(imiss2_req_vec_c7[7:0]), |
| 2218 | .sel0(~sel_c7_req), |
| 2219 | .sel1(sel_c7_req)); |
| 2220 | |
| 2221 | assign rdma_inv_c6 = rdma_state[`ACK_WAIT] & |( dirvec_dirdp_req_vec_c6 ); |
| 2222 | |
| 2223 | l2t_msff_ctl_macro__width_1 ff_rdma_inv_c7 |
| 2224 | (.din(rdma_inv_c6), .l1clk(l1clk), |
| 2225 | .scan_in(ff_rdma_inv_c7_scanin), |
| 2226 | .scan_out(ff_rdma_inv_c7_scanout), |
| 2227 | .dout(rdma_inv_c7), |
| 2228 | .siclk(siclk), |
| 2229 | .soclk(soclk) |
| 2230 | ); |
| 2231 | |
| 2232 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_mux1_rdma_c6 |
| 2233 | (.dout(rdma_to_xbar_tmp_c6), |
| 2234 | .din0(rdma_inv_c6), |
| 2235 | .din1(rdma_inv_c7), |
| 2236 | .sel0(~sel_c7_req), |
| 2237 | .sel1(sel_c7_req)); |
| 2238 | |
| 2239 | ////////////////////////// |
| 2240 | // request Mux2. |
| 2241 | // Select between the following |
| 2242 | // - Mux1 request |
| 2243 | // - invalidation/ack vector. |
| 2244 | ////////////////////////// |
| 2245 | |
| 2246 | |
| 2247 | |
| 2248 | assign mux2_sel_inv_vec_c6 = mux1_sel_def_c6 & |
| 2249 | ( sel_stinv_req_c6 | sel_inv_vec_c6 ); |
| 2250 | |
| 2251 | assign inval_vec_gated_vuad_c6 = inval_vec_c6 & {8{~misbuf_vuad_ce_err_c6}}; |
| 2252 | |
| 2253 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_mux2_req_c6 |
| 2254 | ( .dout (mux2_req_vec_c6[7:0]), |
| 2255 | .din0(mux1_req_vec_c6[7:0]), |
| 2256 | .din1(inval_vec_gated_vuad_c6[7:0]), |
| 2257 | .sel0(~mux2_sel_inv_vec_c6), |
| 2258 | .sel1(mux2_sel_inv_vec_c6)) ; |
| 2259 | |
| 2260 | ////////////////////////// |
| 2261 | // request Mux3. |
| 2262 | // Select between the following |
| 2263 | // - Mux2 request |
| 2264 | // - Oq request. |
| 2265 | // OQ request has priority |
| 2266 | ////////////////////////// |
| 2267 | |
| 2268 | |
| 2269 | |
| 2270 | assign mux3_sel_oq_req = dbb_rst_l & oq_count_nonzero; |
| 2271 | |
| 2272 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_mux3_req_vec_c6 |
| 2273 | ( .dout (mux3_req_vec_c6[7:0]), |
| 2274 | .din0(mux2_req_vec_c6[7:0]), |
| 2275 | .din1(oq_rd_out[7:0]), |
| 2276 | .sel0(~mux3_sel_oq_req), |
| 2277 | .sel1(mux3_sel_oq_req)); |
| 2278 | |
| 2279 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_imiss1_oq_or_pipe |
| 2280 | ( .dout (imiss1_oq_or_pipe), |
| 2281 | .din0(imiss1_to_xbar_tmp_c6), |
| 2282 | .din1(imiss1_rd_out), |
| 2283 | .sel0(~mux3_sel_oq_req), |
| 2284 | .sel1(mux3_sel_oq_req)); |
| 2285 | |
| 2286 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_rdma_oq_or_pipe |
| 2287 | ( .dout (rdma_oq_or_pipe), |
| 2288 | .din0(rdma_to_xbar_tmp_c6), |
| 2289 | .din1(oq_rdma_out), |
| 2290 | .sel0(~mux3_sel_oq_req), |
| 2291 | .sel1(mux3_sel_oq_req)); |
| 2292 | |
| 2293 | assign imiss2_from_oq = {8{imiss2_rd_out}} & req_to_xbarq_c7 ; |
| 2294 | |
| 2295 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_imiss2_oq_or_pipe |
| 2296 | ( .dout (imiss2_oq_or_pipe[7:0]), |
| 2297 | .din0(imiss2_to_xbar_tmp_c6[7:0]), |
| 2298 | .din1(imiss2_from_oq[7:0]), |
| 2299 | .sel0(~mux3_sel_oq_req), |
| 2300 | .sel1(mux3_sel_oq_req)); |
| 2301 | |
| 2302 | |
| 2303 | |
| 2304 | |
| 2305 | ////////////////////////// |
| 2306 | // A 2 to 1 mux flop to select |
| 2307 | // either the old request |
| 2308 | // or a new one. |
| 2309 | ////////////////////////// |
| 2310 | |
| 2311 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_req_to_xbar_c6 |
| 2312 | ( .dout (req_to_xbarq_c6[7:0]), |
| 2313 | .din0(req_to_xbarq_c7[7:0]), |
| 2314 | .din1(mux3_req_vec_c6[7:0]), |
| 2315 | .sel0(sel_old_req), |
| 2316 | .sel1(~sel_old_req)); |
| 2317 | |
| 2318 | l2t_msff_ctl_macro__width_8 ff_xbar_req_c7 |
| 2319 | (.din(req_to_xbarq_c6[7:0]), .l1clk(l1clk), |
| 2320 | .scan_in(ff_xbar_req_c7_scanin), |
| 2321 | .scan_out(ff_xbar_req_c7_scanout), |
| 2322 | .dout(req_to_xbarq_c7[7:0]), |
| 2323 | .siclk(siclk), |
| 2324 | .soclk(soclk) |
| 2325 | ); |
| 2326 | |
| 2327 | // use a mux flop here |
| 2328 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_imiss1_to_xbar_c6 |
| 2329 | ( .dout (imiss1_to_xbarq_c6), |
| 2330 | .din0(imiss1_to_xbarq_c7), |
| 2331 | .din1(imiss1_oq_or_pipe), |
| 2332 | .sel0(sel_old_req), |
| 2333 | .sel1(~sel_old_req)); |
| 2334 | |
| 2335 | l2t_msff_ctl_macro__width_1 ff_imiss1_to_xbarq_c7 |
| 2336 | (.din(imiss1_to_xbarq_c6), .l1clk(l1clk), |
| 2337 | .scan_in(ff_imiss1_to_xbarq_c7_scanin), |
| 2338 | .scan_out(ff_imiss1_to_xbarq_c7_scanout), |
| 2339 | .dout(imiss1_to_xbarq_c7), |
| 2340 | .siclk(siclk), |
| 2341 | .soclk(soclk) |
| 2342 | ); |
| 2343 | |
| 2344 | |
| 2345 | // use a mux flop here |
| 2346 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_rdma_to_xbar_c6 |
| 2347 | ( .dout (rdma_to_xbarq_c6), |
| 2348 | .din0(rdma_to_xbarq_c7), |
| 2349 | .din1(rdma_oq_or_pipe), |
| 2350 | .sel0(sel_old_req), |
| 2351 | .sel1(~sel_old_req)); |
| 2352 | |
| 2353 | l2t_msff_ctl_macro__width_1 ff_rdma_to_xbarq_c7 |
| 2354 | (.din(rdma_to_xbarq_c6), .l1clk(l1clk), |
| 2355 | .scan_in(ff_rdma_to_xbarq_c7_scanin), |
| 2356 | .scan_out(ff_rdma_to_xbarq_c7_scanout), |
| 2357 | .dout(rdma_to_xbarq_c7), |
| 2358 | .siclk(siclk), |
| 2359 | .soclk(soclk) |
| 2360 | ); |
| 2361 | |
| 2362 | // use a mux flop here |
| 2363 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_imiss2_to_xbar_c6 |
| 2364 | ( .dout (imiss2_to_xbarq_c6[7:0]), |
| 2365 | .din0(imiss2_to_xbarq_c7[7:0]), |
| 2366 | .din1(imiss2_oq_or_pipe[7:0]), |
| 2367 | .sel0(sel_old_req), |
| 2368 | .sel1(~sel_old_req)); |
| 2369 | |
| 2370 | l2t_msff_ctl_macro__width_8 ff_imiss2_to_xbarq_c7 |
| 2371 | (.din(imiss2_to_xbarq_c6[7:0]), .l1clk(l1clk), |
| 2372 | .scan_in(ff_imiss2_to_xbarq_c7_scanin), |
| 2373 | .scan_out(ff_imiss2_to_xbarq_c7_scanout), |
| 2374 | .dout(imiss2_to_xbarq_c7[7:0]), |
| 2375 | .siclk(siclk), |
| 2376 | .soclk(soclk) |
| 2377 | ); |
| 2378 | |
| 2379 | |
| 2380 | /////////////////////////////////////////////////////////////////////////// |
| 2381 | // For TSO it is essential that a multicast request be queued up in all |
| 2382 | // Xbar Qs at the same time. In order for this to happen, a request that |
| 2383 | // is multicast will have to wait for all destination Xbar Qs to be |
| 2384 | // available. |
| 2385 | // |
| 2386 | // The following requests are multicast requests. |
| 2387 | // - eviction requests ( that go to atleast one cpu ). |
| 2388 | // - interrupt broadcasts |
| 2389 | // - store invalidates ( that go to more than one cpu ). |
| 2390 | /////////////////////////////////////////////////////////////////////////// |
| 2391 | |
| 2392 | |
| 2393 | assign bcast_st_req_c6 = {8{sel_stinv_req_c6}} & ~dec_cpu_c6 ; |
| 2394 | assign bcast_inval_req_c6 = {8{sel_inv_vec_c6}} ; |
| 2395 | |
| 2396 | assign bcast_req_c6 = int_bcast_c6 | |
| 2397 | (|( ( bcast_st_req_c6 | bcast_inval_req_c6) |
| 2398 | & dirvec_dirdp_req_vec_c6 ) ) ; |
| 2399 | |
| 2400 | l2t_msff_ctl_macro__width_1 ff_bcast_req_c6 |
| 2401 | (.din(bcast_req_c6), .l1clk(l1clk), |
| 2402 | .scan_in(ff_bcast_req_c6_scanin), |
| 2403 | .scan_out(ff_bcast_req_c6_scanout), |
| 2404 | .dout(bcast_req_c7), |
| 2405 | .siclk(siclk), |
| 2406 | .soclk(soclk) |
| 2407 | ); |
| 2408 | |
| 2409 | |
| 2410 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_bcast_req_pipe |
| 2411 | (.dout(bcast_req_pipe), |
| 2412 | .din0(bcast_req_c7),.din1(bcast_req_c6), |
| 2413 | .sel0(sel_c7_req),.sel1(~sel_c7_req)); |
| 2414 | |
| 2415 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_bcast_req_oq_or_pipe |
| 2416 | ( .dout( bcast_req_oq_or_pipe), |
| 2417 | .din0(bcast_req_pipe),.din1(oq_bcast_out), |
| 2418 | .sel0(~oq_count_nonzero),.sel1(oq_count_nonzero)); |
| 2419 | |
| 2420 | // use a mux flop here |
| 2421 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_bcast_to_xbar_c6 |
| 2422 | ( .dout (bcast_to_xbar_c6), |
| 2423 | .din0(bcast_to_xbar_c7), .din1(bcast_req_oq_or_pipe), |
| 2424 | .sel0(sel_old_req), .sel1(~sel_old_req)); |
| 2425 | |
| 2426 | l2t_msff_ctl_macro__width_1 ff_bcast_to_xbar_c7 |
| 2427 | (.din(bcast_to_xbar_c6), .l1clk(l1clk), |
| 2428 | .scan_in(ff_bcast_to_xbar_c7_scanin), |
| 2429 | .scan_out(ff_bcast_to_xbar_c7_scanout), |
| 2430 | .dout(bcast_to_xbar_c7), |
| 2431 | .siclk(siclk), |
| 2432 | .soclk(soclk) |
| 2433 | ); |
| 2434 | |
| 2435 | |
| 2436 | //////////////////////// |
| 2437 | // logic for disallowing a request from transmitting. |
| 2438 | // |
| 2439 | // A request that is in the pipe will be gated off |
| 2440 | // if: |
| 2441 | // - xbar is full or |
| 2442 | // - xbar=1 and incrementing in that cycle. |
| 2443 | // |
| 2444 | // Request that has already made it to the output |
| 2445 | // of the request muxes will be gate off if |
| 2446 | // - xbar is full. |
| 2447 | //////////////////////// |
| 2448 | |
| 2449 | |
| 2450 | |
| 2451 | assign bcast_req_xbarqfull_c6 = ( xbarq_full |
| 2452 | | ( xbarq_cnt1 & que_in_xbarq_c7 ) ); |
| 2453 | |
| 2454 | |
| 2455 | assign allow_new_req_bcast = (&( ~mux3_req_vec_c6 | |
| 2456 | ~bcast_req_xbarqfull_c6 )) | |
| 2457 | ~bcast_req_oq_or_pipe ; |
| 2458 | |
| 2459 | assign allow_old_req_bcast = (&( ~req_to_que_in_xbarq_c7 | |
| 2460 | ~xbarq_full )) | |
| 2461 | ~bcast_to_xbar_c7 ; |
| 2462 | |
| 2463 | |
| 2464 | |
| 2465 | // use a mux flop here |
| 2466 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_allow_req_c6 |
| 2467 | ( .dout (allow_req_c6), |
| 2468 | .din0(allow_old_req_bcast), .din1(allow_new_req_bcast), |
| 2469 | .sel0(sel_old_req), .sel1(~sel_old_req)); |
| 2470 | |
| 2471 | // Bug id 98795 |
| 2472 | // when vuad ce happens the req to crossbar should be cut off |
| 2473 | // with it's associated logic. |
| 2474 | // |
| 2475 | |
| 2476 | assign allow_req_c6_qual = allow_req_c6; |
| 2477 | |
| 2478 | l2t_msff_ctl_macro__width_2 ff_allow_req_c7 |
| 2479 | (.din({allow_req_c6_qual,misbuf_vuad_ce_err_c6}), .l1clk(l1clk), |
| 2480 | .scan_in(ff_allow_req_c7_scanin), |
| 2481 | .scan_out(ff_allow_req_c7_scanout), |
| 2482 | .dout({allow_req_c7,misbuf_vuad_ce_err_c7}), |
| 2483 | .siclk(siclk), |
| 2484 | .soclk(soclk) |
| 2485 | ); |
| 2486 | |
| 2487 | assign req_to_que_in_xbarq_c7 = ( req_to_xbarq_c7 | imiss2_to_xbarq_c7) ; |
| 2488 | |
| 2489 | assign que_in_xbarq_c7 = req_to_que_in_xbarq_c7 & {8{allow_req_c7}}; |
| 2490 | |
| 2491 | assign old_req_vld = |( req_to_que_in_xbarq_c7 & xbarq_full & |
| 2492 | ~cpx_l2t_grant_cx ) | |
| 2493 | ~allow_req_c7 ; |
| 2494 | |
| 2495 | assign sel_old_req = dbb_rst_l & old_req_vld ; |
| 2496 | |
| 2497 | assign l2t_cpx_req_cq_c6[7:0] = (req_to_xbarq_c6 & {8{allow_req_c6}}); |
| 2498 | assign l2t_cpx_atom_cq_c6 = imiss1_to_xbarq_c6 ; |
| 2499 | |
| 2500 | |
| 2501 | l2t_msff_ctl_macro__dmsff_32x__width_8 ff_l2t_cpx_req_cq_c7 |
| 2502 | ( |
| 2503 | .scan_in(ff_l2t_cpx_req_cq_c7_scanin), |
| 2504 | .scan_out(ff_l2t_cpx_req_cq_c7_scanout), |
| 2505 | .dout (l2t_cpx_req_cq[7:0]), |
| 2506 | .din (l2t_cpx_req_cq_c6[7:0]), |
| 2507 | .l1clk (l1clk), |
| 2508 | .siclk(siclk), |
| 2509 | .soclk(soclk) |
| 2510 | ); |
| 2511 | |
| 2512 | l2t_msff_ctl_macro__dmsff_32x__width_1 ff_l2t_cpx_atom_cq_c7 |
| 2513 | ( |
| 2514 | .scan_in(ff_l2t_cpx_atom_cq_c7_scanin), |
| 2515 | .scan_out(ff_l2t_cpx_atom_cq_c7_scanout), |
| 2516 | .dout (l2t_cpx_atom_cq), |
| 2517 | .din (l2t_cpx_atom_cq_c6), |
| 2518 | .l1clk (l1clk), |
| 2519 | .siclk(siclk), |
| 2520 | .soclk(soclk) |
| 2521 | ); |
| 2522 | |
| 2523 | |
| 2524 | l2t_msff_ctl_macro__width_8 ff_l2t_cpx_req_cq_c7_dup |
| 2525 | ( |
| 2526 | .scan_in(ff_l2t_cpx_req_cq_c7_dup_scanin), |
| 2527 | .scan_out(ff_l2t_cpx_req_cq_c7_dup_scanout), |
| 2528 | .dout (l2t_cpx_req_cq_dup[7:0]), |
| 2529 | .din (l2t_cpx_req_cq_c6[7:0]), |
| 2530 | .l1clk (l1clk), |
| 2531 | .siclk(siclk), |
| 2532 | .soclk(soclk) |
| 2533 | ); |
| 2534 | |
| 2535 | |
| 2536 | |
| 2537 | |
| 2538 | /////////////////////////////////////////////////////////// |
| 2539 | // RQTYP and other signals sent to oque |
| 2540 | // RQTYP is generated using several stages of muxing as follows: |
| 2541 | // 1. mux between st ack and fwd reply |
| 2542 | // 2. mux between ld ret and fwd reply |
| 2543 | // 3. mux between int_ack, imiss_ret and err_ack |
| 2544 | // 4. mux between mux1, mux2 and mux3 outputs and eviction_ret. |
| 2545 | // 5. If an ack is a strm load or strm store ret, then the streaming |
| 2546 | // bit of the request type is set. |
| 2547 | // |
| 2548 | // The request type logic is performed in C7. |
| 2549 | /////////////////////////////////////////////////////////// |
| 2550 | |
| 2551 | l2t_msff_ctl_macro__width_1 ff_fwd_req_ret_c52 |
| 2552 | (.din(tag_fwd_req_ret_c5), .l1clk(l1clk), |
| 2553 | .scan_in(ff_fwd_req_ret_c52_scanin), |
| 2554 | .scan_out(ff_fwd_req_ret_c52_scanout), |
| 2555 | .dout(fwd_req_ret_c52), |
| 2556 | .siclk(siclk), |
| 2557 | .soclk(soclk) |
| 2558 | ); |
| 2559 | |
| 2560 | // BS 03/11/04 extra cycle for mem access |
| 2561 | |
| 2562 | l2t_msff_ctl_macro__width_1 ff_fwd_req_ret_c6 |
| 2563 | (.din(fwd_req_ret_c52), .l1clk(l1clk), |
| 2564 | .scan_in(ff_fwd_req_ret_c6_scanin), |
| 2565 | .scan_out(ff_fwd_req_ret_c6_scanout), |
| 2566 | .dout(fwd_req_ret_c6), |
| 2567 | .siclk(siclk), |
| 2568 | .soclk(soclk) |
| 2569 | ); |
| 2570 | |
| 2571 | |
| 2572 | l2t_msff_ctl_macro__width_1 ff_fwd_req_ret_c7 |
| 2573 | (.din(fwd_req_ret_c6), .l1clk(l1clk), |
| 2574 | .scan_in(ff_fwd_req_ret_c7_scanin), |
| 2575 | .scan_out(ff_fwd_req_ret_c7_scanout), |
| 2576 | .dout(oqu_fwd_req_ret_c7), |
| 2577 | .siclk(siclk), |
| 2578 | .soclk(soclk) |
| 2579 | ); |
| 2580 | |
| 2581 | // BS 03/11/04 extra cycle for mem access |
| 2582 | l2t_msff_ctl_macro__width_1 ff_int_ack_c52 |
| 2583 | (.din(tag_int_ack_c5), .l1clk(l1clk), |
| 2584 | .scan_in(ff_int_ack_c52_scanin), |
| 2585 | .scan_out(ff_int_ack_c52_scanout), |
| 2586 | .dout(int_ack_c52), |
| 2587 | .siclk(siclk), |
| 2588 | .soclk(soclk) |
| 2589 | ); |
| 2590 | |
| 2591 | l2t_msff_ctl_macro__width_1 ff_int_ack_c6 |
| 2592 | (.din(int_ack_c52), .l1clk(l1clk), |
| 2593 | .scan_in(ff_int_ack_c6_scanin), |
| 2594 | .scan_out(ff_int_ack_c6_scanout), |
| 2595 | .dout(int_ack_c6), |
| 2596 | .siclk(siclk), |
| 2597 | .soclk(soclk) |
| 2598 | ); |
| 2599 | |
| 2600 | l2t_msff_ctl_macro__width_1 ff_int_ack_c7 |
| 2601 | (.din(int_ack_c6), .l1clk(l1clk), |
| 2602 | .scan_in(ff_int_ack_c7_scanin), |
| 2603 | .scan_out(ff_int_ack_c7_scanout), |
| 2604 | .dout(int_ack_c7), |
| 2605 | .siclk(siclk), |
| 2606 | .soclk(soclk) |
| 2607 | ); |
| 2608 | |
| 2609 | assign oqu_int_ack_c7 = int_ack_c7; |
| 2610 | |
| 2611 | // BS 03/11/04 extra cycle for mem access |
| 2612 | |
| 2613 | l2t_msff_ctl_macro__width_1 ff_ld_hit_c52 |
| 2614 | (.din(tag_ld_hit_c5), .l1clk(l1clk), |
| 2615 | .scan_in(ff_ld_hit_c52_scanin), |
| 2616 | .scan_out(ff_ld_hit_c52_scanout), |
| 2617 | .dout(ld_hit_c52), |
| 2618 | .siclk(siclk), |
| 2619 | .soclk(soclk) |
| 2620 | ); |
| 2621 | |
| 2622 | |
| 2623 | l2t_msff_ctl_macro__width_1 ff_ld_hit_c6 |
| 2624 | (.din(ld_hit_c52), .l1clk(l1clk), |
| 2625 | .scan_in(ff_ld_hit_c6_scanin), |
| 2626 | .scan_out(ff_ld_hit_c6_scanout), |
| 2627 | .dout(ld_hit_c6), |
| 2628 | .siclk(siclk), |
| 2629 | .soclk(soclk) |
| 2630 | ); |
| 2631 | |
| 2632 | l2t_msff_ctl_macro__width_1 ff_ld_hit_c7 |
| 2633 | (.din(ld_hit_c6), .l1clk(l1clk), |
| 2634 | .scan_in(ff_ld_hit_c7_scanin), |
| 2635 | .scan_out(ff_ld_hit_c7_scanout), |
| 2636 | .dout(ld_hit_c7), |
| 2637 | .siclk(siclk), |
| 2638 | .soclk(soclk) |
| 2639 | ); |
| 2640 | |
| 2641 | // BS 03/11/04 extra cycle for mem access |
| 2642 | |
| 2643 | l2t_msff_ctl_macro__width_1 ff_st_req_c52 |
| 2644 | (.din(tag_st_req_c5), .l1clk(l1clk), |
| 2645 | .scan_in(ff_st_req_c52_scanin), |
| 2646 | .scan_out(ff_st_req_c52_scanout), |
| 2647 | .dout(st_req_c52), |
| 2648 | .siclk(siclk), |
| 2649 | .soclk(soclk) |
| 2650 | ); |
| 2651 | |
| 2652 | l2t_msff_ctl_macro__width_1 ff_st_req_c6 |
| 2653 | (.din(st_req_c52), .l1clk(l1clk), |
| 2654 | .scan_in(ff_st_req_c6_scanin), |
| 2655 | .scan_out(ff_st_req_c6_scanout), |
| 2656 | .dout(st_req_c6), |
| 2657 | .siclk(siclk), |
| 2658 | .soclk(soclk) |
| 2659 | ); |
| 2660 | |
| 2661 | l2t_msff_ctl_macro__width_1 ff_st_req_c7 |
| 2662 | (.din(st_req_c6), .l1clk(l1clk), |
| 2663 | .scan_in(ff_st_req_c7_scanin), |
| 2664 | .scan_out(ff_st_req_c7_scanout), |
| 2665 | .dout(st_req_c7), |
| 2666 | .siclk(siclk), |
| 2667 | .soclk(soclk) |
| 2668 | ); |
| 2669 | |
| 2670 | // BS and SR 11/12/03 N2 Xbar Packet format change : |
| 2671 | |
| 2672 | // BS 03/11/04 extra cycle for mem access |
| 2673 | l2t_msff_ctl_macro__width_1 ff_inval_req_c52 |
| 2674 | (.din(tag_inval_req_c5), .l1clk(l1clk), |
| 2675 | .scan_in(ff_inval_req_c52_scanin), |
| 2676 | .scan_out(ff_inval_req_c52_scanout), |
| 2677 | .dout(inval_req_c52), |
| 2678 | .siclk(siclk), |
| 2679 | .soclk(soclk) |
| 2680 | ); |
| 2681 | |
| 2682 | |
| 2683 | l2t_msff_ctl_macro__width_1 ff_inval_req_c6 |
| 2684 | (.din(inval_req_c52), .l1clk(l1clk), |
| 2685 | .scan_in(ff_inval_req_c6_scanin), |
| 2686 | .scan_out(ff_inval_req_c6_scanout), |
| 2687 | .dout(inval_req_c6), |
| 2688 | .siclk(siclk), |
| 2689 | .soclk(soclk) |
| 2690 | ); |
| 2691 | |
| 2692 | l2t_msff_ctl_macro__width_1 ff_inval_req_c7 |
| 2693 | (.din(inval_req_c6), .l1clk(l1clk), |
| 2694 | .scan_in(ff_inval_req_c7_scanin), |
| 2695 | .scan_out(ff_inval_req_c7_scanout), |
| 2696 | .dout(inval_req_c7), |
| 2697 | .siclk(siclk), |
| 2698 | .soclk(soclk) |
| 2699 | ); |
| 2700 | |
| 2701 | // BS 03/11/04 extra cycle for mem access |
| 2702 | l2t_msff_ctl_macro__width_1 ff_strst_ack_c52 |
| 2703 | (.din(tag_strst_ack_c5), .l1clk(l1clk), |
| 2704 | .scan_in(ff_strst_ack_c52_scanin), |
| 2705 | .scan_out(ff_strst_ack_c52_scanout), |
| 2706 | .dout(strst_ack_c52), |
| 2707 | .siclk(siclk), |
| 2708 | .soclk(soclk) |
| 2709 | ); |
| 2710 | |
| 2711 | l2t_msff_ctl_macro__width_1 ff_strst_ack_c6 |
| 2712 | (.din(strst_ack_c52), .l1clk(l1clk), |
| 2713 | .scan_in(ff_strst_ack_c6_scanin), |
| 2714 | .scan_out(ff_strst_ack_c6_scanout), |
| 2715 | .dout(strst_ack_c6), |
| 2716 | .siclk(siclk), |
| 2717 | .soclk(soclk) |
| 2718 | ); |
| 2719 | |
| 2720 | l2t_msff_ctl_macro__width_1 ff_strst_ack_c7 |
| 2721 | (.din(strst_ack_c6), .l1clk(l1clk), |
| 2722 | .scan_in(ff_strst_ack_c7_scanin), |
| 2723 | .scan_out(ff_strst_ack_c7_scanout), |
| 2724 | .dout(oqu_strst_ack_c7), |
| 2725 | .siclk(siclk), |
| 2726 | .soclk(soclk) |
| 2727 | ); |
| 2728 | |
| 2729 | |
| 2730 | // RMO store ACK. |
| 2731 | // BS 03/11/04 extra cycle for mem access |
| 2732 | |
| 2733 | l2t_msff_ctl_macro__width_1 ff_rmo_st_c52 |
| 2734 | (.din(tag_rmo_st_ack_c5), .l1clk(l1clk), |
| 2735 | .scan_in(ff_rmo_st_c52_scanin), |
| 2736 | .scan_out(ff_rmo_st_c52_scanout), |
| 2737 | .dout(rmo_st_c52), |
| 2738 | .siclk(siclk), |
| 2739 | .soclk(soclk) |
| 2740 | ); |
| 2741 | |
| 2742 | l2t_msff_ctl_macro__width_1 ff_rmo_st_c6 |
| 2743 | (.din(rmo_st_c52), .l1clk(l1clk), |
| 2744 | .scan_in(ff_rmo_st_c6_scanin), |
| 2745 | .scan_out(ff_rmo_st_c6_scanout), |
| 2746 | .dout(rmo_st_c6), |
| 2747 | .siclk(siclk), |
| 2748 | .soclk(soclk) |
| 2749 | ); |
| 2750 | |
| 2751 | l2t_msff_ctl_macro__width_1 ff_rmo_st_c7 |
| 2752 | (.din(rmo_st_c6), .l1clk(l1clk), |
| 2753 | .scan_in(ff_rmo_st_c7_scanin), |
| 2754 | .scan_out(ff_rmo_st_c7_scanout), |
| 2755 | .dout(rmo_st_c7), |
| 2756 | .siclk(siclk), |
| 2757 | .soclk(soclk) |
| 2758 | ); |
| 2759 | |
| 2760 | assign oqu_rmo_st_c7 = rmo_st_c7 ; |
| 2761 | |
| 2762 | |
| 2763 | |
| 2764 | l2t_msff_ctl_macro__width_1 ff_sel_inv_vec_c7 |
| 2765 | (.din(sel_inv_vec_c6), .l1clk(l1clk), |
| 2766 | .scan_in(ff_sel_inv_vec_c7_scanin), |
| 2767 | .scan_out(ff_sel_inv_vec_c7_scanout), |
| 2768 | .dout(sel_evict_vec_c7), |
| 2769 | .siclk(siclk), |
| 2770 | .soclk(soclk) |
| 2771 | ); |
| 2772 | |
| 2773 | // BS 03/11/04 extra cycle for mem access |
| 2774 | |
| 2775 | l2t_msff_ctl_macro__width_1 ff_uerr_ack_c52 |
| 2776 | (.din(tag_uerr_ack_c5), .l1clk(l1clk), |
| 2777 | .scan_in(ff_uerr_ack_c52_scanin), |
| 2778 | .scan_out(ff_uerr_ack_c52_scanout), |
| 2779 | .dout(uerr_ack_c52), |
| 2780 | .siclk(siclk), |
| 2781 | .soclk(soclk) |
| 2782 | ); |
| 2783 | |
| 2784 | |
| 2785 | l2t_msff_ctl_macro__width_1 ff_uerr_ack_c6 |
| 2786 | (.din(uerr_ack_c52), .l1clk(l1clk), |
| 2787 | .scan_in(ff_uerr_ack_c6_scanin), |
| 2788 | .scan_out(ff_uerr_ack_c6_scanout), |
| 2789 | .dout(uerr_ack_c6), |
| 2790 | .siclk(siclk), |
| 2791 | .soclk(soclk) |
| 2792 | ); |
| 2793 | |
| 2794 | l2t_msff_ctl_macro__width_1 ff_uerr_ack_c7 |
| 2795 | (.din(uerr_ack_c6), .l1clk(l1clk), |
| 2796 | .scan_in(ff_uerr_ack_c7_scanin), |
| 2797 | .scan_out(ff_uerr_ack_c7_scanout), |
| 2798 | .dout(uerr_ack_c7), |
| 2799 | .siclk(siclk), |
| 2800 | .soclk(soclk) |
| 2801 | ); |
| 2802 | |
| 2803 | |
| 2804 | assign oqu_uerr_ack_c7 = uerr_ack_c7 ; |
| 2805 | |
| 2806 | // BS 03/11/04 extra cycle for mem access |
| 2807 | l2t_msff_ctl_macro__width_1 ff_st_ack_c52 |
| 2808 | (.din(tag_st_ack_c5), .l1clk(l1clk), |
| 2809 | .scan_in(ff_st_ack_c52_scanin), |
| 2810 | .scan_out(ff_st_ack_c52_scanout), |
| 2811 | .dout(st_ack_c52), |
| 2812 | .siclk(siclk), |
| 2813 | .soclk(soclk) |
| 2814 | ); |
| 2815 | |
| 2816 | l2t_msff_ctl_macro__width_1 ff_st_ack_c6 |
| 2817 | (.din(st_ack_c52), .l1clk(l1clk), |
| 2818 | .scan_in(ff_st_ack_c6_scanin), |
| 2819 | .scan_out(ff_st_ack_c6_scanout), |
| 2820 | .dout(st_ack_c6), |
| 2821 | .siclk(siclk), |
| 2822 | .soclk(soclk) |
| 2823 | ); |
| 2824 | |
| 2825 | l2t_msff_ctl_macro__width_1 ff_st_ack_c7 |
| 2826 | (.din(st_ack_c6), .l1clk(l1clk), |
| 2827 | .scan_in(ff_st_ack_c7_scanin), |
| 2828 | .scan_out(ff_st_ack_c7_scanout), |
| 2829 | .dout(st_ack_c7), |
| 2830 | .siclk(siclk), |
| 2831 | .soclk(soclk) |
| 2832 | ); |
| 2833 | |
| 2834 | // BS 03/11/04 extra cycle for mem access |
| 2835 | |
| 2836 | l2t_msff_ctl_macro__width_1 ff_cerr_ack_c52 |
| 2837 | (.din(tag_cerr_ack_c5), .l1clk(l1clk), |
| 2838 | .scan_in(ff_cerr_ack_c52_scanin), |
| 2839 | .scan_out(ff_cerr_ack_c52_scanout), |
| 2840 | .dout(cerr_ack_c52), |
| 2841 | .siclk(siclk), |
| 2842 | .soclk(soclk) |
| 2843 | ); |
| 2844 | |
| 2845 | |
| 2846 | l2t_msff_ctl_macro__width_1 ff_cerr_ack_c6 |
| 2847 | (.din(cerr_ack_c52), .l1clk(l1clk), |
| 2848 | .scan_in(ff_cerr_ack_c6_scanin), |
| 2849 | .scan_out(ff_cerr_ack_c6_scanout), |
| 2850 | .dout(cerr_ack_c6), |
| 2851 | .siclk(siclk), |
| 2852 | .soclk(soclk) |
| 2853 | ); |
| 2854 | |
| 2855 | l2t_msff_ctl_macro__width_1 ff_cerr_ack_c7 |
| 2856 | (.din(cerr_ack_c6), .l1clk(l1clk), |
| 2857 | .scan_in(ff_cerr_ack_c7_scanin), |
| 2858 | .scan_out(ff_cerr_ack_c7_scanout), |
| 2859 | .dout(cerr_ack_c7), |
| 2860 | .siclk(siclk), |
| 2861 | .soclk(soclk) |
| 2862 | ); |
| 2863 | |
| 2864 | assign oqu_cerr_ack_c7 = cerr_ack_c7 ; |
| 2865 | |
| 2866 | l2t_msff_ctl_macro__width_1 ff_strld_inst_c7 |
| 2867 | (.din(arb_decdp_strld_inst_c6), .l1clk(l1clk), |
| 2868 | .scan_in(ff_strld_inst_c7_scanin), |
| 2869 | .scan_out(ff_strld_inst_c7_scanout), |
| 2870 | .dout(strld_inst_c7), |
| 2871 | .siclk(siclk), |
| 2872 | .soclk(soclk) |
| 2873 | ); |
| 2874 | |
| 2875 | // BS and SR 11/12/03 N2 Xbar Packet format change : |
| 2876 | l2t_msff_ctl_macro__width_1 ff_mmuld_inst_c7 |
| 2877 | (.din(arb_decdp_mmuld_inst_c6), .l1clk(l1clk), |
| 2878 | .scan_in(ff_mmuld_inst_c7_scanin), |
| 2879 | .scan_out(ff_mmuld_inst_c7_scanout), |
| 2880 | .dout(mmuld_inst_c7), |
| 2881 | .siclk(siclk), |
| 2882 | .soclk(soclk) |
| 2883 | ); |
| 2884 | |
| 2885 | |
| 2886 | |
| 2887 | l2t_msff_ctl_macro__width_1 ff_atm_inst_c7 |
| 2888 | (.din(arb_decdp_atm_inst_c6), .l1clk(l1clk), |
| 2889 | .scan_in(ff_atm_inst_c7_scanin), |
| 2890 | .scan_out(ff_atm_inst_c7_scanout), |
| 2891 | .dout(atm_inst_c7), |
| 2892 | .siclk(siclk), |
| 2893 | .soclk(soclk) |
| 2894 | ); |
| 2895 | |
| 2896 | |
| 2897 | |
| 2898 | //////////////////////////////////////////////////////// |
| 2899 | // L2 miss is reported for LDs, IMIsses(1st pckt only ) |
| 2900 | // and stores. In all these cases, a miss is reported |
| 2901 | // - if the instruction is issued from the miss Buffer |
| 2902 | // - or if a st ack is sent for an instruction missing the |
| 2903 | // L2. |
| 2904 | //////////////////////////////////////////////////////// |
| 2905 | |
| 2906 | assign l2_miss_c5 = (tag_inst_mb_c5 & |
| 2907 | ( tag_st_ack_c5 | |
| 2908 | tag_ld_hit_c5 | |
| 2909 | tag_imiss_hit_c5 )) | |
| 2910 | ( ~tag_hit_c5 & |
| 2911 | tag_st_ack_c5 ); |
| 2912 | |
| 2913 | // BS 03/11/04 extra cycle for mem access |
| 2914 | |
| 2915 | l2t_msff_ctl_macro__width_1 ff_l2_miss_c52 |
| 2916 | (.din(l2_miss_c5), .l1clk(l1clk), |
| 2917 | .scan_in(ff_l2_miss_c52_scanin), |
| 2918 | .scan_out(ff_l2_miss_c52_scanout), |
| 2919 | .dout(l2_miss_c52), |
| 2920 | .siclk(siclk), |
| 2921 | .soclk(soclk) |
| 2922 | ); |
| 2923 | |
| 2924 | |
| 2925 | l2t_msff_ctl_macro__width_1 ff_l2_miss_c6 |
| 2926 | (.din(l2_miss_c52), .l1clk(l1clk), |
| 2927 | .scan_in(ff_l2_miss_c6_scanin), |
| 2928 | .scan_out(ff_l2_miss_c6_scanout), |
| 2929 | .dout(l2_miss_c6), |
| 2930 | .siclk(siclk), |
| 2931 | .soclk(soclk) |
| 2932 | ); |
| 2933 | |
| 2934 | l2t_msff_ctl_macro__width_1 ff_l2_miss_c7 |
| 2935 | (.din(l2_miss_c6), .l1clk(l1clk), |
| 2936 | .scan_in(ff_l2_miss_c7_scanin), |
| 2937 | .scan_out(ff_l2_miss_c7_scanout), |
| 2938 | .dout(l2_miss_c7), |
| 2939 | .siclk(siclk), |
| 2940 | .soclk(soclk) |
| 2941 | ); |
| 2942 | |
| 2943 | assign oqu_l2_miss_c7 = l2_miss_c7 & ~(oqu_rqtyp_rtn_c7==4'hc); |
| 2944 | |
| 2945 | ///////////////////////////////////////// |
| 2946 | // A prefetch instruction has a "LOAD" |
| 2947 | // opcode . Used to set bit 128 of the CPX |
| 2948 | // packet |
| 2949 | ///////////////////////////////////////// |
| 2950 | |
| 2951 | // BS 03/11/04 extra cycle for mem access |
| 2952 | |
| 2953 | l2t_msff_ctl_macro__width_1 ff_pf_inst_c52 |
| 2954 | (.din(arb_decdp_pf_inst_c5), .l1clk(l1clk), |
| 2955 | .scan_in(ff_pf_inst_c52_scanin), |
| 2956 | .scan_out(ff_pf_inst_c52_scanout), |
| 2957 | .dout(pf_inst_c52), |
| 2958 | .siclk(siclk), |
| 2959 | .soclk(soclk) |
| 2960 | ); |
| 2961 | |
| 2962 | |
| 2963 | l2t_msff_ctl_macro__width_1 ff_pf_inst_c6 |
| 2964 | (.din(pf_inst_c52), .l1clk(l1clk), |
| 2965 | .scan_in(ff_pf_inst_c6_scanin), |
| 2966 | .scan_out(ff_pf_inst_c6_scanout), |
| 2967 | .dout(pf_inst_c6), |
| 2968 | .siclk(siclk), |
| 2969 | .soclk(soclk) |
| 2970 | ); |
| 2971 | |
| 2972 | l2t_msff_ctl_macro__width_1 ff_pf_inst_c7 |
| 2973 | (.din(pf_inst_c6), .l1clk(l1clk), |
| 2974 | .scan_in(ff_pf_inst_c7_scanin), |
| 2975 | .scan_out(ff_pf_inst_c7_scanout), |
| 2976 | .dout(pf_inst_c7), |
| 2977 | .siclk(siclk), |
| 2978 | .soclk(soclk) |
| 2979 | ); |
| 2980 | |
| 2981 | assign oqu_pf_ack_c7 = pf_inst_c7 & ld_hit_c7 ; |
| 2982 | |
| 2983 | |
| 2984 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_load_ret |
| 2985 | ( .dout (load_ret[3:0]), |
| 2986 | .din0(`LOAD_RET), |
| 2987 | .din1(`FWD_RPY_RET), |
| 2988 | .sel0(~oqu_fwd_req_ret_c7), |
| 2989 | .sel1(oqu_fwd_req_ret_c7)); |
| 2990 | |
| 2991 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_stack_ret |
| 2992 | ( .dout (stack_ret[3:0]), |
| 2993 | .din0(`ST_ACK), |
| 2994 | .din1(`FWD_RPY_RET), |
| 2995 | .sel0(~oqu_fwd_req_ret_c7), |
| 2996 | .sel1(oqu_fwd_req_ret_c7)); |
| 2997 | |
| 2998 | |
| 2999 | assign imiss_req_sel_c7 = imiss1_out_c7 | imiss1_out_c8 ; |
| 3000 | assign err_req_sel_c7 = ( ~imiss_req_sel_c7 & ~int_ack_c7 ); |
| 3001 | assign int_req_sel_c7 = int_ack_c7 & ~imiss_req_sel_c7 ; |
| 3002 | |
| 3003 | l2t_mux_ctl_macro__mux_aonpe__ports_3__width_4 mux_imiss_err_or_intreq_c7 |
| 3004 | ( .dout (imiss_err_or_int_rqtyp_c7[3:0]), |
| 3005 | .din0(`IFILL_RET), |
| 3006 | .din1(`INT_RET), |
| 3007 | .din2(`ERR_RET), |
| 3008 | .sel0(imiss_req_sel_c7), |
| 3009 | .sel1(int_req_sel_c7), |
| 3010 | .sel2(err_req_sel_c7)); |
| 3011 | |
| 3012 | // BS,SR 12/07/04 : taking out arb_swap_cas2_req_c2 to l2t_oqu_ctl.sv to disable ERROR |
| 3013 | // Indication packet on a CE,UE, or Notdata on the store part of the swap or CAS2. |
| 3014 | // Instead , regular store ack packet will get sent. |
| 3015 | |
| 3016 | l2t_msff_ctl_macro__width_6 ff_arb_oqu_swap_cas2_req |
| 3017 | (.din({arb_oqu_swap_cas2_req_c2,arb_oqu_swap_cas2_req_c3, |
| 3018 | arb_oqu_swap_cas2_req_c4,arb_oqu_swap_cas2_req_c5, |
| 3019 | arb_oqu_swap_cas2_req_c52,arb_oqu_swap_cas2_req_c6}), .l1clk(l1clk), |
| 3020 | .scan_in(ff_arb_oqu_swap_cas2_req_scanin), |
| 3021 | .scan_out(ff_arb_oqu_swap_cas2_req_scanout), |
| 3022 | .dout({arb_oqu_swap_cas2_req_c3,arb_oqu_swap_cas2_req_c4, |
| 3023 | arb_oqu_swap_cas2_req_c5,arb_oqu_swap_cas2_req_c52, |
| 3024 | arb_oqu_swap_cas2_req_c6,arb_oqu_swap_cas2_req_c7}), |
| 3025 | .siclk(siclk), |
| 3026 | .soclk(soclk) |
| 3027 | ); |
| 3028 | |
| 3029 | assign imiss_err_or_int_sel_c7 = ( imiss_req_sel_c7 | int_ack_c7 | |
| 3030 | (((uerr_ack_c7 | cerr_ack_c7) & ~ld_hit_c7) & ~arb_oqu_swap_cas2_req_c7)) & |
| 3031 | ~sel_evict_vec_c7 ; // no eviction |
| 3032 | |
| 3033 | |
| 3034 | assign sel_st_ack_c7 = ( st_req_c7 | oqu_strst_ack_c7 ) & |
| 3035 | ~imiss_err_or_int_sel_c7 |
| 3036 | & ~sel_evict_vec_c7 ; |
| 3037 | |
| 3038 | // BS and SR 11/12/03 N2 Xbar Packet format change |
| 3039 | assign sel_inval_ack_c7 = inval_req_c7 & ~imiss_err_or_int_sel_c7 & ~sel_evict_vec_c7 ; |
| 3040 | |
| 3041 | assign sel_ld_ret_c7 = ~imiss_err_or_int_sel_c7 & ~sel_st_ack_c7 & ~sel_inval_ack_c7 & |
| 3042 | ~sel_evict_vec_c7 ; |
| 3043 | |
| 3044 | // BS 2/3/04 : During I$ or D$ INval ACk, sel_st_ack_c7 is also valid as st_ack_c3 gets asserted |
| 3045 | // when inval_inst_c3 is true |
| 3046 | // Hence to propagate INVAL_ACK , we need to disable sel_st_ack_c7 with sel_inval_ack_c7 |
| 3047 | // when driven as muxsel to mux_req_type_c7 |
| 3048 | |
| 3049 | assign sel_st_ack_true_c7 = sel_st_ack_c7 & ~sel_inval_ack_c7; // valid only if sel_inval_ack_c7 = 1'b0 |
| 3050 | |
| 3051 | l2t_mux_ctl_macro__mux_aonpe__ports_4__width_4 mux_req_type_c7 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 3052 | ( .dout (rqtyp_rtn_c7_tmp[3:0]), |
| 3053 | .din0(load_ret[3:0]), // load return |
| 3054 | .din1(stack_ret[3:0]), // store ack return |
| 3055 | .din2(`EVICT_REQ), // evict req |
| 3056 | .din3(`INVAL_ACK), // I$ or D$ Inval ack |
| 3057 | .sel0(sel_ld_ret_c7), |
| 3058 | .sel1(sel_st_ack_true_c7), // BS 2/3/04 |
| 3059 | .sel2(sel_evict_vec_c7), |
| 3060 | .sel3(sel_inval_ack_c7)); |
| 3061 | |
| 3062 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_req_type_fnl_c7 // BS and SR 11/12/03 N2 Xbar Packet format change |
| 3063 | ( .dout (rqtyp_rtn_c7[3:0]), |
| 3064 | .din0(rqtyp_rtn_c7_tmp[3:0]), // load return |
| 3065 | .din1(imiss_err_or_int_rqtyp_c7[3:0]), //imiss err or int |
| 3066 | .sel0(~imiss_err_or_int_sel_c7), |
| 3067 | .sel1(imiss_err_or_int_sel_c7)); |
| 3068 | |
| 3069 | |
| 3070 | |
| 3071 | assign oqu_str_ld_hit_c7 = strld_inst_c7 & ld_hit_c7 ; |
| 3072 | assign oqu_mmu_ld_hit_c7 = mmuld_inst_c7 & ld_hit_c7 ; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 3073 | |
| 3074 | assign oqu_rqtyp_rtn_c7[3] = rqtyp_rtn_c7[3] ; |
| 3075 | assign oqu_rqtyp_rtn_c7[2] = rqtyp_rtn_c7[2] | oqu_mmu_ld_hit_c7; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 3076 | assign oqu_rqtyp_rtn_c7[1] = rqtyp_rtn_c7[1] | oqu_str_ld_hit_c7 | oqu_strst_ack_c7 ; |
| 3077 | assign oqu_rqtyp_rtn_c7[0] = rqtyp_rtn_c7[0] | oqu_mmu_ld_hit_c7; // BS and SR 11/12/03 N2 Xbar Packet format change |
| 3078 | |
| 3079 | |
| 3080 | assign oqu_atm_inst_ack_c7 = ( atm_inst_c7 & ( ld_hit_c7 | st_ack_c7 ) ) | |
| 3081 | imiss1_out_c8 ; |
| 3082 | |
| 3083 | |
| 3084 | |
| 3085 | |
| 3086 | |
| 3087 | |
| 3088 | |
| 3089 | //////////////////////////////////////////////////////////////////// |
| 3090 | // Oq counter: The Oq counter is a C9 flop. However, the |
| 3091 | // full signal is generated in C8 using the previous value |
| 3092 | // of the counter. The full signal is asserted when the |
| 3093 | // counter is 7 or higher. THis means that instructions |
| 3094 | // PX2-C8 can be accomodated in the OQ. Here re the pipelines |
| 3095 | // for incrementing and decrementing OQ count. |
| 3096 | //----------------------------------------------------------------- |
| 3097 | // #1(C7) #2(C8) #3 #4 |
| 3098 | //----------------------------------------------------------------- |
| 3099 | // |
| 3100 | // if the C7 req |
| 3101 | // is still vld |
| 3102 | // AND ((oq_count!=0 ) inc counter. |
| 3103 | // OR old_req_vld ). |
| 3104 | // |
| 3105 | // setup wline for wr_Data into |
| 3106 | // oqarray write. oqarray |
| 3107 | // |
| 3108 | // setup wline for |
| 3109 | // req Q write. |
| 3110 | // |
| 3111 | // req Q write. |
| 3112 | //----------------------------------------------------------------- |
| 3113 | // #1 #2 #3 |
| 3114 | //----------------------------------------------------------------- |
| 3115 | // inc rd pointer |
| 3116 | // if ~oldreq dec counter send to CPX |
| 3117 | // and if oq_count |
| 3118 | // non_zero rd data |
| 3119 | // from array |
| 3120 | // setup wline |
| 3121 | // for reading next |
| 3122 | // entry.(earliest |
| 3123 | // issue out of |
| 3124 | // OQ is in C10) |
| 3125 | // |
| 3126 | //////////////////////////////////////////////////////////////////// |
| 3127 | |
| 3128 | |
| 3129 | //////////////////// |
| 3130 | // Wr Pointer |
| 3131 | //////////////////// |
| 3132 | |
| 3133 | |
| 3134 | assign inc_wr_ptr = sel_c7_req |
| 3135 | & (oq_count_nonzero | old_req_vld) ; |
| 3136 | |
| 3137 | // use a big flop that has a fanout of 16 so that the |
| 3138 | // output of the flop can be used directly to mux out |
| 3139 | // the wr ptr |
| 3140 | l2t_msff_ctl_macro__clr_1__width_1 ff_inc_wr_ptr_d1 // sync reset active low |
| 3141 | (.din(inc_wr_ptr), .l1clk(l1clk), |
| 3142 | .scan_in(ff_inc_wr_ptr_d1_scanin), |
| 3143 | .scan_out(ff_inc_wr_ptr_d1_scanout), |
| 3144 | .clr(~dbb_rst_l), |
| 3145 | .dout(inc_wr_ptr_d1), |
| 3146 | .siclk(siclk), |
| 3147 | .soclk(soclk) |
| 3148 | ); |
| 3149 | |
| 3150 | l2t_msff_ctl_macro__clr_1__width_1 ff_inc_wr_ptr_d1_1 // sync reset active low |
| 3151 | (.din(inc_wr_ptr), .l1clk(l1clk), |
| 3152 | .scan_in(ff_inc_wr_ptr_d1_1_scanin), |
| 3153 | .scan_out(ff_inc_wr_ptr_d1_1_scanout), |
| 3154 | .clr(~dbb_rst_l), |
| 3155 | .dout(inc_wr_ptr_d1_1), |
| 3156 | .siclk(siclk), |
| 3157 | .soclk(soclk) |
| 3158 | ); |
| 3159 | |
| 3160 | l2t_msff_ctl_macro__clr_1__width_1 ff_inc_wr_ptr_d1_2 // sync reset active low |
| 3161 | (.din(inc_wr_ptr), .l1clk(l1clk), |
| 3162 | .scan_in(ff_inc_wr_ptr_d1_2_scanin), |
| 3163 | .scan_out(ff_inc_wr_ptr_d1_2_scanout), |
| 3164 | .clr(~dbb_rst_l), |
| 3165 | .dout(inc_wr_ptr_d1_2), |
| 3166 | .siclk(siclk), |
| 3167 | .soclk(soclk) |
| 3168 | ); |
| 3169 | |
| 3170 | |
| 3171 | l2t_msff_ctl_macro__width_1 ff_l2t_mb0_run_r1 |
| 3172 | (.din(l2t_mb0_run), .l1clk(l1clk), |
| 3173 | .scan_in(ff_l2t_mb0_run_r1_scanin), |
| 3174 | .scan_out(ff_l2t_mb0_run_r1_scanout), |
| 3175 | .dout(l2t_mb0_run_r1), |
| 3176 | .siclk(siclk), |
| 3177 | .soclk(soclk) |
| 3178 | ); |
| 3179 | assign oqu_oqarray_wr_en = ~l2t_mb0_run_r1 ? inc_wr_ptr_d1 : l2t_mb0_oqarray_wr_en ; // wen for array write |
| 3180 | |
| 3181 | assign wr_word_line = wr_ptr & {16{~wr_wl_disable}} ; // wline for req Q write. |
| 3182 | |
| 3183 | assign enc_wr_ptr[0] = ( wr_ptr[1] | wr_ptr[3] | wr_ptr[5] | |
| 3184 | wr_ptr[7] | wr_ptr[9] | wr_ptr[11] | |
| 3185 | wr_ptr[13] | wr_ptr[15] ) ; |
| 3186 | |
| 3187 | assign enc_wr_ptr[1] = ( wr_ptr[2] | wr_ptr[3] | wr_ptr[6] | |
| 3188 | wr_ptr[7] | wr_ptr[10] | wr_ptr[11] | |
| 3189 | wr_ptr[14] | wr_ptr[15] ) ; |
| 3190 | |
| 3191 | assign enc_wr_ptr[2] = ( wr_ptr[4] | wr_ptr[5] | wr_ptr[6] | |
| 3192 | wr_ptr[7] | wr_ptr[12] | wr_ptr[13] | |
| 3193 | wr_ptr[14] | wr_ptr[15] ) ; |
| 3194 | |
| 3195 | assign enc_wr_ptr[3] = ( wr_ptr[8] | wr_ptr[9] | wr_ptr[10] | |
| 3196 | wr_ptr[11] | wr_ptr[12] | wr_ptr[13] | |
| 3197 | wr_ptr[14] | wr_ptr[15] ) ; |
| 3198 | |
| 3199 | l2t_msff_ctl_macro__width_4 ff_enc_wr_ptr_d1 |
| 3200 | (.din(enc_wr_ptr[3:0]), .l1clk(l1clk), |
| 3201 | .scan_in(ff_enc_wr_ptr_d1_scanin), |
| 3202 | .scan_out(ff_enc_wr_ptr_d1_scanout), |
| 3203 | .dout(enc_wr_ptr_d1[3:0]), |
| 3204 | .siclk(siclk), |
| 3205 | .soclk(soclk) |
| 3206 | ); |
| 3207 | |
| 3208 | |
| 3209 | |
| 3210 | |
| 3211 | |
| 3212 | assign oqu_oqarray_wr_ptr = ~l2t_mb0_run_r1 ? enc_wr_ptr_d1 : l2t_mb0_addr; // write wline for array |
| 3213 | |
| 3214 | |
| 3215 | assign wr_ptr_lsby1 = { wr_ptr_d1[14:0], wr_ptr_d1[15] } ; |
| 3216 | |
| 3217 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_wr_ptr |
| 3218 | ( .dout (wr_ptr[15:0]), // used for FIFO write |
| 3219 | .din0(wr_ptr_lsby1[15:0]), // advanced |
| 3220 | .din1(wr_ptr_d1[15:0]), // same |
| 3221 | .sel0(inc_wr_ptr_d1_1), // sel advance |
| 3222 | .sel1(~inc_wr_ptr_d1_1)); |
| 3223 | |
| 3224 | |
| 3225 | l2t_msff_ctl_macro__clr_1__width_15 ff_wr_ptr15to1_d1 // sync reset active low |
| 3226 | (.din(wr_ptr[15:1]), .l1clk(l1clk), |
| 3227 | .scan_in(ff_wr_ptr15to1_d1_scanin), |
| 3228 | .scan_out(ff_wr_ptr15to1_d1_scanout), |
| 3229 | .clr(~dbb_rst_l), .dout(wr_ptr_d1[15:1]), |
| 3230 | .siclk(siclk), |
| 3231 | .soclk(soclk) |
| 3232 | ); |
| 3233 | |
| 3234 | assign wr_ptr0_n = ~wr_ptr[0]; |
| 3235 | |
| 3236 | l2t_msff_ctl_macro__clr_1__width_1 ff_wr_ptr0_d1 // sync reset active low |
| 3237 | (.din(wr_ptr0_n), .l1clk(l1clk), |
| 3238 | .scan_in(ff_wr_ptr0_d1_scanin), |
| 3239 | .scan_out(ff_wr_ptr0_d1_scanout), |
| 3240 | .clr(~dbb_rst_l), .dout(wr_ptr0_n_d1), |
| 3241 | .siclk(siclk), |
| 3242 | .soclk(soclk) |
| 3243 | ); |
| 3244 | |
| 3245 | assign wr_ptr_d1[0] = ~wr_ptr0_n_d1; |
| 3246 | |
| 3247 | //////////////////// |
| 3248 | // Rd Pointer |
| 3249 | //////////////////// |
| 3250 | |
| 3251 | assign inc_rd_ptr = oq_count_nonzero & ~old_req_vld ; |
| 3252 | |
| 3253 | l2t_msff_ctl_macro__clr_1__width_1 ff_inc_rd_ptr_d1 // sync reset active low |
| 3254 | (.din(inc_rd_ptr), .l1clk(l1clk), |
| 3255 | .scan_in(ff_inc_rd_ptr_d1_scanin), |
| 3256 | .scan_out(ff_inc_rd_ptr_d1_scanout), |
| 3257 | .clr(~dbb_rst_l), |
| 3258 | .dout(inc_rd_ptr_d1), |
| 3259 | .siclk(siclk), |
| 3260 | .soclk(soclk) |
| 3261 | ); |
| 3262 | |
| 3263 | l2t_msff_ctl_macro__clr_1__width_1 ff_inc_rd_ptr_d1_1 // sync reset active low |
| 3264 | (.din(inc_rd_ptr), .l1clk(l1clk), |
| 3265 | .scan_in(ff_inc_rd_ptr_d1_1_scanin), |
| 3266 | .scan_out(ff_inc_rd_ptr_d1_1_scanout), |
| 3267 | .clr(~dbb_rst_l), |
| 3268 | .dout(inc_rd_ptr_d1_1), |
| 3269 | .siclk(siclk), |
| 3270 | .soclk(soclk) |
| 3271 | ); |
| 3272 | |
| 3273 | l2t_msff_ctl_macro__clr_1__width_1 ff_inc_rd_ptr_d1_2 // sync reset active low |
| 3274 | (.din(inc_rd_ptr), .l1clk(l1clk), |
| 3275 | .scan_in(ff_inc_rd_ptr_d1_2_scanin), |
| 3276 | .scan_out(ff_inc_rd_ptr_d1_2_scanout), |
| 3277 | .clr(~dbb_rst_l), |
| 3278 | .dout(inc_rd_ptr_d1_2), |
| 3279 | .siclk(siclk), |
| 3280 | .soclk(soclk) |
| 3281 | ); |
| 3282 | |
| 3283 | |
| 3284 | |
| 3285 | |
| 3286 | assign oqu_oqarray_rd_en = ~l2t_mb0_run_r1 ? oq_count_nonzero : l2t_mb0_oqarray_rd_en ; // array rd enable |
| 3287 | |
| 3288 | |
| 3289 | assign rd_word_line = rd_ptr ; // wline for req Q read |
| 3290 | |
| 3291 | |
| 3292 | assign enc_rd_ptr[0] = ( rd_ptr[1] | rd_ptr[3] | rd_ptr[5] | |
| 3293 | rd_ptr[7] | rd_ptr[9] | rd_ptr[11] | |
| 3294 | rd_ptr[13] | rd_ptr[15] ) ; |
| 3295 | |
| 3296 | assign enc_rd_ptr[1] = ( rd_ptr[2] | rd_ptr[3] | rd_ptr[6] | |
| 3297 | rd_ptr[7] | rd_ptr[10] | rd_ptr[11] | |
| 3298 | rd_ptr[14] | rd_ptr[15] ) ; |
| 3299 | |
| 3300 | assign enc_rd_ptr[2] = ( rd_ptr[4] | rd_ptr[5] | rd_ptr[6] | |
| 3301 | rd_ptr[7] | rd_ptr[12] | rd_ptr[13] | |
| 3302 | rd_ptr[14] | rd_ptr[15] ) ; |
| 3303 | |
| 3304 | assign enc_rd_ptr[3] = ( rd_ptr[8] | rd_ptr[9] | rd_ptr[10] | |
| 3305 | rd_ptr[11] | rd_ptr[12] | rd_ptr[13] | |
| 3306 | rd_ptr[14] | rd_ptr[15] ) ; |
| 3307 | |
| 3308 | assign oqu_oqarray_rd_ptr = ~l2t_mb0_run_r1 ? enc_rd_ptr : l2t_mb0_addr; // ph1 read |
| 3309 | |
| 3310 | assign rd_ptr_lsby1 = { rd_ptr_d1[14:0], rd_ptr_d1[15] } ; |
| 3311 | |
| 3312 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_rd_ptr |
| 3313 | ( .dout (rd_ptr[15:0]), |
| 3314 | .din0(rd_ptr_lsby1[15:0]), |
| 3315 | .din1(rd_ptr_d1[15:0]), |
| 3316 | .sel0(inc_rd_ptr_d1_1), |
| 3317 | .sel1(~inc_rd_ptr_d1_1)); |
| 3318 | |
| 3319 | l2t_msff_ctl_macro__clr_1__width_15 ff_rd_ptr15to1_d1 // sync reset active low |
| 3320 | (.din(rd_ptr[15:1]), .l1clk(l1clk), |
| 3321 | .scan_in(ff_rd_ptr15to1_d1_scanin), |
| 3322 | .scan_out(ff_rd_ptr15to1_d1_scanout), |
| 3323 | .clr(~dbb_rst_l), .dout(rd_ptr_d1[15:1]), |
| 3324 | .siclk(siclk), |
| 3325 | .soclk(soclk) |
| 3326 | ); |
| 3327 | |
| 3328 | assign rd_ptr0_n = ~rd_ptr[0] ; |
| 3329 | |
| 3330 | l2t_msff_ctl_macro__clr_1__width_1 ff_rd_ptr0_d1 // sync reset active low |
| 3331 | (.din(rd_ptr0_n), .l1clk(l1clk), |
| 3332 | .scan_in(ff_rd_ptr0_d1_scanin), |
| 3333 | .scan_out(ff_rd_ptr0_d1_scanout), |
| 3334 | .clr(~dbb_rst_l), .dout(rd_ptr0_n_d1), |
| 3335 | .siclk(siclk), |
| 3336 | .soclk(soclk) |
| 3337 | ); |
| 3338 | |
| 3339 | assign rd_ptr_d1[0] = ~rd_ptr0_n_d1; |
| 3340 | |
| 3341 | ////////////////// |
| 3342 | // What If???? |
| 3343 | // Wrptr == Rdptr. |
| 3344 | // If the Wr ptr is equal t th eread ptr. |
| 3345 | // the array read data is not going to |
| 3346 | // be correct. In this case, the |
| 3347 | // write data needs to be forwarded to |
| 3348 | // the rd data. |
| 3349 | ////////////////// |
| 3350 | l2t_msff_ctl_macro__width_4 ff_enc_wr_ptr_d2 |
| 3351 | (.din(enc_wr_ptr_d1[3:0]), .l1clk(l1clk), |
| 3352 | .scan_in(ff_enc_wr_ptr_d2_scanin), |
| 3353 | .scan_out(ff_enc_wr_ptr_d2_scanout), |
| 3354 | .dout(enc_wr_ptr_d2[3:0]), |
| 3355 | .siclk(siclk), |
| 3356 | .soclk(soclk) |
| 3357 | ); |
| 3358 | |
| 3359 | l2t_msff_ctl_macro__width_4 ff_enc_rd_ptr_d1 |
| 3360 | (.din(enc_rd_ptr[3:0]), .l1clk(l1clk), |
| 3361 | .scan_in(ff_enc_rd_ptr_d1_scanin), |
| 3362 | .scan_out(ff_enc_rd_ptr_d1_scanout), |
| 3363 | .dout(enc_rd_ptr_d1[3:0]), |
| 3364 | .siclk(siclk), |
| 3365 | .soclk(soclk) |
| 3366 | ); |
| 3367 | |
| 3368 | l2t_msff_ctl_macro__width_1 ff_inc_wr_ptr_d2 |
| 3369 | (.din(inc_wr_ptr_d1), .l1clk(l1clk), |
| 3370 | .scan_in(ff_inc_wr_ptr_d2_scanin), |
| 3371 | .scan_out(ff_inc_wr_ptr_d2_scanout), |
| 3372 | .dout(inc_wr_ptr_d2), |
| 3373 | .siclk(siclk), |
| 3374 | .soclk(soclk) |
| 3375 | ); |
| 3376 | |
| 3377 | // Int 5.0 changes |
| 3378 | //////---\/ FIx for macrotest \/--------- |
| 3379 | |
| 3380 | |
| 3381 | assign oqu_sel_array_out_l = (( enc_wr_ptr_d2 == enc_rd_ptr_d1 ) & |
| 3382 | inc_wr_ptr_d2 & // WR |
| 3383 | oq_count_nonzero_d1); // RD |
| 3384 | |
| 3385 | // int 5.0 changes |
| 3386 | ////////////////// |
| 3387 | // OQ counter. |
| 3388 | // assert full when 5 or greater. |
| 3389 | // |
| 3390 | // Bug#4503. The oqcount full assumption is |
| 3391 | // wrong. Here is why |
| 3392 | // Currently we assert oq_count_full when the |
| 3393 | // counter is 7. |
| 3394 | // The case that will cause the worst case skid |
| 3395 | // and break the above assumption is as follows. |
| 3396 | //------------------------------------- |
| 3397 | // cycle #X cycle #X+1 |
| 3398 | //------------------------------------- |
| 3399 | // |
| 3400 | // C8 (~stall if C9(cnt=5) |
| 3401 | // cnt <= 5) |
| 3402 | // C7 C8(6) |
| 3403 | // C6 C7(7) |
| 3404 | // C52 C6(8) |
| 3405 | // C5 C52(9) |
| 3406 | // C4 C5(10) |
| 3407 | // C3 C4(11) |
| 3408 | // C2 C3(12) |
| 3409 | // C1 C2(13) |
| 3410 | // PX2 C1(14 and 15) |
| 3411 | // PX1 PX2(16 and 17) |
| 3412 | // |
| 3413 | //------------------------------------- |
| 3414 | // The C1 instruction could be an imiss. that requires 2 slots in the IQ. |
| 3415 | // Similarly, the PX2 instruction could be an IMISS/CAS that requires 2 slots. |
| 3416 | // This would put the counter at 17. Hence the oq counter full needs to be asserted |
| 3417 | // at 5 or more |
| 3418 | ////////////////// |
| 3419 | |
| 3420 | |
| 3421 | |
| 3422 | assign sel_count_inc = inc_wr_ptr_d1_2 & ~inc_rd_ptr_d1_2; |
| 3423 | assign sel_count_dec = ~inc_wr_ptr_d1 & inc_rd_ptr_d1 ; |
| 3424 | assign sel_count_def = ~( sel_count_inc | sel_count_dec ) ; |
| 3425 | |
| 3426 | assign oq_count_plus_1 = (oq_count_p + 5'b1 ) ; |
| 3427 | assign oq_count_minus_1 = ( oq_count_p - 5'b1 ) ; |
| 3428 | assign oq_count_reset_p = ( oq_count_p ); |
| 3429 | |
| 3430 | l2t_msff_ctl_macro__clr_1__width_5 ff_oq_cnt_d1 // sync reset active low |
| 3431 | (.din(oq_count_reset_p[4:0]), .l1clk(l1clk), |
| 3432 | .scan_in(ff_oq_cnt_d1_scanin), |
| 3433 | .scan_out(ff_oq_cnt_d1_scanout), |
| 3434 | .clr(~dbb_rst_l),.dout(oq_count_d1[4:0]), |
| 3435 | .siclk(siclk), |
| 3436 | .soclk(soclk) |
| 3437 | ); |
| 3438 | |
| 3439 | l2t_msff_ctl_macro__width_5 ff_oq_cnt_plus1_d1 |
| 3440 | (.din(oq_count_plus_1[4:0]), .l1clk(l1clk), |
| 3441 | .scan_in(ff_oq_cnt_plus1_d1_scanin), |
| 3442 | .scan_out(ff_oq_cnt_plus1_d1_scanout), |
| 3443 | .dout(oq_count_plus_1_d1[4:0]), |
| 3444 | .siclk(siclk), |
| 3445 | .soclk(soclk) |
| 3446 | ); |
| 3447 | |
| 3448 | l2t_msff_ctl_macro__width_5 ff_oq_cnt_minus1_d1 |
| 3449 | (.din(oq_count_minus_1[4:0]), .l1clk(l1clk), |
| 3450 | .scan_in(ff_oq_cnt_minus1_d1_scanin), |
| 3451 | .scan_out(ff_oq_cnt_minus1_d1_scanout), |
| 3452 | .dout(oq_count_minus_1_d1[4:0]), |
| 3453 | .siclk(siclk), |
| 3454 | .soclk(soclk) |
| 3455 | ); |
| 3456 | |
| 3457 | l2t_mux_ctl_macro__mux_aonpe__ports_3__width_5 mux_oq_count |
| 3458 | ( .dout (oq_count_p[4:0]), |
| 3459 | .din0(oq_count_d1[4:0]), |
| 3460 | .din1(oq_count_minus_1_d1[4:0]), |
| 3461 | .din2(oq_count_plus_1_d1[4:0]), |
| 3462 | .sel0(sel_count_def), |
| 3463 | .sel1(sel_count_dec), |
| 3464 | .sel2(sel_count_inc)); |
| 3465 | |
| 3466 | assign oq_count_nonzero = |( oq_count_p) ; |
| 3467 | |
| 3468 | // Read bug report for Bug # 3352. |
| 3469 | // Funtionality to turn OFF the wr_wordline when the |
| 3470 | // counter is at 16 or is going to reach 16 . Since the |
| 3471 | // wr pointer advances with every write, we need to prevent |
| 3472 | // a write when the counter is 16 and the pointer has wrapped |
| 3473 | // around. |
| 3474 | // Here is pipeline. |
| 3475 | //-------------------------------------------------------- |
| 3476 | // X X+1 X+2 |
| 3477 | //-------------------------------------------------------- |
| 3478 | // 1) cnt_p==15 insert=1 |
| 3479 | // delete=0 |
| 3480 | // cnt_p=16 |
| 3481 | // wr_wline!=0 wr_wline=0; |
| 3482 | // |
| 3483 | // 2) cnt_p==16 if delete=0 |
| 3484 | // wr_wline==0 wr_wline=0; |
| 3485 | // |
| 3486 | // if delete=1 |
| 3487 | // wr_wline!=0; |
| 3488 | //-------------------------------------------------------- |
| 3489 | |
| 3490 | assign oq_count_15_p = ( oq_count_p == 5'hf ) ; |
| 3491 | |
| 3492 | l2t_msff_ctl_macro__width_1 ff_oq_count_15_d1 |
| 3493 | (.din(oq_count_15_p), .l1clk(l1clk), |
| 3494 | .scan_in(ff_oq_count_15_d1_scanin), |
| 3495 | .scan_out(ff_oq_count_15_d1_scanout), |
| 3496 | .dout(oq_count_15_d1), |
| 3497 | .siclk(siclk), |
| 3498 | .soclk(soclk) |
| 3499 | ); |
| 3500 | |
| 3501 | assign oq_count_16_p = ( oq_count_p == 5'h10 ) ; |
| 3502 | |
| 3503 | l2t_msff_ctl_macro__width_1 ff_oq_count_16_d1 |
| 3504 | (.din(oq_count_16_p), .l1clk(l1clk), |
| 3505 | .scan_in(ff_oq_count_16_d1_scanin), |
| 3506 | .scan_out(ff_oq_count_16_d1_scanout), |
| 3507 | .dout(oq_count_16_d1), |
| 3508 | .siclk(siclk), |
| 3509 | .soclk(soclk) |
| 3510 | ); |
| 3511 | |
| 3512 | |
| 3513 | assign wr_wl_disable = ( ( oq_count_15_d1 & sel_count_inc ) | |
| 3514 | ( oq_count_16_d1 & ~sel_count_dec ) ) ; |
| 3515 | |
| 3516 | assign oqu_full_px1 = ( oq_count_p[2] & oq_count_p[1]) | // int 5.0 changes |
| 3517 | ( oq_count_p[2] & ~oq_count_p[1] & oq_count_p[0]) | // count = 5 , BS 04/22/04 |
| 3518 | ( oq_count_p[3] ) | |
| 3519 | ( oq_count_p[4] ) ; |
| 3520 | |
| 3521 | l2t_msff_ctl_macro__width_1 ff_oqu_arb_full_px2 |
| 3522 | (.din(oqu_full_px1), .l1clk(l1clk), |
| 3523 | .scan_in(ff_oqu_arb_full_px2_scanin), |
| 3524 | .scan_out(ff_oqu_arb_full_px2_scanout), |
| 3525 | .dout(oqu_arb_full_px2), |
| 3526 | .siclk(siclk), |
| 3527 | .soclk(soclk) |
| 3528 | ); |
| 3529 | |
| 3530 | //////////////////////////////////////////////////////////////////// |
| 3531 | // Oqdp mux select generation: |
| 3532 | //////////////////////////////////////////////////////////////////// |
| 3533 | |
| 3534 | l2t_msff_ctl_macro__width_1 ff_oq_count_nonzero_d1 |
| 3535 | (.din(oq_count_nonzero), .l1clk(l1clk), |
| 3536 | .scan_in(ff_oq_count_nonzero_d1_scanin), |
| 3537 | .scan_out(ff_oq_count_nonzero_d1_scanout), |
| 3538 | .dout(oq_count_nonzero_d1), |
| 3539 | .siclk(siclk), |
| 3540 | .soclk(soclk) |
| 3541 | ); |
| 3542 | |
| 3543 | l2t_msff_ctl_macro__width_1 ff_old_req_vld_d1 |
| 3544 | (.din(old_req_vld), .l1clk(l1clk), |
| 3545 | .scan_in(ff_old_req_vld_d1_scanin), |
| 3546 | .scan_out(ff_old_req_vld_d1_scanout), |
| 3547 | .dout(old_req_vld_d1), |
| 3548 | .siclk(siclk), |
| 3549 | .soclk(soclk) |
| 3550 | ); |
| 3551 | |
| 3552 | |
| 3553 | assign oqu_sel_inval_c6 = ( sel_inv_vec_c6 | sel_stinv_req_c6 | int_ack_c6 | |
| 3554 | mux1_sel_dec_vec_c7 ) ; |
| 3555 | |
| 3556 | assign oqu_sel_old_req_c7 = old_req_vld_d1 ; |
| 3557 | |
| 3558 | assign oqu_sel_oq_c7 = inc_rd_ptr_d1 ; |
| 3559 | |
| 3560 | assign oqu_prev_data_c7 = sel_c7_req_d1 & ~old_req_vld_d1 & |
| 3561 | ~oq_count_nonzero_d1 ; |
| 3562 | |
| 3563 | |
| 3564 | |
| 3565 | /////////////////////////////////////////////////////////////////////////////////// |
| 3566 | // OQ request Q |
| 3567 | /////////////////////////////////////////////////////////////////////////////////// |
| 3568 | |
| 3569 | l2t_msff_ctl_macro__en_1__width_12 ff_oq0_out |
| 3570 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3571 | .scan_in(ff_oq0_out_scanin), |
| 3572 | .scan_out(ff_oq0_out_scanout), |
| 3573 | .en(wr_word_line[0]), |
| 3574 | .l1clk(l1clk), .dout(oq0_out[11:0]), |
| 3575 | .siclk(siclk), |
| 3576 | .soclk(soclk) |
| 3577 | ); |
| 3578 | |
| 3579 | l2t_msff_ctl_macro__en_1__width_12 ff_oq1_out |
| 3580 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3581 | .scan_in(ff_oq1_out_scanin), |
| 3582 | .scan_out(ff_oq1_out_scanout), |
| 3583 | .en(wr_word_line[1]), |
| 3584 | .l1clk(l1clk), .dout(oq1_out[11:0]), |
| 3585 | .siclk(siclk), |
| 3586 | .soclk(soclk) |
| 3587 | ); |
| 3588 | |
| 3589 | l2t_msff_ctl_macro__en_1__width_12 ff_oq2_out |
| 3590 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3591 | .scan_in(ff_oq2_out_scanin), |
| 3592 | .scan_out(ff_oq2_out_scanout), |
| 3593 | .en(wr_word_line[2]), |
| 3594 | .l1clk(l1clk), .dout(oq2_out[11:0]), |
| 3595 | .siclk(siclk), |
| 3596 | .soclk(soclk) |
| 3597 | ); |
| 3598 | |
| 3599 | l2t_msff_ctl_macro__en_1__width_12 ff_oq3_out |
| 3600 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3601 | .scan_in(ff_oq3_out_scanin), |
| 3602 | .scan_out(ff_oq3_out_scanout), |
| 3603 | .en(wr_word_line[3]), |
| 3604 | .l1clk(l1clk), .dout(oq3_out[11:0]), |
| 3605 | .siclk(siclk), |
| 3606 | .soclk(soclk) |
| 3607 | ); |
| 3608 | |
| 3609 | l2t_msff_ctl_macro__en_1__width_12 ff_oq4_out |
| 3610 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3611 | .scan_in(ff_oq4_out_scanin), |
| 3612 | .scan_out(ff_oq4_out_scanout), |
| 3613 | .en(wr_word_line[4]), |
| 3614 | .l1clk(l1clk), .dout(oq4_out[11:0]), |
| 3615 | .siclk(siclk), |
| 3616 | .soclk(soclk) |
| 3617 | ); |
| 3618 | |
| 3619 | l2t_msff_ctl_macro__en_1__width_12 ff_oq5_out |
| 3620 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3621 | .scan_in(ff_oq5_out_scanin), |
| 3622 | .scan_out(ff_oq5_out_scanout), |
| 3623 | .en(wr_word_line[5]), |
| 3624 | .l1clk(l1clk), .dout(oq5_out[11:0]), |
| 3625 | .siclk(siclk), |
| 3626 | .soclk(soclk) |
| 3627 | ); |
| 3628 | |
| 3629 | l2t_msff_ctl_macro__en_1__width_12 ff_oq6_out |
| 3630 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3631 | .scan_in(ff_oq6_out_scanin), |
| 3632 | .scan_out(ff_oq6_out_scanout), |
| 3633 | .en(wr_word_line[6]), |
| 3634 | .l1clk(l1clk), .dout(oq6_out[11:0]), |
| 3635 | .siclk(siclk), |
| 3636 | .soclk(soclk) |
| 3637 | ); |
| 3638 | |
| 3639 | l2t_msff_ctl_macro__en_1__width_12 ff_oq7_out |
| 3640 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3641 | .scan_in(ff_oq7_out_scanin), |
| 3642 | .scan_out(ff_oq7_out_scanout), |
| 3643 | .en(wr_word_line[7]), |
| 3644 | .l1clk(l1clk), .dout(oq7_out[11:0]), |
| 3645 | .siclk(siclk), |
| 3646 | .soclk(soclk) |
| 3647 | ); |
| 3648 | |
| 3649 | l2t_msff_ctl_macro__en_1__width_12 ff_oq8_out |
| 3650 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3651 | .scan_in(ff_oq8_out_scanin), |
| 3652 | .scan_out(ff_oq8_out_scanout), |
| 3653 | .en(wr_word_line[8]), |
| 3654 | .l1clk(l1clk), .dout(oq8_out[11:0]), |
| 3655 | .siclk(siclk), |
| 3656 | .soclk(soclk) |
| 3657 | ); |
| 3658 | |
| 3659 | l2t_msff_ctl_macro__en_1__width_12 ff_oq9_out |
| 3660 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3661 | .scan_in(ff_oq9_out_scanin), |
| 3662 | .scan_out(ff_oq9_out_scanout), |
| 3663 | .en(wr_word_line[9]), |
| 3664 | .l1clk(l1clk), .dout(oq9_out[11:0]), |
| 3665 | .siclk(siclk), |
| 3666 | .soclk(soclk) |
| 3667 | ); |
| 3668 | |
| 3669 | l2t_msff_ctl_macro__en_1__width_12 ff_oq10_out |
| 3670 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3671 | .scan_in(ff_oq10_out_scanin), |
| 3672 | .scan_out(ff_oq10_out_scanout), |
| 3673 | .en(wr_word_line[10]), |
| 3674 | .l1clk(l1clk), .dout(oq10_out[11:0]), |
| 3675 | .siclk(siclk), |
| 3676 | .soclk(soclk) |
| 3677 | ); |
| 3678 | |
| 3679 | l2t_msff_ctl_macro__en_1__width_12 ff_oq11_out |
| 3680 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3681 | .scan_in(ff_oq11_out_scanin), |
| 3682 | .scan_out(ff_oq11_out_scanout), |
| 3683 | .en(wr_word_line[11]), |
| 3684 | .l1clk(l1clk), .dout(oq11_out[11:0]), |
| 3685 | .siclk(siclk), |
| 3686 | .soclk(soclk) |
| 3687 | ); |
| 3688 | |
| 3689 | l2t_msff_ctl_macro__en_1__width_12 ff_oq12_out |
| 3690 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3691 | .scan_in(ff_oq12_out_scanin), |
| 3692 | .scan_out(ff_oq12_out_scanout), |
| 3693 | .en(wr_word_line[12]), |
| 3694 | .l1clk(l1clk), .dout(oq12_out[11:0]), |
| 3695 | .siclk(siclk), |
| 3696 | .soclk(soclk) |
| 3697 | ); |
| 3698 | |
| 3699 | l2t_msff_ctl_macro__en_1__width_12 ff_oq13_out |
| 3700 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3701 | .scan_in(ff_oq13_out_scanin), |
| 3702 | .scan_out(ff_oq13_out_scanout), |
| 3703 | .en(wr_word_line[13]), |
| 3704 | .l1clk(l1clk), .dout(oq13_out[11:0]), |
| 3705 | .siclk(siclk), |
| 3706 | .soclk(soclk) |
| 3707 | ); |
| 3708 | |
| 3709 | l2t_msff_ctl_macro__en_1__width_12 ff_oq14_out |
| 3710 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3711 | .scan_in(ff_oq14_out_scanin), |
| 3712 | .scan_out(ff_oq14_out_scanout), |
| 3713 | .en(wr_word_line[14]), |
| 3714 | .l1clk(l1clk), .dout(oq14_out[11:0]), |
| 3715 | .siclk(siclk), |
| 3716 | .soclk(soclk) |
| 3717 | ); |
| 3718 | |
| 3719 | l2t_msff_ctl_macro__en_1__width_12 ff_oq15_out |
| 3720 | (.din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}), |
| 3721 | .scan_in(ff_oq15_out_scanin), |
| 3722 | .scan_out(ff_oq15_out_scanout), |
| 3723 | .en(wr_word_line[15]), |
| 3724 | .l1clk(l1clk), .dout(oq15_out[11:0]), |
| 3725 | .siclk(siclk), |
| 3726 | .soclk(soclk) |
| 3727 | ); |
| 3728 | |
| 3729 | |
| 3730 | assign oq_out_bit7 = { oq15_out[9],oq14_out[9],oq13_out[9],oq12_out[9], |
| 3731 | oq11_out[9],oq10_out[9],oq9_out[9],oq8_out[9], |
| 3732 | oq7_out[9],oq6_out[9],oq5_out[9],oq4_out[9], |
| 3733 | oq3_out[9],oq2_out[9],oq1_out[9],oq0_out[9] } ; |
| 3734 | |
| 3735 | assign oq_out_bit6 = { oq15_out[8],oq14_out[8],oq13_out[8],oq12_out[8], |
| 3736 | oq11_out[8],oq10_out[8],oq9_out[8],oq8_out[8], |
| 3737 | oq7_out[8],oq6_out[8],oq5_out[8],oq4_out[8], |
| 3738 | oq3_out[8],oq2_out[8],oq1_out[8],oq0_out[8] } ; |
| 3739 | |
| 3740 | assign oq_out_bit5 = { oq15_out[7],oq14_out[7],oq13_out[7],oq12_out[7], |
| 3741 | oq11_out[7],oq10_out[7],oq9_out[7],oq8_out[7], |
| 3742 | oq7_out[7],oq6_out[7],oq5_out[7],oq4_out[7], |
| 3743 | oq3_out[7],oq2_out[7],oq1_out[7],oq0_out[7] } ; |
| 3744 | |
| 3745 | assign oq_out_bit4 = { oq15_out[6],oq14_out[6],oq13_out[6],oq12_out[6], |
| 3746 | oq11_out[6],oq10_out[6],oq9_out[6],oq8_out[6], |
| 3747 | oq7_out[6],oq6_out[6],oq5_out[6],oq4_out[6], |
| 3748 | oq3_out[6],oq2_out[6],oq1_out[6],oq0_out[6] } ; |
| 3749 | |
| 3750 | assign oq_out_bit3 = { oq15_out[5],oq14_out[5],oq13_out[5],oq12_out[5], |
| 3751 | oq11_out[5],oq10_out[5],oq9_out[5],oq8_out[5], |
| 3752 | oq7_out[5],oq6_out[5],oq5_out[5],oq4_out[5], |
| 3753 | oq3_out[5],oq2_out[5],oq1_out[5],oq0_out[5] } ; |
| 3754 | |
| 3755 | assign oq_out_bit2 = { oq15_out[4],oq14_out[4],oq13_out[4],oq12_out[4], |
| 3756 | oq11_out[4],oq10_out[4],oq9_out[4],oq8_out[4], |
| 3757 | oq7_out[4],oq6_out[4],oq5_out[4],oq4_out[4], |
| 3758 | oq3_out[4],oq2_out[4],oq1_out[4],oq0_out[4] } ; |
| 3759 | |
| 3760 | assign oq_out_bit1 = { oq15_out[3],oq14_out[3],oq13_out[3],oq12_out[3], |
| 3761 | oq11_out[3],oq10_out[3],oq9_out[3],oq8_out[3], |
| 3762 | oq7_out[3],oq6_out[3],oq5_out[3],oq4_out[3], |
| 3763 | oq3_out[3],oq2_out[3],oq1_out[3],oq0_out[3] } ; |
| 3764 | |
| 3765 | assign oq_out_bit0 = { oq15_out[2],oq14_out[2],oq13_out[2],oq12_out[2], |
| 3766 | oq11_out[2],oq10_out[2],oq9_out[2],oq8_out[2], |
| 3767 | oq7_out[2],oq6_out[2],oq5_out[2],oq4_out[2], |
| 3768 | oq3_out[2],oq2_out[2],oq1_out[2],oq0_out[2] } ; |
| 3769 | |
| 3770 | assign imiss2_oq_out = { oq15_out[0],oq14_out[0],oq13_out[0],oq12_out[0], |
| 3771 | oq11_out[0],oq10_out[0],oq9_out[0],oq8_out[0], |
| 3772 | oq7_out[0],oq6_out[0],oq5_out[0],oq4_out[0], |
| 3773 | oq3_out[0],oq2_out[0],oq1_out[0],oq0_out[0] }; |
| 3774 | |
| 3775 | assign imiss1_oq_out = { oq15_out[1],oq14_out[1],oq13_out[1],oq12_out[1], |
| 3776 | oq11_out[1],oq10_out[1],oq9_out[1],oq8_out[1], |
| 3777 | oq7_out[1],oq6_out[1],oq5_out[1],oq4_out[1], |
| 3778 | oq3_out[1],oq2_out[1],oq1_out[1],oq0_out[1] }; |
| 3779 | |
| 3780 | assign bcast_oq_out = { oq15_out[10],oq14_out[10],oq13_out[10],oq12_out[10], |
| 3781 | oq11_out[10],oq10_out[10],oq9_out[10],oq8_out[10], |
| 3782 | oq7_out[10],oq6_out[10],oq5_out[10],oq4_out[10], |
| 3783 | oq3_out[10],oq2_out[10],oq1_out[10],oq0_out[10] }; |
| 3784 | |
| 3785 | assign rdma_oq_out = { oq15_out[11],oq14_out[11],oq13_out[11],oq12_out[11], |
| 3786 | oq11_out[11],oq10_out[11],oq9_out[11],oq8_out[11], |
| 3787 | oq7_out[11],oq6_out[11],oq5_out[11],oq4_out[11], |
| 3788 | oq3_out[11],oq2_out[11],oq1_out[11],oq0_out[11] }; |
| 3789 | |
| 3790 | |
| 3791 | assign oq_rd_out[7] = |( oq_out_bit7 & rd_word_line ) ; |
| 3792 | assign oq_rd_out[6] = |( oq_out_bit6 & rd_word_line ) ; |
| 3793 | assign oq_rd_out[5] = |( oq_out_bit5 & rd_word_line ) ; |
| 3794 | assign oq_rd_out[4] = |( oq_out_bit4 & rd_word_line ) ; |
| 3795 | assign oq_rd_out[3] = |( oq_out_bit3 & rd_word_line ) ; |
| 3796 | assign oq_rd_out[2] = |( oq_out_bit2 & rd_word_line ) ; |
| 3797 | assign oq_rd_out[1] = |( oq_out_bit1 & rd_word_line ) ; |
| 3798 | assign oq_rd_out[0] = |( oq_out_bit0 & rd_word_line ) ; |
| 3799 | |
| 3800 | assign imiss1_rd_out = |( imiss1_oq_out & rd_word_line ) ; |
| 3801 | |
| 3802 | assign imiss2_rd_out = |( imiss2_oq_out & rd_word_line ) ; |
| 3803 | |
| 3804 | assign oq_bcast_out = |( bcast_oq_out & rd_word_line ) ; |
| 3805 | |
| 3806 | assign oq_rdma_out = |( rdma_oq_out & rd_word_line ) ; |
| 3807 | |
| 3808 | |
| 3809 | /////////////////////////////////////////////////////////////////////////////////// |
| 3810 | // CROSSBAR Q COUNT |
| 3811 | /** The crossbar q count is maintained here */ |
| 3812 | // Each crossbar queue is incremented if |
| 3813 | // * A request is issued to that destination |
| 3814 | // OR if "atomic" is high and a request was issued to that |
| 3815 | // destination |
| 3816 | // Each crossbar queue is decremented if |
| 3817 | // * A grant is received from the crossbar for a request |
| 3818 | // * crossbar queue counters are initialized to 0 on reset |
| 3819 | |
| 3820 | // The crossbar Q full signal is high if |
| 3821 | // * the crossbar count is 2 |
| 3822 | // * the crossbar count is non-zero and the request is an imiss return. |
| 3823 | /////////////////////////////////////////////////////////////////////////////////// |
| 3824 | |
| 3825 | assign xbarq_full[0] = ( xbar0_cnt[1]) ; |
| 3826 | assign xbarq_full[1] = ( xbar1_cnt[1]) ; |
| 3827 | assign xbarq_full[2] = ( xbar2_cnt[1]) ; |
| 3828 | assign xbarq_full[3] = ( xbar3_cnt[1]) ; |
| 3829 | assign xbarq_full[4] = ( xbar4_cnt[1]) ; |
| 3830 | assign xbarq_full[5] = ( xbar5_cnt[1]) ; |
| 3831 | assign xbarq_full[6] = ( xbar6_cnt[1]) ; |
| 3832 | assign xbarq_full[7] = ( xbar7_cnt[1]) ; |
| 3833 | |
| 3834 | assign xbarq_cnt1[0] = ( xbar0_cnt[0]) ; |
| 3835 | assign xbarq_cnt1[1] = ( xbar1_cnt[0]) ; |
| 3836 | assign xbarq_cnt1[2] = ( xbar2_cnt[0]) ; |
| 3837 | assign xbarq_cnt1[3] = ( xbar3_cnt[0]) ; |
| 3838 | assign xbarq_cnt1[4] = ( xbar4_cnt[0]) ; |
| 3839 | assign xbarq_cnt1[5] = ( xbar5_cnt[0]) ; |
| 3840 | assign xbarq_cnt1[6] = ( xbar6_cnt[0]) ; |
| 3841 | assign xbarq_cnt1[7] = ( xbar7_cnt[0]) ; |
| 3842 | |
| 3843 | assign inc_xbar_cnt[0] = ( que_in_xbarq_c7[0] & ~xbarq_full[0] & ~cpx_l2t_grant_cx[0] ) ; |
| 3844 | assign dec_xbar_cnt[0] = ( ~que_in_xbarq_c7[0] & cpx_l2t_grant_cx[0] ) ; |
| 3845 | assign nochange_xbar_cnt[0] = ~dec_xbar_cnt[0] & ~inc_xbar_cnt[0] ; |
| 3846 | assign change_xbar_cnt[0] = ~nochange_xbar_cnt[0] ; |
| 3847 | assign xbar0_cnt_plus1[1:0] = xbar0_cnt[1:0] + 2'b1 ; |
| 3848 | assign xbar0_cnt_minus1[1:0] = xbar0_cnt[1:0] - 2'b1 ; |
| 3849 | |
| 3850 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar0_cnt |
| 3851 | ( .dout (xbar0_cnt_p[1:0]), |
| 3852 | .din0(xbar0_cnt_plus1[1:0]), .din1(xbar0_cnt_minus1[1:0]), |
| 3853 | .sel0(inc_xbar_cnt[0]), .sel1(~inc_xbar_cnt[0])) ; |
| 3854 | |
| 3855 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar0 // sync reset active low |
| 3856 | (.din(xbar0_cnt_p[1:0]), .l1clk(l1clk), |
| 3857 | .scan_in(ff_xbar0_scanin), |
| 3858 | .scan_out(ff_xbar0_scanout), |
| 3859 | .clr(~dbb_rst_l), .en(change_xbar_cnt[0]), |
| 3860 | .dout(xbar0_cnt[1:0]), |
| 3861 | .siclk(siclk), |
| 3862 | .soclk(soclk) |
| 3863 | ); |
| 3864 | |
| 3865 | |
| 3866 | assign inc_xbar_cnt[1] = ( que_in_xbarq_c7[1] & ~xbarq_full[1] & ~cpx_l2t_grant_cx[1] ) ; |
| 3867 | assign dec_xbar_cnt[1] = ( ~que_in_xbarq_c7[1] & cpx_l2t_grant_cx[1] ) ; |
| 3868 | assign nochange_xbar_cnt[1] = ~dec_xbar_cnt[1] & ~inc_xbar_cnt[1] ; |
| 3869 | assign change_xbar_cnt[1] = ~nochange_xbar_cnt[1] ; |
| 3870 | assign xbar1_cnt_plus1[1:0] = xbar1_cnt[1:0] + 2'b1 ; |
| 3871 | assign xbar1_cnt_minus1[1:0] = xbar1_cnt[1:0] - 2'b1 ; |
| 3872 | |
| 3873 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar1_cnt |
| 3874 | ( .dout (xbar1_cnt_p[1:0]), |
| 3875 | .din0(xbar1_cnt_plus1[1:0]), .din1(xbar1_cnt_minus1[1:0]), |
| 3876 | .sel0(inc_xbar_cnt[1]), .sel1(~inc_xbar_cnt[1])) ; |
| 3877 | |
| 3878 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar1 // sync reset active low |
| 3879 | (.din(xbar1_cnt_p[1:0]), .l1clk(l1clk), |
| 3880 | .scan_in(ff_xbar1_scanin), |
| 3881 | .scan_out(ff_xbar1_scanout), |
| 3882 | .clr(~dbb_rst_l), .en(change_xbar_cnt[1]), |
| 3883 | .dout(xbar1_cnt[1:0]), |
| 3884 | .siclk(siclk), |
| 3885 | .soclk(soclk) |
| 3886 | ); |
| 3887 | |
| 3888 | |
| 3889 | assign inc_xbar_cnt[2] = ( que_in_xbarq_c7[2] & ~xbarq_full[2] & ~cpx_l2t_grant_cx[2] ) ; |
| 3890 | assign dec_xbar_cnt[2] = ( ~que_in_xbarq_c7[2] & cpx_l2t_grant_cx[2] ) ; |
| 3891 | assign nochange_xbar_cnt[2] = ~dec_xbar_cnt[2] & ~inc_xbar_cnt[2] ; |
| 3892 | assign change_xbar_cnt[2] = ~nochange_xbar_cnt[2] ; |
| 3893 | assign xbar2_cnt_plus1[1:0] = xbar2_cnt[1:0] + 2'b1 ; |
| 3894 | assign xbar2_cnt_minus1[1:0] = xbar2_cnt[1:0] - 2'b1 ; |
| 3895 | |
| 3896 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar2_cnt |
| 3897 | ( .dout (xbar2_cnt_p[1:0]), |
| 3898 | .din0(xbar2_cnt_plus1[1:0]), .din1(xbar2_cnt_minus1[1:0]), |
| 3899 | .sel0(inc_xbar_cnt[2]), .sel1(~inc_xbar_cnt[2])) ; |
| 3900 | |
| 3901 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar2 // sync reset active low |
| 3902 | (.din(xbar2_cnt_p[1:0]), .l1clk(l1clk), |
| 3903 | .scan_in(ff_xbar2_scanin), |
| 3904 | .scan_out(ff_xbar2_scanout), |
| 3905 | .clr(~dbb_rst_l), .en(change_xbar_cnt[2]), |
| 3906 | .dout(xbar2_cnt[1:0]), |
| 3907 | .siclk(siclk), |
| 3908 | .soclk(soclk) |
| 3909 | ); |
| 3910 | |
| 3911 | |
| 3912 | assign inc_xbar_cnt[3] = ( que_in_xbarq_c7[3] & ~xbarq_full[3] & ~cpx_l2t_grant_cx[3] ) ; |
| 3913 | assign dec_xbar_cnt[3] = ( ~que_in_xbarq_c7[3] & cpx_l2t_grant_cx[3] ) ; |
| 3914 | assign nochange_xbar_cnt[3] = ~dec_xbar_cnt[3] & ~inc_xbar_cnt[3] ; |
| 3915 | assign change_xbar_cnt[3] = ~nochange_xbar_cnt[3] ; |
| 3916 | assign xbar3_cnt_plus1[1:0] = xbar3_cnt[1:0] + 2'b1 ; |
| 3917 | assign xbar3_cnt_minus1[1:0] = xbar3_cnt[1:0] - 2'b1 ; |
| 3918 | |
| 3919 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar3_cnt |
| 3920 | ( .dout (xbar3_cnt_p[1:0]), |
| 3921 | .din0(xbar3_cnt_plus1[1:0]), .din1(xbar3_cnt_minus1[1:0]), |
| 3922 | .sel0(inc_xbar_cnt[3]), .sel1(~inc_xbar_cnt[3])) ; |
| 3923 | |
| 3924 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar3 // sync reset active low |
| 3925 | (.din(xbar3_cnt_p[1:0]), .l1clk(l1clk), |
| 3926 | .scan_in(ff_xbar3_scanin), |
| 3927 | .scan_out(ff_xbar3_scanout), |
| 3928 | .clr(~dbb_rst_l), .en(change_xbar_cnt[3]), |
| 3929 | .dout(xbar3_cnt[1:0]), |
| 3930 | .siclk(siclk), |
| 3931 | .soclk(soclk) |
| 3932 | ); |
| 3933 | |
| 3934 | |
| 3935 | assign inc_xbar_cnt[4] = ( que_in_xbarq_c7[4] & ~xbarq_full[4] & ~cpx_l2t_grant_cx[4] ) ; |
| 3936 | assign dec_xbar_cnt[4] = ( ~que_in_xbarq_c7[4] & cpx_l2t_grant_cx[4] ) ; |
| 3937 | assign nochange_xbar_cnt[4] = ~dec_xbar_cnt[4] & ~inc_xbar_cnt[4] ; |
| 3938 | assign change_xbar_cnt[4] = ~nochange_xbar_cnt[4] ; |
| 3939 | assign xbar4_cnt_plus1[1:0] = xbar4_cnt[1:0] + 2'b1 ; |
| 3940 | assign xbar4_cnt_minus1[1:0] = xbar4_cnt[1:0] - 2'b1 ; |
| 3941 | |
| 3942 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar4_cnt |
| 3943 | ( .dout (xbar4_cnt_p[1:0]), |
| 3944 | .din0(xbar4_cnt_plus1[1:0]), .din1(xbar4_cnt_minus1[1:0]), |
| 3945 | .sel0(inc_xbar_cnt[4]), .sel1(~inc_xbar_cnt[4])) ; |
| 3946 | |
| 3947 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar4 // sync reset active low |
| 3948 | (.din(xbar4_cnt_p[1:0]), .l1clk(l1clk), |
| 3949 | .scan_in(ff_xbar4_scanin), |
| 3950 | .scan_out(ff_xbar4_scanout), |
| 3951 | .clr(~dbb_rst_l), .en(change_xbar_cnt[4]), |
| 3952 | .dout(xbar4_cnt[1:0]), |
| 3953 | .siclk(siclk), |
| 3954 | .soclk(soclk) |
| 3955 | ); |
| 3956 | |
| 3957 | |
| 3958 | assign inc_xbar_cnt[5] = ( que_in_xbarq_c7[5] & ~xbarq_full[5] & ~cpx_l2t_grant_cx[5] ) ; |
| 3959 | assign dec_xbar_cnt[5] = ( ~que_in_xbarq_c7[5] & cpx_l2t_grant_cx[5] ) ; |
| 3960 | assign nochange_xbar_cnt[5] = ~dec_xbar_cnt[5] & ~inc_xbar_cnt[5] ; |
| 3961 | assign change_xbar_cnt[5] = ~nochange_xbar_cnt[5] ; |
| 3962 | assign xbar5_cnt_plus1[1:0] = xbar5_cnt[1:0] + 2'b1 ; |
| 3963 | assign xbar5_cnt_minus1[1:0] = xbar5_cnt[1:0] - 2'b1 ; |
| 3964 | |
| 3965 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar5_cnt |
| 3966 | ( .dout (xbar5_cnt_p[1:0]), |
| 3967 | .din0(xbar5_cnt_plus1[1:0]), .din1(xbar5_cnt_minus1[1:0]), |
| 3968 | .sel0(inc_xbar_cnt[5]), .sel1(~inc_xbar_cnt[5])) ; |
| 3969 | |
| 3970 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar5 // sync reset active low |
| 3971 | (.din(xbar5_cnt_p[1:0]), .l1clk(l1clk), |
| 3972 | .scan_in(ff_xbar5_scanin), |
| 3973 | .scan_out(ff_xbar5_scanout), |
| 3974 | .clr(~dbb_rst_l), .en(change_xbar_cnt[5]), |
| 3975 | .dout(xbar5_cnt[1:0]), |
| 3976 | .siclk(siclk), |
| 3977 | .soclk(soclk) |
| 3978 | ); |
| 3979 | |
| 3980 | |
| 3981 | assign inc_xbar_cnt[6] = ( que_in_xbarq_c7[6] & ~xbarq_full[6] & ~cpx_l2t_grant_cx[6] ) ; |
| 3982 | assign dec_xbar_cnt[6] = ( ~que_in_xbarq_c7[6] & cpx_l2t_grant_cx[6] ) ; |
| 3983 | assign nochange_xbar_cnt[6] = ~dec_xbar_cnt[6] & ~inc_xbar_cnt[6] ; |
| 3984 | assign change_xbar_cnt[6] = ~nochange_xbar_cnt[6] ; |
| 3985 | assign xbar6_cnt_plus1[1:0] = xbar6_cnt[1:0] + 2'b1 ; |
| 3986 | assign xbar6_cnt_minus1[1:0] = xbar6_cnt[1:0] - 2'b1 ; |
| 3987 | |
| 3988 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar6_cnt |
| 3989 | ( .dout (xbar6_cnt_p[1:0]), |
| 3990 | .din0(xbar6_cnt_plus1[1:0]), .din1(xbar6_cnt_minus1[1:0]), |
| 3991 | .sel0(inc_xbar_cnt[6]), .sel1(~inc_xbar_cnt[6])) ; |
| 3992 | |
| 3993 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar6 // sync reset active low |
| 3994 | (.din(xbar6_cnt_p[1:0]), .l1clk(l1clk), |
| 3995 | .scan_in(ff_xbar6_scanin), |
| 3996 | .scan_out(ff_xbar6_scanout), |
| 3997 | .clr(~dbb_rst_l), .en(change_xbar_cnt[6]), |
| 3998 | .dout(xbar6_cnt[1:0]), |
| 3999 | .siclk(siclk), |
| 4000 | .soclk(soclk) |
| 4001 | ); |
| 4002 | |
| 4003 | |
| 4004 | assign inc_xbar_cnt[7] = ( que_in_xbarq_c7[7] & ~xbarq_full[7] & ~cpx_l2t_grant_cx[7] ) ; |
| 4005 | assign dec_xbar_cnt[7] = ( ~que_in_xbarq_c7[7] & cpx_l2t_grant_cx[7] ) ; |
| 4006 | assign nochange_xbar_cnt[7] = ~dec_xbar_cnt[7] & ~inc_xbar_cnt[7] ; |
| 4007 | assign change_xbar_cnt[7] = ~nochange_xbar_cnt[7] ; |
| 4008 | assign xbar7_cnt_plus1[1:0] = xbar7_cnt[1:0] + 2'b1 ; |
| 4009 | assign xbar7_cnt_minus1[1:0] = xbar7_cnt[1:0] - 2'b1 ; |
| 4010 | |
| 4011 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_xbar7_cnt |
| 4012 | ( .dout (xbar7_cnt_p[1:0]), |
| 4013 | .din0(xbar7_cnt_plus1[1:0]), .din1(xbar7_cnt_minus1[1:0]), |
| 4014 | .sel0(inc_xbar_cnt[7]), .sel1(~inc_xbar_cnt[7])) ; |
| 4015 | |
| 4016 | l2t_msff_ctl_macro__clr_1__en_1__width_2 ff_xbar7 // sync reset active low |
| 4017 | (.din(xbar7_cnt_p[1:0]), .l1clk(l1clk), |
| 4018 | .scan_in(ff_xbar7_scanin), |
| 4019 | .scan_out(ff_xbar7_scanout), |
| 4020 | .clr(~dbb_rst_l), .en(change_xbar_cnt[7]), |
| 4021 | .dout(xbar7_cnt[1:0]), |
| 4022 | .siclk(siclk), |
| 4023 | .soclk(soclk) |
| 4024 | ); |
| 4025 | |
| 4026 | |
| 4027 | |
| 4028 | |
| 4029 | /////////////////////////////////////////////////////////////// |
| 4030 | // |
| 4031 | // RDMA store completion state machine. |
| 4032 | // |
| 4033 | // An RDMA store WR8 or WR64 acks the src only after |
| 4034 | // all the L1$ invalidates have queued up at the crossbar. |
| 4035 | // There are 3 possible cases with stores. |
| 4036 | // |
| 4037 | // - Stores missing the L2 send a completion signal in C7 |
| 4038 | // - Store missing the L1 ( i.e. directory ) will send a |
| 4039 | // completion signal in C7. |
| 4040 | // - Stores hitting the L1 will send a completion signal |
| 4041 | // after making a request to the crossbar. |
| 4042 | // ACK_WAIT state is hit on completion. |
| 4043 | // ACK_CCX_REQ_ST is hit on a completion followed by a directory hit. |
| 4044 | // The following table represents all state transitions in this |
| 4045 | // FSM. |
| 4046 | // |
| 4047 | //--------------------------------------------------------------------------- |
| 4048 | // STATES ACK_IDLE ACK_WAIT ACK_CCX_REQ |
| 4049 | //--------------------------------------------------------------------------- |
| 4050 | // ACK_IDLE ~comp_c5 comp_c5 never |
| 4051 | // |
| 4052 | //--------------------------------------------------------------------------- |
| 4053 | // ACK_WAIT ~hit_c6 directory |
| 4054 | // or no never hit_c6 |
| 4055 | // directory |
| 4056 | // hit |
| 4057 | //--------------------------------------------------------------------------- |
| 4058 | // ACK_CCX_REQ req_cq & never ~(rdma_inv |
| 4059 | // rdma_invtoxbar to xbar & req) |
| 4060 | //--------------------------------------------------------------------------- |
| 4061 | // |
| 4062 | // oqu_st_complete_c7 if there is a transition |
| 4063 | // to the ACK_IDLE state from |
| 4064 | // ACK_WAIT or ACK_CCX_REQ |
| 4065 | // |
| 4066 | /////////////////////////////////////////////////////////////// |
| 4067 | |
| 4068 | |
| 4069 | l2t_msff_ctl_macro__width_1 ff_rdma_wr_comp_c5 |
| 4070 | (.din(tag_rdma_wr_comp_c4), .l1clk(l1clk), |
| 4071 | .scan_in(ff_rdma_wr_comp_c5_scanin), |
| 4072 | .scan_out(ff_rdma_wr_comp_c5_scanout), |
| 4073 | .dout(rdma_wr_comp_c5), |
| 4074 | .siclk(siclk), |
| 4075 | .soclk(soclk) |
| 4076 | ); |
| 4077 | |
| 4078 | // BS 03/11/04 extra cycle for mem access |
| 4079 | |
| 4080 | l2t_msff_ctl_macro__width_1 ff_rdma_wr_comp_c52 |
| 4081 | (.din(rdma_wr_comp_c5), .l1clk(l1clk), |
| 4082 | .scan_in(ff_rdma_wr_comp_c52_scanin), |
| 4083 | .scan_out(ff_rdma_wr_comp_c52_scanout), |
| 4084 | .dout(rdma_wr_comp_c52), |
| 4085 | .siclk(siclk), |
| 4086 | .soclk(soclk) |
| 4087 | ); |
| 4088 | |
| 4089 | assign dir_hit_c6 = |(dirvec_dirdp_req_vec_c6); |
| 4090 | |
| 4091 | assign rdma_req_sent_c7 = |(l2t_cpx_req_cq_dup) & |
| 4092 | rdma_to_xbarq_c7 ; |
| 4093 | |
| 4094 | assign rdma_state_in[`ACK_IDLE] = ( |
| 4095 | (rdma_state[`ACK_WAIT] & ~dir_hit_c6) | // NO L1 INVAL |
| 4096 | (rdma_state[`ACK_CCX_REQ] & |
| 4097 | rdma_req_sent_c7 )| // L1 INVAL SENT |
| 4098 | rdma_state[`ACK_IDLE] |
| 4099 | ) & ~rdma_wr_comp_c52 ; // completion of a write // BS 03/11/04 extra cycle for mem access |
| 4100 | |
| 4101 | assign ack_idle_state_in_l = ~rdma_state_in[`ACK_IDLE] ; |
| 4102 | |
| 4103 | l2t_msff_ctl_macro__clr_1__width_1 ff_rdma_req_state_0 // sync reset active low |
| 4104 | (.din(ack_idle_state_in_l), .l1clk(l1clk), |
| 4105 | .scan_in(ff_rdma_req_state_0_scanin), |
| 4106 | .scan_out(ff_rdma_req_state_0_scanout), |
| 4107 | .clr(~dbb_rst_l), |
| 4108 | .dout(ack_idle_state_l), |
| 4109 | .siclk(siclk), |
| 4110 | .soclk(soclk) |
| 4111 | ); |
| 4112 | |
| 4113 | assign rdma_state[`ACK_IDLE] = ~ack_idle_state_l ; |
| 4114 | |
| 4115 | |
| 4116 | assign rdma_state_in[`ACK_WAIT] = |
| 4117 | (rdma_state[`ACK_IDLE] & rdma_wr_comp_c52 ) ; // BS 03/11/04 extra cycle for mem access |
| 4118 | |
| 4119 | |
| 4120 | assign rdma_state_in[`ACK_CCX_REQ] = ( |
| 4121 | (rdma_state[`ACK_WAIT] & dir_hit_c6 ) | |
| 4122 | // l1 INVAL to BE SENT |
| 4123 | rdma_state[`ACK_CCX_REQ]) & |
| 4124 | ~rdma_req_sent_c7 ; |
| 4125 | |
| 4126 | l2t_msff_ctl_macro__clr_1__width_2 ff_rdma_state // sync reset active low |
| 4127 | (.din(rdma_state_in[`ACK_CCX_REQ:`ACK_WAIT]), |
| 4128 | .scan_in(ff_rdma_state_scanin), |
| 4129 | .scan_out(ff_rdma_state_scanout), |
| 4130 | .l1clk(l1clk), .clr(~dbb_rst_l), |
| 4131 | .dout(rdma_state[`ACK_CCX_REQ:`ACK_WAIT]), |
| 4132 | .siclk(siclk), |
| 4133 | .soclk(soclk) |
| 4134 | |
| 4135 | ); |
| 4136 | |
| 4137 | |
| 4138 | assign oqu_st_complete_c6 = rdma_state_in[`ACK_IDLE] & |
| 4139 | ~rdma_state[`ACK_IDLE] ; |
| 4140 | |
| 4141 | l2t_msff_ctl_macro__width_1 ff_oqu_st_complete_c6 |
| 4142 | (.din(oqu_st_complete_c6), .l1clk(l1clk), |
| 4143 | .scan_in(ff_oqu_st_complete_c6_scanin), |
| 4144 | .scan_out(ff_oqu_st_complete_c6_scanout), |
| 4145 | .dout(oqu_st_complete_c7), |
| 4146 | .siclk(siclk), |
| 4147 | .soclk(soclk) |
| 4148 | ); |
| 4149 | |
| 4150 | |
| 4151 | |
| 4152 | |
| 4153 | |
| 4154 | //////////////////////////////////////// |
| 4155 | // Generation of mux selects for |
| 4156 | // oque. This was previously mbist_done in |
| 4157 | // oq_dctl. Now that logic has been |
| 4158 | // merged into oqu. (11/05/2002). |
| 4159 | //////////////////////////////////////// |
| 4160 | |
| 4161 | |
| 4162 | |
| 4163 | |
| 4164 | |
| 4165 | //////////////////////////////////////////////////////////////////////////////// |
| 4166 | // staging flops. |
| 4167 | |
| 4168 | // BS 03/11/04 extra cycle for mem access |
| 4169 | |
| 4170 | l2t_msff_ctl_macro__width_1 ff_store_inst_c52 |
| 4171 | (.dout (store_inst_c52), |
| 4172 | .scan_in(ff_store_inst_c52_scanin), |
| 4173 | .scan_out(ff_store_inst_c52_scanout), |
| 4174 | .din (tag_store_inst_c5), |
| 4175 | .l1clk (l1clk), |
| 4176 | .siclk(siclk), |
| 4177 | .soclk(soclk) |
| 4178 | |
| 4179 | |
| 4180 | ) ; |
| 4181 | |
| 4182 | |
| 4183 | l2t_msff_ctl_macro__width_1 ff_store_inst_c6 |
| 4184 | (.dout (store_inst_c6), |
| 4185 | .scan_in(ff_store_inst_c6_scanin), |
| 4186 | .scan_out(ff_store_inst_c6_scanout), |
| 4187 | .din (store_inst_c52), |
| 4188 | .l1clk (l1clk), |
| 4189 | .siclk(siclk), |
| 4190 | .soclk(soclk) |
| 4191 | |
| 4192 | |
| 4193 | ) ; |
| 4194 | l2t_msff_ctl_macro__width_1 ff_store_inst_c7 |
| 4195 | (.dout (store_inst_c7), |
| 4196 | .scan_in(ff_store_inst_c7_scanin), |
| 4197 | .scan_out(ff_store_inst_c7_scanout), |
| 4198 | .din (store_inst_c6), |
| 4199 | .l1clk (l1clk), |
| 4200 | .siclk(siclk), |
| 4201 | .soclk(soclk) |
| 4202 | |
| 4203 | |
| 4204 | ) ; |
| 4205 | |
| 4206 | |
| 4207 | l2t_msff_ctl_macro__width_1 ff_csr_reg_rd_en_c8 |
| 4208 | (.dout (csr_reg_rd_en_c8), |
| 4209 | .scan_in(ff_csr_reg_rd_en_c8_scanin), |
| 4210 | .scan_out(ff_csr_reg_rd_en_c8_scanout), |
| 4211 | .din (arb_csr_rd_en_c7), |
| 4212 | .l1clk (l1clk), |
| 4213 | .siclk(siclk), |
| 4214 | .soclk(soclk) |
| 4215 | |
| 4216 | |
| 4217 | ) ; |
| 4218 | |
| 4219 | |
| 4220 | l2t_msff_ctl_macro__width_1 ff_sel_inval_c7 |
| 4221 | (.dout (oqctl_sel_inval_c7), |
| 4222 | .scan_in(ff_sel_inval_c7_scanin), |
| 4223 | .scan_out(ff_sel_inval_c7_scanout), |
| 4224 | .din (oqu_sel_inval_c6), |
| 4225 | .l1clk (l1clk), |
| 4226 | .siclk(siclk), |
| 4227 | .soclk(soclk) |
| 4228 | |
| 4229 | |
| 4230 | ) ; |
| 4231 | |
| 4232 | |
| 4233 | l2t_msff_ctl_macro__width_1 ff_fwd_req_vld_ld_c7 |
| 4234 | (.dout (fwd_req_vld_ld_c7), |
| 4235 | .scan_in(ff_fwd_req_vld_ld_c7_scanin), |
| 4236 | .scan_out(ff_fwd_req_vld_ld_c7_scanout), |
| 4237 | .din (tag_fwd_req_ld_c6), |
| 4238 | .l1clk (l1clk), |
| 4239 | .siclk(siclk), |
| 4240 | .soclk(soclk) |
| 4241 | |
| 4242 | |
| 4243 | ) ; |
| 4244 | |
| 4245 | |
| 4246 | //////////////////////////////////////////////////////////////////////////////// |
| 4247 | // DATA Diagnostic access. |
| 4248 | // remember tag_fwd_req_ld_c6 is only asserted for non-diag accesses. |
| 4249 | // "oqu_mux1_sel_data_c7[3:0]" is used for select signal for a 39 bit 4to1 MUX in |
| 4250 | // OQDP that selects among Diag data, Tag Diag data, VUAD Diag data & Interrupt |
| 4251 | // return data. |
| 4252 | //////////////////////////////////////////////////////////////////////////////// |
| 4253 | l2t_msff_ctl_macro__width_1 ff_diag_data_sel_c7 |
| 4254 | (.dout (diag_data_sel_c7), |
| 4255 | .scan_in(ff_diag_data_sel_c7_scanin), |
| 4256 | .scan_out(ff_diag_data_sel_c7_scanout), |
| 4257 | .din (arb_inst_l2data_vld_c6), |
| 4258 | .l1clk (l1clk), |
| 4259 | .siclk(siclk), |
| 4260 | .soclk(soclk) |
| 4261 | |
| 4262 | |
| 4263 | ) ; |
| 4264 | |
| 4265 | |
| 4266 | assign diag_lddata_sel_c7 = (diag_data_sel_c7 & ~store_inst_c7) | |
| 4267 | tag_fwd_req_ld_c6 ; |
| 4268 | |
| 4269 | |
| 4270 | l2t_msff_ctl_macro__width_1 ff_diag_lddata_sel_c8 |
| 4271 | (.dout (diag_lddata_sel_c8), |
| 4272 | .scan_in(ff_diag_lddata_sel_c8_scanin), |
| 4273 | .scan_out(ff_diag_lddata_sel_c8_scanout), |
| 4274 | .din (diag_lddata_sel_c7), |
| 4275 | .l1clk (l1clk), |
| 4276 | .siclk(siclk), |
| 4277 | .soclk(soclk) |
| 4278 | |
| 4279 | |
| 4280 | ) ; |
| 4281 | |
| 4282 | |
| 4283 | assign oqu_mux1_sel_data_c7[0] = diag_lddata_sel_c8; |
| 4284 | |
| 4285 | //////////////////////////////////////// |
| 4286 | // Tag Diagnostic access. |
| 4287 | //////////////////////////////////////// |
| 4288 | l2t_msff_ctl_macro__width_1 ff_diag_tag_sel_c7 |
| 4289 | (.dout (diag_tag_sel_c7), |
| 4290 | .scan_in(ff_diag_tag_sel_c7_scanin), |
| 4291 | .scan_out(ff_diag_tag_sel_c7_scanout), |
| 4292 | .din (arb_inst_l2tag_vld_c6), |
| 4293 | .l1clk (l1clk), |
| 4294 | .siclk(siclk), |
| 4295 | .soclk(soclk) |
| 4296 | |
| 4297 | |
| 4298 | ) ; |
| 4299 | |
| 4300 | |
| 4301 | assign diag_ldtag_sel_c7 = diag_tag_sel_c7 & ~store_inst_c7 ; |
| 4302 | |
| 4303 | |
| 4304 | l2t_msff_ctl_macro__width_1 ff_diag_ldtag_sel_c8 |
| 4305 | (.dout (diag_ldtag_sel_c8), |
| 4306 | .scan_in(ff_diag_ldtag_sel_c8_scanin), |
| 4307 | .scan_out(ff_diag_ldtag_sel_c8_scanout), |
| 4308 | .din (diag_ldtag_sel_c7), |
| 4309 | .l1clk (l1clk), |
| 4310 | .siclk(siclk), |
| 4311 | .soclk(soclk) |
| 4312 | |
| 4313 | |
| 4314 | ) ; |
| 4315 | |
| 4316 | |
| 4317 | assign oqu_mux1_sel_data_c7[1] = diag_ldtag_sel_c8; |
| 4318 | |
| 4319 | //////////////////////////////////////// |
| 4320 | // VUAD Diagnostic access. |
| 4321 | //////////////////////////////////////// |
| 4322 | l2t_msff_ctl_macro__width_1 ff_diag_vuad_sel_c7 |
| 4323 | (.dout (diag_vuad_sel_c7), |
| 4324 | .scan_in(ff_diag_vuad_sel_c7_scanin), |
| 4325 | .scan_out(ff_diag_vuad_sel_c7_scanout), |
| 4326 | .din (arb_inst_l2vuad_vld_c6), |
| 4327 | .l1clk (l1clk), |
| 4328 | .siclk(siclk), |
| 4329 | .soclk(soclk) |
| 4330 | |
| 4331 | |
| 4332 | ) ; |
| 4333 | |
| 4334 | assign diag_ldvuad_sel_c7 = diag_vuad_sel_c7 & ~store_inst_c7 ; |
| 4335 | |
| 4336 | |
| 4337 | l2t_msff_ctl_macro__width_1 ff_diag_ldvuad_sel_c8 |
| 4338 | (.dout (diag_ldvuad_sel_c8), |
| 4339 | .scan_in(ff_diag_ldvuad_sel_c8_scanin), |
| 4340 | .scan_out(ff_diag_ldvuad_sel_c8_scanout), |
| 4341 | .din (diag_ldvuad_sel_c7), |
| 4342 | .l1clk (l1clk), |
| 4343 | .siclk(siclk), |
| 4344 | .soclk(soclk) |
| 4345 | |
| 4346 | |
| 4347 | ) ; |
| 4348 | |
| 4349 | assign oqu_mux1_sel_data_c7[2] = diag_ldvuad_sel_c8 ; |
| 4350 | |
| 4351 | //////////////////////////////////////// |
| 4352 | // default mux sel |
| 4353 | //////////////////////////////////////// |
| 4354 | assign diag_def_sel_c7 = ~(diag_lddata_sel_c7 | diag_ldtag_sel_c7 | // int 5.0 changes |
| 4355 | diag_ldvuad_sel_c7) ; |
| 4356 | |
| 4357 | l2t_msff_ctl_macro__width_1 ff_diag_def_sel_c8 |
| 4358 | (.dout (diag_def_sel_c8), |
| 4359 | .scan_in(ff_diag_def_sel_c8_scanin), |
| 4360 | .scan_out(ff_diag_def_sel_c8_scanout), |
| 4361 | .din (diag_def_sel_c7), |
| 4362 | .l1clk (l1clk), |
| 4363 | .siclk(siclk), |
| 4364 | .soclk(soclk) |
| 4365 | |
| 4366 | |
| 4367 | ) ; |
| 4368 | |
| 4369 | assign oqu_mux1_sel_data_c7[3] = diag_def_sel_c8 ; |
| 4370 | |
| 4371 | |
| 4372 | //////////////////////////////////////////////////////////////////////////////// |
| 4373 | assign oqu_mux_csr_sel_c7 = csr_reg_rd_en_c8 ; // buferred here. |
| 4374 | |
| 4375 | |
| 4376 | //////////////////////////////////////////////////////////////////////////////// |
| 4377 | // mux select to choose between |
| 4378 | // inval and ret data for oqarray_datain |
| 4379 | //////////////////////////////////////////////////////////////////////////////// |
| 4380 | assign oqu_sel_inval_c7 = oqctl_sel_inval_c7 | diag_lddata_sel_c8 | |
| 4381 | diag_ldtag_sel_c8 | diag_ldvuad_sel_c8 | |
| 4382 | fwd_req_vld_ld_c7 ; |
| 4383 | |
| 4384 | |
| 4385 | //////////////////////////////////////////////////////////////////////////////// |
| 4386 | // mux select for 3-1 mux in oque. |
| 4387 | // sel0 .... old packet |
| 4388 | // sel1 .... oq data |
| 4389 | // sel2 .... def. |
| 4390 | //////////////////////////////////////////////////////////////////////////////// |
| 4391 | |
| 4392 | assign oqu_out_mux1_sel_c7[0] = oqu_sel_old_req_c7 ; |
| 4393 | assign oqu_out_mux1_sel_c7[1] = oqu_sel_oq_c7 ; |
| 4394 | assign oqu_out_mux1_sel_c7[2] = ~(oqu_sel_old_req_c7 | oqu_sel_oq_c7 ) ; |
| 4395 | |
| 4396 | //////////////////////////////////////////////////////////////////////////////// |
| 4397 | // mux2 select for 3-1 mux in oque. |
| 4398 | // sel0.....oq,old or prev data |
| 4399 | // sel1.....inval data |
| 4400 | // sel2.....def |
| 4401 | //////////////////////////////////////////////////////////////////////////////// |
| 4402 | assign sel_old_data_c7 = (oqu_sel_old_req_c7 | oqu_sel_oq_c7 | |
| 4403 | oqu_prev_data_c7); |
| 4404 | |
| 4405 | assign oqu_out_mux2_sel_c7[0] = sel_old_data_c7 ; |
| 4406 | assign oqu_out_mux2_sel_c7[1] = oqu_sel_inval_c7 & ~sel_old_data_c7 ; |
| 4407 | assign oqu_out_mux2_sel_c7[2] = ~(sel_old_data_c7 | oqu_sel_inval_c7) ; |
| 4408 | |
| 4409 | |
| 4410 | |
| 4411 | //////////////////////////////////////////////////////////////////////////////// |
| 4412 | // Directory in L2 is arranged in the form of 32 Panels (8 Rows x 4 Columns). |
| 4413 | // Each panel contains 1 Set (4 Ways) for each of the 8 CPU. A Panel is selected |
| 4414 | // for Camming based on address bit <4,5,8,9,10> for the D$ Cam and address bit |
| 4415 | // <5,8,9,10,11> for the I$ Cam. In D$ bit <10,9,8> is used for selecting a Row |
| 4416 | // and bit <5,4> is used for selecting the a Column. In I$ bit <10,9,8> is used |
| 4417 | // for selecting a Row and bit <5,11> is used for selecting a Column. |
| 4418 | // |
| 4419 | // I$ and D$ Cam produce a 128 bit output which corresponds to the CAM hit or |
| 4420 | // miss output bit for a Row of 4 Panels (each panel have 32 entry, 4 way of a |
| 4421 | // set for each of the 8 cpu). In case of an eviction all the 128 bit of the |
| 4422 | // D$ Cam and only 64 bits of the I$ Cam will be valid. In case of Load only |
| 4423 | // 4 bit of the I$ cam output will be valid (For Load, if the data requested by |
| 4424 | // a particular cpu is also present in the I$ of the same processor then that |
| 4425 | // data in L1's I$ must be invalidated. So for a load only one panel in |
| 4426 | // I$ Cam will be Cammed and only bits corresponding to that particular cpu will |
| 4427 | // be relevant). In case of Imiss, in first cycle one set of the 4 bit of the |
| 4428 | // D$ Cam output will be valid and in the second cycle another set of the 4 bit |
| 4429 | // of the D$ Cam output will be valid. |
| 4430 | // To mux out relevant 4 bits out of the 128 bit output from the I$ and D$ Cam |
| 4431 | // Three stage muxing is mbist_done. First 8to1 muxing is mbist_done in 2 stages (first |
| 4432 | // 4to1 and then 2to1) to mux out all the 16 bits corresponding a particular cpu. |
| 4433 | // This muxing is mbist_done based on the cpu id. Then 4:1 muxing is mbist_done to select a |
| 4434 | // particular column out of the four column, this is mbist_done based on the address |
| 4435 | // bit <5,4> for the D$ and address bit <5,11> for the I$. |
| 4436 | // |
| 4437 | // oqu_sel_mux1_c6[3:0], oqu_sel_mux2_c6[3:0] and oqu_sel_mux3_c6 is used for the 8to1 |
| 4438 | // Muxing. oqu_sel_mux1_c6[3:0] & oqu_sel_mux2_c6[3:0] is used for the 4to1 muxing in |
| 4439 | // the first stage and oqu_sel_mux3_c6 is used to do 2to1 muxing in the second |
| 4440 | // stage. |
| 4441 | // oqu_mux_vec_sel_c6[3:0] is used to do final 4to1 Muxing. |
| 4442 | // |
| 4443 | //////////////////////////////////////////////////////////////////////////////// |
| 4444 | // the arbdec_arbdp_cpuid_c5 requires ~10 gates of setup. |
| 4445 | |
| 4446 | // BS 03/11/04 extra cycle for mem access |
| 4447 | |
| 4448 | l2t_msff_ctl_macro__width_3 ff_dirvec_cpuid_c52 |
| 4449 | (.dout (inst_cpuid_c52[2:0]), |
| 4450 | // .din (arbdec_arbdp_cpuid_c5[2:0]), |
| 4451 | .scan_in(ff_dirvec_cpuid_c52_scanin), |
| 4452 | .scan_out(ff_dirvec_cpuid_c52_scanout), |
| 4453 | .din (arb_cpuid_c5[2:0]), //the mapped cpuid taking into account PA[8:7] in Partial bank Mode |
| 4454 | // needs to be used to generate oqu_mux_sel[1/2/3] to dirvec. |
| 4455 | // this is because to generate the i$ and D$ mutual invals for load |
| 4456 | // and ifill returns, the hit way sel from the dc and ic dirs (way_way_vld*) |
| 4457 | // reflect the remapped cpuid . hence the oqu_mux_sels need to be |
| 4458 | // generated based on the remapped cpuid also. However the remapped cpuid |
| 4459 | // is not used to generate the cpx request. Fix for bug 92557 |
| 4460 | .l1clk (l1clk), |
| 4461 | .siclk(siclk), |
| 4462 | .soclk(soclk) |
| 4463 | |
| 4464 | |
| 4465 | ) ; |
| 4466 | |
| 4467 | |
| 4468 | l2t_msff_ctl_macro__width_3 ff_dirvec_cpuid_c6 |
| 4469 | (.dout (inst_cpuid_c6[2:0]), |
| 4470 | .scan_in(ff_dirvec_cpuid_c6_scanin), |
| 4471 | .scan_out(ff_dirvec_cpuid_c6_scanout), |
| 4472 | .din (inst_cpuid_c52[2:0]), |
| 4473 | .l1clk (l1clk), |
| 4474 | .siclk(siclk), |
| 4475 | .soclk(soclk) |
| 4476 | |
| 4477 | |
| 4478 | ) ; |
| 4479 | |
| 4480 | l2t_mux_ctl_macro__mux_aonpe__ports_2__width_3 mux_dirvec_cpuid_c52 |
| 4481 | (.dout (cpuid_c52[2:0]), |
| 4482 | .din0 (inst_cpuid_c52[2:0]), .sel0 (~imiss1_out_c6), |
| 4483 | .din1 (inst_cpuid_c6[2:0]), .sel1 (imiss1_out_c6) |
| 4484 | ) ; |
| 4485 | |
| 4486 | |
| 4487 | assign dec_cpuid_c52[0] = (cpuid_c52 == 3'd0) ; |
| 4488 | assign dec_cpuid_c52[1] = (cpuid_c52 == 3'd1) ; |
| 4489 | assign dec_cpuid_c52[2] = (cpuid_c52 == 3'd2) ; |
| 4490 | assign dec_cpuid_c52[3] = (cpuid_c52 == 3'd3) ; |
| 4491 | assign dec_cpuid_c52[4] = (cpuid_c52 == 3'd4) ; |
| 4492 | assign dec_cpuid_c52[5] = (cpuid_c52 == 3'd5) ; |
| 4493 | assign dec_cpuid_c52[6] = (cpuid_c52 == 3'd6) ; |
| 4494 | |
| 4495 | l2t_msff_ctl_macro__width_7 ff_dec_cpuid_c6 // int 5.0 changes |
| 4496 | (.dout (dec_cpuid_c6[6:0]), |
| 4497 | .scan_in(ff_dec_cpuid_c6_scanin), |
| 4498 | .scan_out(ff_dec_cpuid_c6_scanout), |
| 4499 | .din (dec_cpuid_c52[6:0]), |
| 4500 | .l1clk (l1clk), |
| 4501 | .siclk(siclk), |
| 4502 | .soclk(soclk) |
| 4503 | |
| 4504 | |
| 4505 | ) ; |
| 4506 | |
| 4507 | |
| 4508 | assign oqu_sel_mux1_c6[0] = dec_cpuid_c6[0] ; |
| 4509 | assign oqu_sel_mux1_c6[1] = dec_cpuid_c6[1] ; |
| 4510 | assign oqu_sel_mux1_c6[2] = dec_cpuid_c6[2] ; |
| 4511 | assign oqu_sel_mux1_c6[3] = ~(dec_cpuid_c6[0] | dec_cpuid_c6[1] | dec_cpuid_c6[2]) ; |
| 4512 | |
| 4513 | assign oqu_sel_mux2_c6[0] = dec_cpuid_c6[4] ; |
| 4514 | assign oqu_sel_mux2_c6[1] = dec_cpuid_c6[5] ; |
| 4515 | assign oqu_sel_mux2_c6[2] = dec_cpuid_c6[6] ; |
| 4516 | assign oqu_sel_mux2_c6[3] = ~(dec_cpuid_c6[4] | dec_cpuid_c6[5] | dec_cpuid_c6[6]); |
| 4517 | |
| 4518 | assign oqu_sel_mux3_c6 = |(dec_cpuid_c6[3:0]) ; |
| 4519 | |
| 4520 | |
| 4521 | |
| 4522 | //////////////////////////////////////////////////////////////////////////////// |
| 4523 | // mux selects for the mux that selects the data |
| 4524 | // for way-wayvld bits of the cpx packet. |
| 4525 | |
| 4526 | l2t_msff_ctl_macro__width_4 ff_lkup_bank_ena_icd_c5 |
| 4527 | (.dout (lkup_bank_ena_icd_c5[3:0]), |
| 4528 | .scan_in(ff_lkup_bank_ena_icd_c5_scanin), |
| 4529 | .scan_out(ff_lkup_bank_ena_icd_c5_scanout), |
| 4530 | .din (lkup_bank_ena_icd_c4[3:0]), |
| 4531 | .l1clk (l1clk), |
| 4532 | .siclk(siclk), |
| 4533 | .soclk(soclk) |
| 4534 | |
| 4535 | |
| 4536 | ) ; |
| 4537 | |
| 4538 | l2t_msff_ctl_macro__width_4 ff_lkup_bank_ena_dcd_c5 |
| 4539 | (.dout (lkup_bank_ena_dcd_c5[3:0]), |
| 4540 | .scan_in(ff_lkup_bank_ena_dcd_c5_scanin), |
| 4541 | .scan_out(ff_lkup_bank_ena_dcd_c5_scanout), |
| 4542 | .din (lkup_bank_ena_dcd_c4[3:0]), |
| 4543 | .l1clk (l1clk), |
| 4544 | .siclk(siclk), |
| 4545 | .soclk(soclk) |
| 4546 | |
| 4547 | |
| 4548 | ) ; |
| 4549 | |
| 4550 | |
| 4551 | assign mux_vec_sel_c5[0] = (lkup_bank_ena_icd_c5[0] | lkup_bank_ena_dcd_c5[0] | |
| 4552 | lkup_bank_ena_icd_c5[1]) ; |
| 4553 | assign mux_vec_sel_c5[1] = lkup_bank_ena_dcd_c5[1] & ~mux_vec_sel_c5[0] ; |
| 4554 | assign mux_vec_sel_c5[2] = (lkup_bank_ena_icd_c5[2] | lkup_bank_ena_dcd_c5[2] | |
| 4555 | lkup_bank_ena_icd_c5[3]) & |
| 4556 | ~(mux_vec_sel_c5[0] | mux_vec_sel_c5[1]) ; |
| 4557 | assign mux_vec_sel_c5[3] = ~(mux_vec_sel_c5[0] | mux_vec_sel_c5[1] | |
| 4558 | mux_vec_sel_c5[2]) ; |
| 4559 | |
| 4560 | // BS 03/11/04 extra cycle for mem access |
| 4561 | l2t_msff_ctl_macro__width_4 ff_mux_vec_sel_c52 |
| 4562 | (.dout (mux_vec_sel_c52[3:0]), |
| 4563 | .scan_in(ff_mux_vec_sel_c52_scanin), |
| 4564 | .scan_out(ff_mux_vec_sel_c52_scanout), |
| 4565 | .din (mux_vec_sel_c5[3:0]), |
| 4566 | .l1clk (l1clk), |
| 4567 | .siclk(siclk), |
| 4568 | .soclk(soclk) |
| 4569 | |
| 4570 | |
| 4571 | ) ; |
| 4572 | |
| 4573 | |
| 4574 | l2t_msff_ctl_macro__width_4 ff_mux_vec_sel_c6 |
| 4575 | (.dout (mux_vec_sel_c6_unqual[3:0]), |
| 4576 | .scan_in(ff_mux_vec_sel_c6_scanin), |
| 4577 | .scan_out(ff_mux_vec_sel_c6_scanout), |
| 4578 | .din (mux_vec_sel_c52[3:0]), |
| 4579 | .l1clk (l1clk), |
| 4580 | .siclk(siclk), |
| 4581 | .soclk(soclk) |
| 4582 | |
| 4583 | |
| 4584 | ) ; |
| 4585 | |
| 4586 | assign oqu_mux_vec_sel_c6[0] = mux_vec_sel_c6_unqual[0]; |
| 4587 | assign oqu_mux_vec_sel_c6[1] = mux_vec_sel_c6_unqual[1]; |
| 4588 | assign oqu_mux_vec_sel_c6[2] = mux_vec_sel_c6_unqual[2]; |
| 4589 | assign oqu_mux_vec_sel_c6[3] = mux_vec_sel_c6_unqual[3]; |
| 4590 | |
| 4591 | |
| 4592 | |
| 4593 | // fixscan start: |
| 4594 | assign spares_scanin = scan_in ; |
| 4595 | assign reset_flop_scanin = spares_scanout ; |
| 4596 | assign ff_int_bcast_c52_scanin = reset_flop_scanout ; |
| 4597 | assign ff_int_bcast_c6_scanin = ff_int_bcast_c52_scanout ; |
| 4598 | assign ff_dec_cpu_c52_scanin = ff_int_bcast_c6_scanout ; |
| 4599 | assign ff_dec_cpu_c6_scanin = ff_dec_cpu_c52_scanout ; |
| 4600 | assign ff_dec_cpu_c7_scanin = ff_dec_cpu_c6_scanout ; |
| 4601 | assign ff_sel_dec_vec_c7_scanin = ff_dec_cpu_c7_scanout ; |
| 4602 | assign ff_diag_acc_c8_scanin = ff_sel_dec_vec_c7_scanout; |
| 4603 | assign ff_sel_stinv_req_c52_scanin = ff_diag_acc_c8_scanout ; |
| 4604 | assign ff_sel_stinv_req_c6_scanin = ff_sel_stinv_req_c52_scanout; |
| 4605 | assign ff_sel_inv_vec_c52_scanin = ff_sel_stinv_req_c6_scanout; |
| 4606 | assign ff_sel_inv_vec_c6_scanin = ff_sel_inv_vec_c52_scanout; |
| 4607 | assign ff_sel_dec_vec_c52_scanin = ff_sel_inv_vec_c6_scanout; |
| 4608 | assign ff_sel_dec_vec_c5_d1_scanin = ff_sel_dec_vec_c52_scanout; |
| 4609 | assign ff_req_out_c7_scanin = ff_sel_dec_vec_c5_d1_scanout; |
| 4610 | assign ff_imiss1_out_c52_scanin = ff_req_out_c7_scanout ; |
| 4611 | assign ff_imiss1_out_c6_scanin = ff_imiss1_out_c52_scanout; |
| 4612 | assign ff_imiss1_out_c7_scanin = ff_imiss1_out_c6_scanout ; |
| 4613 | assign ff_imiss1_out_c8_scanin = ff_imiss1_out_c7_scanout ; |
| 4614 | assign ff_imiss2_req_vec_c7_scanin = ff_imiss1_out_c8_scanout ; |
| 4615 | assign ff_c6_req_vld_scanin = ff_imiss2_req_vec_c7_scanout; |
| 4616 | assign ff_sel_c7_req_d1_scanin = ff_c6_req_vld_scanout ; |
| 4617 | assign ff_rdma_inv_c7_scanin = ff_sel_c7_req_d1_scanout ; |
| 4618 | assign ff_xbar_req_c7_scanin = ff_rdma_inv_c7_scanout ; |
| 4619 | assign ff_imiss1_to_xbarq_c7_scanin = ff_xbar_req_c7_scanout ; |
| 4620 | assign ff_rdma_to_xbarq_c7_scanin = ff_imiss1_to_xbarq_c7_scanout; |
| 4621 | assign ff_imiss2_to_xbarq_c7_scanin = ff_rdma_to_xbarq_c7_scanout; |
| 4622 | assign ff_bcast_req_c6_scanin = ff_imiss2_to_xbarq_c7_scanout; |
| 4623 | assign ff_bcast_to_xbar_c7_scanin = ff_bcast_req_c6_scanout ; |
| 4624 | assign ff_allow_req_c7_scanin = ff_bcast_to_xbar_c7_scanout; |
| 4625 | assign ff_l2t_cpx_req_cq_c7_scanin = ff_allow_req_c7_scanout ; |
| 4626 | assign ff_l2t_cpx_atom_cq_c7_scanin = ff_l2t_cpx_req_cq_c7_scanout; |
| 4627 | assign ff_l2t_cpx_req_cq_c7_dup_scanin = ff_l2t_cpx_atom_cq_c7_scanout; |
| 4628 | assign ff_fwd_req_ret_c52_scanin = ff_l2t_cpx_req_cq_c7_dup_scanout; |
| 4629 | assign ff_fwd_req_ret_c6_scanin = ff_fwd_req_ret_c52_scanout; |
| 4630 | assign ff_fwd_req_ret_c7_scanin = ff_fwd_req_ret_c6_scanout; |
| 4631 | assign ff_int_ack_c52_scanin = ff_fwd_req_ret_c7_scanout; |
| 4632 | assign ff_int_ack_c6_scanin = ff_int_ack_c52_scanout ; |
| 4633 | assign ff_int_ack_c7_scanin = ff_int_ack_c6_scanout ; |
| 4634 | assign ff_ld_hit_c52_scanin = ff_int_ack_c7_scanout ; |
| 4635 | assign ff_ld_hit_c6_scanin = ff_ld_hit_c52_scanout ; |
| 4636 | assign ff_ld_hit_c7_scanin = ff_ld_hit_c6_scanout ; |
| 4637 | assign ff_st_req_c52_scanin = ff_ld_hit_c7_scanout ; |
| 4638 | assign ff_st_req_c6_scanin = ff_st_req_c52_scanout ; |
| 4639 | assign ff_st_req_c7_scanin = ff_st_req_c6_scanout ; |
| 4640 | assign ff_inval_req_c52_scanin = ff_st_req_c7_scanout ; |
| 4641 | assign ff_inval_req_c6_scanin = ff_inval_req_c52_scanout ; |
| 4642 | assign ff_inval_req_c7_scanin = ff_inval_req_c6_scanout ; |
| 4643 | assign ff_strst_ack_c52_scanin = ff_inval_req_c7_scanout ; |
| 4644 | assign ff_strst_ack_c6_scanin = ff_strst_ack_c52_scanout ; |
| 4645 | assign ff_strst_ack_c7_scanin = ff_strst_ack_c6_scanout ; |
| 4646 | assign ff_rmo_st_c52_scanin = ff_strst_ack_c7_scanout ; |
| 4647 | assign ff_rmo_st_c6_scanin = ff_rmo_st_c52_scanout ; |
| 4648 | assign ff_rmo_st_c7_scanin = ff_rmo_st_c6_scanout ; |
| 4649 | assign ff_sel_inv_vec_c7_scanin = ff_rmo_st_c7_scanout ; |
| 4650 | assign ff_uerr_ack_c52_scanin = ff_sel_inv_vec_c7_scanout; |
| 4651 | assign ff_uerr_ack_c6_scanin = ff_uerr_ack_c52_scanout ; |
| 4652 | assign ff_uerr_ack_c7_scanin = ff_uerr_ack_c6_scanout ; |
| 4653 | assign ff_st_ack_c52_scanin = ff_uerr_ack_c7_scanout ; |
| 4654 | assign ff_st_ack_c6_scanin = ff_st_ack_c52_scanout ; |
| 4655 | assign ff_st_ack_c7_scanin = ff_st_ack_c6_scanout ; |
| 4656 | assign ff_cerr_ack_c52_scanin = ff_st_ack_c7_scanout ; |
| 4657 | assign ff_cerr_ack_c6_scanin = ff_cerr_ack_c52_scanout ; |
| 4658 | assign ff_cerr_ack_c7_scanin = ff_cerr_ack_c6_scanout ; |
| 4659 | assign ff_strld_inst_c7_scanin = ff_cerr_ack_c7_scanout ; |
| 4660 | assign ff_mmuld_inst_c7_scanin = ff_strld_inst_c7_scanout ; |
| 4661 | assign ff_atm_inst_c7_scanin = ff_mmuld_inst_c7_scanout ; |
| 4662 | assign ff_l2_miss_c52_scanin = ff_atm_inst_c7_scanout ; |
| 4663 | assign ff_l2_miss_c6_scanin = ff_l2_miss_c52_scanout ; |
| 4664 | assign ff_l2_miss_c7_scanin = ff_l2_miss_c6_scanout ; |
| 4665 | assign ff_pf_inst_c52_scanin = ff_l2_miss_c7_scanout ; |
| 4666 | assign ff_pf_inst_c6_scanin = ff_pf_inst_c52_scanout ; |
| 4667 | assign ff_pf_inst_c7_scanin = ff_pf_inst_c6_scanout ; |
| 4668 | assign ff_arb_oqu_swap_cas2_req_scanin = ff_pf_inst_c7_scanout ; |
| 4669 | assign ff_inc_wr_ptr_d1_scanin = ff_arb_oqu_swap_cas2_req_scanout; |
| 4670 | assign ff_inc_wr_ptr_d1_1_scanin = ff_inc_wr_ptr_d1_scanout ; |
| 4671 | assign ff_inc_wr_ptr_d1_2_scanin = ff_inc_wr_ptr_d1_1_scanout; |
| 4672 | assign ff_l2t_mb0_run_r1_scanin = ff_inc_wr_ptr_d1_2_scanout; |
| 4673 | assign ff_enc_wr_ptr_d1_scanin = ff_l2t_mb0_run_r1_scanout; |
| 4674 | assign ff_wr_ptr15to1_d1_scanin = ff_enc_wr_ptr_d1_scanout ; |
| 4675 | assign ff_wr_ptr0_d1_scanin = ff_wr_ptr15to1_d1_scanout; |
| 4676 | assign ff_inc_rd_ptr_d1_scanin = ff_wr_ptr0_d1_scanout ; |
| 4677 | assign ff_inc_rd_ptr_d1_1_scanin = ff_inc_rd_ptr_d1_scanout ; |
| 4678 | assign ff_inc_rd_ptr_d1_2_scanin = ff_inc_rd_ptr_d1_1_scanout; |
| 4679 | assign ff_rd_ptr15to1_d1_scanin = ff_inc_rd_ptr_d1_2_scanout; |
| 4680 | assign ff_rd_ptr0_d1_scanin = ff_rd_ptr15to1_d1_scanout; |
| 4681 | assign ff_enc_wr_ptr_d2_scanin = ff_rd_ptr0_d1_scanout ; |
| 4682 | assign ff_enc_rd_ptr_d1_scanin = ff_enc_wr_ptr_d2_scanout ; |
| 4683 | assign ff_inc_wr_ptr_d2_scanin = ff_enc_rd_ptr_d1_scanout ; |
| 4684 | assign ff_oq_cnt_d1_scanin = ff_inc_wr_ptr_d2_scanout ; |
| 4685 | assign ff_oq_cnt_plus1_d1_scanin = ff_oq_cnt_d1_scanout ; |
| 4686 | assign ff_oq_cnt_minus1_d1_scanin = ff_oq_cnt_plus1_d1_scanout; |
| 4687 | assign ff_oq_count_15_d1_scanin = ff_oq_cnt_minus1_d1_scanout; |
| 4688 | assign ff_oq_count_16_d1_scanin = ff_oq_count_15_d1_scanout; |
| 4689 | assign ff_oqu_arb_full_px2_scanin = ff_oq_count_16_d1_scanout; |
| 4690 | assign ff_oq_count_nonzero_d1_scanin = ff_oqu_arb_full_px2_scanout; |
| 4691 | assign ff_old_req_vld_d1_scanin = ff_oq_count_nonzero_d1_scanout; |
| 4692 | assign ff_oq0_out_scanin = ff_old_req_vld_d1_scanout; |
| 4693 | assign ff_oq1_out_scanin = ff_oq0_out_scanout ; |
| 4694 | assign ff_oq2_out_scanin = ff_oq1_out_scanout ; |
| 4695 | assign ff_oq3_out_scanin = ff_oq2_out_scanout ; |
| 4696 | assign ff_oq4_out_scanin = ff_oq3_out_scanout ; |
| 4697 | assign ff_oq5_out_scanin = ff_oq4_out_scanout ; |
| 4698 | assign ff_oq6_out_scanin = ff_oq5_out_scanout ; |
| 4699 | assign ff_oq7_out_scanin = ff_oq6_out_scanout ; |
| 4700 | assign ff_oq8_out_scanin = ff_oq7_out_scanout ; |
| 4701 | assign ff_oq9_out_scanin = ff_oq8_out_scanout ; |
| 4702 | assign ff_oq10_out_scanin = ff_oq9_out_scanout ; |
| 4703 | assign ff_oq11_out_scanin = ff_oq10_out_scanout ; |
| 4704 | assign ff_oq12_out_scanin = ff_oq11_out_scanout ; |
| 4705 | assign ff_oq13_out_scanin = ff_oq12_out_scanout ; |
| 4706 | assign ff_oq14_out_scanin = ff_oq13_out_scanout ; |
| 4707 | assign ff_oq15_out_scanin = ff_oq14_out_scanout ; |
| 4708 | assign ff_xbar0_scanin = ff_oq15_out_scanout ; |
| 4709 | assign ff_xbar1_scanin = ff_xbar0_scanout ; |
| 4710 | assign ff_xbar2_scanin = ff_xbar1_scanout ; |
| 4711 | assign ff_xbar3_scanin = ff_xbar2_scanout ; |
| 4712 | assign ff_xbar4_scanin = ff_xbar3_scanout ; |
| 4713 | assign ff_xbar5_scanin = ff_xbar4_scanout ; |
| 4714 | assign ff_xbar6_scanin = ff_xbar5_scanout ; |
| 4715 | assign ff_xbar7_scanin = ff_xbar6_scanout ; |
| 4716 | assign ff_rdma_wr_comp_c5_scanin = ff_xbar7_scanout ; |
| 4717 | assign ff_rdma_wr_comp_c52_scanin = ff_rdma_wr_comp_c5_scanout; |
| 4718 | assign ff_rdma_req_state_0_scanin = ff_rdma_wr_comp_c52_scanout; |
| 4719 | assign ff_rdma_state_scanin = ff_rdma_req_state_0_scanout; |
| 4720 | assign ff_oqu_st_complete_c6_scanin = ff_rdma_state_scanout ; |
| 4721 | assign ff_store_inst_c52_scanin = ff_oqu_st_complete_c6_scanout; |
| 4722 | assign ff_store_inst_c6_scanin = ff_store_inst_c52_scanout; |
| 4723 | assign ff_store_inst_c7_scanin = ff_store_inst_c6_scanout ; |
| 4724 | assign ff_csr_reg_rd_en_c8_scanin = ff_store_inst_c7_scanout ; |
| 4725 | assign ff_sel_inval_c7_scanin = ff_csr_reg_rd_en_c8_scanout; |
| 4726 | assign ff_fwd_req_vld_ld_c7_scanin = ff_sel_inval_c7_scanout ; |
| 4727 | assign ff_diag_data_sel_c7_scanin = ff_fwd_req_vld_ld_c7_scanout; |
| 4728 | assign ff_diag_lddata_sel_c8_scanin = ff_diag_data_sel_c7_scanout; |
| 4729 | assign ff_diag_tag_sel_c7_scanin = ff_diag_lddata_sel_c8_scanout; |
| 4730 | assign ff_diag_ldtag_sel_c8_scanin = ff_diag_tag_sel_c7_scanout; |
| 4731 | assign ff_diag_vuad_sel_c7_scanin = ff_diag_ldtag_sel_c8_scanout; |
| 4732 | assign ff_diag_ldvuad_sel_c8_scanin = ff_diag_vuad_sel_c7_scanout; |
| 4733 | assign ff_diag_def_sel_c8_scanin = ff_diag_ldvuad_sel_c8_scanout; |
| 4734 | assign ff_dirvec_cpuid_c52_scanin = ff_diag_def_sel_c8_scanout; |
| 4735 | assign ff_dirvec_cpuid_c6_scanin = ff_dirvec_cpuid_c52_scanout; |
| 4736 | assign ff_dec_cpuid_c6_scanin = ff_dirvec_cpuid_c6_scanout; |
| 4737 | assign ff_lkup_bank_ena_icd_c5_scanin = ff_dec_cpuid_c6_scanout ; |
| 4738 | assign ff_lkup_bank_ena_dcd_c5_scanin = ff_lkup_bank_ena_icd_c5_scanout; |
| 4739 | assign ff_mux_vec_sel_c52_scanin = ff_lkup_bank_ena_dcd_c5_scanout; |
| 4740 | assign ff_mux_vec_sel_c6_scanin = ff_mux_vec_sel_c52_scanout; |
| 4741 | assign scan_out = ff_mux_vec_sel_c6_scanout; |
| 4742 | // fixscan end: |
| 4743 | endmodule |
| 4744 | |
| 4745 | |
| 4746 | |
| 4747 | |
| 4748 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4749 | // also for pass-gate with decoder |
| 4750 | |
| 4751 | |
| 4752 | |
| 4753 | |
| 4754 | |
| 4755 | // any PARAMS parms go into naming of macro |
| 4756 | |
| 4757 | module l2t_mux_ctl_macro__mux_aonpe__ports_2__width_1 ( |
| 4758 | din0, |
| 4759 | sel0, |
| 4760 | din1, |
| 4761 | sel1, |
| 4762 | dout); |
| 4763 | input [0:0] din0; |
| 4764 | input sel0; |
| 4765 | input [0:0] din1; |
| 4766 | input sel1; |
| 4767 | output [0:0] dout; |
| 4768 | |
| 4769 | |
| 4770 | |
| 4771 | |
| 4772 | |
| 4773 | assign dout[0:0] = ( {1{sel0}} & din0[0:0] ) | |
| 4774 | ( {1{sel1}} & din1[0:0]); |
| 4775 | |
| 4776 | |
| 4777 | |
| 4778 | |
| 4779 | |
| 4780 | endmodule |
| 4781 | |
| 4782 | |
| 4783 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4784 | // also for pass-gate with decoder |
| 4785 | |
| 4786 | |
| 4787 | |
| 4788 | |
| 4789 | |
| 4790 | // any PARAMS parms go into naming of macro |
| 4791 | |
| 4792 | module l2t_mux_ctl_macro__mux_aonpe__ports_2__width_2 ( |
| 4793 | din0, |
| 4794 | sel0, |
| 4795 | din1, |
| 4796 | sel1, |
| 4797 | dout); |
| 4798 | input [1:0] din0; |
| 4799 | input sel0; |
| 4800 | input [1:0] din1; |
| 4801 | input sel1; |
| 4802 | output [1:0] dout; |
| 4803 | |
| 4804 | |
| 4805 | |
| 4806 | |
| 4807 | |
| 4808 | assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) | |
| 4809 | ( {2{sel1}} & din1[1:0]); |
| 4810 | |
| 4811 | |
| 4812 | |
| 4813 | |
| 4814 | |
| 4815 | endmodule |
| 4816 | |
| 4817 | |
| 4818 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4819 | // also for pass-gate with decoder |
| 4820 | |
| 4821 | |
| 4822 | |
| 4823 | |
| 4824 | |
| 4825 | // any PARAMS parms go into naming of macro |
| 4826 | |
| 4827 | module l2t_mux_ctl_macro__mux_aonpe__ports_2__width_3 ( |
| 4828 | din0, |
| 4829 | sel0, |
| 4830 | din1, |
| 4831 | sel1, |
| 4832 | dout); |
| 4833 | input [2:0] din0; |
| 4834 | input sel0; |
| 4835 | input [2:0] din1; |
| 4836 | input sel1; |
| 4837 | output [2:0] dout; |
| 4838 | |
| 4839 | |
| 4840 | |
| 4841 | |
| 4842 | |
| 4843 | assign dout[2:0] = ( {3{sel0}} & din0[2:0] ) | |
| 4844 | ( {3{sel1}} & din1[2:0]); |
| 4845 | |
| 4846 | |
| 4847 | |
| 4848 | |
| 4849 | |
| 4850 | endmodule |
| 4851 | |
| 4852 | |
| 4853 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4854 | // also for pass-gate with decoder |
| 4855 | |
| 4856 | |
| 4857 | |
| 4858 | |
| 4859 | |
| 4860 | // any PARAMS parms go into naming of macro |
| 4861 | |
| 4862 | module l2t_mux_ctl_macro__mux_aonpe__ports_2__width_4 ( |
| 4863 | din0, |
| 4864 | sel0, |
| 4865 | din1, |
| 4866 | sel1, |
| 4867 | dout); |
| 4868 | input [3:0] din0; |
| 4869 | input sel0; |
| 4870 | input [3:0] din1; |
| 4871 | input sel1; |
| 4872 | output [3:0] dout; |
| 4873 | |
| 4874 | |
| 4875 | |
| 4876 | |
| 4877 | |
| 4878 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 4879 | ( {4{sel1}} & din1[3:0]); |
| 4880 | |
| 4881 | |
| 4882 | |
| 4883 | |
| 4884 | |
| 4885 | endmodule |
| 4886 | |
| 4887 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4888 | // also for pass-gate with decoder |
| 4889 | |
| 4890 | |
| 4891 | |
| 4892 | |
| 4893 | |
| 4894 | // any PARAMS parms go into naming of macro |
| 4895 | |
| 4896 | module l2t_mux_ctl_macro__mux_aonpe__ports_2__width_8 ( |
| 4897 | din0, |
| 4898 | sel0, |
| 4899 | din1, |
| 4900 | sel1, |
| 4901 | dout); |
| 4902 | input [7:0] din0; |
| 4903 | input sel0; |
| 4904 | input [7:0] din1; |
| 4905 | input sel1; |
| 4906 | output [7:0] dout; |
| 4907 | |
| 4908 | |
| 4909 | |
| 4910 | |
| 4911 | |
| 4912 | assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) | |
| 4913 | ( {8{sel1}} & din1[7:0]); |
| 4914 | |
| 4915 | |
| 4916 | |
| 4917 | |
| 4918 | |
| 4919 | endmodule |
| 4920 | |
| 4921 | |
| 4922 | |
| 4923 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4924 | // also for pass-gate with decoder |
| 4925 | |
| 4926 | |
| 4927 | |
| 4928 | |
| 4929 | |
| 4930 | // any PARAMS parms go into naming of macro |
| 4931 | |
| 4932 | module l2t_mux_ctl_macro__mux_aonpe__ports_3__width_4 ( |
| 4933 | din0, |
| 4934 | sel0, |
| 4935 | din1, |
| 4936 | sel1, |
| 4937 | din2, |
| 4938 | sel2, |
| 4939 | dout); |
| 4940 | input [3:0] din0; |
| 4941 | input sel0; |
| 4942 | input [3:0] din1; |
| 4943 | input sel1; |
| 4944 | input [3:0] din2; |
| 4945 | input sel2; |
| 4946 | output [3:0] dout; |
| 4947 | |
| 4948 | |
| 4949 | |
| 4950 | |
| 4951 | |
| 4952 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 4953 | ( {4{sel1}} & din1[3:0]) | |
| 4954 | ( {4{sel2}} & din2[3:0]); |
| 4955 | |
| 4956 | |
| 4957 | |
| 4958 | |
| 4959 | |
| 4960 | endmodule |
| 4961 | |
| 4962 | |
| 4963 | |
| 4964 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4965 | // also for pass-gate with decoder |
| 4966 | |
| 4967 | |
| 4968 | |
| 4969 | |
| 4970 | |
| 4971 | // any PARAMS parms go into naming of macro |
| 4972 | |
| 4973 | module l2t_mux_ctl_macro__mux_aonpe__ports_3__width_5 ( |
| 4974 | din0, |
| 4975 | sel0, |
| 4976 | din1, |
| 4977 | sel1, |
| 4978 | din2, |
| 4979 | sel2, |
| 4980 | dout); |
| 4981 | input [4:0] din0; |
| 4982 | input sel0; |
| 4983 | input [4:0] din1; |
| 4984 | input sel1; |
| 4985 | input [4:0] din2; |
| 4986 | input sel2; |
| 4987 | output [4:0] dout; |
| 4988 | |
| 4989 | |
| 4990 | |
| 4991 | |
| 4992 | |
| 4993 | assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) | |
| 4994 | ( {5{sel1}} & din1[4:0]) | |
| 4995 | ( {5{sel2}} & din2[4:0]); |
| 4996 | |
| 4997 | |
| 4998 | |
| 4999 | |
| 5000 | |
| 5001 | endmodule |
| 5002 | |
| 5003 | |
| 5004 | |
| 5005 | |
| 5006 | |
| 5007 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 5008 | // also for pass-gate with decoder |
| 5009 | |
| 5010 | |
| 5011 | |
| 5012 | |
| 5013 | |
| 5014 | // any PARAMS parms go into naming of macro |
| 5015 | |
| 5016 | module l2t_mux_ctl_macro__mux_aonpe__ports_4__width_4 ( |
| 5017 | din0, |
| 5018 | sel0, |
| 5019 | din1, |
| 5020 | sel1, |
| 5021 | din2, |
| 5022 | sel2, |
| 5023 | din3, |
| 5024 | sel3, |
| 5025 | dout); |
| 5026 | input [3:0] din0; |
| 5027 | input sel0; |
| 5028 | input [3:0] din1; |
| 5029 | input sel1; |
| 5030 | input [3:0] din2; |
| 5031 | input sel2; |
| 5032 | input [3:0] din3; |
| 5033 | input sel3; |
| 5034 | output [3:0] dout; |
| 5035 | |
| 5036 | |
| 5037 | |
| 5038 | |
| 5039 | |
| 5040 | assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) | |
| 5041 | ( {4{sel1}} & din1[3:0]) | |
| 5042 | ( {4{sel2}} & din2[3:0]) | |
| 5043 | ( {4{sel3}} & din3[3:0]); |
| 5044 | |
| 5045 | |
| 5046 | |
| 5047 | |
| 5048 | |
| 5049 | endmodule |
| 5050 | |
| 5051 | |
| 5052 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 5053 | // also for pass-gate with decoder |
| 5054 | |
| 5055 | |
| 5056 | |
| 5057 | |
| 5058 | |
| 5059 | // any PARAMS parms go into naming of macro |
| 5060 | |
| 5061 | module l2t_mux_ctl_macro__mux_aonpe__ports_4__width_5 ( |
| 5062 | din0, |
| 5063 | sel0, |
| 5064 | din1, |
| 5065 | sel1, |
| 5066 | din2, |
| 5067 | sel2, |
| 5068 | din3, |
| 5069 | sel3, |
| 5070 | dout); |
| 5071 | input [4:0] din0; |
| 5072 | input sel0; |
| 5073 | input [4:0] din1; |
| 5074 | input sel1; |
| 5075 | input [4:0] din2; |
| 5076 | input sel2; |
| 5077 | input [4:0] din3; |
| 5078 | input sel3; |
| 5079 | output [4:0] dout; |
| 5080 | |
| 5081 | |
| 5082 | |
| 5083 | |
| 5084 | |
| 5085 | assign dout[4:0] = ( {5{sel0}} & din0[4:0] ) | |
| 5086 | ( {5{sel1}} & din1[4:0]) | |
| 5087 | ( {5{sel2}} & din2[4:0]) | |
| 5088 | ( {5{sel3}} & din3[4:0]); |
| 5089 | |
| 5090 | |
| 5091 | |
| 5092 | |
| 5093 | |
| 5094 | endmodule |
| 5095 | |
| 5096 | |
| 5097 | |
| 5098 | |
| 5099 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 5100 | // also for pass-gate with decoder |
| 5101 | |
| 5102 | |
| 5103 | |
| 5104 | |
| 5105 | |
| 5106 | // any PARAMS parms go into naming of macro |
| 5107 | |
| 5108 | module l2t_mux_ctl_macro__mux_aonpe__ports_4__width_8 ( |
| 5109 | din0, |
| 5110 | sel0, |
| 5111 | din1, |
| 5112 | sel1, |
| 5113 | din2, |
| 5114 | sel2, |
| 5115 | din3, |
| 5116 | sel3, |
| 5117 | dout); |
| 5118 | input [7:0] din0; |
| 5119 | input sel0; |
| 5120 | input [7:0] din1; |
| 5121 | input sel1; |
| 5122 | input [7:0] din2; |
| 5123 | input sel2; |
| 5124 | input [7:0] din3; |
| 5125 | input sel3; |
| 5126 | output [7:0] dout; |
| 5127 | |
| 5128 | |
| 5129 | |
| 5130 | |
| 5131 | |
| 5132 | assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) | |
| 5133 | ( {8{sel1}} & din1[7:0]) | |
| 5134 | ( {8{sel2}} & din2[7:0]) | |
| 5135 | ( {8{sel3}} & din3[7:0]); |
| 5136 | |
| 5137 | |
| 5138 | |
| 5139 | |
| 5140 | |
| 5141 | endmodule |
| 5142 | |
| 5143 | |
| 5144 | |
| 5145 | |
| 5146 | |
| 5147 | |
| 5148 | // any PARAMS parms go into naming of macro |
| 5149 | |
| 5150 | module l2t_msff_ctl_macro__clr_1__width_15 ( |
| 5151 | din, |
| 5152 | clr, |
| 5153 | l1clk, |
| 5154 | scan_in, |
| 5155 | siclk, |
| 5156 | soclk, |
| 5157 | dout, |
| 5158 | scan_out); |
| 5159 | wire [14:0] fdin; |
| 5160 | wire [13:0] so; |
| 5161 | |
| 5162 | input [14:0] din; |
| 5163 | input clr; |
| 5164 | input l1clk; |
| 5165 | input scan_in; |
| 5166 | |
| 5167 | |
| 5168 | input siclk; |
| 5169 | input soclk; |
| 5170 | |
| 5171 | output [14:0] dout; |
| 5172 | output scan_out; |
| 5173 | assign fdin[14:0] = din[14:0] & ~{15{clr}}; |
| 5174 | |
| 5175 | |
| 5176 | |
| 5177 | |
| 5178 | |
| 5179 | |
| 5180 | dff #(15) d0_0 ( |
| 5181 | .l1clk(l1clk), |
| 5182 | .siclk(siclk), |
| 5183 | .soclk(soclk), |
| 5184 | .d(fdin[14:0]), |
| 5185 | .si({scan_in,so[13:0]}), |
| 5186 | .so({so[13:0],scan_out}), |
| 5187 | .q(dout[14:0]) |
| 5188 | ); |
| 5189 | |
| 5190 | |
| 5191 | |
| 5192 | |
| 5193 | |
| 5194 | |
| 5195 | |
| 5196 | |
| 5197 | |
| 5198 | |
| 5199 | |
| 5200 | |
| 5201 | endmodule |
| 5202 | |
| 5203 | |
| 5204 | |
| 5205 | |
| 5206 | |
| 5207 | |
| 5208 | // any PARAMS parms go into naming of macro |
| 5209 | |
| 5210 | module l2t_msff_ctl_macro__en_1__width_12 ( |
| 5211 | din, |
| 5212 | en, |
| 5213 | l1clk, |
| 5214 | scan_in, |
| 5215 | siclk, |
| 5216 | soclk, |
| 5217 | dout, |
| 5218 | scan_out); |
| 5219 | wire [11:0] fdin; |
| 5220 | wire [10:0] so; |
| 5221 | |
| 5222 | input [11:0] din; |
| 5223 | input en; |
| 5224 | input l1clk; |
| 5225 | input scan_in; |
| 5226 | |
| 5227 | |
| 5228 | input siclk; |
| 5229 | input soclk; |
| 5230 | |
| 5231 | output [11:0] dout; |
| 5232 | output scan_out; |
| 5233 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); |
| 5234 | |
| 5235 | |
| 5236 | |
| 5237 | |
| 5238 | |
| 5239 | |
| 5240 | dff #(12) d0_0 ( |
| 5241 | .l1clk(l1clk), |
| 5242 | .siclk(siclk), |
| 5243 | .soclk(soclk), |
| 5244 | .d(fdin[11:0]), |
| 5245 | .si({scan_in,so[10:0]}), |
| 5246 | .so({so[10:0],scan_out}), |
| 5247 | .q(dout[11:0]) |
| 5248 | ); |
| 5249 | |
| 5250 | |
| 5251 | |
| 5252 | |
| 5253 | |
| 5254 | |
| 5255 | |
| 5256 | |
| 5257 | |
| 5258 | |
| 5259 | |
| 5260 | |
| 5261 | endmodule |
| 5262 | |
| 5263 | |
| 5264 | |
| 5265 | |
| 5266 | |
| 5267 | // any PARAMS parms go into naming of macro |
| 5268 | |
| 5269 | module l2t_msff_ctl_macro__dmsff_32x__width_1 ( |
| 5270 | din, |
| 5271 | l1clk, |
| 5272 | scan_in, |
| 5273 | siclk, |
| 5274 | soclk, |
| 5275 | dout, |
| 5276 | scan_out); |
| 5277 | wire [0:0] fdin; |
| 5278 | |
| 5279 | input [0:0] din; |
| 5280 | input l1clk; |
| 5281 | input scan_in; |
| 5282 | |
| 5283 | |
| 5284 | input siclk; |
| 5285 | input soclk; |
| 5286 | |
| 5287 | output [0:0] dout; |
| 5288 | output scan_out; |
| 5289 | assign fdin[0:0] = din[0:0]; |
| 5290 | |
| 5291 | |
| 5292 | |
| 5293 | |
| 5294 | |
| 5295 | |
| 5296 | dff #(1) d0_0 ( |
| 5297 | .l1clk(l1clk), |
| 5298 | .siclk(siclk), |
| 5299 | .soclk(soclk), |
| 5300 | .d(fdin[0:0]), |
| 5301 | .si(scan_in), |
| 5302 | .so(scan_out), |
| 5303 | .q(dout[0:0]) |
| 5304 | ); |
| 5305 | |
| 5306 | |
| 5307 | |
| 5308 | |
| 5309 | |
| 5310 | |
| 5311 | |
| 5312 | |
| 5313 | |
| 5314 | |
| 5315 | |
| 5316 | |
| 5317 | endmodule |
| 5318 | |
| 5319 | |
| 5320 | |
| 5321 | |
| 5322 | |
| 5323 | // any PARAMS parms go into naming of macro |
| 5324 | |
| 5325 | module l2t_msff_ctl_macro__dmsff_32x__width_8 ( |
| 5326 | din, |
| 5327 | l1clk, |
| 5328 | scan_in, |
| 5329 | siclk, |
| 5330 | soclk, |
| 5331 | dout, |
| 5332 | scan_out); |
| 5333 | wire [7:0] fdin; |
| 5334 | wire [6:0] so; |
| 5335 | |
| 5336 | input [7:0] din; |
| 5337 | input l1clk; |
| 5338 | input scan_in; |
| 5339 | |
| 5340 | |
| 5341 | input siclk; |
| 5342 | input soclk; |
| 5343 | |
| 5344 | output [7:0] dout; |
| 5345 | output scan_out; |
| 5346 | assign fdin[7:0] = din[7:0]; |
| 5347 | |
| 5348 | |
| 5349 | |
| 5350 | |
| 5351 | |
| 5352 | |
| 5353 | dff #(8) d0_0 ( |
| 5354 | .l1clk(l1clk), |
| 5355 | .siclk(siclk), |
| 5356 | .soclk(soclk), |
| 5357 | .d(fdin[7:0]), |
| 5358 | .si({scan_in,so[6:0]}), |
| 5359 | .so({so[6:0],scan_out}), |
| 5360 | .q(dout[7:0]) |
| 5361 | ); |
| 5362 | |
| 5363 | |
| 5364 | |
| 5365 | |
| 5366 | |
| 5367 | |
| 5368 | |
| 5369 | |
| 5370 | |
| 5371 | |
| 5372 | |
| 5373 | |
| 5374 | endmodule |
| 5375 | |
| 5376 | |
| 5377 | |
| 5378 | |
| 5379 | |
| 5380 | |
| 5381 | |
| 5382 | |
| 5383 | // any PARAMS parms go into naming of macro |
| 5384 | |
| 5385 | module l2t_msff_ctl_macro__clr_1__en_1__width_2 ( |
| 5386 | din, |
| 5387 | en, |
| 5388 | clr, |
| 5389 | l1clk, |
| 5390 | scan_in, |
| 5391 | siclk, |
| 5392 | soclk, |
| 5393 | dout, |
| 5394 | scan_out); |
| 5395 | wire [1:0] fdin; |
| 5396 | wire [0:0] so; |
| 5397 | |
| 5398 | input [1:0] din; |
| 5399 | input en; |
| 5400 | input clr; |
| 5401 | input l1clk; |
| 5402 | input scan_in; |
| 5403 | |
| 5404 | |
| 5405 | input siclk; |
| 5406 | input soclk; |
| 5407 | |
| 5408 | output [1:0] dout; |
| 5409 | output scan_out; |
| 5410 | assign fdin[1:0] = (din[1:0] & {2{en}} & ~{2{clr}}) | (dout[1:0] & ~{2{en}} & ~{2{clr}}); |
| 5411 | |
| 5412 | |
| 5413 | |
| 5414 | |
| 5415 | |
| 5416 | |
| 5417 | dff #(2) d0_0 ( |
| 5418 | .l1clk(l1clk), |
| 5419 | .siclk(siclk), |
| 5420 | .soclk(soclk), |
| 5421 | .d(fdin[1:0]), |
| 5422 | .si({scan_in,so[0:0]}), |
| 5423 | .so({so[0:0],scan_out}), |
| 5424 | .q(dout[1:0]) |
| 5425 | ); |
| 5426 | |
| 5427 | |
| 5428 | |
| 5429 | |
| 5430 | |
| 5431 | |
| 5432 | |
| 5433 | |
| 5434 | |
| 5435 | |
| 5436 | |
| 5437 | |
| 5438 | endmodule |
| 5439 | |
| 5440 | |
| 5441 | |
| 5442 | |
| 5443 | |
| 5444 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 5445 | // also for pass-gate with decoder |
| 5446 | |
| 5447 | |
| 5448 | |
| 5449 | |
| 5450 | |
| 5451 | // any PARAMS parms go into naming of macro |
| 5452 | |
| 5453 | module l2t_mux_ctl_macro__mux_aonpe__ports_2__width_16 ( |
| 5454 | din0, |
| 5455 | sel0, |
| 5456 | din1, |
| 5457 | sel1, |
| 5458 | dout); |
| 5459 | input [15:0] din0; |
| 5460 | input sel0; |
| 5461 | input [15:0] din1; |
| 5462 | input sel1; |
| 5463 | output [15:0] dout; |
| 5464 | |
| 5465 | |
| 5466 | |
| 5467 | |
| 5468 | |
| 5469 | assign dout[15:0] = ( {16{sel0}} & din0[15:0] ) | |
| 5470 | ( {16{sel1}} & din1[15:0]); |
| 5471 | |
| 5472 | |
| 5473 | |
| 5474 | |
| 5475 | |
| 5476 | endmodule |
| 5477 | |
| 5478 | |
| 5479 | |
| 5480 | |
| 5481 | // any PARAMS parms go into naming of macro |
| 5482 | |
| 5483 | module l2t_msff_ctl_macro__clr_1__width_1 ( |
| 5484 | din, |
| 5485 | clr, |
| 5486 | l1clk, |
| 5487 | scan_in, |
| 5488 | siclk, |
| 5489 | soclk, |
| 5490 | dout, |
| 5491 | scan_out); |
| 5492 | wire [0:0] fdin; |
| 5493 | |
| 5494 | input [0:0] din; |
| 5495 | input clr; |
| 5496 | input l1clk; |
| 5497 | input scan_in; |
| 5498 | |
| 5499 | |
| 5500 | input siclk; |
| 5501 | input soclk; |
| 5502 | |
| 5503 | output [0:0] dout; |
| 5504 | output scan_out; |
| 5505 | assign fdin[0:0] = din[0:0] & ~{1{clr}}; |
| 5506 | |
| 5507 | |
| 5508 | |
| 5509 | |
| 5510 | |
| 5511 | |
| 5512 | dff #(1) d0_0 ( |
| 5513 | .l1clk(l1clk), |
| 5514 | .siclk(siclk), |
| 5515 | .soclk(soclk), |
| 5516 | .d(fdin[0:0]), |
| 5517 | .si(scan_in), |
| 5518 | .so(scan_out), |
| 5519 | .q(dout[0:0]) |
| 5520 | ); |
| 5521 | |
| 5522 | |
| 5523 | |
| 5524 | |
| 5525 | |
| 5526 | |
| 5527 | |
| 5528 | |
| 5529 | |
| 5530 | |
| 5531 | |
| 5532 | |
| 5533 | endmodule |
| 5534 | |
| 5535 | |
| 5536 | |
| 5537 | |
| 5538 | |
| 5539 | |
| 5540 | |
| 5541 | // any PARAMS parms go into naming of macro |
| 5542 | |
| 5543 | module l2t_msff_ctl_macro__clr_1__width_2 ( |
| 5544 | din, |
| 5545 | clr, |
| 5546 | l1clk, |
| 5547 | scan_in, |
| 5548 | siclk, |
| 5549 | soclk, |
| 5550 | dout, |
| 5551 | scan_out); |
| 5552 | wire [1:0] fdin; |
| 5553 | wire [0:0] so; |
| 5554 | |
| 5555 | input [1:0] din; |
| 5556 | input clr; |
| 5557 | input l1clk; |
| 5558 | input scan_in; |
| 5559 | |
| 5560 | |
| 5561 | input siclk; |
| 5562 | input soclk; |
| 5563 | |
| 5564 | output [1:0] dout; |
| 5565 | output scan_out; |
| 5566 | assign fdin[1:0] = din[1:0] & ~{2{clr}}; |
| 5567 | |
| 5568 | |
| 5569 | |
| 5570 | |
| 5571 | |
| 5572 | |
| 5573 | dff #(2) d0_0 ( |
| 5574 | .l1clk(l1clk), |
| 5575 | .siclk(siclk), |
| 5576 | .soclk(soclk), |
| 5577 | .d(fdin[1:0]), |
| 5578 | .si({scan_in,so[0:0]}), |
| 5579 | .so({so[0:0],scan_out}), |
| 5580 | .q(dout[1:0]) |
| 5581 | ); |
| 5582 | |
| 5583 | |
| 5584 | |
| 5585 | |
| 5586 | |
| 5587 | |
| 5588 | |
| 5589 | |
| 5590 | |
| 5591 | |
| 5592 | |
| 5593 | |
| 5594 | endmodule |
| 5595 | |
| 5596 | |
| 5597 | |
| 5598 | |
| 5599 | |
| 5600 | // any PARAMS parms go into naming of macro |
| 5601 | |
| 5602 | module l2t_msff_ctl_macro__clr_1__width_5 ( |
| 5603 | din, |
| 5604 | clr, |
| 5605 | l1clk, |
| 5606 | scan_in, |
| 5607 | siclk, |
| 5608 | soclk, |
| 5609 | dout, |
| 5610 | scan_out); |
| 5611 | wire [4:0] fdin; |
| 5612 | wire [3:0] so; |
| 5613 | |
| 5614 | input [4:0] din; |
| 5615 | input clr; |
| 5616 | input l1clk; |
| 5617 | input scan_in; |
| 5618 | |
| 5619 | |
| 5620 | input siclk; |
| 5621 | input soclk; |
| 5622 | |
| 5623 | output [4:0] dout; |
| 5624 | output scan_out; |
| 5625 | assign fdin[4:0] = din[4:0] & ~{5{clr}}; |
| 5626 | |
| 5627 | |
| 5628 | |
| 5629 | |
| 5630 | |
| 5631 | |
| 5632 | dff #(5) d0_0 ( |
| 5633 | .l1clk(l1clk), |
| 5634 | .siclk(siclk), |
| 5635 | .soclk(soclk), |
| 5636 | .d(fdin[4:0]), |
| 5637 | .si({scan_in,so[3:0]}), |
| 5638 | .so({so[3:0],scan_out}), |
| 5639 | .q(dout[4:0]) |
| 5640 | ); |
| 5641 | |
| 5642 | |
| 5643 | |
| 5644 | |
| 5645 | |
| 5646 | |
| 5647 | |
| 5648 | |
| 5649 | |
| 5650 | |
| 5651 | |
| 5652 | |
| 5653 | endmodule |
| 5654 | |
| 5655 | |