| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_taghdr_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2t_taghdr_ctl ( |
| 36 | hdr_efu_read_data, |
| 37 | hdr_efu_xfer_en, |
| 38 | hdr_sram_rvalue, |
| 39 | hdr_sram_rid, |
| 40 | hdr_sram_wr_en, |
| 41 | hdr_sram_red_clr, |
| 42 | scan_out, |
| 43 | efu_hdr_write_data, |
| 44 | efu_hdr_xfer_en, |
| 45 | efu_hdr_clr, |
| 46 | sram_hdr_read_data, |
| 47 | l2clk, |
| 48 | tcu_pce_ov, |
| 49 | tcu_aclk, |
| 50 | tcu_bclk, |
| 51 | tcu_scan_en, |
| 52 | tcu_clk_stop, |
| 53 | scan_in, |
| 54 | io_cmp_sync_en, |
| 55 | cmp_io_sync_en); |
| 56 | wire [10:0] unused; |
| 57 | wire efuse_l2d_header_scanin; |
| 58 | wire efuse_l2d_header_scanout; |
| 59 | |
| 60 | |
| 61 | |
| 62 | output hdr_efu_read_data; |
| 63 | output hdr_efu_xfer_en; |
| 64 | output [6:0] hdr_sram_rvalue; |
| 65 | output [3:0] hdr_sram_rid; |
| 66 | output hdr_sram_wr_en; |
| 67 | output hdr_sram_red_clr; |
| 68 | output scan_out; |
| 69 | |
| 70 | input efu_hdr_write_data; |
| 71 | input efu_hdr_xfer_en; |
| 72 | input efu_hdr_clr; |
| 73 | input [6:0] sram_hdr_read_data; |
| 74 | input l2clk; |
| 75 | input tcu_pce_ov; |
| 76 | input tcu_aclk; |
| 77 | input tcu_bclk; |
| 78 | input tcu_scan_en; |
| 79 | input tcu_clk_stop; |
| 80 | input scan_in; |
| 81 | input io_cmp_sync_en; |
| 82 | input cmp_io_sync_en; |
| 83 | |
| 84 | |
| 85 | |
| 86 | |
| 87 | |
| 88 | |
| 89 | n2_efuhdr1_ctl efuse_l2d_header |
| 90 | ( |
| 91 | .efu_hdr_write_data (efu_hdr_write_data), |
| 92 | .efu_hdr_xfer_en (efu_hdr_xfer_en), |
| 93 | .efu_hdr_clr (efu_hdr_clr), |
| 94 | .hdr_efu_read_data (hdr_efu_read_data), |
| 95 | .hdr_efu_xfer_en (hdr_efu_xfer_en), |
| 96 | .hdr_sram_rvalue ({unused[3:0],hdr_sram_rvalue[6:0]}), |
| 97 | .hdr_sram_rid ({unused[10:4],hdr_sram_rid[3:0]}), |
| 98 | .hdr_sram_wr_en (hdr_sram_wr_en), |
| 99 | .hdr_sram_red_clr (hdr_sram_red_clr), |
| 100 | .cmp_io_sync_en (cmp_io_sync_en), |
| 101 | .io_cmp_sync_en (io_cmp_sync_en), |
| 102 | .sram_hdr_read_data ({4'b0,sram_hdr_read_data[6:0]}), |
| 103 | .scan_in(efuse_l2d_header_scanin), |
| 104 | .scan_out(efuse_l2d_header_scanout), |
| 105 | .l2clk (l2clk), |
| 106 | .tcu_pce_ov (tcu_pce_ov), |
| 107 | .tcu_aclk (tcu_aclk), |
| 108 | .tcu_bclk (tcu_bclk), |
| 109 | .tcu_scan_en (tcu_scan_en), |
| 110 | .tcu_clk_stop (tcu_clk_stop) |
| 111 | ); |
| 112 | |
| 113 | // fixscan start: |
| 114 | assign efuse_l2d_header_scanin = scan_in ; |
| 115 | assign scan_out = efuse_l2d_header_scanout ; |
| 116 | // fixscan end: |
| 117 | endmodule |
| 118 | |
| 119 | |
| 120 | |
| 121 | |
| 122 | // any PARAMS parms go into naming of macro |
| 123 | |
| 124 | module l2t_taghdr_ctl_l1clkhdr_ctl_macro ( |
| 125 | l2clk, |
| 126 | l1en, |
| 127 | pce_ov, |
| 128 | stop, |
| 129 | se, |
| 130 | l1clk); |
| 131 | |
| 132 | |
| 133 | input l2clk; |
| 134 | input l1en; |
| 135 | input pce_ov; |
| 136 | input stop; |
| 137 | input se; |
| 138 | output l1clk; |
| 139 | |
| 140 | |
| 141 | |
| 142 | |
| 143 | |
| 144 | cl_sc1_l1hdr_8x c_0 ( |
| 145 | |
| 146 | |
| 147 | .l2clk(l2clk), |
| 148 | .pce(l1en), |
| 149 | .l1clk(l1clk), |
| 150 | .se(se), |
| 151 | .pce_ov(pce_ov), |
| 152 | .stop(stop) |
| 153 | ); |
| 154 | |
| 155 | |
| 156 | |
| 157 | endmodule |
| 158 | |
| 159 | |
| 160 | |
| 161 | |
| 162 | |
| 163 | |
| 164 | |
| 165 | |
| 166 | |
| 167 | |
| 168 | |
| 169 | |
| 170 | |
| 171 | // any PARAMS parms go into naming of macro |
| 172 | |
| 173 | module l2t_taghdr_ctl_msff_ctl_macro__width_1 ( |
| 174 | din, |
| 175 | l1clk, |
| 176 | scan_in, |
| 177 | siclk, |
| 178 | soclk, |
| 179 | dout, |
| 180 | scan_out); |
| 181 | wire [0:0] fdin; |
| 182 | |
| 183 | input [0:0] din; |
| 184 | input l1clk; |
| 185 | input scan_in; |
| 186 | |
| 187 | |
| 188 | input siclk; |
| 189 | input soclk; |
| 190 | |
| 191 | output [0:0] dout; |
| 192 | output scan_out; |
| 193 | assign fdin[0:0] = din[0:0]; |
| 194 | |
| 195 | |
| 196 | |
| 197 | |
| 198 | |
| 199 | |
| 200 | dff #(1) d0_0 ( |
| 201 | .l1clk(l1clk), |
| 202 | .siclk(siclk), |
| 203 | .soclk(soclk), |
| 204 | .d(fdin[0:0]), |
| 205 | .si(scan_in), |
| 206 | .so(scan_out), |
| 207 | .q(dout[0:0]) |
| 208 | ); |
| 209 | |
| 210 | |
| 211 | |
| 212 | |
| 213 | |
| 214 | |
| 215 | |
| 216 | |
| 217 | |
| 218 | |
| 219 | |
| 220 | |
| 221 | endmodule |
| 222 | |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | |
| 228 | |
| 229 | |
| 230 | |
| 231 | |
| 232 | |
| 233 | |
| 234 | |
| 235 | // any PARAMS parms go into naming of macro |
| 236 | |
| 237 | module l2t_taghdr_ctl_msff_ctl_macro__en_1__width_4 ( |
| 238 | din, |
| 239 | en, |
| 240 | l1clk, |
| 241 | scan_in, |
| 242 | siclk, |
| 243 | soclk, |
| 244 | dout, |
| 245 | scan_out); |
| 246 | wire [3:0] fdin; |
| 247 | wire [2:0] so; |
| 248 | |
| 249 | input [3:0] din; |
| 250 | input en; |
| 251 | input l1clk; |
| 252 | input scan_in; |
| 253 | |
| 254 | |
| 255 | input siclk; |
| 256 | input soclk; |
| 257 | |
| 258 | output [3:0] dout; |
| 259 | output scan_out; |
| 260 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); |
| 261 | |
| 262 | |
| 263 | |
| 264 | |
| 265 | |
| 266 | |
| 267 | dff #(4) d0_0 ( |
| 268 | .l1clk(l1clk), |
| 269 | .siclk(siclk), |
| 270 | .soclk(soclk), |
| 271 | .d(fdin[3:0]), |
| 272 | .si({scan_in,so[2:0]}), |
| 273 | .so({so[2:0],scan_out}), |
| 274 | .q(dout[3:0]) |
| 275 | ); |
| 276 | |
| 277 | |
| 278 | |
| 279 | |
| 280 | |
| 281 | |
| 282 | |
| 283 | |
| 284 | |
| 285 | |
| 286 | |
| 287 | |
| 288 | endmodule |
| 289 | |
| 290 | |
| 291 | |
| 292 | |
| 293 | |
| 294 | |
| 295 | |
| 296 | |
| 297 | |
| 298 | |
| 299 | |
| 300 | |
| 301 | |
| 302 | // any PARAMS parms go into naming of macro |
| 303 | |
| 304 | module l2t_taghdr_ctl_msff_ctl_macro__en_1__width_22 ( |
| 305 | din, |
| 306 | en, |
| 307 | l1clk, |
| 308 | scan_in, |
| 309 | siclk, |
| 310 | soclk, |
| 311 | dout, |
| 312 | scan_out); |
| 313 | wire [21:0] fdin; |
| 314 | wire [20:0] so; |
| 315 | |
| 316 | input [21:0] din; |
| 317 | input en; |
| 318 | input l1clk; |
| 319 | input scan_in; |
| 320 | |
| 321 | |
| 322 | input siclk; |
| 323 | input soclk; |
| 324 | |
| 325 | output [21:0] dout; |
| 326 | output scan_out; |
| 327 | assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}}); |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | |
| 333 | |
| 334 | dff #(22) d0_0 ( |
| 335 | .l1clk(l1clk), |
| 336 | .siclk(siclk), |
| 337 | .soclk(soclk), |
| 338 | .d(fdin[21:0]), |
| 339 | .si({scan_in,so[20:0]}), |
| 340 | .so({so[20:0],scan_out}), |
| 341 | .q(dout[21:0]) |
| 342 | ); |
| 343 | |
| 344 | |
| 345 | |
| 346 | |
| 347 | |
| 348 | |
| 349 | |
| 350 | |
| 351 | |
| 352 | |
| 353 | |
| 354 | |
| 355 | endmodule |
| 356 | |
| 357 | |
| 358 | |
| 359 | |
| 360 | |
| 361 | |
| 362 | |
| 363 | |
| 364 | |
| 365 | |
| 366 | |
| 367 | |
| 368 | |
| 369 | // any PARAMS parms go into naming of macro |
| 370 | |
| 371 | module l2t_taghdr_ctl_msff_ctl_macro__en_1__width_1 ( |
| 372 | din, |
| 373 | en, |
| 374 | l1clk, |
| 375 | scan_in, |
| 376 | siclk, |
| 377 | soclk, |
| 378 | dout, |
| 379 | scan_out); |
| 380 | wire [0:0] fdin; |
| 381 | |
| 382 | input [0:0] din; |
| 383 | input en; |
| 384 | input l1clk; |
| 385 | input scan_in; |
| 386 | |
| 387 | |
| 388 | input siclk; |
| 389 | input soclk; |
| 390 | |
| 391 | output [0:0] dout; |
| 392 | output scan_out; |
| 393 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 394 | |
| 395 | |
| 396 | |
| 397 | |
| 398 | |
| 399 | |
| 400 | dff #(1) d0_0 ( |
| 401 | .l1clk(l1clk), |
| 402 | .siclk(siclk), |
| 403 | .soclk(soclk), |
| 404 | .d(fdin[0:0]), |
| 405 | .si(scan_in), |
| 406 | .so(scan_out), |
| 407 | .q(dout[0:0]) |
| 408 | ); |
| 409 | |
| 410 | |
| 411 | |
| 412 | |
| 413 | |
| 414 | |
| 415 | |
| 416 | |
| 417 | |
| 418 | |
| 419 | |
| 420 | |
| 421 | endmodule |
| 422 | |
| 423 | |
| 424 | |
| 425 | |
| 426 | |
| 427 | |
| 428 | |
| 429 | |
| 430 | |
| 431 | |
| 432 | |
| 433 | |
| 434 | |
| 435 | // any PARAMS parms go into naming of macro |
| 436 | |
| 437 | module l2t_taghdr_ctl_msff_ctl_macro__en_1__width_5 ( |
| 438 | din, |
| 439 | en, |
| 440 | l1clk, |
| 441 | scan_in, |
| 442 | siclk, |
| 443 | soclk, |
| 444 | dout, |
| 445 | scan_out); |
| 446 | wire [4:0] fdin; |
| 447 | wire [3:0] so; |
| 448 | |
| 449 | input [4:0] din; |
| 450 | input en; |
| 451 | input l1clk; |
| 452 | input scan_in; |
| 453 | |
| 454 | |
| 455 | input siclk; |
| 456 | input soclk; |
| 457 | |
| 458 | output [4:0] dout; |
| 459 | output scan_out; |
| 460 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); |
| 461 | |
| 462 | |
| 463 | |
| 464 | |
| 465 | |
| 466 | |
| 467 | dff #(5) d0_0 ( |
| 468 | .l1clk(l1clk), |
| 469 | .siclk(siclk), |
| 470 | .soclk(soclk), |
| 471 | .d(fdin[4:0]), |
| 472 | .si({scan_in,so[3:0]}), |
| 473 | .so({so[3:0],scan_out}), |
| 474 | .q(dout[4:0]) |
| 475 | ); |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | |
| 481 | |
| 482 | |
| 483 | |
| 484 | |
| 485 | |
| 486 | |
| 487 | |
| 488 | endmodule |
| 489 | |
| 490 | |
| 491 | |
| 492 | |
| 493 | |
| 494 | |
| 495 | |
| 496 | |
| 497 | |
| 498 | // Description: Spare gate macro for control blocks |
| 499 | // |
| 500 | // Param num controls the number of times the macro is added |
| 501 | // flops=0 can be used to use only combination spare logic |
| 502 | |
| 503 | |
| 504 | module l2t_taghdr_ctl_spare_ctl_macro__num_4 ( |
| 505 | l1clk, |
| 506 | scan_in, |
| 507 | siclk, |
| 508 | soclk, |
| 509 | scan_out); |
| 510 | wire si_0; |
| 511 | wire so_0; |
| 512 | wire spare0_flop_unused; |
| 513 | wire spare0_buf_32x_unused; |
| 514 | wire spare0_nand3_8x_unused; |
| 515 | wire spare0_inv_8x_unused; |
| 516 | wire spare0_aoi22_4x_unused; |
| 517 | wire spare0_buf_8x_unused; |
| 518 | wire spare0_oai22_4x_unused; |
| 519 | wire spare0_inv_16x_unused; |
| 520 | wire spare0_nand2_16x_unused; |
| 521 | wire spare0_nor3_4x_unused; |
| 522 | wire spare0_nand2_8x_unused; |
| 523 | wire spare0_buf_16x_unused; |
| 524 | wire spare0_nor2_16x_unused; |
| 525 | wire spare0_inv_32x_unused; |
| 526 | wire si_1; |
| 527 | wire so_1; |
| 528 | wire spare1_flop_unused; |
| 529 | wire spare1_buf_32x_unused; |
| 530 | wire spare1_nand3_8x_unused; |
| 531 | wire spare1_inv_8x_unused; |
| 532 | wire spare1_aoi22_4x_unused; |
| 533 | wire spare1_buf_8x_unused; |
| 534 | wire spare1_oai22_4x_unused; |
| 535 | wire spare1_inv_16x_unused; |
| 536 | wire spare1_nand2_16x_unused; |
| 537 | wire spare1_nor3_4x_unused; |
| 538 | wire spare1_nand2_8x_unused; |
| 539 | wire spare1_buf_16x_unused; |
| 540 | wire spare1_nor2_16x_unused; |
| 541 | wire spare1_inv_32x_unused; |
| 542 | wire si_2; |
| 543 | wire so_2; |
| 544 | wire spare2_flop_unused; |
| 545 | wire spare2_buf_32x_unused; |
| 546 | wire spare2_nand3_8x_unused; |
| 547 | wire spare2_inv_8x_unused; |
| 548 | wire spare2_aoi22_4x_unused; |
| 549 | wire spare2_buf_8x_unused; |
| 550 | wire spare2_oai22_4x_unused; |
| 551 | wire spare2_inv_16x_unused; |
| 552 | wire spare2_nand2_16x_unused; |
| 553 | wire spare2_nor3_4x_unused; |
| 554 | wire spare2_nand2_8x_unused; |
| 555 | wire spare2_buf_16x_unused; |
| 556 | wire spare2_nor2_16x_unused; |
| 557 | wire spare2_inv_32x_unused; |
| 558 | wire si_3; |
| 559 | wire so_3; |
| 560 | wire spare3_flop_unused; |
| 561 | wire spare3_buf_32x_unused; |
| 562 | wire spare3_nand3_8x_unused; |
| 563 | wire spare3_inv_8x_unused; |
| 564 | wire spare3_aoi22_4x_unused; |
| 565 | wire spare3_buf_8x_unused; |
| 566 | wire spare3_oai22_4x_unused; |
| 567 | wire spare3_inv_16x_unused; |
| 568 | wire spare3_nand2_16x_unused; |
| 569 | wire spare3_nor3_4x_unused; |
| 570 | wire spare3_nand2_8x_unused; |
| 571 | wire spare3_buf_16x_unused; |
| 572 | wire spare3_nor2_16x_unused; |
| 573 | wire spare3_inv_32x_unused; |
| 574 | |
| 575 | |
| 576 | input l1clk; |
| 577 | input scan_in; |
| 578 | input siclk; |
| 579 | input soclk; |
| 580 | output scan_out; |
| 581 | |
| 582 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 583 | .siclk(siclk), |
| 584 | .soclk(soclk), |
| 585 | .si(si_0), |
| 586 | .so(so_0), |
| 587 | .d(1'b0), |
| 588 | .q(spare0_flop_unused)); |
| 589 | assign si_0 = scan_in; |
| 590 | |
| 591 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 592 | .out(spare0_buf_32x_unused)); |
| 593 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 594 | .in1(1'b1), |
| 595 | .in2(1'b1), |
| 596 | .out(spare0_nand3_8x_unused)); |
| 597 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 598 | .out(spare0_inv_8x_unused)); |
| 599 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 600 | .in01(1'b1), |
| 601 | .in10(1'b1), |
| 602 | .in11(1'b1), |
| 603 | .out(spare0_aoi22_4x_unused)); |
| 604 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 605 | .out(spare0_buf_8x_unused)); |
| 606 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 607 | .in01(1'b1), |
| 608 | .in10(1'b1), |
| 609 | .in11(1'b1), |
| 610 | .out(spare0_oai22_4x_unused)); |
| 611 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 612 | .out(spare0_inv_16x_unused)); |
| 613 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 614 | .in1(1'b1), |
| 615 | .out(spare0_nand2_16x_unused)); |
| 616 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 617 | .in1(1'b0), |
| 618 | .in2(1'b0), |
| 619 | .out(spare0_nor3_4x_unused)); |
| 620 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 621 | .in1(1'b1), |
| 622 | .out(spare0_nand2_8x_unused)); |
| 623 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 624 | .out(spare0_buf_16x_unused)); |
| 625 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 626 | .in1(1'b0), |
| 627 | .out(spare0_nor2_16x_unused)); |
| 628 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 629 | .out(spare0_inv_32x_unused)); |
| 630 | |
| 631 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 632 | .siclk(siclk), |
| 633 | .soclk(soclk), |
| 634 | .si(si_1), |
| 635 | .so(so_1), |
| 636 | .d(1'b0), |
| 637 | .q(spare1_flop_unused)); |
| 638 | assign si_1 = so_0; |
| 639 | |
| 640 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 641 | .out(spare1_buf_32x_unused)); |
| 642 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 643 | .in1(1'b1), |
| 644 | .in2(1'b1), |
| 645 | .out(spare1_nand3_8x_unused)); |
| 646 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 647 | .out(spare1_inv_8x_unused)); |
| 648 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 649 | .in01(1'b1), |
| 650 | .in10(1'b1), |
| 651 | .in11(1'b1), |
| 652 | .out(spare1_aoi22_4x_unused)); |
| 653 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 654 | .out(spare1_buf_8x_unused)); |
| 655 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 656 | .in01(1'b1), |
| 657 | .in10(1'b1), |
| 658 | .in11(1'b1), |
| 659 | .out(spare1_oai22_4x_unused)); |
| 660 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 661 | .out(spare1_inv_16x_unused)); |
| 662 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 663 | .in1(1'b1), |
| 664 | .out(spare1_nand2_16x_unused)); |
| 665 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 666 | .in1(1'b0), |
| 667 | .in2(1'b0), |
| 668 | .out(spare1_nor3_4x_unused)); |
| 669 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 670 | .in1(1'b1), |
| 671 | .out(spare1_nand2_8x_unused)); |
| 672 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 673 | .out(spare1_buf_16x_unused)); |
| 674 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 675 | .in1(1'b0), |
| 676 | .out(spare1_nor2_16x_unused)); |
| 677 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 678 | .out(spare1_inv_32x_unused)); |
| 679 | |
| 680 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 681 | .siclk(siclk), |
| 682 | .soclk(soclk), |
| 683 | .si(si_2), |
| 684 | .so(so_2), |
| 685 | .d(1'b0), |
| 686 | .q(spare2_flop_unused)); |
| 687 | assign si_2 = so_1; |
| 688 | |
| 689 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 690 | .out(spare2_buf_32x_unused)); |
| 691 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 692 | .in1(1'b1), |
| 693 | .in2(1'b1), |
| 694 | .out(spare2_nand3_8x_unused)); |
| 695 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 696 | .out(spare2_inv_8x_unused)); |
| 697 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 698 | .in01(1'b1), |
| 699 | .in10(1'b1), |
| 700 | .in11(1'b1), |
| 701 | .out(spare2_aoi22_4x_unused)); |
| 702 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 703 | .out(spare2_buf_8x_unused)); |
| 704 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 705 | .in01(1'b1), |
| 706 | .in10(1'b1), |
| 707 | .in11(1'b1), |
| 708 | .out(spare2_oai22_4x_unused)); |
| 709 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 710 | .out(spare2_inv_16x_unused)); |
| 711 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 712 | .in1(1'b1), |
| 713 | .out(spare2_nand2_16x_unused)); |
| 714 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 715 | .in1(1'b0), |
| 716 | .in2(1'b0), |
| 717 | .out(spare2_nor3_4x_unused)); |
| 718 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 719 | .in1(1'b1), |
| 720 | .out(spare2_nand2_8x_unused)); |
| 721 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 722 | .out(spare2_buf_16x_unused)); |
| 723 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 724 | .in1(1'b0), |
| 725 | .out(spare2_nor2_16x_unused)); |
| 726 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 727 | .out(spare2_inv_32x_unused)); |
| 728 | |
| 729 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 730 | .siclk(siclk), |
| 731 | .soclk(soclk), |
| 732 | .si(si_3), |
| 733 | .so(so_3), |
| 734 | .d(1'b0), |
| 735 | .q(spare3_flop_unused)); |
| 736 | assign si_3 = so_2; |
| 737 | |
| 738 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 739 | .out(spare3_buf_32x_unused)); |
| 740 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 741 | .in1(1'b1), |
| 742 | .in2(1'b1), |
| 743 | .out(spare3_nand3_8x_unused)); |
| 744 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 745 | .out(spare3_inv_8x_unused)); |
| 746 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 747 | .in01(1'b1), |
| 748 | .in10(1'b1), |
| 749 | .in11(1'b1), |
| 750 | .out(spare3_aoi22_4x_unused)); |
| 751 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 752 | .out(spare3_buf_8x_unused)); |
| 753 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 754 | .in01(1'b1), |
| 755 | .in10(1'b1), |
| 756 | .in11(1'b1), |
| 757 | .out(spare3_oai22_4x_unused)); |
| 758 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 759 | .out(spare3_inv_16x_unused)); |
| 760 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 761 | .in1(1'b1), |
| 762 | .out(spare3_nand2_16x_unused)); |
| 763 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 764 | .in1(1'b0), |
| 765 | .in2(1'b0), |
| 766 | .out(spare3_nor3_4x_unused)); |
| 767 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 768 | .in1(1'b1), |
| 769 | .out(spare3_nand2_8x_unused)); |
| 770 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 771 | .out(spare3_buf_16x_unused)); |
| 772 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 773 | .in1(1'b0), |
| 774 | .out(spare3_nor2_16x_unused)); |
| 775 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 776 | .out(spare3_inv_32x_unused)); |
| 777 | assign scan_out = so_3; |
| 778 | |
| 779 | |
| 780 | |
| 781 | endmodule |
| 782 | |