| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_usaloc_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2t_usaloc_dp ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | scan_out, |
| 39 | tcu_pce_ov, |
| 40 | tcu_muxtest, |
| 41 | tcu_aclk, |
| 42 | tcu_bclk, |
| 43 | tcu_scan_en, |
| 44 | tcu_clk_stop, |
| 45 | tagdp_lru_way_sel_c3, |
| 46 | vuaddp_fill_way_c3, |
| 47 | tag_hit_way_vld_c3, |
| 48 | arb_vuad_ce_err_c3, |
| 49 | vuadpm_bistordiag_ua_data, |
| 50 | vuaddp_vuad_evict_c3, |
| 51 | vuaddp_wr64_inst_c3, |
| 52 | vuaddp_vuad_sel_c4, |
| 53 | vuaddp_vuad_sel_rd, |
| 54 | vuaddp_vuad_sel_c2_d1, |
| 55 | vuaddp_bistordiag_wr_ua_c4, |
| 56 | vuaddp_sel_ua_wr_data_byp, |
| 57 | vuaddp_alloc_set_cond_c3, |
| 58 | vuaddp_alloc_rst_cond_c3, |
| 59 | filbuf_vuad_bypassed_c3, |
| 60 | arb_bs_or_bis_inst_c2, |
| 61 | vuad_array_rd_data_c1, |
| 62 | usaloc_vuad_array_wr_data_c4, |
| 63 | usaloc_vuad_used_c2, |
| 64 | usaloc_vuad_alloc_c2, |
| 65 | usaloc_diag_rd_ua_out, |
| 66 | usaloc_ua_ue_c2, |
| 67 | usaloc_ua_ce_c2, |
| 68 | usaloc_ua_synd_c2, |
| 69 | vuad_usaloc_mux_used_and_alloc_comb_sel0, |
| 70 | vuad_usaloc_mux_used_and_alloc_comb_sel1, |
| 71 | vuad_usaloc_mux_used_and_alloc_comb_sel2, |
| 72 | vuad_usaloc_mux_used_and_alloc_comb_sel3, |
| 73 | vuad_usaloc_mux_used_and_alloc_comb_sel4, |
| 74 | vuad_usaloc_mux_used_and_alloc_comb_sel5); |
| 75 | wire stop; |
| 76 | wire pce_ov; |
| 77 | wire siclk; |
| 78 | wire soclk; |
| 79 | wire se; |
| 80 | wire muxtst; |
| 81 | wire vuaddp_vuad_evict_c3_qual; |
| 82 | wire ua_ecc_synd_zero; |
| 83 | wire usaloc_ua_ue_c2_unbuff; |
| 84 | wire vuaddp_vuad_sel_rd_c2_n; |
| 85 | wire usaloc_ua_ce_c2_n; |
| 86 | wire vuaddp_vuad_sel_rd_c2; |
| 87 | wire [5:0] usaloc_ua_synd_c2_n; |
| 88 | wire [15:0] vuaddp_fill_way_c3_n; |
| 89 | wire [15:0] tag_hit_way_vld_c3_n; |
| 90 | wire [15:0] vuaddp_hit_wayvld_c3; |
| 91 | wire [15:0] vuaddp_hit_wayvld_c3_n; |
| 92 | wire [15:0] used_byp_c3_in_1; |
| 93 | wire [15:0] used_c3_n; |
| 94 | wire [15:0] used_or_alloc_c3; |
| 95 | wire [15:0] alloc_c3_n; |
| 96 | wire mux_used_byp_c3_in_2_3_4_sel1; |
| 97 | wire arb_bs_or_bis_inst_c3; |
| 98 | wire used_byp_c3_in_4; |
| 99 | wire [15:0] used_byp_c3_in_2_3_4; |
| 100 | wire [15:0] used_byp_c3_in_2_3_4_n; |
| 101 | wire [15:0] used_byp_c3_in_n; |
| 102 | wire [15:0] used_byp_c3_in_buf; |
| 103 | wire [15:0] alloc_byp_c3_in_buf; |
| 104 | wire vuaddp_bistordiag_wr_ua_c4_n; |
| 105 | wire vuaddp_vuad_sel_c4_n; |
| 106 | wire vuaddp_sel_ua_wr_data_byp_n; |
| 107 | wire ff_used_and_alloc_c2_scanin; |
| 108 | wire ff_used_and_alloc_c2_scanout; |
| 109 | wire ff_used_and_alloc_rd_c2_scanin; |
| 110 | wire ff_used_and_alloc_rd_c2_scanout; |
| 111 | wire vuaddp_vuad_sel_c2_d1_n; |
| 112 | wire [15:0] used_fnl_c2_buf; |
| 113 | wire ff_used_alloc_c3_scanin; |
| 114 | wire ff_used_alloc_c3_scanout; |
| 115 | wire arb_bs_or_bis_inst_c2_n; |
| 116 | wire [15:0] alloc_byp_c3_in_12_13; |
| 117 | wire [15:0] alloc_byp_c3_in_12_13_n; |
| 118 | wire [15:0] alloc_byp_c3_in_1; |
| 119 | wire [15:0] alloc_byp_c3_in_2; |
| 120 | wire [15:0] alloc_byp_c3_in_2_n; |
| 121 | wire ff_used_alloc_c4_scanin; |
| 122 | wire ff_used_alloc_c4_scanout; |
| 123 | wire ff_used_alloc_wr_c5_scanin; |
| 124 | wire ff_used_alloc_wr_c5_scanout; |
| 125 | wire ff_used_alloc_wr_c52_scanin; |
| 126 | wire ff_used_alloc_wr_c52_scanout; |
| 127 | |
| 128 | |
| 129 | input l2clk; |
| 130 | input scan_in; |
| 131 | output scan_out; |
| 132 | input tcu_pce_ov; |
| 133 | input tcu_muxtest; |
| 134 | input tcu_aclk; |
| 135 | input tcu_bclk; |
| 136 | input tcu_scan_en; |
| 137 | input tcu_clk_stop; |
| 138 | |
| 139 | |
| 140 | |
| 141 | // 100+ pins on the right. |
| 142 | input [15:0] tagdp_lru_way_sel_c3; // Right |
| 143 | input [15:0] vuaddp_fill_way_c3; // Right |
| 144 | //input [15:0] vuaddp_hit_wayvld_c3; // Right |
| 145 | |
| 146 | input [15:0] tag_hit_way_vld_c3; // Right |
| 147 | input arb_vuad_ce_err_c3; // Right |
| 148 | |
| 149 | input [38:0] vuadpm_bistordiag_ua_data; // Right |
| 150 | |
| 151 | // Right |
| 152 | input vuaddp_vuad_evict_c3; |
| 153 | input vuaddp_wr64_inst_c3; |
| 154 | |
| 155 | // Right |
| 156 | input vuaddp_vuad_sel_c4; |
| 157 | input vuaddp_vuad_sel_rd; |
| 158 | input vuaddp_vuad_sel_c2_d1; |
| 159 | |
| 160 | input vuaddp_bistordiag_wr_ua_c4; |
| 161 | input vuaddp_sel_ua_wr_data_byp; |
| 162 | input vuaddp_alloc_set_cond_c3; |
| 163 | input vuaddp_alloc_rst_cond_c3; |
| 164 | input filbuf_vuad_bypassed_c3; |
| 165 | input arb_bs_or_bis_inst_c2; |
| 166 | |
| 167 | // Bottom |
| 168 | input [77:39] vuad_array_rd_data_c1 ; |
| 169 | |
| 170 | output [77:39] usaloc_vuad_array_wr_data_c4; // Bottom |
| 171 | |
| 172 | output [15:0] usaloc_vuad_used_c2; // Top |
| 173 | output [15:0] usaloc_vuad_alloc_c2; // Top |
| 174 | |
| 175 | output [38:0] usaloc_diag_rd_ua_out ; // Right |
| 176 | |
| 177 | |
| 178 | output usaloc_ua_ue_c2; |
| 179 | output usaloc_ua_ce_c2; |
| 180 | output [5:0] usaloc_ua_synd_c2; |
| 181 | |
| 182 | input vuad_usaloc_mux_used_and_alloc_comb_sel0; |
| 183 | input vuad_usaloc_mux_used_and_alloc_comb_sel1; |
| 184 | input vuad_usaloc_mux_used_and_alloc_comb_sel2; |
| 185 | input vuad_usaloc_mux_used_and_alloc_comb_sel3; |
| 186 | input vuad_usaloc_mux_used_and_alloc_comb_sel4; |
| 187 | input vuad_usaloc_mux_used_and_alloc_comb_sel5; |
| 188 | |
| 189 | assign stop = tcu_clk_stop; |
| 190 | assign pce_ov = tcu_pce_ov; |
| 191 | assign siclk = tcu_aclk; |
| 192 | assign soclk = tcu_bclk; |
| 193 | assign se = tcu_scan_en; |
| 194 | assign muxtst = tcu_muxtest; |
| 195 | |
| 196 | wire [15:0] used_rd_byp_c2; |
| 197 | wire [15:0] used_rd_c2; |
| 198 | wire [15:0] used_byp_c1; |
| 199 | wire [15:0] used_byp_c3_in; |
| 200 | wire [15:0] used_c1; |
| 201 | wire [15:0] used_c2; |
| 202 | wire [15:0] used_c3; |
| 203 | wire [15:0] used_c4; |
| 204 | wire [15:0] used_corr_c2; |
| 205 | wire [15:0] used_fnl_c2; |
| 206 | wire [15:0] used_wr_data_c5; |
| 207 | wire [15:0] used_wr_data_c52; // BS 03/11/04 extra cycle for mem access |
| 208 | wire [15:0] alloc_rd_byp_c2; |
| 209 | wire [15:0] alloc_rd_c2; |
| 210 | wire [15:0] alloc_byp_c1; |
| 211 | wire [15:0] alloc_byp_c2_in; |
| 212 | wire [15:0] alloc_byp_c3_in; |
| 213 | wire [15:0] alloc_corr_c2; |
| 214 | wire [15:0] alloc_fnl_c2; |
| 215 | wire [15:0] alloc_c1; |
| 216 | wire [15:0] alloc_c2; |
| 217 | wire [15:0] alloc_c3; |
| 218 | wire [15:0] alloc_c4; |
| 219 | wire [15:0] alloc_wr_data_c5; |
| 220 | wire [15:0] alloc_wr_data_c52; // BS 03/11/04 extra cycle for mem access |
| 221 | wire [15:0] used_byp_c2c3; |
| 222 | wire [15:0] used_byp_c4c5; |
| 223 | wire [15:0] alloc_byp_c4c5; |
| 224 | wire [6:0] ua_ecc_wr_data_c3; |
| 225 | wire [6:0] ua_ecc_wr_data_c4; |
| 226 | wire [6:0] ua_ecc_wr_data_c5; |
| 227 | wire [6:0] ua_ecc_wr_data_c52; |
| 228 | wire [6:0] ua_ecc_rd_data_c2; |
| 229 | wire [6:0] ua_ecc_c2; |
| 230 | wire [6:0] ua_ecc_synd; |
| 231 | |
| 232 | l2t_usaloc_dp_nor_macro__dnor_16x__width_1 nor_vuaddp_vuad_evict_c3_qual |
| 233 | ( |
| 234 | .dout (vuaddp_vuad_evict_c3_qual), |
| 235 | .din0 (arb_vuad_ce_err_c3), |
| 236 | .din1 (vuaddp_vuad_evict_c3) |
| 237 | ); |
| 238 | |
| 239 | //////////////////////////////////////////////////////////////////////////////// |
| 240 | //// ALLOC AND USED BIT 32 dp pitches |
| 241 | ////////////////////////////////////////////////////////////////////////////////// |
| 242 | //assign usaloc_ua_ue_c2 = ((|(ua_ecc_synd[5:0])) & ~ua_ecc_synd[6]) & vuaddp_vuad_sel_rd_c2 ; |
| 243 | |
| 244 | l2t_usaloc_dp_cmp_macro__width_8 cmp_ua_ecc_synd_nonzero |
| 245 | ( |
| 246 | .dout (ua_ecc_synd_zero), |
| 247 | .din0 ({2'b0,ua_ecc_synd[5:0]}), |
| 248 | .din1 ({8'b0}) |
| 249 | ); |
| 250 | |
| 251 | l2t_usaloc_dp_nor_macro__ports_3__width_1 nor_usaloc_ua_ue_c2 |
| 252 | ( |
| 253 | .dout (usaloc_ua_ue_c2_unbuff), |
| 254 | .din0 (ua_ecc_synd[6]), |
| 255 | .din1 (vuaddp_vuad_sel_rd_c2_n), |
| 256 | .din2 (ua_ecc_synd_zero) |
| 257 | ); |
| 258 | |
| 259 | l2t_usaloc_dp_buff_macro__dbuff_48x__width_1 buff_usaloc_ua_ue_c2 |
| 260 | ( |
| 261 | .dout (usaloc_ua_ue_c2), |
| 262 | .din (usaloc_ua_ue_c2_unbuff) |
| 263 | ); |
| 264 | |
| 265 | |
| 266 | ///////////////////////////////////////////////////////////////////// |
| 267 | //assign usaloc_ua_ce_c2 = (ua_ecc_synd[6] & (vuaddp_vuad_sel_rd_c2 )); |
| 268 | l2t_usaloc_dp_nand_macro__width_1 nand_usaloc_ua_ce_c2 |
| 269 | ( |
| 270 | .dout (usaloc_ua_ce_c2_n), |
| 271 | .din0 (ua_ecc_synd[6]), |
| 272 | .din1 (vuaddp_vuad_sel_rd_c2) |
| 273 | ); |
| 274 | |
| 275 | l2t_usaloc_dp_inv_macro__width_1 inv_usaloc_ua_ce_c2 |
| 276 | ( |
| 277 | .dout (usaloc_ua_ce_c2), |
| 278 | .din (usaloc_ua_ce_c2_n) |
| 279 | ); |
| 280 | |
| 281 | ///////////////////////////////////////////////////////////////////// |
| 282 | //assign usaloc_ua_synd_c2 = (ua_ecc_synd[5:0] & {6{(vuaddp_vuad_sel_rd_c2 )}}); |
| 283 | |
| 284 | l2t_usaloc_dp_nand_macro__width_6 nand_usaloc_ua_synd_c2_n |
| 285 | ( |
| 286 | .dout (usaloc_ua_synd_c2_n[5:0]), |
| 287 | .din0 (ua_ecc_synd[5:0]), |
| 288 | .din1 ({6{vuaddp_vuad_sel_rd_c2}}) |
| 289 | ); |
| 290 | |
| 291 | l2t_usaloc_dp_inv_macro__dinv_48x__width_6 inv_usaloc_ua_synd_c2 |
| 292 | ( |
| 293 | .dout (usaloc_ua_synd_c2[5:0]), |
| 294 | .din (usaloc_ua_synd_c2_n[5:0]) |
| 295 | ); |
| 296 | |
| 297 | //////////////////////////////////////// |
| 298 | // in case of BIST and BST , to mitigate L2 cache pollution on copy routines, |
| 299 | // we will reset the Use bit everytime the BIST or BST hits in the L2 cache |
| 300 | // and does the store to L2. This way the same line that the BST or BIST |
| 301 | // is updating can be picked for replacement in the near future instead of |
| 302 | // another line which is not getting |
| 303 | // touched by the copy routine. |
| 304 | |
| 305 | //assign used_byp_c3_in_5[15:0] = ~used_byp_c3_in_2_3_4[15:0]); |
| 306 | //assign used_or_alloc_c3[15:0] = used_c3[15:0] | alloc_c3[15:0]; |
| 307 | |
| 308 | l2t_usaloc_dp_inv_macro__width_16 inv_vuaddp_fill_way_c3 |
| 309 | ( |
| 310 | .dout (vuaddp_fill_way_c3_n[15:0]), |
| 311 | .din (vuaddp_fill_way_c3[15:0]) |
| 312 | ); |
| 313 | |
| 314 | //////// Timing fix bypassed vuad ctl /////////////// |
| 315 | //inv_macro inv_arb_vuad_ce_err_c3 (width=1,dinv=16x) |
| 316 | // ( |
| 317 | // .dout (arb_vuad_ce_err_c3_n), |
| 318 | // .din (arb_vuad_ce_err_c3) |
| 319 | // ); |
| 320 | // |
| 321 | // |
| 322 | l2t_usaloc_dp_inv_macro__dinv_16x__width_16 inv_tag_hit_way_vld_c3 |
| 323 | ( |
| 324 | .dout (tag_hit_way_vld_c3_n[15:0]), |
| 325 | .din (tag_hit_way_vld_c3[15:0]) |
| 326 | ); |
| 327 | |
| 328 | |
| 329 | l2t_usaloc_dp_nor_macro__width_16 nor_vuaddp_hit_wayvld_c3 |
| 330 | ( |
| 331 | .dout (vuaddp_hit_wayvld_c3[15:0]), |
| 332 | .din0 (tag_hit_way_vld_c3_n[15:0]), |
| 333 | .din1 ({16{arb_vuad_ce_err_c3}}) |
| 334 | ); |
| 335 | ////////// Timing fix bypassed vuad ctl /////////////// |
| 336 | |
| 337 | l2t_usaloc_dp_inv_macro__width_16 inv_vuaddp_hit_wayvld_c3 |
| 338 | ( |
| 339 | .dout (vuaddp_hit_wayvld_c3_n[15:0]), |
| 340 | .din (vuaddp_hit_wayvld_c3[15:0]) |
| 341 | ); |
| 342 | |
| 343 | l2t_usaloc_dp_nand_macro__ports_3__width_16 nand_used_byp_c3_in_1 |
| 344 | ( |
| 345 | .dout (used_byp_c3_in_1[15:0]), |
| 346 | .din0 (used_c3_n[15:0]), |
| 347 | .din1 (vuaddp_fill_way_c3_n[15:0]), |
| 348 | .din2 (vuaddp_hit_wayvld_c3_n[15:0]) |
| 349 | ); |
| 350 | |
| 351 | // |
| 352 | //inv_macro inv_alloc_used_c3 (width=32,dinv=16x) |
| 353 | // ( |
| 354 | // .dout ({used_c3_n[15:0],alloc_c3_n[15:0]}), |
| 355 | // .din ({used_c3[15:0],alloc_c3[15:0]}) |
| 356 | // ); |
| 357 | // |
| 358 | l2t_usaloc_dp_nand_macro__width_16 nand_used_or_alloc_c3 |
| 359 | ( |
| 360 | .dout (used_or_alloc_c3[15:0]), |
| 361 | .din0 (used_c3_n[15:0]), |
| 362 | .din1 (alloc_c3_n[15:0]) |
| 363 | ); |
| 364 | |
| 365 | l2t_usaloc_dp_or_macro__width_1 or_for_sel_1 |
| 366 | ( |
| 367 | .dout (mux_used_byp_c3_in_2_3_4_sel1), |
| 368 | .din0 (vuaddp_wr64_inst_c3), |
| 369 | .din1 (arb_bs_or_bis_inst_c3) |
| 370 | ); |
| 371 | |
| 372 | l2t_usaloc_dp_cmp_macro__width_16 cmp_used_byp_c3_in_4 |
| 373 | ( |
| 374 | .dout (used_byp_c3_in_4), |
| 375 | .din0 (used_or_alloc_c3[15:0]), |
| 376 | .din1 (16'hFFFF) |
| 377 | ); |
| 378 | |
| 379 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_16r__width_16 mux_used_byp_c3_in_2_3_4 |
| 380 | ( |
| 381 | .dout (used_byp_c3_in_2_3_4[15:0]), |
| 382 | .din0 (tagdp_lru_way_sel_c3[15:0]), |
| 383 | .din1 (vuaddp_hit_wayvld_c3[15:0]), |
| 384 | .din2 (16'hffff), |
| 385 | .sel0 (vuaddp_vuad_evict_c3_qual), |
| 386 | .sel1 (mux_used_byp_c3_in_2_3_4_sel1), |
| 387 | .sel2 (used_byp_c3_in_4) |
| 388 | ); |
| 389 | |
| 390 | l2t_usaloc_dp_inv_macro__dinv_32x__width_16 inv_used_byp_c3_in_2_3_4 |
| 391 | ( |
| 392 | .dout (used_byp_c3_in_2_3_4_n[15:0]), |
| 393 | .din (used_byp_c3_in_2_3_4[15:0]) |
| 394 | ); |
| 395 | |
| 396 | //assign used_byp_c3_in[15:0] = used_byp_c3_in_1[15:0] & ~used_byp_c3_in_2_3_4[15:0] ; |
| 397 | |
| 398 | l2t_usaloc_dp_nand_macro__dnand_16x__width_16 and_used_byp_c3_in |
| 399 | ( |
| 400 | .dout (used_byp_c3_in_n[15:0]), |
| 401 | .din0 (used_byp_c3_in_1[15:0]), |
| 402 | .din1 (used_byp_c3_in_2_3_4_n[15:0]) |
| 403 | ); |
| 404 | |
| 405 | l2t_usaloc_dp_inv_macro__dinv_32x__width_16 inv_used_byp_c3_in |
| 406 | ( |
| 407 | .dout (used_byp_c3_in[15:0]), |
| 408 | .din (used_byp_c3_in_n[15:0]) |
| 409 | ); |
| 410 | |
| 411 | l2t_pgen32b_dp ua_ecc_gen |
| 412 | ( |
| 413 | .parity (ua_ecc_wr_data_c3[6:0]), |
| 414 | .dout ({used_byp_c3_in_buf[15:0],alloc_byp_c3_in_buf[15:0]}), |
| 415 | .din ({used_byp_c3_in[15:0],alloc_byp_c3_in[15:0]}) |
| 416 | ); |
| 417 | |
| 418 | |
| 419 | l2t_usaloc_dp_inv_macro__dinv_32x__width_1 vuaddp_bistordiag_wr_ua_c4_inv_slice |
| 420 | ( |
| 421 | .dout (vuaddp_bistordiag_wr_ua_c4_n ), |
| 422 | .din (vuaddp_bistordiag_wr_ua_c4 ) |
| 423 | ); |
| 424 | |
| 425 | l2t_usaloc_dp_inv_macro__dinv_32x__width_1 vuaddp_vuad_sel_c4_inv_slice |
| 426 | ( |
| 427 | .dout (vuaddp_vuad_sel_c4_n ), |
| 428 | .din (vuaddp_vuad_sel_c4 ) |
| 429 | ); |
| 430 | |
| 431 | //inv_macro vuaddp_vuad_sel_rd_inv_slice (width=1,dinv=32x) |
| 432 | // ( |
| 433 | // .dout (vuaddp_vuad_sel_rd_n ), |
| 434 | // .din (vuaddp_vuad_sel_rd ) |
| 435 | // ); |
| 436 | |
| 437 | l2t_usaloc_dp_inv_macro__dinv_32x__width_1 vuaddp_vuad_sel_rd_inv_c2_slice |
| 438 | ( |
| 439 | .dout (vuaddp_vuad_sel_rd_c2_n ), |
| 440 | .din (vuaddp_vuad_sel_rd_c2 ) |
| 441 | ); |
| 442 | l2t_usaloc_dp_inv_macro__dinv_32x__width_1 vuaddp_sel_ua_wr_data_byp_inv_slice |
| 443 | ( |
| 444 | .dout (vuaddp_sel_ua_wr_data_byp_n ), |
| 445 | .din (vuaddp_sel_ua_wr_data_byp ) |
| 446 | ); |
| 447 | |
| 448 | //inv_macro vuaddp_vuad_sel_c2_inv_slice (width=1,dinv=32x) |
| 449 | // ( |
| 450 | // .dout (vuaddp_vuad_sel_c2_n ), |
| 451 | // .din (vuaddp_vuad_sel_c2 ) |
| 452 | // ); |
| 453 | // |
| 454 | //inv_macro vuaddp_vuad_sel_c2orc3_inv_slice (width=1,dinv=32x) |
| 455 | // ( |
| 456 | // .dout (vuaddp_vuad_sel_c2orc3_n ), |
| 457 | // .din (vuaddp_vuad_sel_c2orc3 ) |
| 458 | // ); |
| 459 | // |
| 460 | |
| 461 | |
| 462 | l2t_usaloc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ff_used_and_alloc_c2 |
| 463 | ( |
| 464 | .scan_in(ff_used_and_alloc_c2_scanin), |
| 465 | .scan_out(ff_used_and_alloc_c2_scanout), |
| 466 | .dout ({ua_ecc_c2[6:0],used_c2[15:0],alloc_c2[15:0]}), |
| 467 | .din ({vuad_array_rd_data_c1[77:71],used_c1[15:0],alloc_c1[15:0]}), |
| 468 | .clk (l2clk), |
| 469 | .en (1'b1), |
| 470 | .se(se), |
| 471 | .siclk(siclk), |
| 472 | .soclk(soclk), |
| 473 | .pce_ov(pce_ov), |
| 474 | .stop(stop) |
| 475 | ) ; |
| 476 | |
| 477 | l2t_ecc39_dp ua_ecc_corr |
| 478 | ( |
| 479 | .dout ({used_corr_c2[15:0],alloc_corr_c2[15:0]}), |
| 480 | .cflag (ua_ecc_synd[5:0]), |
| 481 | .pflag (ua_ecc_synd[6]), |
| 482 | .din ({used_c2[15:0],alloc_c2[15:0]}), |
| 483 | .parity (ua_ecc_c2[6:0]) |
| 484 | ); |
| 485 | |
| 486 | l2t_usaloc_dp_msff_macro__dmsff_32x__stack_33r__width_33 ff_used_and_alloc_rd_c2 |
| 487 | ( |
| 488 | .scan_in(ff_used_and_alloc_rd_c2_scanin), |
| 489 | .scan_out(ff_used_and_alloc_rd_c2_scanout), |
| 490 | .dout({vuaddp_vuad_sel_rd_c2,used_rd_byp_c2[15:0],alloc_rd_byp_c2[15:0]}), |
| 491 | .din({vuaddp_vuad_sel_rd,vuad_array_rd_data_c1[70:55],vuad_array_rd_data_c1[54:39]}), |
| 492 | .clk(l2clk), |
| 493 | .en(1'b1), |
| 494 | .se(se), |
| 495 | .siclk(siclk), |
| 496 | .soclk(soclk), |
| 497 | .pce_ov(pce_ov), |
| 498 | .stop(stop) |
| 499 | ); |
| 500 | |
| 501 | l2t_usaloc_dp_buff_macro__dbuff_48x__width_32 buff_usaloc_vuad_alloc_c2 |
| 502 | ( |
| 503 | .dout ({usaloc_vuad_used_c2[15:0],usaloc_vuad_alloc_c2[15:0]}), |
| 504 | .din ({used_c2[15:0],alloc_c2[15:0]}) |
| 505 | ); |
| 506 | |
| 507 | |
| 508 | |
| 509 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_39r__width_39 mux_used_alloc_rd_c2 |
| 510 | ( |
| 511 | .dout ({ua_ecc_rd_data_c2[6:0],used_rd_c2[15:0],alloc_rd_c2[15:0]}), |
| 512 | .din0 ({ua_ecc_wr_data_c52[6:0],used_wr_data_c52[15:0],alloc_wr_data_c52[15:0]}), |
| 513 | .din1 ({ua_ecc_c2[6:0],used_rd_byp_c2[15:0],alloc_rd_byp_c2[15:0]}), |
| 514 | .sel0 (vuaddp_sel_ua_wr_data_byp), |
| 515 | .sel1 (vuaddp_sel_ua_wr_data_byp_n) |
| 516 | ); |
| 517 | |
| 518 | |
| 519 | l2t_usaloc_dp_buff_macro__dbuff_48x__width_39 buff_usaloc_diag_rd_ua_out |
| 520 | ( |
| 521 | .dout (usaloc_diag_rd_ua_out[38:0]), |
| 522 | .din ({ua_ecc_rd_data_c2[6:0],used_rd_c2[15:0],alloc_rd_c2[15:0]}) |
| 523 | ); |
| 524 | |
| 525 | // assign usaloc_diag_rd_ua_out[38:32] = ua_ecc_rd_data_c2[6:0]; |
| 526 | // assign usaloc_diag_rd_ua_out[31:16] = used_rd_c2[15:0]; |
| 527 | // assign usaloc_diag_rd_ua_out[15:0] = alloc_rd_c2[15:0]; |
| 528 | |
| 529 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32r__width_32 mux_fnl_used_alloc_c2 |
| 530 | ( |
| 531 | .dout({used_fnl_c2[15:0],alloc_fnl_c2[15:0]}), |
| 532 | .din0 ({used_corr_c2[15:0],alloc_corr_c2[15:0]}), |
| 533 | .din1 ({used_c2[15:0],alloc_c2[15:0]}), |
| 534 | .sel0 (vuaddp_vuad_sel_rd_c2), |
| 535 | .sel1 (vuaddp_vuad_sel_rd_c2_n) |
| 536 | ); |
| 537 | |
| 538 | |
| 539 | |
| 540 | |
| 541 | |
| 542 | l2t_usaloc_dp_inv_macro__dinv_32x__width_1 vuaddp_vuad_sel_c2_d1_inv_slice |
| 543 | ( |
| 544 | .dout (vuaddp_vuad_sel_c2_d1_n ), |
| 545 | .din (vuaddp_vuad_sel_c2_d1 ) |
| 546 | ); |
| 547 | |
| 548 | |
| 549 | |
| 550 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_16r__width_16 mux_used_alloc_byp_c2_in |
| 551 | ( |
| 552 | .dout (alloc_byp_c2_in[15:0]), |
| 553 | .din0 (alloc_fnl_c2[15:0]), |
| 554 | .din1 (alloc_byp_c3_in[15:0]), |
| 555 | .sel0 (vuaddp_vuad_sel_c2_d1_n), |
| 556 | .sel1 (vuaddp_vuad_sel_c2_d1) |
| 557 | ) ; |
| 558 | |
| 559 | l2t_usaloc_dp_buff_macro__minbuff_1__stack_33r__width_16 used_alloc_c3_minbuff ( |
| 560 | .din (used_fnl_c2[15:0]), |
| 561 | .dout(used_fnl_c2_buf[15:0])); |
| 562 | |
| 563 | l2t_usaloc_dp_msffi_macro__dmsffi_32x__stack_33r__width_33 ff_used_alloc_c3 |
| 564 | ( |
| 565 | .scan_in(ff_used_alloc_c3_scanin), |
| 566 | .scan_out(ff_used_alloc_c3_scanout), |
| 567 | .dout_l({arb_bs_or_bis_inst_c3,used_c3_n[15:0],alloc_c3_n[15:0]}), |
| 568 | .din({arb_bs_or_bis_inst_c2_n,used_fnl_c2_buf[15:0],alloc_byp_c2_in[15:0]}), |
| 569 | .clk(l2clk), |
| 570 | .en(1'b1), |
| 571 | .se(se), |
| 572 | .siclk(siclk), |
| 573 | .soclk(soclk), |
| 574 | .pce_ov(pce_ov), |
| 575 | .stop(stop) |
| 576 | ) ; |
| 577 | |
| 578 | l2t_usaloc_dp_inv_macro__dinv_16x__width_1 inv_arb_bs_or_bis_inst_c2 |
| 579 | ( |
| 580 | .dout (arb_bs_or_bis_inst_c2_n), |
| 581 | .din (arb_bs_or_bis_inst_c2) |
| 582 | ); |
| 583 | |
| 584 | //////////////////////////////////////////////////////////////////////////////////// |
| 585 | //////////////////////////////////////////////////////////////////////////////////// |
| 586 | //////////////////////////////////////////////////////////////////////////////////// |
| 587 | //////////////////////////////////////////////////////////////////////////////////// |
| 588 | //////////////////////////////////////////////////////////////////////////////////// |
| 589 | //////////////////////////////////////////////////////////////////////////////////// |
| 590 | //////////////////////////////////////////////////////////////////////////////////// |
| 591 | //////////////////////////////////////////////////////////////////////////////////// |
| 592 | //////////////////////////////////////////////////////////////////////////////////// |
| 593 | //////////////////////////////////////////////////////////////////////////////////// |
| 594 | //////////////////////////////////////////////////////////////////////////////////// |
| 595 | //////////////////////////////////////////////////////////////////////////////////// |
| 596 | //assign alloc_byp_c3_in[15:0] = ( alloc_c3[15:0] | |
| 597 | // ({16{vuaddp_alloc_set_cond_c3}} & vuaddp_hit_wayvld_c3[15:0]) | |
| 598 | // ({16{vuaddp_vuad_evict_c3}} & tagdp_lru_way_sel_c3[15:0]) ) & |
| 599 | // ~( ({16{vuaddp_alloc_rst_cond_c3}} & vuaddp_hit_wayvld_c3[15:0]) | |
| 600 | // ({16{filbuf_vuad_bypassed_c3}} & vuaddp_fill_way_c3[15:0])); |
| 601 | // |
| 602 | |
| 603 | //assign alloc_byp_c3_in_11[15:0] = alloc_c3[15:0]; |
| 604 | //assign alloc_byp_c3_in_12[15:0] = ({16{vuaddp_alloc_set_cond_c3}} & vuaddp_hit_wayvld_c3[15:0]); |
| 605 | //assign alloc_byp_c3_in_13[15:0] = ({16{vuaddp_vuad_evict_c3}} & tagdp_lru_way_sel_c3[15:0]); |
| 606 | //assign alloc_byp_c3_in_1[15:0] = alloc_byp_c3_in_11[15:0] | alloc_byp_c3_in_12[15:0] | alloc_byp_c3_in_13[15:0]; |
| 607 | |
| 608 | |
| 609 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_16r__width_16 mux_alloc_byp_c3_in_12_13 |
| 610 | ( |
| 611 | .dout (alloc_byp_c3_in_12_13[15:0]), |
| 612 | .din0 (vuaddp_hit_wayvld_c3[15:0]), |
| 613 | .din1 (tagdp_lru_way_sel_c3[15:0]), |
| 614 | .sel0 (vuaddp_alloc_set_cond_c3), |
| 615 | .sel1 (vuaddp_vuad_evict_c3_qual) |
| 616 | ); |
| 617 | |
| 618 | l2t_usaloc_dp_inv_macro__dinv_32x__width_16 inv_alloc_byp_c3_in_12_13 |
| 619 | ( |
| 620 | .dout (alloc_byp_c3_in_12_13_n[15:0]), |
| 621 | .din (alloc_byp_c3_in_12_13[15:0]) |
| 622 | ); |
| 623 | |
| 624 | l2t_usaloc_dp_nand_macro__dnand_16x__width_16 nand_alloc_byp_c3_in_1 |
| 625 | ( |
| 626 | .dout (alloc_byp_c3_in_1[15:0]), |
| 627 | .din0 (alloc_byp_c3_in_12_13_n[15:0]), |
| 628 | .din1 (alloc_c3_n[15:0]) |
| 629 | ); |
| 630 | |
| 631 | |
| 632 | //assign alloc_byp_c3_in_21[15:0] = ({16{vuaddp_alloc_rst_cond_c3}} & vuaddp_hit_wayvld_c3[15:0]); |
| 633 | //assign alloc_byp_c3_in_22[15:0] = ({16{filbuf_vuad_bypassed_c3}} & vuaddp_fill_way_c3[15:0]); |
| 634 | //assign alloc_byp_c3_in_2[15:0] = ~(alloc_byp_c3_in_21[15:0] | alloc_byp_c3_in_22[15:0]); |
| 635 | |
| 636 | |
| 637 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_16r__width_16 mux_alloc_byp_c3_in_21_22 |
| 638 | ( |
| 639 | .dout (alloc_byp_c3_in_2[15:0]), |
| 640 | .din0 (vuaddp_hit_wayvld_c3[15:0]), |
| 641 | .din1 (vuaddp_fill_way_c3[15:0]), |
| 642 | .sel0 (vuaddp_alloc_rst_cond_c3), |
| 643 | .sel1 (filbuf_vuad_bypassed_c3) |
| 644 | ); |
| 645 | |
| 646 | l2t_usaloc_dp_inv_macro__dinv_32x__width_16 inv_alloc_byp_c3_in_2 |
| 647 | ( |
| 648 | .dout (alloc_byp_c3_in_2_n[15:0]), |
| 649 | .din (alloc_byp_c3_in_2[15:0]) |
| 650 | ); |
| 651 | |
| 652 | l2t_usaloc_dp_and_macro__width_16 or_alloc_byp_c3_in |
| 653 | ( |
| 654 | .dout (alloc_byp_c3_in[15:0]), |
| 655 | .din0 (alloc_byp_c3_in_1[15:0]), |
| 656 | .din1 (alloc_byp_c3_in_2_n[15:0]) |
| 657 | ); |
| 658 | |
| 659 | |
| 660 | //assign alloc_byp_c3_in[15:0] = alloc_byp_c3_in_1[15:0] & alloc_byp_c3_in_2[15:0]; |
| 661 | |
| 662 | |
| 663 | |
| 664 | |
| 665 | //////////////////////////////////////////////////////////////////////////////////// |
| 666 | //////////////////////////////////////////////////////////////////////////////////// |
| 667 | //////////////////////////////////////////////////////////////////////////////////// |
| 668 | //////////////////////////////////////////////////////////////////////////////////// |
| 669 | //////////////////////////////////////////////////////////////////////////////////// |
| 670 | //////////////////////////////////////////////////////////////////////////////////// |
| 671 | //////////////////////////////////////////////////////////////////////////////////// |
| 672 | //////////////////////////////////////////////////////////////////////////////////// |
| 673 | //////////////////////////////////////////////////////////////////////////////////// |
| 674 | //////////////////////////////////////////////////////////////////////////////////// |
| 675 | //////////////////////////////////////////////////////////////////////////////////// |
| 676 | //////////////////////////////////////////////////////////////////////////////////// |
| 677 | |
| 678 | |
| 679 | |
| 680 | l2t_usaloc_dp_msff_macro__stack_39r__width_39 ff_used_alloc_c4 |
| 681 | ( |
| 682 | .scan_in(ff_used_alloc_c4_scanin), |
| 683 | .scan_out(ff_used_alloc_c4_scanout), |
| 684 | .dout({ua_ecc_wr_data_c4[6:0],used_c4[15:0],alloc_c4[15:0]}), |
| 685 | .din({ua_ecc_wr_data_c3[6:0],used_byp_c3_in_buf[15:0],alloc_byp_c3_in_buf[15:0]}), |
| 686 | .clk(l2clk), |
| 687 | .en(1'b1), |
| 688 | .se(se), |
| 689 | .siclk(siclk), |
| 690 | .soclk(soclk), |
| 691 | .pce_ov(pce_ov), |
| 692 | .stop(stop) |
| 693 | ) ; |
| 694 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_39r__width_39 mux_wr_array_used_alloc_c4 |
| 695 | ( |
| 696 | .dout (usaloc_vuad_array_wr_data_c4[77:39]), |
| 697 | .din0 ({ua_ecc_wr_data_c4[6:0],used_c4[15:0],alloc_c4[15:0]}), |
| 698 | .din1 (vuadpm_bistordiag_ua_data[38:0]), |
| 699 | .sel0 (vuaddp_bistordiag_wr_ua_c4_n), |
| 700 | .sel1 (vuaddp_bistordiag_wr_ua_c4) |
| 701 | ) ; |
| 702 | |
| 703 | |
| 704 | l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32r__width_32 mux_used_alloc_byp_c4c5 |
| 705 | ( |
| 706 | .dout ({used_byp_c4c5[15:0],alloc_byp_c4c5[15:0]}), |
| 707 | .din0 ({used_c4[15:0],alloc_c4[15:0]}), |
| 708 | .din1 ({used_wr_data_c5[15:0],alloc_wr_data_c5[15:0]}), |
| 709 | .sel0 (vuaddp_vuad_sel_c4), |
| 710 | .sel1 (vuaddp_vuad_sel_c4_n) |
| 711 | ); |
| 712 | |
| 713 | // Row 2, Vuad C5 flop |
| 714 | l2t_usaloc_dp_msff_macro__stack_39r__width_39 ff_used_alloc_wr_c5 |
| 715 | ( |
| 716 | .scan_in(ff_used_alloc_wr_c5_scanin), |
| 717 | .scan_out(ff_used_alloc_wr_c5_scanout), |
| 718 | .dout({ua_ecc_wr_data_c5[6:0],used_wr_data_c5[15:0],alloc_wr_data_c5[15:0]}), |
| 719 | .din({ua_ecc_wr_data_c4[6:0],used_c4[15:0],alloc_c4[15:0]}), |
| 720 | .clk(l2clk), |
| 721 | .en(1'b1), |
| 722 | .se(se), |
| 723 | .siclk(siclk), |
| 724 | .soclk(soclk), |
| 725 | .pce_ov(pce_ov), |
| 726 | .stop(stop) |
| 727 | ) ; |
| 728 | |
| 729 | |
| 730 | // Row1, Vuad C6 flop |
| 731 | l2t_usaloc_dp_msff_macro__stack_39r__width_39 ff_used_alloc_wr_c52 |
| 732 | ( |
| 733 | .scan_in(ff_used_alloc_wr_c52_scanin), |
| 734 | .scan_out(ff_used_alloc_wr_c52_scanout), |
| 735 | .dout({ua_ecc_wr_data_c52[6:0],used_wr_data_c52[15:0],alloc_wr_data_c52[15:0]}), |
| 736 | .din({ua_ecc_wr_data_c5[6:0],used_wr_data_c5[15:0],alloc_wr_data_c5[15:0]}), |
| 737 | .clk(l2clk), |
| 738 | .en(1'b1), |
| 739 | .se(se), |
| 740 | .siclk(siclk), |
| 741 | .soclk(soclk), |
| 742 | .pce_ov(pce_ov), |
| 743 | .stop(stop) |
| 744 | ) ; |
| 745 | |
| 746 | |
| 747 | //mux_macro mux_fnl_used_alloc_c2 (width=32,stack=32r,ports=2,mux=aonpe,dmux=8x) |
| 748 | // ( |
| 749 | // .dout({used_fnl_c2[15:0],alloc_fnl_c2[15:0]}), |
| 750 | // .din0 ({used_corr_c2[15:0],alloc_corr_c2[15:0]}), |
| 751 | // .din1 ({used_c2[15:0],alloc_c2[15:0]}), |
| 752 | // .sel0 (vuaddp_vuad_sel_rd_c2), |
| 753 | // .sel1 (vuaddp_vuad_sel_rd_c2_n) |
| 754 | // ); |
| 755 | // |
| 756 | // |
| 757 | //mux_macro mux_used_alloc_byp_c2_in (width=16,ports=2,mux=aonpe,stack=16r,dmux=8x) |
| 758 | // ( |
| 759 | // .dout (alloc_byp_c2_in[15:0]), |
| 760 | // .din0 (alloc_fnl_c2[15:0]), |
| 761 | // .din1 (alloc_byp_c3_in[15:0]), |
| 762 | // .sel0 (vuaddp_vuad_sel_c2_d1_n), |
| 763 | // .sel1 (vuaddp_vuad_sel_c2_d1) |
| 764 | // ) ; |
| 765 | // |
| 766 | // |
| 767 | // |
| 768 | // |
| 769 | //msff_macro ff_used_and_alloc_c2 (width=39,stack=39r) |
| 770 | // ( |
| 771 | // .scan_in(ff_used_and_alloc_c2_scanin), |
| 772 | // .scan_out(ff_used_and_alloc_c2_scanout), |
| 773 | // .dout ({ua_ecc_c2[6:0],used_c2[15:0],alloc_c2[15:0]}), |
| 774 | // .din ({vuad_array_rd_data_c1[77:71],used_c1[15:0],alloc_c1[15:0]}), |
| 775 | // .clk (l2clk), |
| 776 | // .en (1'b1) |
| 777 | // ) ; |
| 778 | // |
| 779 | //------------------------------------------------------------------------------------- |
| 780 | // assign mux_used_and_alloc_comb_sel0 = vuaddp_vuad_sel_rd_c2 & vuaddp_vuad_sel_c2_d1_n & |
| 781 | // vuaddp_vuad_sel_c2 & vuaddp_vuad_sel_c2orc3 & vuaddp_vuad_sel_rd_n; |
| 782 | // assign mux_used_and_alloc_comb_sel1 = vuaddp_vuad_sel_rd_c2_n & vuaddp_vuad_sel_c2_d1_n & |
| 783 | // vuaddp_vuad_sel_c2 & vuaddp_vuad_sel_c2orc3 & vuaddp_vuad_sel_rd_n; |
| 784 | // assign mux_used_and_alloc_comb_sel2 = vuaddp_vuad_sel_c2_d1 & |
| 785 | // vuaddp_vuad_sel_c2 & vuaddp_vuad_sel_c2orc3 & vuaddp_vuad_sel_rd_n; |
| 786 | // assign mux_used_and_alloc_comb_sel3 = vuaddp_vuad_sel_c2_n & vuaddp_vuad_sel_c2orc3 & vuaddp_vuad_sel_rd_n ; |
| 787 | // assign mux_used_and_alloc_comb_sel4 = vuaddp_vuad_sel_c2orc3_n & vuaddp_vuad_sel_rd_n ; |
| 788 | // assign mux_used_and_alloc_comb_sel5 = vuaddp_vuad_sel_rd ; |
| 789 | |
| 790 | //------------------------------------------------------------------------------------- |
| 791 | //// sel0 |
| 792 | //and_macro alloc_comb_and_sel0_and0 (width=1,ports=3) |
| 793 | // ( |
| 794 | // .dout (mux_u_and_a_comb_sel0_and0), |
| 795 | // .din0 (vuaddp_vuad_sel_rd_c2), |
| 796 | // .din1 (vuaddp_vuad_sel_c2_d1_n), |
| 797 | // .din2 (vuaddp_vuad_sel_c2) |
| 798 | // ); |
| 799 | //and_macro alloc_comb_and_sel0_and1 (width=1,ports=3) |
| 800 | // ( |
| 801 | // .dout (mux_used_and_alloc_comb_sel0), |
| 802 | // .din0 (mux_u_and_a_comb_sel0_and0), |
| 803 | // .din1 (vuaddp_vuad_sel_c2orc3), |
| 804 | // .din2 (vuaddp_vuad_sel_rd_n) |
| 805 | // ); |
| 806 | // |
| 807 | // |
| 808 | //// sel1 |
| 809 | //and_macro alloc_comb_and_sel1_and0 (width=1,ports=3) |
| 810 | // ( |
| 811 | // .dout (mux_u_and_a_comb_sel1_and0), |
| 812 | // .din0 (vuaddp_vuad_sel_rd_c2_n), |
| 813 | // .din1 (vuaddp_vuad_sel_c2_d1_n), |
| 814 | // .din2 (vuaddp_vuad_sel_c2) |
| 815 | // ); |
| 816 | // |
| 817 | //and_macro alloc_comb_and_sel1_and1 (width=1,ports=3) |
| 818 | // ( |
| 819 | // .dout (mux_used_and_alloc_comb_sel1), |
| 820 | // .din0 (mux_u_and_a_comb_sel1_and0), |
| 821 | // .din1 (vuaddp_vuad_sel_c2orc3), |
| 822 | // .din2 (vuaddp_vuad_sel_rd_n) |
| 823 | // ); |
| 824 | // |
| 825 | //// sel2 |
| 826 | //and_macro alloc_comb_and_sel2_and0 (width=1,ports=3) |
| 827 | // ( |
| 828 | // .dout (mux_u_and_a_comb_sel2_and0), |
| 829 | // .din0 (vuaddp_vuad_sel_c2_d1), |
| 830 | // .din1 (vuaddp_vuad_sel_c2), |
| 831 | // .din2 (vuaddp_vuad_sel_c2orc3) |
| 832 | // ); |
| 833 | // |
| 834 | //and_macro alloc_comb_and_sel2_and1 (width=1,ports=2) |
| 835 | // ( |
| 836 | // .dout (mux_used_and_alloc_comb_sel2), |
| 837 | // .din0 (mux_u_and_a_comb_sel2_and0), |
| 838 | // .din1 (vuaddp_vuad_sel_rd_n) |
| 839 | // ); |
| 840 | // |
| 841 | //// sel3 |
| 842 | //and_macro alloc_comb_and_sel3_and0 (width=1,ports=3) |
| 843 | // ( |
| 844 | // .dout (mux_used_and_alloc_comb_sel3), |
| 845 | // .din0 (vuaddp_vuad_sel_c2_n), |
| 846 | // .din1 (vuaddp_vuad_sel_c2orc3), |
| 847 | // .din2 (vuaddp_vuad_sel_rd_n) |
| 848 | // ); |
| 849 | // |
| 850 | //// sel4 |
| 851 | //and_macro alloc_comb_and_sel4_and0 (width=1,ports=2) |
| 852 | // ( |
| 853 | // .dout (mux_used_and_alloc_comb_sel4), |
| 854 | // .din0 (vuaddp_vuad_sel_c2orc3_n), |
| 855 | // .din1 (vuaddp_vuad_sel_rd_n) |
| 856 | // ); |
| 857 | // |
| 858 | //// sel5 |
| 859 | //assign mux_used_and_alloc_comb_sel5 = vuaddp_vuad_sel_rd ; |
| 860 | |
| 861 | l2t_usaloc_dp_mux_macro__dmux_16x__mux_pgnpe__ports_6__stack_32r__width_32 mux_used_and_alloc_comb |
| 862 | ( |
| 863 | .dout ({used_c1[15:0],alloc_c1[15:0]}), |
| 864 | .din0 ({used_corr_c2[15:0],alloc_corr_c2[15:0]}), |
| 865 | .din1 ({used_c2[15:0],alloc_c2[15:0]}), |
| 866 | .din2 ({used_c2[15:0],alloc_byp_c3_in[15:0]}), |
| 867 | .din3 ({used_byp_c3_in[15:0],alloc_byp_c3_in[15:0]}), |
| 868 | .din4 ({used_byp_c4c5[15:0],alloc_byp_c4c5[15:0]}), |
| 869 | .din5 ({vuad_array_rd_data_c1[70:55],vuad_array_rd_data_c1[54:39]}), |
| 870 | .sel0 ( vuad_usaloc_mux_used_and_alloc_comb_sel0) , |
| 871 | .sel1 ( vuad_usaloc_mux_used_and_alloc_comb_sel1) , |
| 872 | .sel2 ( vuad_usaloc_mux_used_and_alloc_comb_sel2) , |
| 873 | .sel3 ( vuad_usaloc_mux_used_and_alloc_comb_sel3) , |
| 874 | .sel4 ( vuad_usaloc_mux_used_and_alloc_comb_sel4) , |
| 875 | .sel5 ( vuad_usaloc_mux_used_and_alloc_comb_sel5), |
| 876 | .muxtst(muxtst) |
| 877 | ) ; |
| 878 | |
| 879 | |
| 880 | // fixscan start: |
| 881 | assign ff_used_and_alloc_c2_scanin = scan_in ; |
| 882 | assign ff_used_and_alloc_rd_c2_scanin = ff_used_and_alloc_c2_scanout; |
| 883 | assign ff_used_alloc_c3_scanin = ff_used_and_alloc_rd_c2_scanout; |
| 884 | assign ff_used_alloc_c4_scanin = ff_used_alloc_c3_scanout ; |
| 885 | assign ff_used_alloc_wr_c5_scanin = ff_used_alloc_c4_scanout ; |
| 886 | assign ff_used_alloc_wr_c52_scanin = ff_used_alloc_wr_c5_scanout; |
| 887 | assign scan_out = ff_used_alloc_wr_c52_scanout; |
| 888 | // fixscan end: |
| 889 | endmodule |
| 890 | |
| 891 | |
| 892 | |
| 893 | // |
| 894 | // nor macro for ports = 2,3 |
| 895 | // |
| 896 | // |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | |
| 902 | module l2t_usaloc_dp_nor_macro__dnor_16x__width_1 ( |
| 903 | din0, |
| 904 | din1, |
| 905 | dout); |
| 906 | input [0:0] din0; |
| 907 | input [0:0] din1; |
| 908 | output [0:0] dout; |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | |
| 914 | |
| 915 | nor2 #(1) d0_0 ( |
| 916 | .in0(din0[0:0]), |
| 917 | .in1(din1[0:0]), |
| 918 | .out(dout[0:0]) |
| 919 | ); |
| 920 | |
| 921 | |
| 922 | |
| 923 | |
| 924 | |
| 925 | |
| 926 | |
| 927 | endmodule |
| 928 | |
| 929 | |
| 930 | |
| 931 | |
| 932 | |
| 933 | // |
| 934 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 935 | // |
| 936 | // |
| 937 | |
| 938 | |
| 939 | |
| 940 | |
| 941 | |
| 942 | module l2t_usaloc_dp_cmp_macro__width_8 ( |
| 943 | din0, |
| 944 | din1, |
| 945 | dout); |
| 946 | input [7:0] din0; |
| 947 | input [7:0] din1; |
| 948 | output dout; |
| 949 | |
| 950 | |
| 951 | |
| 952 | |
| 953 | |
| 954 | |
| 955 | cmp #(8) m0_0 ( |
| 956 | .in0(din0[7:0]), |
| 957 | .in1(din1[7:0]), |
| 958 | .out(dout) |
| 959 | ); |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | |
| 967 | |
| 968 | |
| 969 | |
| 970 | endmodule |
| 971 | |
| 972 | |
| 973 | |
| 974 | |
| 975 | |
| 976 | // |
| 977 | // nor macro for ports = 2,3 |
| 978 | // |
| 979 | // |
| 980 | |
| 981 | |
| 982 | |
| 983 | |
| 984 | |
| 985 | module l2t_usaloc_dp_nor_macro__ports_3__width_1 ( |
| 986 | din0, |
| 987 | din1, |
| 988 | din2, |
| 989 | dout); |
| 990 | input [0:0] din0; |
| 991 | input [0:0] din1; |
| 992 | input [0:0] din2; |
| 993 | output [0:0] dout; |
| 994 | |
| 995 | |
| 996 | |
| 997 | |
| 998 | |
| 999 | |
| 1000 | nor3 #(1) d0_0 ( |
| 1001 | .in0(din0[0:0]), |
| 1002 | .in1(din1[0:0]), |
| 1003 | .in2(din2[0:0]), |
| 1004 | .out(dout[0:0]) |
| 1005 | ); |
| 1006 | |
| 1007 | |
| 1008 | |
| 1009 | |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | endmodule |
| 1014 | |
| 1015 | |
| 1016 | |
| 1017 | |
| 1018 | |
| 1019 | // |
| 1020 | // buff macro |
| 1021 | // |
| 1022 | // |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | |
| 1028 | module l2t_usaloc_dp_buff_macro__dbuff_48x__width_1 ( |
| 1029 | din, |
| 1030 | dout); |
| 1031 | input [0:0] din; |
| 1032 | output [0:0] dout; |
| 1033 | |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | buff #(1) d0_0 ( |
| 1040 | .in(din[0:0]), |
| 1041 | .out(dout[0:0]) |
| 1042 | ); |
| 1043 | |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 | endmodule |
| 1052 | |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | // |
| 1058 | // nand macro for ports = 2,3,4 |
| 1059 | // |
| 1060 | // |
| 1061 | |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | module l2t_usaloc_dp_nand_macro__width_1 ( |
| 1067 | din0, |
| 1068 | din1, |
| 1069 | dout); |
| 1070 | input [0:0] din0; |
| 1071 | input [0:0] din1; |
| 1072 | output [0:0] dout; |
| 1073 | |
| 1074 | |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | |
| 1079 | nand2 #(1) d0_0 ( |
| 1080 | .in0(din0[0:0]), |
| 1081 | .in1(din1[0:0]), |
| 1082 | .out(dout[0:0]) |
| 1083 | ); |
| 1084 | |
| 1085 | |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | |
| 1092 | |
| 1093 | endmodule |
| 1094 | |
| 1095 | |
| 1096 | |
| 1097 | |
| 1098 | |
| 1099 | // |
| 1100 | // invert macro |
| 1101 | // |
| 1102 | // |
| 1103 | |
| 1104 | |
| 1105 | |
| 1106 | |
| 1107 | |
| 1108 | module l2t_usaloc_dp_inv_macro__width_1 ( |
| 1109 | din, |
| 1110 | dout); |
| 1111 | input [0:0] din; |
| 1112 | output [0:0] dout; |
| 1113 | |
| 1114 | |
| 1115 | |
| 1116 | |
| 1117 | |
| 1118 | |
| 1119 | inv #(1) d0_0 ( |
| 1120 | .in(din[0:0]), |
| 1121 | .out(dout[0:0]) |
| 1122 | ); |
| 1123 | |
| 1124 | |
| 1125 | |
| 1126 | |
| 1127 | |
| 1128 | |
| 1129 | |
| 1130 | |
| 1131 | |
| 1132 | endmodule |
| 1133 | |
| 1134 | |
| 1135 | |
| 1136 | |
| 1137 | |
| 1138 | // |
| 1139 | // nand macro for ports = 2,3,4 |
| 1140 | // |
| 1141 | // |
| 1142 | |
| 1143 | |
| 1144 | |
| 1145 | |
| 1146 | |
| 1147 | module l2t_usaloc_dp_nand_macro__width_6 ( |
| 1148 | din0, |
| 1149 | din1, |
| 1150 | dout); |
| 1151 | input [5:0] din0; |
| 1152 | input [5:0] din1; |
| 1153 | output [5:0] dout; |
| 1154 | |
| 1155 | |
| 1156 | |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | nand2 #(6) d0_0 ( |
| 1161 | .in0(din0[5:0]), |
| 1162 | .in1(din1[5:0]), |
| 1163 | .out(dout[5:0]) |
| 1164 | ); |
| 1165 | |
| 1166 | |
| 1167 | |
| 1168 | |
| 1169 | |
| 1170 | |
| 1171 | |
| 1172 | |
| 1173 | |
| 1174 | endmodule |
| 1175 | |
| 1176 | |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | // |
| 1181 | // invert macro |
| 1182 | // |
| 1183 | // |
| 1184 | |
| 1185 | |
| 1186 | |
| 1187 | |
| 1188 | |
| 1189 | module l2t_usaloc_dp_inv_macro__dinv_48x__width_6 ( |
| 1190 | din, |
| 1191 | dout); |
| 1192 | input [5:0] din; |
| 1193 | output [5:0] dout; |
| 1194 | |
| 1195 | |
| 1196 | |
| 1197 | |
| 1198 | |
| 1199 | |
| 1200 | inv #(6) d0_0 ( |
| 1201 | .in(din[5:0]), |
| 1202 | .out(dout[5:0]) |
| 1203 | ); |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | |
| 1212 | |
| 1213 | endmodule |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | // |
| 1220 | // invert macro |
| 1221 | // |
| 1222 | // |
| 1223 | |
| 1224 | |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | module l2t_usaloc_dp_inv_macro__width_16 ( |
| 1229 | din, |
| 1230 | dout); |
| 1231 | input [15:0] din; |
| 1232 | output [15:0] dout; |
| 1233 | |
| 1234 | |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | inv #(16) d0_0 ( |
| 1240 | .in(din[15:0]), |
| 1241 | .out(dout[15:0]) |
| 1242 | ); |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | endmodule |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | |
| 1258 | // |
| 1259 | // invert macro |
| 1260 | // |
| 1261 | // |
| 1262 | |
| 1263 | |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | module l2t_usaloc_dp_inv_macro__dinv_16x__width_16 ( |
| 1268 | din, |
| 1269 | dout); |
| 1270 | input [15:0] din; |
| 1271 | output [15:0] dout; |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | |
| 1277 | |
| 1278 | inv #(16) d0_0 ( |
| 1279 | .in(din[15:0]), |
| 1280 | .out(dout[15:0]) |
| 1281 | ); |
| 1282 | |
| 1283 | |
| 1284 | |
| 1285 | |
| 1286 | |
| 1287 | |
| 1288 | |
| 1289 | |
| 1290 | |
| 1291 | endmodule |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | // |
| 1298 | // nor macro for ports = 2,3 |
| 1299 | // |
| 1300 | // |
| 1301 | |
| 1302 | |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | module l2t_usaloc_dp_nor_macro__width_16 ( |
| 1307 | din0, |
| 1308 | din1, |
| 1309 | dout); |
| 1310 | input [15:0] din0; |
| 1311 | input [15:0] din1; |
| 1312 | output [15:0] dout; |
| 1313 | |
| 1314 | |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | |
| 1319 | nor2 #(16) d0_0 ( |
| 1320 | .in0(din0[15:0]), |
| 1321 | .in1(din1[15:0]), |
| 1322 | .out(dout[15:0]) |
| 1323 | ); |
| 1324 | |
| 1325 | |
| 1326 | |
| 1327 | |
| 1328 | |
| 1329 | |
| 1330 | |
| 1331 | endmodule |
| 1332 | |
| 1333 | |
| 1334 | |
| 1335 | |
| 1336 | |
| 1337 | // |
| 1338 | // nand macro for ports = 2,3,4 |
| 1339 | // |
| 1340 | // |
| 1341 | |
| 1342 | |
| 1343 | |
| 1344 | |
| 1345 | |
| 1346 | module l2t_usaloc_dp_nand_macro__ports_3__width_16 ( |
| 1347 | din0, |
| 1348 | din1, |
| 1349 | din2, |
| 1350 | dout); |
| 1351 | input [15:0] din0; |
| 1352 | input [15:0] din1; |
| 1353 | input [15:0] din2; |
| 1354 | output [15:0] dout; |
| 1355 | |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | |
| 1360 | |
| 1361 | nand3 #(16) d0_0 ( |
| 1362 | .in0(din0[15:0]), |
| 1363 | .in1(din1[15:0]), |
| 1364 | .in2(din2[15:0]), |
| 1365 | .out(dout[15:0]) |
| 1366 | ); |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | endmodule |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | // |
| 1383 | // nand macro for ports = 2,3,4 |
| 1384 | // |
| 1385 | // |
| 1386 | |
| 1387 | |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | module l2t_usaloc_dp_nand_macro__width_16 ( |
| 1392 | din0, |
| 1393 | din1, |
| 1394 | dout); |
| 1395 | input [15:0] din0; |
| 1396 | input [15:0] din1; |
| 1397 | output [15:0] dout; |
| 1398 | |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | |
| 1403 | |
| 1404 | nand2 #(16) d0_0 ( |
| 1405 | .in0(din0[15:0]), |
| 1406 | .in1(din1[15:0]), |
| 1407 | .out(dout[15:0]) |
| 1408 | ); |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | |
| 1415 | |
| 1416 | |
| 1417 | |
| 1418 | endmodule |
| 1419 | |
| 1420 | |
| 1421 | |
| 1422 | |
| 1423 | |
| 1424 | // |
| 1425 | // or macro for ports = 2,3 |
| 1426 | // |
| 1427 | // |
| 1428 | |
| 1429 | |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | module l2t_usaloc_dp_or_macro__width_1 ( |
| 1434 | din0, |
| 1435 | din1, |
| 1436 | dout); |
| 1437 | input [0:0] din0; |
| 1438 | input [0:0] din1; |
| 1439 | output [0:0] dout; |
| 1440 | |
| 1441 | |
| 1442 | |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | or2 #(1) d0_0 ( |
| 1447 | .in0(din0[0:0]), |
| 1448 | .in1(din1[0:0]), |
| 1449 | .out(dout[0:0]) |
| 1450 | ); |
| 1451 | |
| 1452 | |
| 1453 | |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | |
| 1460 | endmodule |
| 1461 | |
| 1462 | |
| 1463 | |
| 1464 | |
| 1465 | |
| 1466 | // |
| 1467 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 1468 | // |
| 1469 | // |
| 1470 | |
| 1471 | |
| 1472 | |
| 1473 | |
| 1474 | |
| 1475 | module l2t_usaloc_dp_cmp_macro__width_16 ( |
| 1476 | din0, |
| 1477 | din1, |
| 1478 | dout); |
| 1479 | input [15:0] din0; |
| 1480 | input [15:0] din1; |
| 1481 | output dout; |
| 1482 | |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | |
| 1487 | |
| 1488 | cmp #(16) m0_0 ( |
| 1489 | .in0(din0[15:0]), |
| 1490 | .in1(din1[15:0]), |
| 1491 | .out(dout) |
| 1492 | ); |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |
| 1498 | |
| 1499 | |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | endmodule |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1510 | // also for pass-gate with decoder |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | // any PARAMS parms go into naming of macro |
| 1517 | |
| 1518 | module l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_16r__width_16 ( |
| 1519 | din0, |
| 1520 | sel0, |
| 1521 | din1, |
| 1522 | sel1, |
| 1523 | din2, |
| 1524 | sel2, |
| 1525 | dout); |
| 1526 | wire buffout0; |
| 1527 | wire buffout1; |
| 1528 | wire buffout2; |
| 1529 | |
| 1530 | input [15:0] din0; |
| 1531 | input sel0; |
| 1532 | input [15:0] din1; |
| 1533 | input sel1; |
| 1534 | input [15:0] din2; |
| 1535 | input sel2; |
| 1536 | output [15:0] dout; |
| 1537 | |
| 1538 | |
| 1539 | |
| 1540 | |
| 1541 | |
| 1542 | cl_dp1_muxbuff3_8x c0_0 ( |
| 1543 | .in0(sel0), |
| 1544 | .in1(sel1), |
| 1545 | .in2(sel2), |
| 1546 | .out0(buffout0), |
| 1547 | .out1(buffout1), |
| 1548 | .out2(buffout2) |
| 1549 | ); |
| 1550 | mux3s #(16) d0_0 ( |
| 1551 | .sel0(buffout0), |
| 1552 | .sel1(buffout1), |
| 1553 | .sel2(buffout2), |
| 1554 | .in0(din0[15:0]), |
| 1555 | .in1(din1[15:0]), |
| 1556 | .in2(din2[15:0]), |
| 1557 | .dout(dout[15:0]) |
| 1558 | ); |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | |
| 1569 | |
| 1570 | |
| 1571 | |
| 1572 | endmodule |
| 1573 | |
| 1574 | |
| 1575 | // |
| 1576 | // invert macro |
| 1577 | // |
| 1578 | // |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | module l2t_usaloc_dp_inv_macro__dinv_32x__width_16 ( |
| 1585 | din, |
| 1586 | dout); |
| 1587 | input [15:0] din; |
| 1588 | output [15:0] dout; |
| 1589 | |
| 1590 | |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | inv #(16) d0_0 ( |
| 1596 | .in(din[15:0]), |
| 1597 | .out(dout[15:0]) |
| 1598 | ); |
| 1599 | |
| 1600 | |
| 1601 | |
| 1602 | |
| 1603 | |
| 1604 | |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | endmodule |
| 1609 | |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | |
| 1614 | // |
| 1615 | // nand macro for ports = 2,3,4 |
| 1616 | // |
| 1617 | // |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | |
| 1623 | module l2t_usaloc_dp_nand_macro__dnand_16x__width_16 ( |
| 1624 | din0, |
| 1625 | din1, |
| 1626 | dout); |
| 1627 | input [15:0] din0; |
| 1628 | input [15:0] din1; |
| 1629 | output [15:0] dout; |
| 1630 | |
| 1631 | |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | |
| 1636 | nand2 #(16) d0_0 ( |
| 1637 | .in0(din0[15:0]), |
| 1638 | .in1(din1[15:0]), |
| 1639 | .out(dout[15:0]) |
| 1640 | ); |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | |
| 1650 | endmodule |
| 1651 | |
| 1652 | |
| 1653 | |
| 1654 | |
| 1655 | // |
| 1656 | // xor macro for ports = 2,3 |
| 1657 | // |
| 1658 | // |
| 1659 | |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | module l2t_usaloc_dp_xor_macro__dxor_8x__ports_3__width_1 ( |
| 1665 | din0, |
| 1666 | din1, |
| 1667 | din2, |
| 1668 | dout); |
| 1669 | input [0:0] din0; |
| 1670 | input [0:0] din1; |
| 1671 | input [0:0] din2; |
| 1672 | output [0:0] dout; |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | |
| 1677 | |
| 1678 | xor3 #(1) d0_0 ( |
| 1679 | .in0(din0[0:0]), |
| 1680 | .in1(din1[0:0]), |
| 1681 | .in2(din2[0:0]), |
| 1682 | .out(dout[0:0]) |
| 1683 | ); |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | |
| 1690 | |
| 1691 | |
| 1692 | endmodule |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | // |
| 1699 | // xor macro for ports = 2,3 |
| 1700 | // |
| 1701 | // |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | module l2t_usaloc_dp_xor_macro__dxor_8x__ports_2__width_1 ( |
| 1708 | din0, |
| 1709 | din1, |
| 1710 | dout); |
| 1711 | input [0:0] din0; |
| 1712 | input [0:0] din1; |
| 1713 | output [0:0] dout; |
| 1714 | |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 | |
| 1719 | xor2 #(1) d0_0 ( |
| 1720 | .in0(din0[0:0]), |
| 1721 | .in1(din1[0:0]), |
| 1722 | .out(dout[0:0]) |
| 1723 | ); |
| 1724 | |
| 1725 | |
| 1726 | |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | |
| 1731 | |
| 1732 | endmodule |
| 1733 | |
| 1734 | |
| 1735 | |
| 1736 | |
| 1737 | |
| 1738 | // |
| 1739 | // invert macro |
| 1740 | // |
| 1741 | // |
| 1742 | |
| 1743 | |
| 1744 | |
| 1745 | |
| 1746 | |
| 1747 | module l2t_usaloc_dp_inv_macro__dinv_32x__width_1 ( |
| 1748 | din, |
| 1749 | dout); |
| 1750 | input [0:0] din; |
| 1751 | output [0:0] dout; |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | inv #(1) d0_0 ( |
| 1759 | .in(din[0:0]), |
| 1760 | .out(dout[0:0]) |
| 1761 | ); |
| 1762 | |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | endmodule |
| 1772 | |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | |
| 1778 | |
| 1779 | |
| 1780 | |
| 1781 | // any PARAMS parms go into naming of macro |
| 1782 | |
| 1783 | module l2t_usaloc_dp_msff_macro__dmsff_32x__stack_39r__width_39 ( |
| 1784 | din, |
| 1785 | clk, |
| 1786 | en, |
| 1787 | se, |
| 1788 | scan_in, |
| 1789 | siclk, |
| 1790 | soclk, |
| 1791 | pce_ov, |
| 1792 | stop, |
| 1793 | dout, |
| 1794 | scan_out); |
| 1795 | wire l1clk; |
| 1796 | wire siclk_out; |
| 1797 | wire soclk_out; |
| 1798 | wire [37:0] so; |
| 1799 | |
| 1800 | input [38:0] din; |
| 1801 | |
| 1802 | |
| 1803 | input clk; |
| 1804 | input en; |
| 1805 | input se; |
| 1806 | input scan_in; |
| 1807 | input siclk; |
| 1808 | input soclk; |
| 1809 | input pce_ov; |
| 1810 | input stop; |
| 1811 | |
| 1812 | |
| 1813 | |
| 1814 | output [38:0] dout; |
| 1815 | |
| 1816 | |
| 1817 | output scan_out; |
| 1818 | |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | cl_dp1_l1hdr_8x c0_0 ( |
| 1823 | .l2clk(clk), |
| 1824 | .pce(en), |
| 1825 | .aclk(siclk), |
| 1826 | .bclk(soclk), |
| 1827 | .l1clk(l1clk), |
| 1828 | .se(se), |
| 1829 | .pce_ov(pce_ov), |
| 1830 | .stop(stop), |
| 1831 | .siclk_out(siclk_out), |
| 1832 | .soclk_out(soclk_out) |
| 1833 | ); |
| 1834 | dff #(39) d0_0 ( |
| 1835 | .l1clk(l1clk), |
| 1836 | .siclk(siclk_out), |
| 1837 | .soclk(soclk_out), |
| 1838 | .d(din[38:0]), |
| 1839 | .si({scan_in,so[37:0]}), |
| 1840 | .so({so[37:0],scan_out}), |
| 1841 | .q(dout[38:0]) |
| 1842 | ); |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | |
| 1848 | |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | |
| 1855 | |
| 1856 | |
| 1857 | |
| 1858 | |
| 1859 | |
| 1860 | |
| 1861 | |
| 1862 | |
| 1863 | endmodule |
| 1864 | |
| 1865 | |
| 1866 | |
| 1867 | |
| 1868 | |
| 1869 | // |
| 1870 | // xor macro for ports = 2,3 |
| 1871 | // |
| 1872 | // |
| 1873 | |
| 1874 | |
| 1875 | |
| 1876 | |
| 1877 | |
| 1878 | module l2t_usaloc_dp_xor_macro__dxor_16x__ports_3__width_1 ( |
| 1879 | din0, |
| 1880 | din1, |
| 1881 | din2, |
| 1882 | dout); |
| 1883 | input [0:0] din0; |
| 1884 | input [0:0] din1; |
| 1885 | input [0:0] din2; |
| 1886 | output [0:0] dout; |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | xor3 #(1) d0_0 ( |
| 1893 | .in0(din0[0:0]), |
| 1894 | .in1(din1[0:0]), |
| 1895 | .in2(din2[0:0]), |
| 1896 | .out(dout[0:0]) |
| 1897 | ); |
| 1898 | |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | |
| 1906 | endmodule |
| 1907 | |
| 1908 | |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | // |
| 1913 | // xor macro for ports = 2,3 |
| 1914 | // |
| 1915 | // |
| 1916 | |
| 1917 | |
| 1918 | |
| 1919 | |
| 1920 | |
| 1921 | module l2t_usaloc_dp_xor_macro__dxor_16x__ports_2__width_1 ( |
| 1922 | din0, |
| 1923 | din1, |
| 1924 | dout); |
| 1925 | input [0:0] din0; |
| 1926 | input [0:0] din1; |
| 1927 | output [0:0] dout; |
| 1928 | |
| 1929 | |
| 1930 | |
| 1931 | |
| 1932 | |
| 1933 | xor2 #(1) d0_0 ( |
| 1934 | .in0(din0[0:0]), |
| 1935 | .in1(din1[0:0]), |
| 1936 | .out(dout[0:0]) |
| 1937 | ); |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | endmodule |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | // |
| 1953 | // nand macro for ports = 2,3,4 |
| 1954 | // |
| 1955 | // |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | module l2t_usaloc_dp_nand_macro__ports_3__width_1 ( |
| 1962 | din0, |
| 1963 | din1, |
| 1964 | din2, |
| 1965 | dout); |
| 1966 | input [0:0] din0; |
| 1967 | input [0:0] din1; |
| 1968 | input [0:0] din2; |
| 1969 | output [0:0] dout; |
| 1970 | |
| 1971 | |
| 1972 | |
| 1973 | |
| 1974 | |
| 1975 | |
| 1976 | nand3 #(1) d0_0 ( |
| 1977 | .in0(din0[0:0]), |
| 1978 | .in1(din1[0:0]), |
| 1979 | .in2(din2[0:0]), |
| 1980 | .out(dout[0:0]) |
| 1981 | ); |
| 1982 | |
| 1983 | |
| 1984 | |
| 1985 | |
| 1986 | |
| 1987 | |
| 1988 | |
| 1989 | |
| 1990 | |
| 1991 | endmodule |
| 1992 | |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | // |
| 1998 | // nor macro for ports = 2,3 |
| 1999 | // |
| 2000 | // |
| 2001 | |
| 2002 | |
| 2003 | |
| 2004 | |
| 2005 | |
| 2006 | module l2t_usaloc_dp_nor_macro__ports_2__width_1 ( |
| 2007 | din0, |
| 2008 | din1, |
| 2009 | dout); |
| 2010 | input [0:0] din0; |
| 2011 | input [0:0] din1; |
| 2012 | output [0:0] dout; |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | nor2 #(1) d0_0 ( |
| 2020 | .in0(din0[0:0]), |
| 2021 | .in1(din1[0:0]), |
| 2022 | .out(dout[0:0]) |
| 2023 | ); |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | endmodule |
| 2032 | |
| 2033 | |
| 2034 | |
| 2035 | |
| 2036 | |
| 2037 | // |
| 2038 | // xor macro for ports = 2,3 |
| 2039 | // |
| 2040 | // |
| 2041 | |
| 2042 | |
| 2043 | |
| 2044 | |
| 2045 | |
| 2046 | module l2t_usaloc_dp_xor_macro__width_32 ( |
| 2047 | din0, |
| 2048 | din1, |
| 2049 | dout); |
| 2050 | input [31:0] din0; |
| 2051 | input [31:0] din1; |
| 2052 | output [31:0] dout; |
| 2053 | |
| 2054 | |
| 2055 | |
| 2056 | |
| 2057 | |
| 2058 | xor2 #(32) d0_0 ( |
| 2059 | .in0(din0[31:0]), |
| 2060 | .in1(din1[31:0]), |
| 2061 | .out(dout[31:0]) |
| 2062 | ); |
| 2063 | |
| 2064 | |
| 2065 | |
| 2066 | |
| 2067 | |
| 2068 | |
| 2069 | |
| 2070 | |
| 2071 | endmodule |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | // any PARAMS parms go into naming of macro |
| 2082 | |
| 2083 | module l2t_usaloc_dp_msff_macro__dmsff_32x__stack_33r__width_33 ( |
| 2084 | din, |
| 2085 | clk, |
| 2086 | en, |
| 2087 | se, |
| 2088 | scan_in, |
| 2089 | siclk, |
| 2090 | soclk, |
| 2091 | pce_ov, |
| 2092 | stop, |
| 2093 | dout, |
| 2094 | scan_out); |
| 2095 | wire l1clk; |
| 2096 | wire siclk_out; |
| 2097 | wire soclk_out; |
| 2098 | wire [31:0] so; |
| 2099 | |
| 2100 | input [32:0] din; |
| 2101 | |
| 2102 | |
| 2103 | input clk; |
| 2104 | input en; |
| 2105 | input se; |
| 2106 | input scan_in; |
| 2107 | input siclk; |
| 2108 | input soclk; |
| 2109 | input pce_ov; |
| 2110 | input stop; |
| 2111 | |
| 2112 | |
| 2113 | |
| 2114 | output [32:0] dout; |
| 2115 | |
| 2116 | |
| 2117 | output scan_out; |
| 2118 | |
| 2119 | |
| 2120 | |
| 2121 | |
| 2122 | cl_dp1_l1hdr_8x c0_0 ( |
| 2123 | .l2clk(clk), |
| 2124 | .pce(en), |
| 2125 | .aclk(siclk), |
| 2126 | .bclk(soclk), |
| 2127 | .l1clk(l1clk), |
| 2128 | .se(se), |
| 2129 | .pce_ov(pce_ov), |
| 2130 | .stop(stop), |
| 2131 | .siclk_out(siclk_out), |
| 2132 | .soclk_out(soclk_out) |
| 2133 | ); |
| 2134 | dff #(33) d0_0 ( |
| 2135 | .l1clk(l1clk), |
| 2136 | .siclk(siclk_out), |
| 2137 | .soclk(soclk_out), |
| 2138 | .d(din[32:0]), |
| 2139 | .si({scan_in,so[31:0]}), |
| 2140 | .so({so[31:0],scan_out}), |
| 2141 | .q(dout[32:0]) |
| 2142 | ); |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | endmodule |
| 2164 | |
| 2165 | |
| 2166 | |
| 2167 | |
| 2168 | |
| 2169 | |
| 2170 | |
| 2171 | |
| 2172 | |
| 2173 | // |
| 2174 | // buff macro |
| 2175 | // |
| 2176 | // |
| 2177 | |
| 2178 | |
| 2179 | |
| 2180 | |
| 2181 | |
| 2182 | module l2t_usaloc_dp_buff_macro__dbuff_48x__width_32 ( |
| 2183 | din, |
| 2184 | dout); |
| 2185 | input [31:0] din; |
| 2186 | output [31:0] dout; |
| 2187 | |
| 2188 | |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | buff #(32) d0_0 ( |
| 2194 | .in(din[31:0]), |
| 2195 | .out(dout[31:0]) |
| 2196 | ); |
| 2197 | |
| 2198 | |
| 2199 | |
| 2200 | |
| 2201 | |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | endmodule |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2212 | // also for pass-gate with decoder |
| 2213 | |
| 2214 | |
| 2215 | |
| 2216 | |
| 2217 | |
| 2218 | // any PARAMS parms go into naming of macro |
| 2219 | |
| 2220 | module l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_39r__width_39 ( |
| 2221 | din0, |
| 2222 | sel0, |
| 2223 | din1, |
| 2224 | sel1, |
| 2225 | dout); |
| 2226 | wire buffout0; |
| 2227 | wire buffout1; |
| 2228 | |
| 2229 | input [38:0] din0; |
| 2230 | input sel0; |
| 2231 | input [38:0] din1; |
| 2232 | input sel1; |
| 2233 | output [38:0] dout; |
| 2234 | |
| 2235 | |
| 2236 | |
| 2237 | |
| 2238 | |
| 2239 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2240 | .in0(sel0), |
| 2241 | .in1(sel1), |
| 2242 | .out0(buffout0), |
| 2243 | .out1(buffout1) |
| 2244 | ); |
| 2245 | mux2s #(39) d0_0 ( |
| 2246 | .sel0(buffout0), |
| 2247 | .sel1(buffout1), |
| 2248 | .in0(din0[38:0]), |
| 2249 | .in1(din1[38:0]), |
| 2250 | .dout(dout[38:0]) |
| 2251 | ); |
| 2252 | |
| 2253 | |
| 2254 | |
| 2255 | |
| 2256 | |
| 2257 | |
| 2258 | |
| 2259 | |
| 2260 | |
| 2261 | |
| 2262 | |
| 2263 | |
| 2264 | |
| 2265 | endmodule |
| 2266 | |
| 2267 | |
| 2268 | // |
| 2269 | // buff macro |
| 2270 | // |
| 2271 | // |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | module l2t_usaloc_dp_buff_macro__dbuff_48x__width_39 ( |
| 2278 | din, |
| 2279 | dout); |
| 2280 | input [38:0] din; |
| 2281 | output [38:0] dout; |
| 2282 | |
| 2283 | |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | buff #(39) d0_0 ( |
| 2289 | .in(din[38:0]), |
| 2290 | .out(dout[38:0]) |
| 2291 | ); |
| 2292 | |
| 2293 | |
| 2294 | |
| 2295 | |
| 2296 | |
| 2297 | |
| 2298 | |
| 2299 | |
| 2300 | endmodule |
| 2301 | |
| 2302 | |
| 2303 | |
| 2304 | |
| 2305 | |
| 2306 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2307 | // also for pass-gate with decoder |
| 2308 | |
| 2309 | |
| 2310 | |
| 2311 | |
| 2312 | |
| 2313 | // any PARAMS parms go into naming of macro |
| 2314 | |
| 2315 | module l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_32r__width_32 ( |
| 2316 | din0, |
| 2317 | sel0, |
| 2318 | din1, |
| 2319 | sel1, |
| 2320 | dout); |
| 2321 | wire buffout0; |
| 2322 | wire buffout1; |
| 2323 | |
| 2324 | input [31:0] din0; |
| 2325 | input sel0; |
| 2326 | input [31:0] din1; |
| 2327 | input sel1; |
| 2328 | output [31:0] dout; |
| 2329 | |
| 2330 | |
| 2331 | |
| 2332 | |
| 2333 | |
| 2334 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2335 | .in0(sel0), |
| 2336 | .in1(sel1), |
| 2337 | .out0(buffout0), |
| 2338 | .out1(buffout1) |
| 2339 | ); |
| 2340 | mux2s #(32) d0_0 ( |
| 2341 | .sel0(buffout0), |
| 2342 | .sel1(buffout1), |
| 2343 | .in0(din0[31:0]), |
| 2344 | .in1(din1[31:0]), |
| 2345 | .dout(dout[31:0]) |
| 2346 | ); |
| 2347 | |
| 2348 | |
| 2349 | |
| 2350 | |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | |
| 2356 | |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | endmodule |
| 2361 | |
| 2362 | |
| 2363 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2364 | // also for pass-gate with decoder |
| 2365 | |
| 2366 | |
| 2367 | |
| 2368 | |
| 2369 | |
| 2370 | // any PARAMS parms go into naming of macro |
| 2371 | |
| 2372 | module l2t_usaloc_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_16r__width_16 ( |
| 2373 | din0, |
| 2374 | sel0, |
| 2375 | din1, |
| 2376 | sel1, |
| 2377 | dout); |
| 2378 | wire buffout0; |
| 2379 | wire buffout1; |
| 2380 | |
| 2381 | input [15:0] din0; |
| 2382 | input sel0; |
| 2383 | input [15:0] din1; |
| 2384 | input sel1; |
| 2385 | output [15:0] dout; |
| 2386 | |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2392 | .in0(sel0), |
| 2393 | .in1(sel1), |
| 2394 | .out0(buffout0), |
| 2395 | .out1(buffout1) |
| 2396 | ); |
| 2397 | mux2s #(16) d0_0 ( |
| 2398 | .sel0(buffout0), |
| 2399 | .sel1(buffout1), |
| 2400 | .in0(din0[15:0]), |
| 2401 | .in1(din1[15:0]), |
| 2402 | .dout(dout[15:0]) |
| 2403 | ); |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | |
| 2408 | |
| 2409 | |
| 2410 | |
| 2411 | |
| 2412 | |
| 2413 | |
| 2414 | |
| 2415 | |
| 2416 | |
| 2417 | endmodule |
| 2418 | |
| 2419 | |
| 2420 | // |
| 2421 | // buff macro |
| 2422 | // |
| 2423 | // |
| 2424 | |
| 2425 | |
| 2426 | |
| 2427 | |
| 2428 | |
| 2429 | module l2t_usaloc_dp_buff_macro__minbuff_1__stack_33r__width_16 ( |
| 2430 | din, |
| 2431 | dout); |
| 2432 | input [15:0] din; |
| 2433 | output [15:0] dout; |
| 2434 | |
| 2435 | |
| 2436 | |
| 2437 | |
| 2438 | |
| 2439 | |
| 2440 | buff #(16) d0_0 ( |
| 2441 | .in(din[15:0]), |
| 2442 | .out(dout[15:0]) |
| 2443 | ); |
| 2444 | |
| 2445 | |
| 2446 | |
| 2447 | |
| 2448 | |
| 2449 | |
| 2450 | |
| 2451 | |
| 2452 | endmodule |
| 2453 | |
| 2454 | |
| 2455 | |
| 2456 | |
| 2457 | |
| 2458 | |
| 2459 | |
| 2460 | |
| 2461 | |
| 2462 | // any PARAMS parms go into naming of macro |
| 2463 | |
| 2464 | module l2t_usaloc_dp_msffi_macro__dmsffi_32x__stack_33r__width_33 ( |
| 2465 | din, |
| 2466 | clk, |
| 2467 | en, |
| 2468 | se, |
| 2469 | scan_in, |
| 2470 | siclk, |
| 2471 | soclk, |
| 2472 | pce_ov, |
| 2473 | stop, |
| 2474 | dout_l, |
| 2475 | scan_out); |
| 2476 | wire l1clk; |
| 2477 | wire siclk_out; |
| 2478 | wire soclk_out; |
| 2479 | wire [31:0] so; |
| 2480 | |
| 2481 | input [32:0] din; |
| 2482 | |
| 2483 | |
| 2484 | input clk; |
| 2485 | input en; |
| 2486 | input se; |
| 2487 | input scan_in; |
| 2488 | input siclk; |
| 2489 | input soclk; |
| 2490 | input pce_ov; |
| 2491 | input stop; |
| 2492 | |
| 2493 | |
| 2494 | |
| 2495 | output [32:0] dout_l; |
| 2496 | |
| 2497 | |
| 2498 | output scan_out; |
| 2499 | |
| 2500 | |
| 2501 | |
| 2502 | |
| 2503 | cl_dp1_l1hdr_8x c0_0 ( |
| 2504 | .l2clk(clk), |
| 2505 | .pce(en), |
| 2506 | .aclk(siclk), |
| 2507 | .bclk(soclk), |
| 2508 | .l1clk(l1clk), |
| 2509 | .se(se), |
| 2510 | .pce_ov(pce_ov), |
| 2511 | .stop(stop), |
| 2512 | .siclk_out(siclk_out), |
| 2513 | .soclk_out(soclk_out) |
| 2514 | ); |
| 2515 | msffi_dp #(33) d0_0 ( |
| 2516 | .l1clk(l1clk), |
| 2517 | .siclk(siclk_out), |
| 2518 | .soclk(soclk_out), |
| 2519 | .d(din[32:0]), |
| 2520 | .si({scan_in,so[31:0]}), |
| 2521 | .so({so[31:0],scan_out}), |
| 2522 | .q_l(dout_l[32:0]) |
| 2523 | ); |
| 2524 | |
| 2525 | |
| 2526 | |
| 2527 | |
| 2528 | |
| 2529 | |
| 2530 | |
| 2531 | |
| 2532 | |
| 2533 | |
| 2534 | |
| 2535 | |
| 2536 | |
| 2537 | |
| 2538 | |
| 2539 | |
| 2540 | |
| 2541 | |
| 2542 | |
| 2543 | endmodule |
| 2544 | |
| 2545 | |
| 2546 | |
| 2547 | |
| 2548 | |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | |
| 2553 | // |
| 2554 | // invert macro |
| 2555 | // |
| 2556 | // |
| 2557 | |
| 2558 | |
| 2559 | |
| 2560 | |
| 2561 | |
| 2562 | module l2t_usaloc_dp_inv_macro__dinv_16x__width_1 ( |
| 2563 | din, |
| 2564 | dout); |
| 2565 | input [0:0] din; |
| 2566 | output [0:0] dout; |
| 2567 | |
| 2568 | |
| 2569 | |
| 2570 | |
| 2571 | |
| 2572 | |
| 2573 | inv #(1) d0_0 ( |
| 2574 | .in(din[0:0]), |
| 2575 | .out(dout[0:0]) |
| 2576 | ); |
| 2577 | |
| 2578 | |
| 2579 | |
| 2580 | |
| 2581 | |
| 2582 | |
| 2583 | |
| 2584 | |
| 2585 | |
| 2586 | endmodule |
| 2587 | |
| 2588 | |
| 2589 | |
| 2590 | |
| 2591 | |
| 2592 | // |
| 2593 | // and macro for ports = 2,3,4 |
| 2594 | // |
| 2595 | // |
| 2596 | |
| 2597 | |
| 2598 | |
| 2599 | |
| 2600 | |
| 2601 | module l2t_usaloc_dp_and_macro__width_16 ( |
| 2602 | din0, |
| 2603 | din1, |
| 2604 | dout); |
| 2605 | input [15:0] din0; |
| 2606 | input [15:0] din1; |
| 2607 | output [15:0] dout; |
| 2608 | |
| 2609 | |
| 2610 | |
| 2611 | |
| 2612 | |
| 2613 | |
| 2614 | and2 #(16) d0_0 ( |
| 2615 | .in0(din0[15:0]), |
| 2616 | .in1(din1[15:0]), |
| 2617 | .out(dout[15:0]) |
| 2618 | ); |
| 2619 | |
| 2620 | |
| 2621 | |
| 2622 | |
| 2623 | |
| 2624 | |
| 2625 | |
| 2626 | |
| 2627 | |
| 2628 | endmodule |
| 2629 | |
| 2630 | |
| 2631 | |
| 2632 | |
| 2633 | |
| 2634 | |
| 2635 | |
| 2636 | |
| 2637 | |
| 2638 | // any PARAMS parms go into naming of macro |
| 2639 | |
| 2640 | module l2t_usaloc_dp_msff_macro__stack_39r__width_39 ( |
| 2641 | din, |
| 2642 | clk, |
| 2643 | en, |
| 2644 | se, |
| 2645 | scan_in, |
| 2646 | siclk, |
| 2647 | soclk, |
| 2648 | pce_ov, |
| 2649 | stop, |
| 2650 | dout, |
| 2651 | scan_out); |
| 2652 | wire l1clk; |
| 2653 | wire siclk_out; |
| 2654 | wire soclk_out; |
| 2655 | wire [37:0] so; |
| 2656 | |
| 2657 | input [38:0] din; |
| 2658 | |
| 2659 | |
| 2660 | input clk; |
| 2661 | input en; |
| 2662 | input se; |
| 2663 | input scan_in; |
| 2664 | input siclk; |
| 2665 | input soclk; |
| 2666 | input pce_ov; |
| 2667 | input stop; |
| 2668 | |
| 2669 | |
| 2670 | |
| 2671 | output [38:0] dout; |
| 2672 | |
| 2673 | |
| 2674 | output scan_out; |
| 2675 | |
| 2676 | |
| 2677 | |
| 2678 | |
| 2679 | cl_dp1_l1hdr_8x c0_0 ( |
| 2680 | .l2clk(clk), |
| 2681 | .pce(en), |
| 2682 | .aclk(siclk), |
| 2683 | .bclk(soclk), |
| 2684 | .l1clk(l1clk), |
| 2685 | .se(se), |
| 2686 | .pce_ov(pce_ov), |
| 2687 | .stop(stop), |
| 2688 | .siclk_out(siclk_out), |
| 2689 | .soclk_out(soclk_out) |
| 2690 | ); |
| 2691 | dff #(39) d0_0 ( |
| 2692 | .l1clk(l1clk), |
| 2693 | .siclk(siclk_out), |
| 2694 | .soclk(soclk_out), |
| 2695 | .d(din[38:0]), |
| 2696 | .si({scan_in,so[37:0]}), |
| 2697 | .so({so[37:0],scan_out}), |
| 2698 | .q(dout[38:0]) |
| 2699 | ); |
| 2700 | |
| 2701 | |
| 2702 | |
| 2703 | |
| 2704 | |
| 2705 | |
| 2706 | |
| 2707 | |
| 2708 | |
| 2709 | |
| 2710 | |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | |
| 2715 | |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | |
| 2720 | endmodule |
| 2721 | |
| 2722 | |
| 2723 | |
| 2724 | |
| 2725 | |
| 2726 | |
| 2727 | |
| 2728 | |
| 2729 | |
| 2730 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2731 | // also for pass-gate with decoder |
| 2732 | |
| 2733 | |
| 2734 | |
| 2735 | |
| 2736 | |
| 2737 | // any PARAMS parms go into naming of macro |
| 2738 | |
| 2739 | module l2t_usaloc_dp_mux_macro__dmux_16x__mux_pgnpe__ports_6__stack_32r__width_32 ( |
| 2740 | din0, |
| 2741 | sel0, |
| 2742 | din1, |
| 2743 | sel1, |
| 2744 | din2, |
| 2745 | sel2, |
| 2746 | din3, |
| 2747 | sel3, |
| 2748 | din4, |
| 2749 | sel4, |
| 2750 | din5, |
| 2751 | sel5, |
| 2752 | muxtst, |
| 2753 | dout); |
| 2754 | wire buffout0; |
| 2755 | wire buffout1; |
| 2756 | wire buffout2; |
| 2757 | wire buffout3; |
| 2758 | wire buffout4; |
| 2759 | wire buffout5; |
| 2760 | |
| 2761 | input [31:0] din0; |
| 2762 | input sel0; |
| 2763 | input [31:0] din1; |
| 2764 | input sel1; |
| 2765 | input [31:0] din2; |
| 2766 | input sel2; |
| 2767 | input [31:0] din3; |
| 2768 | input sel3; |
| 2769 | input [31:0] din4; |
| 2770 | input sel4; |
| 2771 | input [31:0] din5; |
| 2772 | input sel5; |
| 2773 | input muxtst; |
| 2774 | output [31:0] dout; |
| 2775 | |
| 2776 | |
| 2777 | |
| 2778 | |
| 2779 | |
| 2780 | cl_dp1_muxbuff6_8x c0_0 ( |
| 2781 | .in0(sel0), |
| 2782 | .in1(sel1), |
| 2783 | .in2(sel2), |
| 2784 | .in3(sel3), |
| 2785 | .in4(sel4), |
| 2786 | .in5(sel5), |
| 2787 | .out0(buffout0), |
| 2788 | .out1(buffout1), |
| 2789 | .out2(buffout2), |
| 2790 | .out3(buffout3), |
| 2791 | .out4(buffout4), |
| 2792 | .out5(buffout5) |
| 2793 | ); |
| 2794 | mux6 #(32) d0_0 ( |
| 2795 | .sel0(buffout0), |
| 2796 | .sel1(buffout1), |
| 2797 | .sel2(buffout2), |
| 2798 | .sel3(buffout3), |
| 2799 | .sel4(buffout4), |
| 2800 | .sel5(buffout5), |
| 2801 | .in0(din0[31:0]), |
| 2802 | .in1(din1[31:0]), |
| 2803 | .in2(din2[31:0]), |
| 2804 | .in3(din3[31:0]), |
| 2805 | .in4(din4[31:0]), |
| 2806 | .in5(din5[31:0]), |
| 2807 | .dout(dout[31:0]), |
| 2808 | .muxtst(muxtst) |
| 2809 | ); |
| 2810 | |
| 2811 | |
| 2812 | |
| 2813 | |
| 2814 | |
| 2815 | |
| 2816 | |
| 2817 | |
| 2818 | |
| 2819 | |
| 2820 | |
| 2821 | |
| 2822 | |
| 2823 | endmodule |
| 2824 | |