| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_fbdtm_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcu_fbdtm_ctl ( |
| 36 | fbdic_sync_frm_period, |
| 37 | fbdic_sds_config, |
| 38 | fbdic_sds_invert, |
| 39 | fbdic_sds_testcfg, |
| 40 | rdpctl_kp_lnk_up, |
| 41 | rdpctl_kp_lnk_up_clr, |
| 42 | fbdic_idle_lfsr_reset, |
| 43 | mcu_fsr0_cfgrx_align, |
| 44 | mcu_fsr1_cfgrx_align, |
| 45 | mcu_fsr0_cfgtx_enidl, |
| 46 | mcu_fsr1_cfgtx_enidl, |
| 47 | drif_ucb_wr_req_vld, |
| 48 | drif_ucb_data, |
| 49 | drif_ucb_addr, |
| 50 | drif_dbg_trig_reg_ld, |
| 51 | drif_single_channel_mode, |
| 52 | fbdic_fbd_state, |
| 53 | fbd0_frame_lock, |
| 54 | fbd1_frame_lock, |
| 55 | fbdic_loopback_1, |
| 56 | fbdic_disable_state, |
| 57 | fbdic_serdes_dtm, |
| 58 | fbdic_status_frame, |
| 59 | drl2clk, |
| 60 | scan_in, |
| 61 | scan_out, |
| 62 | wmr_scan_in, |
| 63 | wmr_scan_out, |
| 64 | tcu_pce_ov, |
| 65 | tcu_aclk, |
| 66 | tcu_bclk, |
| 67 | fbdic_aclk_wmr, |
| 68 | tcu_scan_en, |
| 69 | wmr_protect, |
| 70 | tcu_mcu_testmode, |
| 71 | fbdtm_si, |
| 72 | fbdtm_so, |
| 73 | fbdtm_wmr_si, |
| 74 | fbdtm_wmr_so); |
| 75 | wire pce_ov; |
| 76 | wire se; |
| 77 | wire aclk_wmr; |
| 78 | wire siclk; |
| 79 | wire soclk; |
| 80 | wire l1clk; |
| 81 | wire fbdic_sync_frm_period_en; |
| 82 | wire [5:0] fbdic_sync_frm_period_in; |
| 83 | wire [5:0] fbdic_sync_frm_period_out; |
| 84 | wire pff_sync_frm_period_wmr_scanin; |
| 85 | wire pff_sync_frm_period_wmr_scanout; |
| 86 | wire fbdic_sds_config_en; |
| 87 | wire [29:0] fbdic_sds_config_in; |
| 88 | wire [29:0] fbdic_sds_config_reset_val; |
| 89 | wire [29:0] fbdic_sds_config_out; |
| 90 | wire pff_sds_config_wmr_scanin; |
| 91 | wire pff_sds_config_wmr_scanout; |
| 92 | wire fbdic_sds_invert_en; |
| 93 | wire [47:0] fbdic_sds_invert_in; |
| 94 | wire pff_sds_invert_wmr_scanin; |
| 95 | wire pff_sds_invert_wmr_scanout; |
| 96 | wire [13:0] mcu_fsr0_cfgrx_invpair; |
| 97 | wire [13:0] mcu_fsr1_cfgrx_invpair; |
| 98 | wire [9:0] mcu_fsr0_cfgtx_invpair; |
| 99 | wire [9:0] mcu_fsr1_cfgtx_invpair; |
| 100 | wire fbdic_sds_testcfg_en; |
| 101 | wire [31:0] fbdic_sds_testcfg_in; |
| 102 | wire [31:0] fbdic_sds_testcfg_rstval; |
| 103 | wire pff_sds_testcfg_wmr_scanin; |
| 104 | wire pff_sds_testcfg_wmr_scanout; |
| 105 | wire [31:0] fbdic_sds_testcfg_out; |
| 106 | wire mcu_fsr0_cfgtx_enidl_in; |
| 107 | wire mcu_fsr1_cfgtx_enidl_in; |
| 108 | wire inv_mcu_fsr0_cfgtx_enidl_in; |
| 109 | wire inv_mcu_fsr1_cfgtx_enidl_in; |
| 110 | wire inv_mcu_fsr0_cfgtx_enidl; |
| 111 | wire inv_mcu_fsr1_cfgtx_enidl; |
| 112 | wire pff_cfgtx_enidl_scanin; |
| 113 | wire pff_cfgtx_enidl_scanout; |
| 114 | wire mcu_fsr0_cfgrx_align_in; |
| 115 | wire mcu_fsr1_cfgrx_align_in; |
| 116 | wire ff_cfgrx_align_scanin; |
| 117 | wire ff_cfgrx_align_scanout; |
| 118 | wire fbdic_idle_lfsr_reset_in; |
| 119 | wire ff_idle_lfsr_reset_scanin; |
| 120 | wire ff_idle_lfsr_reset_scanout; |
| 121 | wire rdpctl_kp_lnk_up_in; |
| 122 | wire ff_kp_lnk_up_scanin; |
| 123 | wire ff_kp_lnk_up_scanout; |
| 124 | |
| 125 | |
| 126 | output [5:0] fbdic_sync_frm_period; |
| 127 | output [29:0] fbdic_sds_config; |
| 128 | output [47:0] fbdic_sds_invert; |
| 129 | output [31:0] fbdic_sds_testcfg; |
| 130 | output rdpctl_kp_lnk_up; |
| 131 | output rdpctl_kp_lnk_up_clr; |
| 132 | output fbdic_idle_lfsr_reset; |
| 133 | output mcu_fsr0_cfgrx_align; |
| 134 | output mcu_fsr1_cfgrx_align; |
| 135 | output mcu_fsr0_cfgtx_enidl; |
| 136 | output mcu_fsr1_cfgtx_enidl; |
| 137 | |
| 138 | input drif_ucb_wr_req_vld; |
| 139 | input [47:0] drif_ucb_data; |
| 140 | input [12:0] drif_ucb_addr; |
| 141 | input drif_dbg_trig_reg_ld; |
| 142 | |
| 143 | input drif_single_channel_mode; |
| 144 | input [2:0] fbdic_fbd_state; |
| 145 | input [13:0] fbd0_frame_lock; |
| 146 | input [13:0] fbd1_frame_lock; |
| 147 | input fbdic_loopback_1; |
| 148 | input fbdic_disable_state; |
| 149 | input fbdic_serdes_dtm; |
| 150 | input fbdic_status_frame; |
| 151 | |
| 152 | input drl2clk; |
| 153 | input scan_in; |
| 154 | output scan_out; |
| 155 | input wmr_scan_in; |
| 156 | output wmr_scan_out; |
| 157 | input tcu_pce_ov; |
| 158 | input tcu_aclk; |
| 159 | input tcu_bclk; |
| 160 | input fbdic_aclk_wmr; |
| 161 | input tcu_scan_en; |
| 162 | input wmr_protect; |
| 163 | input tcu_mcu_testmode; |
| 164 | |
| 165 | input fbdtm_si; |
| 166 | output fbdtm_so; |
| 167 | input fbdtm_wmr_si; |
| 168 | output fbdtm_wmr_so; |
| 169 | |
| 170 | assign pce_ov = tcu_pce_ov; |
| 171 | assign se = tcu_scan_en & tcu_mcu_testmode; |
| 172 | assign aclk_wmr = fbdic_aclk_wmr & tcu_mcu_testmode; |
| 173 | assign siclk = tcu_aclk & tcu_mcu_testmode; |
| 174 | assign soclk = tcu_bclk & tcu_mcu_testmode; |
| 175 | |
| 176 | assign scan_out = scan_in; |
| 177 | assign wmr_scan_out = wmr_scan_in; |
| 178 | |
| 179 | mcu_fbdtm_ctl_l1clkhdr_ctl_macro clkgen_tm ( |
| 180 | .l2clk(drl2clk), |
| 181 | .l1en (1'b1), |
| 182 | .stop(1'b0), |
| 183 | .se(se), |
| 184 | .l1clk(l1clk), |
| 185 | .pce_ov(pce_ov)); |
| 186 | |
| 187 | ///////////////////////////////// |
| 188 | // FBD Sync Frame Frequency Register |
| 189 | ///////////////////////////////// |
| 190 | assign fbdic_sync_frm_period_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8B0; |
| 191 | assign fbdic_sync_frm_period_in[5:0] = drif_ucb_data[5:0] ^ 6'h2a; |
| 192 | assign fbdic_sync_frm_period[5:0] = fbdic_sync_frm_period_out[5:0] ^ 6'h2a; |
| 193 | |
| 194 | mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_6 pff_sync_frm_period ( // FS:wmr_protect |
| 195 | .scan_in(pff_sync_frm_period_wmr_scanin), |
| 196 | .scan_out(pff_sync_frm_period_wmr_scanout), |
| 197 | .siclk(fbdic_aclk_wmr), |
| 198 | .din(fbdic_sync_frm_period_in[5:0]), |
| 199 | .dout(fbdic_sync_frm_period_out[5:0]), |
| 200 | .en(fbdic_sync_frm_period_en), |
| 201 | .l1clk(l1clk), |
| 202 | .soclk(soclk)); |
| 203 | |
| 204 | ///////////////////////////////// |
| 205 | // SERDES Configuration Bus Register |
| 206 | ///////////////////////////////// |
| 207 | assign fbdic_sds_config_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8D0; |
| 208 | assign fbdic_sds_config_in[29:0] = drif_ucb_data[29:0] ^ fbdic_sds_config_reset_val[29:0]; |
| 209 | assign fbdic_sds_config[29:0] = fbdic_sds_config_out[29:0] ^ fbdic_sds_config_reset_val[29:0]; |
| 210 | assign fbdic_sds_config_reset_val[29:0] = {3'h0,3'h1,18'h0,4'h6,2'h0}; |
| 211 | |
| 212 | mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_27 pff_sds_config ( // FS:wmr_protect |
| 213 | .scan_in(pff_sds_config_wmr_scanin), |
| 214 | .scan_out(pff_sds_config_wmr_scanout), |
| 215 | .siclk(fbdic_aclk_wmr), |
| 216 | .din({fbdic_sds_config_in[29:16],fbdic_sds_config_in[14:8],fbdic_sds_config_in[5:0]}), |
| 217 | .dout({fbdic_sds_config_out[29:16],fbdic_sds_config_out[14:8],fbdic_sds_config_out[5:0]}), |
| 218 | .en(fbdic_sds_config_en), |
| 219 | .l1clk(l1clk), |
| 220 | .soclk(soclk)); |
| 221 | |
| 222 | assign fbdic_sds_config_out[7:6] = 2'h0; |
| 223 | assign fbdic_sds_config_out[15] = 1'b0; |
| 224 | |
| 225 | ///////////////////////////////// |
| 226 | // SERDES Transmitter and Receiver Differential Pair Inversion Register |
| 227 | ///////////////////////////////// |
| 228 | assign fbdic_sds_invert_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8D8; |
| 229 | assign fbdic_sds_invert_in[47:0] = drif_ucb_data[47:0]; |
| 230 | |
| 231 | mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_48 pff_sds_invert ( // FS:wmr_protect |
| 232 | .scan_in(pff_sds_invert_wmr_scanin), |
| 233 | .scan_out(pff_sds_invert_wmr_scanout), |
| 234 | .siclk(fbdic_aclk_wmr), |
| 235 | .din(fbdic_sds_invert_in[47:0]), |
| 236 | .dout(fbdic_sds_invert[47:0]), |
| 237 | .en(fbdic_sds_invert_en), |
| 238 | .l1clk(l1clk), |
| 239 | .soclk(soclk)); |
| 240 | |
| 241 | assign mcu_fsr0_cfgrx_invpair[13:0] = fbdic_sds_invert[13:0]; |
| 242 | assign mcu_fsr1_cfgrx_invpair[13:0] = fbdic_sds_invert[27:14]; |
| 243 | assign mcu_fsr0_cfgtx_invpair[9:0] = fbdic_sds_invert[37:28]; |
| 244 | assign mcu_fsr1_cfgtx_invpair[9:0] = fbdic_sds_invert[47:38]; |
| 245 | |
| 246 | ///////////////////////////////// |
| 247 | // SERDES Test Configuration Bus Register |
| 248 | ///////////////////////////////// |
| 249 | assign fbdic_sds_testcfg_en = drif_ucb_wr_req_vld & drif_ucb_addr[12:0] == 13'h8E0; |
| 250 | assign fbdic_sds_testcfg_in[31:0] = drif_ucb_data[31:0] ^ fbdic_sds_testcfg_rstval[31:0]; |
| 251 | assign fbdic_sds_testcfg_rstval[31:0] = {4'h0, 14'h3, 14'h3}; |
| 252 | |
| 253 | mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_32 pff_sds_testcfg ( // FS:wmr_protect |
| 254 | .scan_in(pff_sds_testcfg_wmr_scanin), |
| 255 | .scan_out(pff_sds_testcfg_wmr_scanout), |
| 256 | .siclk(fbdic_aclk_wmr), |
| 257 | .din(fbdic_sds_testcfg_in[31:0]), |
| 258 | .dout(fbdic_sds_testcfg_out[31:0]), |
| 259 | .en(fbdic_sds_testcfg_en), |
| 260 | .l1clk(l1clk), |
| 261 | .soclk(soclk)); |
| 262 | |
| 263 | assign fbdic_sds_testcfg[31:0] = fbdic_sds_testcfg_out[31:0] ^ fbdic_sds_testcfg_rstval[31:0]; |
| 264 | |
| 265 | // Enable Idle signal to FSRs |
| 266 | assign mcu_fsr0_cfgtx_enidl_in = rdpctl_kp_lnk_up ? mcu_fsr0_cfgtx_enidl : ~(|fbdic_fbd_state[2:0]); |
| 267 | assign mcu_fsr1_cfgtx_enidl_in = mcu_fsr0_cfgtx_enidl_in & ~drif_single_channel_mode; |
| 268 | |
| 269 | assign inv_mcu_fsr0_cfgtx_enidl_in = ~mcu_fsr0_cfgtx_enidl_in; |
| 270 | assign inv_mcu_fsr1_cfgtx_enidl_in = ~mcu_fsr1_cfgtx_enidl_in; |
| 271 | assign mcu_fsr0_cfgtx_enidl = ~inv_mcu_fsr0_cfgtx_enidl; |
| 272 | assign mcu_fsr1_cfgtx_enidl = ~inv_mcu_fsr1_cfgtx_enidl; |
| 273 | |
| 274 | mcu_fbdtm_ctl_msff_ctl_macro__width_2 pff_cfgtx_enidl ( |
| 275 | .scan_in(pff_cfgtx_enidl_scanin), |
| 276 | .scan_out(pff_cfgtx_enidl_scanout), |
| 277 | .din({inv_mcu_fsr0_cfgtx_enidl_in,inv_mcu_fsr1_cfgtx_enidl_in}), |
| 278 | .dout({inv_mcu_fsr0_cfgtx_enidl,inv_mcu_fsr1_cfgtx_enidl}), |
| 279 | .l1clk(l1clk), |
| 280 | .siclk(siclk), |
| 281 | .soclk(soclk)); |
| 282 | |
| 283 | assign mcu_fsr0_cfgrx_align_in = (fbdic_fbd_state[2:0] == 3'h2) & ~(&fbd0_frame_lock[13:0]) | |
| 284 | (fbdic_serdes_dtm | fbdic_loopback_1) & fbdic_disable_state; |
| 285 | assign mcu_fsr1_cfgrx_align_in = ((fbdic_fbd_state[2:0] == 3'h2) & ~(&fbd1_frame_lock[13:0]) | |
| 286 | (fbdic_serdes_dtm | fbdic_loopback_1) & fbdic_disable_state) & ~drif_single_channel_mode; |
| 287 | |
| 288 | mcu_fbdtm_ctl_msff_ctl_macro__width_2 ff_cfgrx_align ( |
| 289 | .scan_in(ff_cfgrx_align_scanin), |
| 290 | .scan_out(ff_cfgrx_align_scanout), |
| 291 | .din({mcu_fsr0_cfgrx_align_in,mcu_fsr1_cfgrx_align_in}), |
| 292 | .dout({mcu_fsr0_cfgrx_align,mcu_fsr1_cfgrx_align}), |
| 293 | .l1clk(l1clk), |
| 294 | .siclk(siclk), |
| 295 | .soclk(soclk)); |
| 296 | |
| 297 | // Control signals from fbdird data path block |
| 298 | assign fbdic_idle_lfsr_reset_in = (fbdic_fbd_state[2:1] != 2'h3) & ~rdpctl_kp_lnk_up ? 1'b1 : |
| 299 | fbdic_status_frame ? 1'b0 : fbdic_idle_lfsr_reset; |
| 300 | |
| 301 | mcu_fbdtm_ctl_msff_ctl_macro ff_idle_lfsr_reset ( |
| 302 | .scan_in(ff_idle_lfsr_reset_scanin), |
| 303 | .scan_out(ff_idle_lfsr_reset_scanout), |
| 304 | .din(fbdic_idle_lfsr_reset_in), |
| 305 | .dout(fbdic_idle_lfsr_reset), |
| 306 | .l1clk(l1clk), |
| 307 | .siclk(siclk), |
| 308 | .soclk(soclk)); |
| 309 | |
| 310 | assign rdpctl_kp_lnk_up_in = drif_ucb_data[0]; |
| 311 | |
| 312 | mcu_fbdtm_ctl_msff_ctl_macro__en_1 ff_kp_lnk_up ( |
| 313 | .scan_in(ff_kp_lnk_up_scanin), |
| 314 | .scan_out(ff_kp_lnk_up_scanout), |
| 315 | .din(rdpctl_kp_lnk_up_in), |
| 316 | .dout(rdpctl_kp_lnk_up), |
| 317 | .en(drif_dbg_trig_reg_ld), |
| 318 | .l1clk(l1clk), |
| 319 | .siclk(siclk), |
| 320 | .soclk(soclk)); |
| 321 | |
| 322 | assign rdpctl_kp_lnk_up_clr = rdpctl_kp_lnk_up & drif_dbg_trig_reg_ld & ~drif_ucb_data[0]; |
| 323 | |
| 324 | assign pff_cfgtx_enidl_scanin = fbdtm_si ; |
| 325 | assign ff_cfgrx_align_scanin = pff_cfgtx_enidl_scanout ; |
| 326 | assign ff_idle_lfsr_reset_scanin = ff_cfgrx_align_scanout ; |
| 327 | assign ff_kp_lnk_up_scanin = ff_idle_lfsr_reset_scanout; |
| 328 | assign fbdtm_so = tcu_mcu_testmode ? ff_kp_lnk_up_scanout : fbdtm_si; |
| 329 | |
| 330 | assign pff_sync_frm_period_wmr_scanin = fbdtm_wmr_si ; |
| 331 | assign pff_sds_config_wmr_scanin = pff_sync_frm_period_wmr_scanout; |
| 332 | assign pff_sds_invert_wmr_scanin = pff_sds_config_wmr_scanout; |
| 333 | assign pff_sds_testcfg_wmr_scanin = pff_sds_invert_wmr_scanout; |
| 334 | assign fbdtm_wmr_so = tcu_mcu_testmode ? pff_sds_testcfg_wmr_scanout : fbdtm_wmr_si; |
| 335 | |
| 336 | endmodule |
| 337 | |
| 338 | |
| 339 | |
| 340 | |
| 341 | |
| 342 | |
| 343 | // any PARAMS parms go into naming of macro |
| 344 | |
| 345 | module mcu_fbdtm_ctl_l1clkhdr_ctl_macro ( |
| 346 | l2clk, |
| 347 | l1en, |
| 348 | pce_ov, |
| 349 | stop, |
| 350 | se, |
| 351 | l1clk); |
| 352 | |
| 353 | |
| 354 | input l2clk; |
| 355 | input l1en; |
| 356 | input pce_ov; |
| 357 | input stop; |
| 358 | input se; |
| 359 | output l1clk; |
| 360 | |
| 361 | |
| 362 | |
| 363 | |
| 364 | |
| 365 | cl_sc1_l1hdr_8x c_0 ( |
| 366 | |
| 367 | |
| 368 | .l2clk(l2clk), |
| 369 | .pce(l1en), |
| 370 | .l1clk(l1clk), |
| 371 | .se(se), |
| 372 | .pce_ov(pce_ov), |
| 373 | .stop(stop) |
| 374 | ); |
| 375 | |
| 376 | |
| 377 | |
| 378 | endmodule |
| 379 | |
| 380 | |
| 381 | |
| 382 | |
| 383 | |
| 384 | |
| 385 | |
| 386 | |
| 387 | |
| 388 | |
| 389 | |
| 390 | |
| 391 | |
| 392 | // any PARAMS parms go into naming of macro |
| 393 | |
| 394 | module mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_6 ( |
| 395 | din, |
| 396 | en, |
| 397 | l1clk, |
| 398 | scan_in, |
| 399 | siclk, |
| 400 | soclk, |
| 401 | dout, |
| 402 | scan_out); |
| 403 | wire [5:0] fdin; |
| 404 | wire [4:0] so; |
| 405 | |
| 406 | input [5:0] din; |
| 407 | input en; |
| 408 | input l1clk; |
| 409 | input scan_in; |
| 410 | |
| 411 | |
| 412 | input siclk; |
| 413 | input soclk; |
| 414 | |
| 415 | output [5:0] dout; |
| 416 | output scan_out; |
| 417 | assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}}); |
| 418 | |
| 419 | |
| 420 | |
| 421 | |
| 422 | |
| 423 | |
| 424 | dff #(6) d0_0 ( |
| 425 | .l1clk(l1clk), |
| 426 | .siclk(siclk), |
| 427 | .soclk(soclk), |
| 428 | .d(fdin[5:0]), |
| 429 | .si({scan_in,so[4:0]}), |
| 430 | .so({so[4:0],scan_out}), |
| 431 | .q(dout[5:0]) |
| 432 | ); |
| 433 | |
| 434 | |
| 435 | |
| 436 | |
| 437 | |
| 438 | |
| 439 | |
| 440 | |
| 441 | |
| 442 | |
| 443 | |
| 444 | |
| 445 | endmodule |
| 446 | |
| 447 | |
| 448 | |
| 449 | |
| 450 | |
| 451 | |
| 452 | |
| 453 | |
| 454 | |
| 455 | |
| 456 | |
| 457 | |
| 458 | |
| 459 | // any PARAMS parms go into naming of macro |
| 460 | |
| 461 | module mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_27 ( |
| 462 | din, |
| 463 | en, |
| 464 | l1clk, |
| 465 | scan_in, |
| 466 | siclk, |
| 467 | soclk, |
| 468 | dout, |
| 469 | scan_out); |
| 470 | wire [26:0] fdin; |
| 471 | wire [25:0] so; |
| 472 | |
| 473 | input [26:0] din; |
| 474 | input en; |
| 475 | input l1clk; |
| 476 | input scan_in; |
| 477 | |
| 478 | |
| 479 | input siclk; |
| 480 | input soclk; |
| 481 | |
| 482 | output [26:0] dout; |
| 483 | output scan_out; |
| 484 | assign fdin[26:0] = (din[26:0] & {27{en}}) | (dout[26:0] & ~{27{en}}); |
| 485 | |
| 486 | |
| 487 | |
| 488 | |
| 489 | |
| 490 | |
| 491 | dff #(27) d0_0 ( |
| 492 | .l1clk(l1clk), |
| 493 | .siclk(siclk), |
| 494 | .soclk(soclk), |
| 495 | .d(fdin[26:0]), |
| 496 | .si({scan_in,so[25:0]}), |
| 497 | .so({so[25:0],scan_out}), |
| 498 | .q(dout[26:0]) |
| 499 | ); |
| 500 | |
| 501 | |
| 502 | |
| 503 | |
| 504 | |
| 505 | |
| 506 | |
| 507 | |
| 508 | |
| 509 | |
| 510 | |
| 511 | |
| 512 | endmodule |
| 513 | |
| 514 | |
| 515 | |
| 516 | |
| 517 | |
| 518 | |
| 519 | |
| 520 | |
| 521 | |
| 522 | |
| 523 | |
| 524 | |
| 525 | |
| 526 | // any PARAMS parms go into naming of macro |
| 527 | |
| 528 | module mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_48 ( |
| 529 | din, |
| 530 | en, |
| 531 | l1clk, |
| 532 | scan_in, |
| 533 | siclk, |
| 534 | soclk, |
| 535 | dout, |
| 536 | scan_out); |
| 537 | wire [47:0] fdin; |
| 538 | wire [46:0] so; |
| 539 | |
| 540 | input [47:0] din; |
| 541 | input en; |
| 542 | input l1clk; |
| 543 | input scan_in; |
| 544 | |
| 545 | |
| 546 | input siclk; |
| 547 | input soclk; |
| 548 | |
| 549 | output [47:0] dout; |
| 550 | output scan_out; |
| 551 | assign fdin[47:0] = (din[47:0] & {48{en}}) | (dout[47:0] & ~{48{en}}); |
| 552 | |
| 553 | |
| 554 | |
| 555 | |
| 556 | |
| 557 | |
| 558 | dff #(48) d0_0 ( |
| 559 | .l1clk(l1clk), |
| 560 | .siclk(siclk), |
| 561 | .soclk(soclk), |
| 562 | .d(fdin[47:0]), |
| 563 | .si({scan_in,so[46:0]}), |
| 564 | .so({so[46:0],scan_out}), |
| 565 | .q(dout[47:0]) |
| 566 | ); |
| 567 | |
| 568 | |
| 569 | |
| 570 | |
| 571 | |
| 572 | |
| 573 | |
| 574 | |
| 575 | |
| 576 | |
| 577 | |
| 578 | |
| 579 | endmodule |
| 580 | |
| 581 | |
| 582 | |
| 583 | |
| 584 | |
| 585 | |
| 586 | |
| 587 | |
| 588 | |
| 589 | |
| 590 | |
| 591 | |
| 592 | |
| 593 | // any PARAMS parms go into naming of macro |
| 594 | |
| 595 | module mcu_fbdtm_ctl_msff_ctl_macro__en_1__width_32 ( |
| 596 | din, |
| 597 | en, |
| 598 | l1clk, |
| 599 | scan_in, |
| 600 | siclk, |
| 601 | soclk, |
| 602 | dout, |
| 603 | scan_out); |
| 604 | wire [31:0] fdin; |
| 605 | wire [30:0] so; |
| 606 | |
| 607 | input [31:0] din; |
| 608 | input en; |
| 609 | input l1clk; |
| 610 | input scan_in; |
| 611 | |
| 612 | |
| 613 | input siclk; |
| 614 | input soclk; |
| 615 | |
| 616 | output [31:0] dout; |
| 617 | output scan_out; |
| 618 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); |
| 619 | |
| 620 | |
| 621 | |
| 622 | |
| 623 | |
| 624 | |
| 625 | dff #(32) d0_0 ( |
| 626 | .l1clk(l1clk), |
| 627 | .siclk(siclk), |
| 628 | .soclk(soclk), |
| 629 | .d(fdin[31:0]), |
| 630 | .si({scan_in,so[30:0]}), |
| 631 | .so({so[30:0],scan_out}), |
| 632 | .q(dout[31:0]) |
| 633 | ); |
| 634 | |
| 635 | |
| 636 | |
| 637 | |
| 638 | |
| 639 | |
| 640 | |
| 641 | |
| 642 | |
| 643 | |
| 644 | |
| 645 | |
| 646 | endmodule |
| 647 | |
| 648 | |
| 649 | |
| 650 | |
| 651 | |
| 652 | |
| 653 | |
| 654 | |
| 655 | |
| 656 | |
| 657 | |
| 658 | |
| 659 | |
| 660 | // any PARAMS parms go into naming of macro |
| 661 | |
| 662 | module mcu_fbdtm_ctl_msff_ctl_macro__width_2 ( |
| 663 | din, |
| 664 | l1clk, |
| 665 | scan_in, |
| 666 | siclk, |
| 667 | soclk, |
| 668 | dout, |
| 669 | scan_out); |
| 670 | wire [1:0] fdin; |
| 671 | wire [0:0] so; |
| 672 | |
| 673 | input [1:0] din; |
| 674 | input l1clk; |
| 675 | input scan_in; |
| 676 | |
| 677 | |
| 678 | input siclk; |
| 679 | input soclk; |
| 680 | |
| 681 | output [1:0] dout; |
| 682 | output scan_out; |
| 683 | assign fdin[1:0] = din[1:0]; |
| 684 | |
| 685 | |
| 686 | |
| 687 | |
| 688 | |
| 689 | |
| 690 | dff #(2) d0_0 ( |
| 691 | .l1clk(l1clk), |
| 692 | .siclk(siclk), |
| 693 | .soclk(soclk), |
| 694 | .d(fdin[1:0]), |
| 695 | .si({scan_in,so[0:0]}), |
| 696 | .so({so[0:0],scan_out}), |
| 697 | .q(dout[1:0]) |
| 698 | ); |
| 699 | |
| 700 | |
| 701 | |
| 702 | |
| 703 | |
| 704 | |
| 705 | |
| 706 | |
| 707 | |
| 708 | |
| 709 | |
| 710 | |
| 711 | endmodule |
| 712 | |
| 713 | |
| 714 | |
| 715 | |
| 716 | |
| 717 | |
| 718 | |
| 719 | |
| 720 | |
| 721 | |
| 722 | |
| 723 | |
| 724 | |
| 725 | // any PARAMS parms go into naming of macro |
| 726 | |
| 727 | module mcu_fbdtm_ctl_msff_ctl_macro ( |
| 728 | din, |
| 729 | l1clk, |
| 730 | scan_in, |
| 731 | siclk, |
| 732 | soclk, |
| 733 | dout, |
| 734 | scan_out); |
| 735 | wire [0:0] fdin; |
| 736 | |
| 737 | input [0:0] din; |
| 738 | input l1clk; |
| 739 | input scan_in; |
| 740 | |
| 741 | |
| 742 | input siclk; |
| 743 | input soclk; |
| 744 | |
| 745 | output [0:0] dout; |
| 746 | output scan_out; |
| 747 | assign fdin[0:0] = din[0:0]; |
| 748 | |
| 749 | |
| 750 | |
| 751 | |
| 752 | |
| 753 | |
| 754 | dff #(1) d0_0 ( |
| 755 | .l1clk(l1clk), |
| 756 | .siclk(siclk), |
| 757 | .soclk(soclk), |
| 758 | .d(fdin[0:0]), |
| 759 | .si(scan_in), |
| 760 | .so(scan_out), |
| 761 | .q(dout[0:0]) |
| 762 | ); |
| 763 | |
| 764 | |
| 765 | |
| 766 | |
| 767 | |
| 768 | |
| 769 | |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | endmodule |
| 776 | |
| 777 | |
| 778 | |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | |
| 788 | |
| 789 | // any PARAMS parms go into naming of macro |
| 790 | |
| 791 | module mcu_fbdtm_ctl_msff_ctl_macro__en_1 ( |
| 792 | din, |
| 793 | en, |
| 794 | l1clk, |
| 795 | scan_in, |
| 796 | siclk, |
| 797 | soclk, |
| 798 | dout, |
| 799 | scan_out); |
| 800 | wire [0:0] fdin; |
| 801 | |
| 802 | input [0:0] din; |
| 803 | input en; |
| 804 | input l1clk; |
| 805 | input scan_in; |
| 806 | |
| 807 | |
| 808 | input siclk; |
| 809 | input soclk; |
| 810 | |
| 811 | output [0:0] dout; |
| 812 | output scan_out; |
| 813 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 814 | |
| 815 | |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | dff #(1) d0_0 ( |
| 821 | .l1clk(l1clk), |
| 822 | .siclk(siclk), |
| 823 | .soclk(soclk), |
| 824 | .d(fdin[0:0]), |
| 825 | .si(scan_in), |
| 826 | .so(scan_out), |
| 827 | .q(dout[0:0]) |
| 828 | ); |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | |
| 837 | |
| 838 | |
| 839 | |
| 840 | |
| 841 | endmodule |
| 842 | |
| 843 | |
| 844 | |
| 845 | |
| 846 | |
| 847 | |
| 848 | |
| 849 | |