| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_rdpctl_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define DRIF_MCU_STATE_00 5'd0 |
| 36 | `define DRIF_MCU_STATE_01 5'd1 |
| 37 | `define DRIF_MCU_STATE_02 5'd2 |
| 38 | `define DRIF_MCU_STATE_03 5'd3 |
| 39 | `define DRIF_MCU_STATE_04 5'd4 |
| 40 | `define DRIF_MCU_STATE_05 5'd5 |
| 41 | `define DRIF_MCU_STATE_06 5'd6 |
| 42 | `define DRIF_MCU_STATE_07 5'd7 |
| 43 | `define DRIF_MCU_STATE_08 5'd8 |
| 44 | `define DRIF_MCU_STATE_09 5'd9 |
| 45 | `define DRIF_MCU_STATE_10 5'd10 |
| 46 | `define DRIF_MCU_STATE_11 5'd11 |
| 47 | `define DRIF_MCU_STATE_12 5'd12 |
| 48 | `define DRIF_MCU_STATE_13 5'd13 |
| 49 | `define DRIF_MCU_STATE_14 5'd14 |
| 50 | `define DRIF_MCU_STATE_15 5'd15 |
| 51 | `define DRIF_MCU_STATE_16 5'd16 |
| 52 | `define DRIF_MCU_STATE_17 5'd17 |
| 53 | `define DRIF_MCU_STATE_18 5'd18 |
| 54 | `define DRIF_MCU_STATE_19 5'd19 |
| 55 | `define DRIF_MCU_STATE_20 5'd20 |
| 56 | `define DRIF_MCU_STATE_21 5'd21 |
| 57 | `define DRIF_MCU_STATE_22 5'd22 |
| 58 | `define DRIF_MCU_STATE_23 5'd23 |
| 59 | `define DRIF_MCU_STATE_24 5'd24 |
| 60 | `define DRIF_MCU_STATE_25 5'd25 |
| 61 | `define DRIF_MCU_STATE_26 5'd26 |
| 62 | |
| 63 | `define DRIF_MCU_STATE_MAX 4 |
| 64 | `define DRIF_MCU_STATE_WIDTH 5 |
| 65 | |
| 66 | // |
| 67 | // UCB Packet Type |
| 68 | // =============== |
| 69 | // |
| 70 | `define UCB_READ_NACK 4'b0000 // ack/nack types |
| 71 | `define UCB_READ_ACK 4'b0001 |
| 72 | `define UCB_WRITE_ACK 4'b0010 |
| 73 | `define UCB_IFILL_ACK 4'b0011 |
| 74 | `define UCB_IFILL_NACK 4'b0111 |
| 75 | |
| 76 | `define UCB_READ_REQ 4'b0100 // req types |
| 77 | `define UCB_WRITE_REQ 4'b0101 |
| 78 | `define UCB_IFILL_REQ 4'b0110 |
| 79 | |
| 80 | `define UCB_INT 4'b1000 // plain interrupt |
| 81 | `define UCB_INT_VEC 4'b1100 // interrupt with vector |
| 82 | `define UCB_RESET_VEC 4'b1101 // reset with vector |
| 83 | `define UCB_IDLE_VEC 4'b1110 // idle with vector |
| 84 | `define UCB_RESUME_VEC 4'b1111 // resume with vector |
| 85 | |
| 86 | |
| 87 | // |
| 88 | // UCB Data Packet Format |
| 89 | // ====================== |
| 90 | // |
| 91 | `define UCB_NOPAY_PKT_WIDTH 64 // packet without payload |
| 92 | `define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload |
| 93 | `define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload |
| 94 | |
| 95 | `define UCB_DATA_EXT_HI 191 // (64) extended data |
| 96 | `define UCB_DATA_EXT_LO 128 |
| 97 | `define UCB_DATA_HI 127 // (64) data |
| 98 | `define UCB_DATA_LO 64 |
| 99 | `define UCB_RSV_HI 63 // (9) reserved bits |
| 100 | `define UCB_RSV_LO 55 |
| 101 | `define UCB_ADDR_HI 54 // (40) bit address |
| 102 | `define UCB_ADDR_LO 15 |
| 103 | `define UCB_SIZE_HI 14 // (3) request size |
| 104 | `define UCB_SIZE_LO 12 |
| 105 | `define UCB_BUF_HI 11 // (2) buffer ID |
| 106 | `define UCB_BUF_LO 10 |
| 107 | `define UCB_THR_HI 9 // (6) cpu/thread ID |
| 108 | `define UCB_THR_LO 4 |
| 109 | `define UCB_PKT_HI 3 // (4) packet type |
| 110 | `define UCB_PKT_LO 0 |
| 111 | |
| 112 | `define UCB_DATA_EXT_WIDTH 64 |
| 113 | `define UCB_DATA_WIDTH 64 |
| 114 | `define UCB_RSV_WIDTH 9 |
| 115 | `define UCB_ADDR_WIDTH 40 |
| 116 | `define UCB_SIZE_WIDTH 3 |
| 117 | `define UCB_BUF_WIDTH 2 |
| 118 | `define UCB_THR_WIDTH 6 |
| 119 | `define UCB_PKT_WIDTH 4 |
| 120 | |
| 121 | // Size encoding for the UCB_SIZE_HI/LO field |
| 122 | // 000 - byte |
| 123 | // 001 - half-word |
| 124 | // 010 - word |
| 125 | // 011 - double-word |
| 126 | `define UCB_SIZE_1B 3'b000 |
| 127 | `define UCB_SIZE_2B 3'b001 |
| 128 | `define UCB_SIZE_4B 3'b010 |
| 129 | `define UCB_SIZE_8B 3'b011 |
| 130 | `define UCB_SIZE_16B 3'b100 |
| 131 | |
| 132 | |
| 133 | // |
| 134 | // UCB Interrupt Packet Format |
| 135 | // =========================== |
| 136 | // |
| 137 | `define UCB_INT_PKT_WIDTH 64 |
| 138 | |
| 139 | `define UCB_INT_RSV_HI 63 // (7) reserved bits |
| 140 | `define UCB_INT_RSV_LO 57 |
| 141 | `define UCB_INT_VEC_HI 56 // (6) interrupt vector |
| 142 | `define UCB_INT_VEC_LO 51 |
| 143 | `define UCB_INT_STAT_HI 50 // (32) interrupt status |
| 144 | `define UCB_INT_STAT_LO 19 |
| 145 | `define UCB_INT_DEV_HI 18 // (9) device ID |
| 146 | `define UCB_INT_DEV_LO 10 |
| 147 | //`define UCB_THR_HI 9 // (6) cpu/thread ID shared with |
| 148 | //`define UCB_THR_LO 4 data packet format |
| 149 | //`define UCB_PKT_HI 3 // (4) packet type shared with |
| 150 | //`define UCB_PKT_LO 0 // data packet format |
| 151 | |
| 152 | `define UCB_INT_RSV_WIDTH 7 |
| 153 | `define UCB_INT_VEC_WIDTH 6 |
| 154 | `define UCB_INT_STAT_WIDTH 32 |
| 155 | `define UCB_INT_DEV_WIDTH 9 |
| 156 | |
| 157 | |
| 158 | `define MCU_CAS_BIT2_SEL_PA10 4'h1 |
| 159 | `define MCU_CAS_BIT2_SEL_PA32 4'h2 |
| 160 | `define MCU_CAS_BIT2_SEL_PA33 4'h4 |
| 161 | `define MCU_CAS_BIT2_SEL_PA34 4'h8 |
| 162 | |
| 163 | `define MCU_CAS_BIT3_SEL_PA11 4'h1 |
| 164 | `define MCU_CAS_BIT3_SEL_PA33 4'h2 |
| 165 | `define MCU_CAS_BIT3_SEL_PA34 4'h4 |
| 166 | `define MCU_CAS_BIT3_SEL_PA35 4'h8 |
| 167 | |
| 168 | `define MCU_CAS_BIT4_SEL_PA12 3'h1 |
| 169 | `define MCU_CAS_BIT4_SEL_PA35 3'h2 |
| 170 | `define MCU_CAS_BIT4_SEL_PA36 3'h4 |
| 171 | |
| 172 | `define MCU_DIMMHI_SEL_ZERO 6'h01 |
| 173 | `define MCU_DIMMHI_SEL_PA32 6'h02 |
| 174 | `define MCU_DIMMHI_SEL_PA33 6'h04 |
| 175 | `define MCU_DIMMHI_SEL_PA34 6'h08 |
| 176 | `define MCU_DIMMHI_SEL_PA35 6'h10 |
| 177 | `define MCU_DIMMHI_SEL_PA36 6'h20 |
| 178 | |
| 179 | `define MCU_DIMMLO_SEL_ZERO 4'h1 |
| 180 | `define MCU_DIMMLO_SEL_PA10 4'h2 |
| 181 | `define MCU_DIMMLO_SEL_PA11 4'h4 |
| 182 | `define MCU_DIMMLO_SEL_PA12 4'h8 |
| 183 | |
| 184 | `define MCU_RANK_SEL_ZERO 7'h01 |
| 185 | `define MCU_RANK_SEL_PA32 7'h02 |
| 186 | `define MCU_RANK_SEL_PA33 7'h04 |
| 187 | `define MCU_RANK_SEL_PA34 7'h08 |
| 188 | `define MCU_RANK_SEL_PA35 7'h10 |
| 189 | `define MCU_RANK_SEL_PA10 7'h20 |
| 190 | `define MCU_RANK_SEL_PA11 7'h40 |
| 191 | |
| 192 | `define MCU_ADDR_ERR_SEL_39_32 6'h01 |
| 193 | `define MCU_ADDR_ERR_SEL_39_33 6'h02 |
| 194 | `define MCU_ADDR_ERR_SEL_39_34 6'h04 |
| 195 | `define MCU_ADDR_ERR_SEL_39_35 6'h08 |
| 196 | `define MCU_ADDR_ERR_SEL_39_36 6'h10 |
| 197 | `define MCU_ADDR_ERR_SEL_39_37 6'h20 |
| 198 | |
| 199 | `define DRIF_ERR_IDLE 0 |
| 200 | `define DRIF_ERR_IDLE_ST 5'h1 |
| 201 | `define DRIF_ERR_READ0 1 |
| 202 | `define DRIF_ERR_READ0_ST 5'h2 |
| 203 | `define DRIF_ERR_WRITE 2 |
| 204 | `define DRIF_ERR_WRITE_ST 5'h4 |
| 205 | `define DRIF_ERR_READ1 3 |
| 206 | `define DRIF_ERR_READ1_ST 5'h8 |
| 207 | `define DRIF_ERR_CRC_FR 4 |
| 208 | `define DRIF_ERR_CRC_FR_ST 5'h10 |
| 209 | |
| 210 | `define MCU_WDQ_RF_DATA_WIDTH 72 |
| 211 | `define MCU_WDQ_RF_ADDR_WIDTH 5 |
| 212 | `define MCU_WDQ_RF_DEPTH 32 |
| 213 | |
| 214 | // FBDIMM header defines |
| 215 | `define FBD_TS0_HDR 12'hbfe |
| 216 | `define FBD_TS1_HDR 12'hffe |
| 217 | `define FBD_TS2_HDR 12'h7fe |
| 218 | `define FBD_TS3_HDR 12'h3fe |
| 219 | |
| 220 | // MCU FBDIMM Channel commands |
| 221 | `define FBD_DRAM_CMD_NOP 3'h0 |
| 222 | `define FBD_DRAM_CMD_OTHER 3'h1 |
| 223 | `define FBD_DRAM_CMD_RD 3'h2 |
| 224 | `define FBD_DRAM_CMD_WR 3'h3 |
| 225 | `define FBD_DRAM_CMD_ACT 3'h4 |
| 226 | `define FBD_DRAM_CMD_WDATA 3'h5 |
| 227 | |
| 228 | `define FBD_DRAM_CMD_OTHER_REF 3'h5 |
| 229 | `define FBD_DRAM_CMD_OTHER_SRE 3'h4 |
| 230 | `define FBD_DRAM_CMD_OTHER_PDE 3'h2 |
| 231 | `define FBD_DRAM_CMD_OTHER_SRPDX 3'h3 |
| 232 | |
| 233 | `define FBD_CHNL_CMD_NOP 2'h0 |
| 234 | `define FBD_CHNL_CMD_SYNC 2'h1 |
| 235 | `define FBD_CHNL_CMD_SCRST 2'h2 |
| 236 | |
| 237 | `define FBDIC_ERR_IDLE_ST 7'h01 |
| 238 | `define FBDIC_ERR_IDLE 0 |
| 239 | |
| 240 | `define FBDIC_ERR_STS_ST 7'h02 |
| 241 | `define FBDIC_ERR_STS 1 |
| 242 | |
| 243 | `define FBDIC_ERR_SCRST_ST 7'h04 |
| 244 | `define FBDIC_ERR_SCRST 2 |
| 245 | |
| 246 | `define FBDIC_ERR_SCRST_STS_ST 7'h08 |
| 247 | `define FBDIC_ERR_SCRST_STS 3 |
| 248 | |
| 249 | `define FBDIC_ERR_STS2_ST 7'h10 |
| 250 | `define FBDIC_ERR_STS2 4 |
| 251 | |
| 252 | `define FBDIC_ERR_FASTRST_ST 7'h20 |
| 253 | `define FBDIC_ERR_FASTRST 5 |
| 254 | |
| 255 | `define FBDIC_ERR_FASTRST_STS_ST 7'h40 |
| 256 | `define FBDIC_ERR_FASTRST_STS 6 |
| 257 | |
| 258 | |
| 259 | // IBIST DEFINITION |
| 260 | |
| 261 | `define L_2_0 12'h555 |
| 262 | `define L_2_1 12'h555 |
| 263 | `define L_4_0 12'h333 |
| 264 | `define L_4_1 12'h333 |
| 265 | `define L_6_0 12'h1c7 |
| 266 | `define L_6_1 12'h1c7 |
| 267 | `define L_8_0 12'h0f0 |
| 268 | `define L_8_1 12'hf0f |
| 269 | `define L_24_0 12'h000 |
| 270 | `define L_24_1 12'hfff |
| 271 | |
| 272 | `define idle 4'h0 |
| 273 | |
| 274 | `define error_0 4'h1 |
| 275 | `define error_1 4'h2 |
| 276 | |
| 277 | `define start1_0 4'h3 |
| 278 | `define start1_1 4'h4 |
| 279 | `define start2_0 4'h5 |
| 280 | `define start2_1 4'h6 |
| 281 | |
| 282 | `define pat1_0 4'h7 |
| 283 | `define pat1_1 4'h8 |
| 284 | |
| 285 | `define clkpat_0 4'h9 |
| 286 | `define clkpat_1 4'ha |
| 287 | |
| 288 | `define const_0 4'hb |
| 289 | `define const_1 4'hc |
| 290 | |
| 291 | `define stop1_0 4'h1 |
| 292 | `define stop1_1 4'h2 |
| 293 | |
| 294 | `define stop2_0 4'hd |
| 295 | `define stop2_1 4'he |
| 296 | `define error 4'hf |
| 297 | |
| 298 | `define IBTX_STATE_IDLE 0 |
| 299 | `define IBTX_STATE_PATT 1 |
| 300 | `define IBTX_STATE_MODN 2 |
| 301 | `define IBTX_STATE_CONST 3 |
| 302 | |
| 303 | `define IBRX_STATE_IDLE 0 |
| 304 | `define IBRX_STATE_PATT 1 |
| 305 | `define IBRX_STATE_MODN 2 |
| 306 | `define IBRX_STATE_CONST 3 |
| 307 | |
| 308 | |
| 309 | |
| 310 | module mcu_rdpctl_ctl ( |
| 311 | rdpctl_scrub_addrinc_en, |
| 312 | rdpctl_err_addr_reg, |
| 313 | rdpctl_err_sts_reg, |
| 314 | rdpctl_err_loc, |
| 315 | rdpctl_err_cnt, |
| 316 | rdpctl_err_retry_reg, |
| 317 | rdpctl_dbg_trig_enable, |
| 318 | rdpctl_drq0_clear_ent, |
| 319 | rdpctl_drq1_clear_ent, |
| 320 | rdpctl_err_fifo_enq, |
| 321 | rdpctl_err_fifo_data, |
| 322 | rdpctl_fifo_empty, |
| 323 | rdpctl_fifo_full, |
| 324 | rdpctl_no_crc_err, |
| 325 | rdpctl_crc_err, |
| 326 | rdpctl_fbd0_recov_err, |
| 327 | rdpctl_fbd1_recov_err, |
| 328 | rdpctl_fbd_unrecov_err, |
| 329 | rdpctl_crc_recov_err, |
| 330 | rdpctl_crc_unrecov_err, |
| 331 | rdpctl_scrub_read_done, |
| 332 | rdpctl_scrb0_err_valid, |
| 333 | rdpctl_scrb1_err_valid, |
| 334 | rdpctl_l2t0_data_valid, |
| 335 | rdpctl_l2t1_data_valid, |
| 336 | rdpctl_qword_id, |
| 337 | rdpctl_rd_req_id, |
| 338 | rdpctl_pa_err, |
| 339 | rdpctl_radr_parity, |
| 340 | rdpctl_rddata_en, |
| 341 | rdpctl_inj_ecc_err, |
| 342 | rdpctl0_dummy_data_valid, |
| 343 | rdpctl1_dummy_data_valid, |
| 344 | rdpctl_secc_cnt_intr, |
| 345 | rdpctl_scrub_wren, |
| 346 | rdpctl_mask_err, |
| 347 | rdpctl_dtm_mask_chnl, |
| 348 | rdpctl_dtm_atspeed, |
| 349 | rdpctl_dtm_chnl_enable, |
| 350 | fbdic_serdes_dtm, |
| 351 | fbdic_rddata_vld, |
| 352 | fbdic_crc_error, |
| 353 | fbdic_chnl_reset_error, |
| 354 | drif_err_state_crc_fr, |
| 355 | fbdic_chnl_reset_error_mode, |
| 356 | fbdic_err_unrecov, |
| 357 | fbdic_err_recov, |
| 358 | fbdic_cfgrd_crc_error, |
| 359 | drif_send_info_val, |
| 360 | drif_send_info, |
| 361 | readdp_ecc_single_err, |
| 362 | readdp_ecc_multi_err, |
| 363 | readdp0_syndrome, |
| 364 | readdp1_syndrome, |
| 365 | readdp0_ecc_loc, |
| 366 | readdp1_ecc_loc, |
| 367 | drif_scrub_addr, |
| 368 | mcu_id, |
| 369 | drif_single_channel_mode, |
| 370 | l2if0_rd_dummy_req, |
| 371 | l2if0_rd_dummy_req_addr5, |
| 372 | l2if0_rd_dummy_req_id, |
| 373 | l2if0_rd_dummy_addr_err, |
| 374 | l2if1_rd_dummy_req, |
| 375 | l2if1_rd_dummy_req_addr5, |
| 376 | l2if1_rd_dummy_req_id, |
| 377 | l2if1_rd_dummy_addr_err, |
| 378 | drif_ucb_data_39to0, |
| 379 | drif_ucb_data_63to54, |
| 380 | drif_err_sts_reg_ld, |
| 381 | drif_err_addr_reg_ld, |
| 382 | drif_err_cnt_reg_ld, |
| 383 | drif_err_loc_reg_ld, |
| 384 | drif_err_retry_reg_ld, |
| 385 | drif_dbg_trig_reg_ld, |
| 386 | rdata_err_ecci, |
| 387 | rdata_pm_1mcu, |
| 388 | rdata_pm_2mcu, |
| 389 | drl2clk, |
| 390 | scan_in, |
| 391 | scan_out, |
| 392 | wmr_scan_in, |
| 393 | wmr_scan_out, |
| 394 | tcu_pce_ov, |
| 395 | tcu_aclk, |
| 396 | tcu_bclk, |
| 397 | aclk_wmr, |
| 398 | tcu_scan_en, |
| 399 | wmr_protect); |
| 400 | wire pce_ov; |
| 401 | wire siclk; |
| 402 | wire soclk; |
| 403 | wire se; |
| 404 | wire l1clk; |
| 405 | wire ff_pm_mcus_scanin; |
| 406 | wire ff_pm_mcus_scanout; |
| 407 | wire rdpctl_pm_1mcu; |
| 408 | wire rdpctl_pm_2mcu; |
| 409 | wire ff_dummy_req0_scanin; |
| 410 | wire ff_dummy_req0_scanout; |
| 411 | wire rdpctl0_rd_dummy_req_en; |
| 412 | wire rdpctl0_rd_dummy_req_addr5_in; |
| 413 | wire [2:0] rdpctl0_rd_dummy_req_id_in; |
| 414 | wire rdpctl0_rd_dummy_addr_err_in; |
| 415 | wire ff_dummy_req1_scanin; |
| 416 | wire ff_dummy_req1_scanout; |
| 417 | wire rdpctl1_rd_dummy_req_en; |
| 418 | wire rdpctl1_rd_dummy_req_addr5_in; |
| 419 | wire [2:0] rdpctl1_rd_dummy_req_id_in; |
| 420 | wire rdpctl1_rd_dummy_addr_err_in; |
| 421 | wire ff_ddp_data_valid_scanin; |
| 422 | wire ff_ddp_data_valid_scanout; |
| 423 | wire rdpctl_rddata_vld; |
| 424 | wire rdpctl_mcu_data_valid; |
| 425 | wire ff_ecc_loc_scanin; |
| 426 | wire ff_ecc_loc_scanout; |
| 427 | wire [35:0] rdpctl0_ecc_loc; |
| 428 | wire [35:0] rdpctl1_ecc_loc; |
| 429 | wire rdpctl_fifo_deq; |
| 430 | wire rdpctl_data_cnt; |
| 431 | wire rdpctl_data_cnt_in; |
| 432 | wire rdpctl0_dummy_data_valid_in; |
| 433 | wire rdpctl1_dummy_data_valid_in; |
| 434 | wire ff_data_cnt_scanin; |
| 435 | wire ff_data_cnt_scanout; |
| 436 | wire rdpctl_fifo_err_crc; |
| 437 | wire [19:0] rdpctl_fifo_ent0; |
| 438 | wire rdpctl_fifo_err_xaction; |
| 439 | wire rdpctl_fifo_rank_adr; |
| 440 | wire [2:0] rdpctl_fifo_dimm_adr; |
| 441 | wire [2:0] rdpctl_fifo_bank_adr; |
| 442 | wire rdpctl_fifo_addr_pa_err; |
| 443 | wire rdpctl_fifo_err_type; |
| 444 | wire rdpctl_fifo_addr_parity; |
| 445 | wire rdpctl_fifo_scrub; |
| 446 | wire [2:0] rdpctl_fifo_rd_index; |
| 447 | wire [2:0] rdpctl_fifo_rd_req_id; |
| 448 | wire rdpctl_fifo_err_xactnum; |
| 449 | wire rdpctl_fifo_qword_id; |
| 450 | wire rdpctl_fifo_l2bank; |
| 451 | wire otq_scanin; |
| 452 | wire otq_scanout; |
| 453 | wire rdpctl_fifo_addr_parity_p1; |
| 454 | wire rdpctl_clear_drq_entry; |
| 455 | wire rdpctl_fifo_deq_d1; |
| 456 | wire rdpctl_fifo_scrub_d1; |
| 457 | wire rdpctl_fifo_err_xaction_d1; |
| 458 | wire rdpctl_ecc_error; |
| 459 | wire rdpctl_crc_error_d1; |
| 460 | wire drif_err_state_crc_fr_d1; |
| 461 | wire rdpctl_clear_drq0_entry; |
| 462 | wire rdpctl_fifo_l2bank_d1; |
| 463 | wire rdpctl_clear_drq1_entry; |
| 464 | wire [7:0] rdpctl_drq0_clear_ent_in; |
| 465 | wire [2:0] rdpctl_fifo_rd_index_d1; |
| 466 | wire [7:0] rdpctl_drq1_clear_ent_in; |
| 467 | wire ff_drif_clear_ent_scanin; |
| 468 | wire ff_drif_clear_ent_scanout; |
| 469 | wire rdpctl_l2t0_data_valid_in; |
| 470 | wire rdpctl_crc_error_in; |
| 471 | wire rdpctl_crc_error; |
| 472 | wire rdpctl_l2t1_data_valid_in; |
| 473 | wire rdpctl_l2t_data_valid; |
| 474 | wire ff_l2t_data_valid_scanin; |
| 475 | wire ff_l2t_data_valid_scanout; |
| 476 | wire rdpctl_scrub_data_valid_in; |
| 477 | wire ff_scrub_data_valid_scanin; |
| 478 | wire ff_scrub_data_valid_scanout; |
| 479 | wire rdpctl_scrub_data_valid_out; |
| 480 | wire rdpctl_scrub_data_valid; |
| 481 | wire rdpctl_qword_id_in; |
| 482 | wire rdpctl0_rd_dummy_req_addr5; |
| 483 | wire rdpctl1_rd_dummy_req_addr5; |
| 484 | wire ff_qword_id_scanin; |
| 485 | wire ff_qword_id_scanout; |
| 486 | wire [2:0] rdpctl_rd_req_id_in; |
| 487 | wire [2:0] rdpctl0_rd_dummy_req_id; |
| 488 | wire [2:0] rdpctl1_rd_dummy_req_id; |
| 489 | wire ff_rd_req_id_scanin; |
| 490 | wire ff_rd_req_id_scanout; |
| 491 | wire rdpctl_pa_err_in; |
| 492 | wire rdpctl0_rd_dummy_addr_err; |
| 493 | wire rdpctl1_rd_dummy_addr_err; |
| 494 | wire ff_pa_err_scanin; |
| 495 | wire ff_pa_err_scanout; |
| 496 | wire rdpctl_crc_err_st0; |
| 497 | wire [1:0] rdpctl_rddata_state; |
| 498 | wire rdpctl_crc_err_st1; |
| 499 | wire rdpctl_crc_err_st0_d1; |
| 500 | wire rdpctl_crc_err_st2; |
| 501 | wire rdpctl_crc_err_st1_d1; |
| 502 | wire rdpctl_crc_err_st3; |
| 503 | wire rdpctl_crc_err_st2_d1; |
| 504 | wire ff_crc_err_dly_scanin; |
| 505 | wire ff_crc_err_dly_scanout; |
| 506 | wire readdp_ecc_multi_err_d1_in; |
| 507 | wire ff_mecc_errors_scanin; |
| 508 | wire ff_mecc_errors_scanout; |
| 509 | wire readdp_ecc_multi_err_d1; |
| 510 | wire readdp_ecc_multi_err_d2; |
| 511 | wire readdp_ecc_multi_err_d3; |
| 512 | wire rdpctl_ecc_multi_err; |
| 513 | wire [1:0] rdpctl_ecc_multi_err_d1; |
| 514 | wire rdpctl_ecc_single_err; |
| 515 | wire [1:0] rdpctl_ecc_single_err_d1; |
| 516 | wire rdpctl_err_type; |
| 517 | wire rdpctl_fifo_err_crc_d1; |
| 518 | wire [13:0] rdpctl_err_fifo_data_in; |
| 519 | wire ff_err_fifo_data_scanin; |
| 520 | wire ff_err_fifo_data_scanout; |
| 521 | wire ff_fifo_deq_d1_scanin; |
| 522 | wire ff_fifo_deq_d1_scanout; |
| 523 | wire rdpctl_fifo_err_type_d1; |
| 524 | wire rdpctl_fifo_err_xactnum_d1; |
| 525 | wire rdpctl_meu_error; |
| 526 | wire rdpctl_mec_error; |
| 527 | wire rdpctl_dac_error; |
| 528 | wire rdpctl_dau_error; |
| 529 | wire rdpctl_dsc_error; |
| 530 | wire rdpctl_dsu_error; |
| 531 | wire rdpctl_dbu_error; |
| 532 | wire rdpctl_meb_error; |
| 533 | wire rdpctl_fbu_error; |
| 534 | wire rdpctl_fbr_error; |
| 535 | wire rdpctl_meu_error_en; |
| 536 | wire rdpctl_meu_error_in; |
| 537 | wire pff_err_sts_bit63_wmr_scanin; |
| 538 | wire pff_err_sts_bit63_wmr_scanout; |
| 539 | wire rdpctl_mec_error_en; |
| 540 | wire rdpctl_mec_error_in; |
| 541 | wire pff_err_sts_bit62_wmr_scanin; |
| 542 | wire pff_err_sts_bit62_wmr_scanout; |
| 543 | wire rdpctl_dac_error_en; |
| 544 | wire rdpctl_dac_error_in; |
| 545 | wire pff_err_sts_bit61_wmr_scanin; |
| 546 | wire pff_err_sts_bit61_wmr_scanout; |
| 547 | wire rdpctl_dau_error_en; |
| 548 | wire rdpctl_dau_error_in; |
| 549 | wire pff_err_sts_bit60_wmr_scanin; |
| 550 | wire pff_err_sts_bit60_wmr_scanout; |
| 551 | wire rdpctl_dsc_error_en; |
| 552 | wire rdpctl_dsc_error_in; |
| 553 | wire pff_err_sts_bit59_wmr_scanin; |
| 554 | wire pff_err_sts_bit59_wmr_scanout; |
| 555 | wire rdpctl_dsu_error_en; |
| 556 | wire rdpctl_dsu_error_in; |
| 557 | wire pff_err_sts_bit58_wmr_scanin; |
| 558 | wire pff_err_sts_bit58_wmr_scanout; |
| 559 | wire rdpctl_dummy_dbu; |
| 560 | wire rdpctl_dbu_error_en; |
| 561 | wire rdpctl_dbu_error_in; |
| 562 | wire pff_err_sts_bit57_wmr_scanin; |
| 563 | wire pff_err_sts_bit57_wmr_scanout; |
| 564 | wire rdpctl_meb_error_en; |
| 565 | wire rdpctl_meb_error_in; |
| 566 | wire pff_err_sts_bit56_wmr_scanin; |
| 567 | wire pff_err_sts_bit56_wmr_scanout; |
| 568 | wire rdpctl_fbu_error_en; |
| 569 | wire rdpctl_fbu_error_in; |
| 570 | wire pff_err_sts_bit55_wmr_scanin; |
| 571 | wire pff_err_sts_bit55_wmr_scanout; |
| 572 | wire ff_fbd_unrecov_err_scanin; |
| 573 | wire ff_fbd_unrecov_err_scanout; |
| 574 | wire rdpctl_fbd_unrecov_err_1_in; |
| 575 | wire rdpctl_crc_unrecov_err_in; |
| 576 | wire ff_crc_unrecov_err_scanin; |
| 577 | wire ff_crc_unrecov_err_scanout; |
| 578 | wire rdpctl_fbr_error_en; |
| 579 | wire rdpctl_fbr_error_in; |
| 580 | wire pff_err_sts_bit54_wmr_scanin; |
| 581 | wire pff_err_sts_bit54_wmr_scanout; |
| 582 | wire rdpctl_fbd0_recov_err_in; |
| 583 | wire rdpctl_fbd1_recov_err_in; |
| 584 | wire ff_fbd_recov_err_scanin; |
| 585 | wire ff_fbd_recov_err_scanout; |
| 586 | wire rdpctl_crc_recov_err_in; |
| 587 | wire ff_crc_recov_err_scanin; |
| 588 | wire ff_crc_recov_err_scanout; |
| 589 | wire rdpctl_crc_recov_err_out; |
| 590 | wire ff_ecc_d1_scanin; |
| 591 | wire ff_ecc_d1_scanout; |
| 592 | wire [15:0] rdpctl0_syndrome; |
| 593 | wire [15:0] rdpctl1_syndrome; |
| 594 | wire rdpctl_err_sts_reg_en; |
| 595 | wire [15:0] rdpctl_err_sts_reg_in; |
| 596 | wire pff_err_syn_wmr_scanin; |
| 597 | wire pff_err_syn_wmr_scanout; |
| 598 | wire rdpctl_err_retry_ld_en; |
| 599 | wire rdpctl_err_retry_ld_clr; |
| 600 | wire ff_err_retry_ld_scanin; |
| 601 | wire ff_err_retry_ld_scanout; |
| 602 | wire rdpctl_err_retry_ld_out; |
| 603 | wire rdpctl_err_retry_ld; |
| 604 | wire rdpctl_retry_reg_valid; |
| 605 | wire [17:0] rdpctl_err_retry2_reg; |
| 606 | wire [17:0] rdpctl_err_retry1_reg; |
| 607 | wire rdpctl_err_retry1_reg_en; |
| 608 | wire [17:0] rdpctl_err_retry1_reg_in; |
| 609 | wire [15:0] rdpctl_retry_syndrome; |
| 610 | wire pff_err_retry1_wmr_scanin; |
| 611 | wire pff_err_retry1_wmr_scanout; |
| 612 | wire rdpctl_err_retry2_reg_en; |
| 613 | wire [17:0] rdpctl_err_retry2_reg_in; |
| 614 | wire pff_err_retry2_wmr_scanin; |
| 615 | wire pff_err_retry2_wmr_scanout; |
| 616 | wire rdpctl_err_retry2_reg_en_no_ld; |
| 617 | wire rdpctl_err_retry1_reg_en_no_ld; |
| 618 | wire rdpctl_retry_reg_valid_in; |
| 619 | wire rdpctl_retry_reg_valid_en; |
| 620 | wire pff_retry_reg_valid_wmr_scanin; |
| 621 | wire pff_retry_reg_valid_wmr_scanout; |
| 622 | wire rdpctl_syndrome_dly_en; |
| 623 | wire ff_syndrome_dly_scanin; |
| 624 | wire ff_syndrome_dly_scanout; |
| 625 | wire [15:0] rdpctl0_syndrome_d1; |
| 626 | wire [15:0] rdpctl1_syndrome_d1; |
| 627 | wire rdpctl_err_addr_reg_en; |
| 628 | wire [35:0] rdpctl_err_addr_reg_in; |
| 629 | wire [35:0] rdpctl_err_addr; |
| 630 | wire [1:0] rdpctl_scrub_data_cnt; |
| 631 | wire pff_err_addr_reg_wmr_scanin; |
| 632 | wire pff_err_addr_reg_wmr_scanout; |
| 633 | wire [1:1] rdpctl_scrub_data_cnt_in; |
| 634 | wire rdpctl_scrub_data_cnt_en; |
| 635 | wire ff_scrub_data_cnt_scanin; |
| 636 | wire ff_scrub_data_cnt_scanout; |
| 637 | wire [15:0] rdpctl_secc_cnt; |
| 638 | wire rdpctl_secc_int_en; |
| 639 | wire rdpctl_secc_cnt_intr_in; |
| 640 | wire rdpctl_secc_int_in; |
| 641 | wire pff_secc_int_en_wmr_scanin; |
| 642 | wire pff_secc_int_en_wmr_scanout; |
| 643 | wire rdpctl_secc_int_enabled; |
| 644 | wire rdpctl_secc_cnt_en; |
| 645 | wire [15:0] rdpctl_secc_cnt_next; |
| 646 | wire [15:0] rdpctl_secc_cnt_in; |
| 647 | wire pff_secc_cnt_wmr_scanin; |
| 648 | wire pff_secc_cnt_wmr_scanout; |
| 649 | wire ff_secc_cnt_intr_scanin; |
| 650 | wire ff_secc_cnt_intr_scanout; |
| 651 | wire [5:1] rdpctl_dbg_trig_enable_in; |
| 652 | wire pff_dbg_trig_wmr_scanin; |
| 653 | wire pff_dbg_trig_wmr_scanout; |
| 654 | wire rdpctl_secc_loc_en; |
| 655 | wire [35:0] rdpctl_err_loc_in; |
| 656 | wire pff_err_loc_wmr_scanin; |
| 657 | wire pff_err_loc_wmr_scanout; |
| 658 | wire rdpctl_scrb0_err_valid_in; |
| 659 | wire rdpctl_scrb1_err_valid_in; |
| 660 | wire ff_scrub_ecc_err_scanin; |
| 661 | wire ff_scrub_ecc_err_scanout; |
| 662 | wire ff_rd_dummy_req0_scanin; |
| 663 | wire ff_rd_dummy_req0_scanout; |
| 664 | wire rdpctl0_rd_dummy_req; |
| 665 | wire ff_rd_dummy0_scanin; |
| 666 | wire ff_rd_dummy0_scanout; |
| 667 | wire ff_rd_dummy_req1_scanin; |
| 668 | wire ff_rd_dummy_req1_scanout; |
| 669 | wire rdpctl1_rd_dummy_req; |
| 670 | wire ff_rd_dummy1_scanin; |
| 671 | wire ff_rd_dummy1_scanout; |
| 672 | wire rdpctl_dummy_priority_in; |
| 673 | wire rdpctl_dummy_priority; |
| 674 | wire ff_dummy_priority_scanin; |
| 675 | wire ff_dummy_priority_scanout; |
| 676 | wire ff_dummy_data_valid_scanin; |
| 677 | wire ff_dummy_data_valid_scanout; |
| 678 | wire rdpctl_scrub_wren_out; |
| 679 | wire rdpctl_scrub_wren_in; |
| 680 | wire ff_scrub_wren_scanin; |
| 681 | wire ff_scrub_wren_scanout; |
| 682 | wire [1:0] rdpctl_rddata_state_in; |
| 683 | wire ff_rddata_state_scanin; |
| 684 | wire ff_rddata_state_scanout; |
| 685 | wire ff_err_ecci_scanin; |
| 686 | wire ff_err_ecci_scanout; |
| 687 | wire rdpctl_err_ecci; |
| 688 | wire spares_scanin; |
| 689 | wire spares_scanout; |
| 690 | |
| 691 | |
| 692 | output rdpctl_scrub_addrinc_en; // increment scrub address |
| 693 | |
| 694 | // error registers to drif block for read access |
| 695 | output [35:0] rdpctl_err_addr_reg; |
| 696 | output [25:0] rdpctl_err_sts_reg; |
| 697 | output [35:0] rdpctl_err_loc; |
| 698 | output [15:0] rdpctl_err_cnt; |
| 699 | output [36:0] rdpctl_err_retry_reg; |
| 700 | output rdpctl_dbg_trig_enable; // debug mode trigger enable |
| 701 | |
| 702 | // clear entries from read queues when dequeued from rdpctl fifo if no errors |
| 703 | output [7:0] rdpctl_drq0_clear_ent; |
| 704 | output [7:0] rdpctl_drq1_clear_ent; |
| 705 | |
| 706 | // error information to drif for error retries |
| 707 | output rdpctl_err_fifo_enq; |
| 708 | output [14:0] rdpctl_err_fifo_data; |
| 709 | output rdpctl_fifo_empty; |
| 710 | output rdpctl_fifo_full; |
| 711 | output rdpctl_no_crc_err; |
| 712 | output rdpctl_crc_err; |
| 713 | output rdpctl_fbd0_recov_err; |
| 714 | output rdpctl_fbd1_recov_err; |
| 715 | output [1:0] rdpctl_fbd_unrecov_err; |
| 716 | output rdpctl_crc_recov_err; |
| 717 | output rdpctl_crc_unrecov_err; |
| 718 | |
| 719 | output rdpctl_scrub_read_done; // resets outstanding scrub flop |
| 720 | |
| 721 | output rdpctl_scrb0_err_valid; |
| 722 | output rdpctl_scrb1_err_valid; |
| 723 | |
| 724 | output rdpctl_l2t0_data_valid; // data valid signal to rdata_ctl for L2 0 |
| 725 | output rdpctl_l2t1_data_valid; // data valid signal to rdata_ctl for L2 1 |
| 726 | output rdpctl_qword_id; // quad-word id for returning data sub-packet |
| 727 | output [2:0] rdpctl_rd_req_id; // read request id for returning data packet |
| 728 | output rdpctl_pa_err; // physical address error bit to OR with mecc |
| 729 | |
| 730 | output rdpctl_radr_parity; // parity to readdp |
| 731 | output [2:0] rdpctl_rddata_en; // read data enable for single-dimm mode |
| 732 | output rdpctl_inj_ecc_err; // ecc error injection for readdp |
| 733 | |
| 734 | // indicates to rdata block when empty is coming to respond to dummy read |
| 735 | output rdpctl0_dummy_data_valid; |
| 736 | output rdpctl1_dummy_data_valid; |
| 737 | |
| 738 | output rdpctl_secc_cnt_intr; // single ecc error counter interrupt |
| 739 | |
| 740 | output rdpctl_scrub_wren; // write enable for wrdp scrub data buffer |
| 741 | |
| 742 | output rdpctl_mask_err; |
| 743 | output [1:0] rdpctl_dtm_mask_chnl; |
| 744 | output rdpctl_dtm_atspeed; |
| 745 | output [1:0] rdpctl_dtm_chnl_enable; |
| 746 | |
| 747 | input fbdic_serdes_dtm; |
| 748 | |
| 749 | input fbdic_rddata_vld; // read data from fbdic valid |
| 750 | input fbdic_crc_error; |
| 751 | input fbdic_chnl_reset_error; |
| 752 | input drif_err_state_crc_fr; |
| 753 | input fbdic_chnl_reset_error_mode; |
| 754 | input fbdic_err_unrecov; |
| 755 | input fbdic_err_recov; |
| 756 | input fbdic_cfgrd_crc_error; |
| 757 | |
| 758 | // information associated with returning read data |
| 759 | input drif_send_info_val; // which send_info buses are valid |
| 760 | input [19:0] drif_send_info; // info for CMD A slot (rd or wr) |
| 761 | |
| 762 | input [1:0] readdp_ecc_single_err; // single-bit ecc error detected |
| 763 | input [1:0] readdp_ecc_multi_err; // multiple-bit ecc error detected |
| 764 | input [15:0] readdp0_syndrome; // ecc syndrome bits for error reporting |
| 765 | input [15:0] readdp1_syndrome; // ecc syndrome bits for error reporting |
| 766 | input [35:0] readdp0_ecc_loc; // error nibble for error reporting |
| 767 | input [35:0] readdp1_ecc_loc; // error nibble for error reporting |
| 768 | |
| 769 | input [31:0] drif_scrub_addr; // scrub address for error logging |
| 770 | input [1:0] mcu_id; // for scrub address in address error register, |
| 771 | // to indicate in which mcu error occurred |
| 772 | |
| 773 | // SDRAM address generation information |
| 774 | input drif_single_channel_mode; |
| 775 | |
| 776 | // |
| 777 | input l2if0_rd_dummy_req; |
| 778 | input l2if0_rd_dummy_req_addr5; |
| 779 | input [2:0] l2if0_rd_dummy_req_id; |
| 780 | input l2if0_rd_dummy_addr_err; |
| 781 | input l2if1_rd_dummy_req; |
| 782 | input l2if1_rd_dummy_req_addr5; |
| 783 | input [2:0] l2if1_rd_dummy_req_id; |
| 784 | input l2if1_rd_dummy_addr_err; |
| 785 | |
| 786 | // register write interface for rdpctl |
| 787 | input [39:0] drif_ucb_data_39to0; |
| 788 | input [63:54] drif_ucb_data_63to54; |
| 789 | input drif_err_sts_reg_ld; |
| 790 | input drif_err_addr_reg_ld; |
| 791 | input drif_err_cnt_reg_ld; |
| 792 | input drif_err_loc_reg_ld; |
| 793 | input drif_err_retry_reg_ld; |
| 794 | input drif_dbg_trig_reg_ld; |
| 795 | |
| 796 | input rdata_err_ecci; |
| 797 | |
| 798 | input rdata_pm_1mcu; |
| 799 | input rdata_pm_2mcu; |
| 800 | |
| 801 | input drl2clk; |
| 802 | input scan_in; |
| 803 | output scan_out; |
| 804 | input wmr_scan_in; |
| 805 | output wmr_scan_out; |
| 806 | input tcu_pce_ov; |
| 807 | input tcu_aclk; |
| 808 | input tcu_bclk; |
| 809 | input aclk_wmr; |
| 810 | input tcu_scan_en; |
| 811 | input wmr_protect; |
| 812 | |
| 813 | // Code |
| 814 | assign pce_ov = tcu_pce_ov; |
| 815 | assign siclk = tcu_aclk; |
| 816 | assign soclk = tcu_bclk; |
| 817 | assign se = tcu_scan_en; |
| 818 | |
| 819 | // 0in set_clock drl2clk -default |
| 820 | mcu_rdpctl_ctl_l1clkhdr_ctl_macro clkgen ( |
| 821 | .l2clk(drl2clk), |
| 822 | .l1en(1'b1 ), |
| 823 | .stop(1'b0), |
| 824 | .l1clk(l1clk), |
| 825 | .pce_ov(pce_ov), |
| 826 | .se(se)); |
| 827 | |
| 828 | mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_pm_mcus ( |
| 829 | .scan_in(ff_pm_mcus_scanin), |
| 830 | .scan_out(ff_pm_mcus_scanout), |
| 831 | .din({rdata_pm_1mcu,rdata_pm_2mcu}), |
| 832 | .dout({rdpctl_pm_1mcu,rdpctl_pm_2mcu}), |
| 833 | .l1clk(l1clk), |
| 834 | .siclk(siclk), |
| 835 | .soclk(soclk)); |
| 836 | |
| 837 | mcu_rdpctl_ctl_msff_ctl_macro__width_6 ff_dummy_req0 ( |
| 838 | .scan_in(ff_dummy_req0_scanin), |
| 839 | .scan_out(ff_dummy_req0_scanout), |
| 840 | .din({l2if0_rd_dummy_req, l2if0_rd_dummy_req_addr5, l2if0_rd_dummy_req_id[2:0], l2if0_rd_dummy_addr_err}), |
| 841 | .dout({rdpctl0_rd_dummy_req_en, rdpctl0_rd_dummy_req_addr5_in, rdpctl0_rd_dummy_req_id_in[2:0], rdpctl0_rd_dummy_addr_err_in}), |
| 842 | .l1clk(l1clk), |
| 843 | .siclk(siclk), |
| 844 | .soclk(soclk)); |
| 845 | |
| 846 | mcu_rdpctl_ctl_msff_ctl_macro__width_6 ff_dummy_req1 ( |
| 847 | .scan_in(ff_dummy_req1_scanin), |
| 848 | .scan_out(ff_dummy_req1_scanout), |
| 849 | .din({l2if1_rd_dummy_req, l2if1_rd_dummy_req_addr5, l2if1_rd_dummy_req_id[2:0], l2if1_rd_dummy_addr_err}), |
| 850 | .dout({rdpctl1_rd_dummy_req_en, rdpctl1_rd_dummy_req_addr5_in, rdpctl1_rd_dummy_req_id_in[2:0], rdpctl1_rd_dummy_addr_err_in}), |
| 851 | .l1clk(l1clk), |
| 852 | .siclk(siclk), |
| 853 | .soclk(soclk)); |
| 854 | |
| 855 | mcu_rdpctl_ctl_msff_ctl_macro ff_ddp_data_valid ( |
| 856 | .scan_in(ff_ddp_data_valid_scanin), |
| 857 | .scan_out(ff_ddp_data_valid_scanout), |
| 858 | .din(rdpctl_rddata_vld), |
| 859 | .dout(rdpctl_mcu_data_valid), |
| 860 | .l1clk(l1clk), |
| 861 | .siclk(siclk), |
| 862 | .soclk(soclk)); |
| 863 | |
| 864 | mcu_rdpctl_ctl_msff_ctl_macro__width_72 ff_ecc_loc ( |
| 865 | .scan_in(ff_ecc_loc_scanin), |
| 866 | .scan_out(ff_ecc_loc_scanout), |
| 867 | .din({readdp0_ecc_loc[35:0],readdp1_ecc_loc[35:0]}), |
| 868 | .dout({rdpctl0_ecc_loc[35:0],rdpctl1_ecc_loc[35:0]}), |
| 869 | .l1clk(l1clk), |
| 870 | .siclk(siclk), |
| 871 | .soclk(soclk)); |
| 872 | |
| 873 | // This part of code controls the 16 deep FIFO that directs the data that comes back |
| 874 | // from the SDRAMs |
| 875 | |
| 876 | assign rdpctl_fifo_deq = rdpctl_data_cnt & rdpctl_mcu_data_valid; |
| 877 | |
| 878 | assign rdpctl_data_cnt_in = rdpctl_mcu_data_valid | rdpctl0_dummy_data_valid_in | rdpctl1_dummy_data_valid_in ? |
| 879 | ~rdpctl_data_cnt : rdpctl_data_cnt; |
| 880 | |
| 881 | mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_data_cnt ( |
| 882 | .scan_in(ff_data_cnt_scanin), |
| 883 | .scan_out(ff_data_cnt_scanout), |
| 884 | .din(rdpctl_data_cnt_in), |
| 885 | .dout(rdpctl_data_cnt), |
| 886 | .l1clk(l1clk), |
| 887 | .siclk(siclk), |
| 888 | .soclk(soclk)); |
| 889 | |
| 890 | // 19 - crc error retry |
| 891 | // 18 - error mode transaction |
| 892 | // 17 - drif_rank_adr_d1 - for error retry |
| 893 | // 16:14 - drif_dimm_adr_d1 - for error retry |
| 894 | // 13:11 - drif_bank_adr_d1[2:0] - for error retry |
| 895 | // 10 - drif_addr_err_d1 - out of bound error |
| 896 | // 9 - drif_addr_parity_d1 |
| 897 | // 8 - drif_scrub_picked_d1 |
| 898 | // 7:5 - drif_rd_index_d1[2:0] - index to free |
| 899 | // 4:2 - drif_rd_req_id_d1[2:0] |
| 900 | // 1 - drif_cas_adr_d1[1] - qword_id (PA[5]) |
| 901 | // 0 - drif1_rd_picked_d1 - return to l2t1 |
| 902 | |
| 903 | assign rdpctl_fifo_err_crc = rdpctl_fifo_ent0[19]; |
| 904 | assign rdpctl_fifo_err_xaction = rdpctl_fifo_ent0[18]; |
| 905 | assign rdpctl_fifo_rank_adr = rdpctl_fifo_ent0[17]; |
| 906 | assign rdpctl_fifo_dimm_adr[2:0] = rdpctl_fifo_ent0[16:14]; |
| 907 | assign rdpctl_fifo_bank_adr[2:0] = rdpctl_fifo_ent0[13:11]; |
| 908 | assign rdpctl_fifo_addr_pa_err = rdpctl_fifo_ent0[10] & ~rdpctl_fifo_err_xaction; |
| 909 | assign rdpctl_fifo_err_type = rdpctl_fifo_ent0[10] & rdpctl_fifo_err_xaction; |
| 910 | assign rdpctl_fifo_addr_parity = rdpctl_fifo_ent0[9]; |
| 911 | assign rdpctl_fifo_scrub = rdpctl_fifo_ent0[8]; |
| 912 | assign rdpctl_fifo_rd_index[2:0] = rdpctl_fifo_ent0[7:5]; |
| 913 | assign rdpctl_fifo_rd_req_id[2:0] = rdpctl_fifo_ent0[4:2]; |
| 914 | assign rdpctl_fifo_err_xactnum = rdpctl_fifo_ent0[2]; |
| 915 | assign rdpctl_fifo_qword_id = rdpctl_fifo_ent0[1]; |
| 916 | assign rdpctl_fifo_l2bank = rdpctl_fifo_ent0[0]; |
| 917 | |
| 918 | mcu_otq_ctl otq ( |
| 919 | .scan_in(otq_scanin), |
| 920 | .scan_out(otq_scanout), |
| 921 | .l1clk(l1clk), |
| 922 | .otq_enq(drif_send_info_val), |
| 923 | .otq_din(drif_send_info[19:0]), |
| 924 | .otq_deq(rdpctl_fifo_deq), |
| 925 | .otq_dout(rdpctl_fifo_ent0[19:0]), |
| 926 | .next_otq_dout_9(rdpctl_fifo_addr_parity_p1), |
| 927 | .otq_full(rdpctl_fifo_full), |
| 928 | .otq_empty(rdpctl_fifo_empty), |
| 929 | .tcu_aclk(tcu_aclk), |
| 930 | .tcu_bclk(tcu_bclk), |
| 931 | .tcu_scan_en(tcu_scan_en) |
| 932 | ); |
| 933 | |
| 934 | // Clear a read entry in the Read Request Queues |
| 935 | assign rdpctl_clear_drq_entry = rdpctl_fifo_deq_d1 & (~rdpctl_fifo_scrub_d1 & ~rdpctl_fifo_err_xaction_d1 & |
| 936 | (~rdpctl_ecc_error | rdpctl_pa_err) & (~rdpctl_crc_error_d1 | drif_err_state_crc_fr_d1) | |
| 937 | fbdic_chnl_reset_error_mode); |
| 938 | assign rdpctl_clear_drq0_entry = rdpctl_clear_drq_entry & ~rdpctl_fifo_l2bank_d1; |
| 939 | assign rdpctl_clear_drq1_entry = rdpctl_clear_drq_entry & rdpctl_fifo_l2bank_d1; |
| 940 | |
| 941 | assign rdpctl_drq0_clear_ent_in[0] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h0) & rdpctl_clear_drq0_entry; |
| 942 | assign rdpctl_drq0_clear_ent_in[1] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h1) & rdpctl_clear_drq0_entry; |
| 943 | assign rdpctl_drq0_clear_ent_in[2] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h2) & rdpctl_clear_drq0_entry; |
| 944 | assign rdpctl_drq0_clear_ent_in[3] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h3) & rdpctl_clear_drq0_entry; |
| 945 | assign rdpctl_drq0_clear_ent_in[4] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h4) & rdpctl_clear_drq0_entry; |
| 946 | assign rdpctl_drq0_clear_ent_in[5] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h5) & rdpctl_clear_drq0_entry; |
| 947 | assign rdpctl_drq0_clear_ent_in[6] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h6) & rdpctl_clear_drq0_entry; |
| 948 | assign rdpctl_drq0_clear_ent_in[7] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h7) & rdpctl_clear_drq0_entry; |
| 949 | |
| 950 | assign rdpctl_drq1_clear_ent_in[0] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h0) & rdpctl_clear_drq1_entry; |
| 951 | assign rdpctl_drq1_clear_ent_in[1] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h1) & rdpctl_clear_drq1_entry; |
| 952 | assign rdpctl_drq1_clear_ent_in[2] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h2) & rdpctl_clear_drq1_entry; |
| 953 | assign rdpctl_drq1_clear_ent_in[3] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h3) & rdpctl_clear_drq1_entry; |
| 954 | assign rdpctl_drq1_clear_ent_in[4] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h4) & rdpctl_clear_drq1_entry; |
| 955 | assign rdpctl_drq1_clear_ent_in[5] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h5) & rdpctl_clear_drq1_entry; |
| 956 | assign rdpctl_drq1_clear_ent_in[6] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h6) & rdpctl_clear_drq1_entry; |
| 957 | assign rdpctl_drq1_clear_ent_in[7] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h7) & rdpctl_clear_drq1_entry; |
| 958 | |
| 959 | mcu_rdpctl_ctl_msff_ctl_macro__width_16 ff_drif_clear_ent ( |
| 960 | .scan_in(ff_drif_clear_ent_scanin), |
| 961 | .scan_out(ff_drif_clear_ent_scanout), |
| 962 | .din({rdpctl_drq0_clear_ent_in[7:0],rdpctl_drq1_clear_ent_in[7:0]}), |
| 963 | .dout({rdpctl_drq0_clear_ent[7:0],rdpctl_drq1_clear_ent[7:0]}), |
| 964 | .l1clk(l1clk), |
| 965 | .siclk(siclk), |
| 966 | .soclk(soclk)); |
| 967 | |
| 968 | // generate data valid signals for rdata block |
| 969 | assign rdpctl_l2t0_data_valid_in = ~rdpctl_fifo_l2bank & ~rdpctl_fifo_scrub & ~rdpctl_fifo_err_xaction & |
| 970 | (~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr) & |
| 971 | rdpctl_mcu_data_valid | rdpctl0_dummy_data_valid_in; |
| 972 | assign rdpctl_l2t1_data_valid_in = rdpctl_fifo_l2bank & ~rdpctl_fifo_scrub & ~rdpctl_fifo_err_xaction & |
| 973 | (~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr) & |
| 974 | rdpctl_mcu_data_valid | rdpctl1_dummy_data_valid_in; |
| 975 | assign rdpctl_l2t_data_valid = rdpctl_l2t0_data_valid & ~rdpctl0_dummy_data_valid | |
| 976 | rdpctl_l2t1_data_valid & ~rdpctl1_dummy_data_valid; |
| 977 | |
| 978 | mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_l2t_data_valid ( |
| 979 | .scan_in(ff_l2t_data_valid_scanin), |
| 980 | .scan_out(ff_l2t_data_valid_scanout), |
| 981 | .din({rdpctl_l2t0_data_valid_in,rdpctl_l2t1_data_valid_in}), |
| 982 | .dout({rdpctl_l2t0_data_valid, rdpctl_l2t1_data_valid}), |
| 983 | .l1clk(l1clk), |
| 984 | .siclk(siclk), |
| 985 | .soclk(soclk)); |
| 986 | |
| 987 | assign rdpctl_scrub_data_valid_in = rdpctl_fifo_scrub & rdpctl_mcu_data_valid & ~rdpctl_fifo_err_xaction; |
| 988 | |
| 989 | mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_scrub_data_valid ( |
| 990 | .scan_in(ff_scrub_data_valid_scanin), |
| 991 | .scan_out(ff_scrub_data_valid_scanout), |
| 992 | .din(rdpctl_scrub_data_valid_in), |
| 993 | .dout(rdpctl_scrub_data_valid_out), |
| 994 | .l1clk(l1clk), |
| 995 | .siclk(siclk), |
| 996 | .soclk(soclk)); |
| 997 | |
| 998 | assign rdpctl_scrub_data_valid = rdpctl_scrub_data_valid_out & ~rdpctl_crc_error & ~rdpctl_crc_error_d1; |
| 999 | |
| 1000 | // generate qword id for rdata block |
| 1001 | assign rdpctl_qword_id_in = (rdpctl0_dummy_data_valid_in ? rdpctl0_rd_dummy_req_addr5 : |
| 1002 | rdpctl1_dummy_data_valid_in ? rdpctl1_rd_dummy_req_addr5 : rdpctl_fifo_qword_id) ^ rdpctl_data_cnt; |
| 1003 | mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_qword_id ( |
| 1004 | .scan_in(ff_qword_id_scanin), |
| 1005 | .scan_out(ff_qword_id_scanout), |
| 1006 | .din(rdpctl_qword_id_in), |
| 1007 | .dout(rdpctl_qword_id), |
| 1008 | .l1clk(l1clk), |
| 1009 | .siclk(siclk), |
| 1010 | .soclk(soclk)); |
| 1011 | |
| 1012 | // generate read request id for rdata block |
| 1013 | assign rdpctl_rd_req_id_in[2:0] = rdpctl0_dummy_data_valid_in ? rdpctl0_rd_dummy_req_id[2:0] : |
| 1014 | rdpctl1_dummy_data_valid_in ? rdpctl1_rd_dummy_req_id[2:0] : rdpctl_fifo_rd_req_id[2:0]; |
| 1015 | mcu_rdpctl_ctl_msff_ctl_macro__width_3 ff_rd_req_id ( |
| 1016 | .scan_in(ff_rd_req_id_scanin), |
| 1017 | .scan_out(ff_rd_req_id_scanout), |
| 1018 | .din(rdpctl_rd_req_id_in[2:0]), |
| 1019 | .dout(rdpctl_rd_req_id[2:0]), |
| 1020 | .l1clk(l1clk), |
| 1021 | .siclk(siclk), |
| 1022 | .soclk(soclk)); |
| 1023 | |
| 1024 | // generate pa error bit for rdata block |
| 1025 | assign rdpctl_pa_err_in = rdpctl0_dummy_data_valid_in ? rdpctl0_rd_dummy_addr_err : |
| 1026 | rdpctl1_dummy_data_valid_in ? rdpctl1_rd_dummy_addr_err : rdpctl_fifo_addr_pa_err; |
| 1027 | mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_pa_err ( |
| 1028 | .scan_in(ff_pa_err_scanin), |
| 1029 | .scan_out(ff_pa_err_scanout), |
| 1030 | .din(rdpctl_pa_err_in), |
| 1031 | .dout(rdpctl_pa_err), |
| 1032 | .l1clk(l1clk), |
| 1033 | .siclk(siclk), |
| 1034 | .soclk(soclk)); |
| 1035 | |
| 1036 | // CRC error - nay need to drop data going to L2 |
| 1037 | assign rdpctl_crc_err_st0 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h0); |
| 1038 | assign rdpctl_crc_err_st1 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h1) | rdpctl_crc_err_st0_d1; |
| 1039 | assign rdpctl_crc_err_st2 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h2) | rdpctl_crc_err_st1_d1; |
| 1040 | assign rdpctl_crc_err_st3 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h3) | rdpctl_crc_err_st2_d1; |
| 1041 | assign rdpctl_crc_error_in = ~rdpctl_fifo_addr_pa_err & |
| 1042 | (drif_single_channel_mode ? rdpctl_crc_err_st3 : rdpctl_crc_err_st1); |
| 1043 | |
| 1044 | mcu_rdpctl_ctl_msff_ctl_macro__width_6 ff_crc_err_dly ( |
| 1045 | .scan_in(ff_crc_err_dly_scanin), |
| 1046 | .scan_out(ff_crc_err_dly_scanout), |
| 1047 | .din({ rdpctl_crc_err_st0, rdpctl_crc_err_st1, rdpctl_crc_err_st2, rdpctl_crc_error_in, |
| 1048 | rdpctl_crc_error, drif_err_state_crc_fr}), |
| 1049 | .dout({rdpctl_crc_err_st0_d1, rdpctl_crc_err_st1_d1, rdpctl_crc_err_st2_d1, rdpctl_crc_error, |
| 1050 | rdpctl_crc_error_d1, drif_err_state_crc_fr_d1}), |
| 1051 | .l1clk(l1clk), |
| 1052 | .siclk(siclk), |
| 1053 | .soclk(soclk)); |
| 1054 | |
| 1055 | assign rdpctl_no_crc_err = rdpctl_fifo_deq & ~rdpctl_crc_error & rdpctl_fifo_err_crc; |
| 1056 | assign rdpctl_crc_err = rdpctl_fifo_deq & rdpctl_crc_error & rdpctl_fifo_err_crc; |
| 1057 | |
| 1058 | |
| 1059 | // set rdpctl_ecc_error when error occurs, clear when dequeued from rdpctl fifo; |
| 1060 | // entry will be written into error fifo in drif_ctl and error fifo's not_empty |
| 1061 | // will disable additional requests from being issued. |
| 1062 | |
| 1063 | assign readdp_ecc_multi_err_d1_in = |readdp_ecc_multi_err[1:0]; |
| 1064 | mcu_rdpctl_ctl_msff_ctl_macro__width_3 ff_mecc_errors ( |
| 1065 | .scan_in(ff_mecc_errors_scanin), |
| 1066 | .scan_out(ff_mecc_errors_scanout), |
| 1067 | .din({readdp_ecc_multi_err_d1_in,readdp_ecc_multi_err_d1,readdp_ecc_multi_err_d2}), |
| 1068 | .dout({readdp_ecc_multi_err_d1,readdp_ecc_multi_err_d2,readdp_ecc_multi_err_d3}), |
| 1069 | .l1clk(l1clk), |
| 1070 | .siclk(siclk), |
| 1071 | .soclk(soclk)); |
| 1072 | |
| 1073 | assign rdpctl_ecc_multi_err = (|readdp_ecc_multi_err[1:0]) | (|rdpctl_ecc_multi_err_d1[1:0]); |
| 1074 | |
| 1075 | //assign readdp_ecc_single_err_d1_in = |readdp_ecc_single_err[1:0]; |
| 1076 | //msff_ctl_macro ff_secc_errors (width=3) ( |
| 1077 | // .scan_in(ff_secc_errors_scanin), |
| 1078 | // .scan_out(ff_secc_errors_scanout), |
| 1079 | // .din({readdp_ecc_single_err_d1_in,readdp_ecc_single_err_d1,readdp_ecc_single_err_d2}), |
| 1080 | // .dout({readdp_ecc_single_err_d1,readdp_ecc_single_err_d2,readdp_ecc_single_err_d3}), |
| 1081 | // .l1clk(l1clk)); |
| 1082 | |
| 1083 | assign rdpctl_ecc_single_err = (|readdp_ecc_single_err[1:0]) | (|rdpctl_ecc_single_err_d1[1:0]); |
| 1084 | |
| 1085 | assign rdpctl_ecc_error = rdpctl_ecc_multi_err | rdpctl_ecc_single_err; |
| 1086 | assign rdpctl_err_type = rdpctl_ecc_multi_err; |
| 1087 | |
| 1088 | // send error retry info to drif when error occurs (if it is not already a retry) |
| 1089 | assign rdpctl_err_fifo_enq = rdpctl_fifo_deq_d1 & ((rdpctl_ecc_multi_err | rdpctl_ecc_single_err) & |
| 1090 | ~(rdpctl_fifo_err_xaction_d1 | rdpctl_crc_error_d1) | |
| 1091 | rdpctl_crc_error_d1 & ~(rdpctl_fifo_err_crc_d1 | rdpctl_fifo_err_xaction_d1)) & |
| 1092 | ~(rdpctl_pa_err | fbdic_chnl_reset_error_mode); |
| 1093 | |
| 1094 | assign rdpctl_err_fifo_data_in[13:0] = {rdpctl_crc_error, rdpctl_fifo_rank_adr,rdpctl_fifo_dimm_adr[2:0], |
| 1095 | rdpctl_fifo_bank_adr[2:0], rdpctl_fifo_addr_parity, rdpctl_fifo_scrub, |
| 1096 | rdpctl_fifo_rd_index[2:0], rdpctl_fifo_l2bank}; |
| 1097 | |
| 1098 | assign rdpctl_fifo_scrub_d1 = rdpctl_err_fifo_data[5]; |
| 1099 | assign rdpctl_fifo_rd_index_d1[2:0] = rdpctl_err_fifo_data[4:2]; |
| 1100 | assign rdpctl_fifo_l2bank_d1 = rdpctl_err_fifo_data[0]; |
| 1101 | |
| 1102 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_14 ff_err_fifo_data ( |
| 1103 | .scan_in(ff_err_fifo_data_scanin), |
| 1104 | .scan_out(ff_err_fifo_data_scanout), |
| 1105 | .din(rdpctl_err_fifo_data_in[13:0]), |
| 1106 | .dout({rdpctl_err_fifo_data[14:2],rdpctl_err_fifo_data[0]}), |
| 1107 | .en(rdpctl_fifo_deq), |
| 1108 | .l1clk(l1clk), |
| 1109 | .siclk(siclk), |
| 1110 | .soclk(soclk)); |
| 1111 | |
| 1112 | assign rdpctl_err_fifo_data[1] = ~rdpctl_crc_error; |
| 1113 | |
| 1114 | mcu_rdpctl_ctl_msff_ctl_macro__width_5 ff_fifo_deq_d1 ( |
| 1115 | .scan_in(ff_fifo_deq_d1_scanin), |
| 1116 | .scan_out(ff_fifo_deq_d1_scanout), |
| 1117 | .din({rdpctl_fifo_deq,rdpctl_fifo_err_xaction,rdpctl_fifo_err_type,rdpctl_fifo_err_xactnum, |
| 1118 | rdpctl_fifo_err_crc}), |
| 1119 | .dout({rdpctl_fifo_deq_d1,rdpctl_fifo_err_xaction_d1,rdpctl_fifo_err_type_d1,rdpctl_fifo_err_xactnum_d1, |
| 1120 | rdpctl_fifo_err_crc_d1}), |
| 1121 | .l1clk(l1clk), |
| 1122 | .siclk(siclk), |
| 1123 | .soclk(soclk)); |
| 1124 | |
| 1125 | // scrub addressing |
| 1126 | assign rdpctl_scrub_addrinc_en = rdpctl_fifo_deq_d1 & rdpctl_fifo_scrub_d1 & ~rdpctl_ecc_error & |
| 1127 | ~rdpctl_fifo_err_xaction_d1; |
| 1128 | |
| 1129 | // let drif know scrub is done so next scrub can be issued |
| 1130 | assign rdpctl_scrub_read_done = rdpctl_fifo_deq_d1 & rdpctl_fifo_scrub_d1 & |
| 1131 | ~rdpctl_fifo_err_xaction_d1; |
| 1132 | |
| 1133 | // Error type bits for error status register |
| 1134 | assign rdpctl_err_sts_reg[25:16] = {rdpctl_meu_error, rdpctl_mec_error, rdpctl_dac_error, rdpctl_dau_error, |
| 1135 | rdpctl_dsc_error, rdpctl_dsu_error, rdpctl_dbu_error, rdpctl_meb_error, |
| 1136 | rdpctl_fbu_error, rdpctl_fbr_error}; |
| 1137 | /////// |
| 1138 | // Multiple uncorrected errors |
| 1139 | // If s/w write and error occurs in same cycle, h/w update has priority. |
| 1140 | /////// |
| 1141 | |
| 1142 | assign rdpctl_meu_error_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & ~rdpctl_pa_err & |
| 1143 | ((rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_multi_err[1:0]) | |
| 1144 | (&readdp_ecc_multi_err[1:0])) | |
| 1145 | (rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & |
| 1146 | (drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc | |
| 1147 | fbdic_err_unrecov | fbdic_chnl_reset_error) | |
| 1148 | drif_err_sts_reg_ld; |
| 1149 | assign rdpctl_meu_error_in = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & ~rdpctl_pa_err & |
| 1150 | ((rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_multi_err[1:0]) | |
| 1151 | (&readdp_ecc_multi_err[1:0])) | |
| 1152 | (rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & |
| 1153 | (drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc | |
| 1154 | fbdic_err_unrecov | fbdic_chnl_reset_error) ? 1'b1 : |
| 1155 | ~drif_ucb_data_63to54[63] & rdpctl_meu_error; |
| 1156 | |
| 1157 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit63 ( // FS:wmr_protect |
| 1158 | .scan_in(pff_err_sts_bit63_wmr_scanin), |
| 1159 | .scan_out(pff_err_sts_bit63_wmr_scanout), |
| 1160 | .siclk(aclk_wmr), |
| 1161 | .din(rdpctl_meu_error_in), |
| 1162 | .dout(rdpctl_meu_error), |
| 1163 | .en(rdpctl_meu_error_en), |
| 1164 | .l1clk(l1clk), |
| 1165 | .soclk(soclk)); |
| 1166 | |
| 1167 | /////// |
| 1168 | // Multiple corrected errors |
| 1169 | /////// |
| 1170 | |
| 1171 | assign rdpctl_mec_error_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & |
| 1172 | ((rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error | |
| 1173 | rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_single_err[1:0]) | |
| 1174 | (&readdp_ecc_single_err[1:0]) | |
| 1175 | (|readdp_ecc_single_err[1:0]) & (|readdp_ecc_multi_err[1:0])) | |
| 1176 | (rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error | |
| 1177 | rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & |
| 1178 | (rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov) | |
| 1179 | drif_err_sts_reg_ld; |
| 1180 | assign rdpctl_mec_error_in = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & |
| 1181 | ((rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error | |
| 1182 | rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_single_err[1:0]) | |
| 1183 | (&readdp_ecc_single_err[1:0]) | |
| 1184 | (|readdp_ecc_single_err[1:0]) & (|readdp_ecc_multi_err[1:0])) | |
| 1185 | (rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error | |
| 1186 | rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & |
| 1187 | (rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov) ? 1'b1 : |
| 1188 | ~drif_ucb_data_63to54[62] & rdpctl_mec_error; |
| 1189 | |
| 1190 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit62 ( // FS:wmr_protect |
| 1191 | .scan_in(pff_err_sts_bit62_wmr_scanin), |
| 1192 | .scan_out(pff_err_sts_bit62_wmr_scanout), |
| 1193 | .siclk(aclk_wmr), |
| 1194 | .din(rdpctl_mec_error_in), |
| 1195 | .dout(rdpctl_mec_error), |
| 1196 | .en(rdpctl_mec_error_en), |
| 1197 | .l1clk(l1clk), |
| 1198 | .soclk(soclk)); |
| 1199 | |
| 1200 | /////// |
| 1201 | // DRAM access correctable error |
| 1202 | /////// |
| 1203 | assign rdpctl_dac_error_en = rdpctl_l2t_data_valid & ~rdpctl_dac_error & (|readdp_ecc_single_err[1:0]) | |
| 1204 | drif_err_sts_reg_ld; |
| 1205 | assign rdpctl_dac_error_in = rdpctl_l2t_data_valid & ~rdpctl_dac_error & (|readdp_ecc_single_err[1:0]) ? 1'b1 : |
| 1206 | ~drif_ucb_data_63to54[61] & rdpctl_dac_error; |
| 1207 | |
| 1208 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit61 ( // FS:wmr_protect |
| 1209 | .scan_in(pff_err_sts_bit61_wmr_scanin), |
| 1210 | .scan_out(pff_err_sts_bit61_wmr_scanout), |
| 1211 | .siclk(aclk_wmr), |
| 1212 | .din(rdpctl_dac_error_in), |
| 1213 | .dout(rdpctl_dac_error), |
| 1214 | .en(rdpctl_dac_error_en), |
| 1215 | .l1clk(l1clk), |
| 1216 | .soclk(soclk)); |
| 1217 | |
| 1218 | /////// |
| 1219 | // DRAM access uncorrectable error |
| 1220 | /////// |
| 1221 | |
| 1222 | assign rdpctl_dau_error_en = rdpctl_l2t_data_valid & ~rdpctl_dau_error & (|readdp_ecc_multi_err[1:0]) & |
| 1223 | ~rdpctl_pa_err & ~rdpctl_fbd_unrecov_err[0] | drif_err_sts_reg_ld; |
| 1224 | assign rdpctl_dau_error_in = rdpctl_l2t_data_valid & ~rdpctl_dau_error & (|readdp_ecc_multi_err[1:0]) & |
| 1225 | ~rdpctl_pa_err & ~rdpctl_fbd_unrecov_err[0] ? 1'b1 : |
| 1226 | ~drif_ucb_data_63to54[60] & rdpctl_dau_error; |
| 1227 | |
| 1228 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit60 ( // FS:wmr_protect |
| 1229 | .scan_in(pff_err_sts_bit60_wmr_scanin), |
| 1230 | .scan_out(pff_err_sts_bit60_wmr_scanout), |
| 1231 | .siclk(aclk_wmr), |
| 1232 | .din(rdpctl_dau_error_in), |
| 1233 | .dout(rdpctl_dau_error), |
| 1234 | .en(rdpctl_dau_error_en), |
| 1235 | .l1clk(l1clk), |
| 1236 | .soclk(soclk)); |
| 1237 | |
| 1238 | /////// |
| 1239 | // Scrub access correctable error |
| 1240 | /////// |
| 1241 | assign rdpctl_dsc_error_en = rdpctl_scrub_data_valid & ~rdpctl_dsc_error & (|readdp_ecc_single_err[1:0]) | drif_err_sts_reg_ld; |
| 1242 | assign rdpctl_dsc_error_in = rdpctl_scrub_data_valid & ~rdpctl_dsc_error & (|readdp_ecc_single_err[1:0]) ? |
| 1243 | 1'b1 : ~drif_ucb_data_63to54[59] & rdpctl_dsc_error; |
| 1244 | |
| 1245 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit59 ( // FS:wmr_protect |
| 1246 | .scan_in(pff_err_sts_bit59_wmr_scanin), |
| 1247 | .scan_out(pff_err_sts_bit59_wmr_scanout), |
| 1248 | .siclk(aclk_wmr), |
| 1249 | .din(rdpctl_dsc_error_in), |
| 1250 | .dout(rdpctl_dsc_error), |
| 1251 | .en(rdpctl_dsc_error_en), |
| 1252 | .l1clk(l1clk), |
| 1253 | .soclk(soclk)); |
| 1254 | |
| 1255 | /////// |
| 1256 | // Scrub access uncorrectable error |
| 1257 | /////// |
| 1258 | |
| 1259 | assign rdpctl_dsu_error_en = rdpctl_scrub_data_valid & ~rdpctl_dsu_error & (|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err | |
| 1260 | drif_err_sts_reg_ld; |
| 1261 | assign rdpctl_dsu_error_in = rdpctl_scrub_data_valid & ~rdpctl_dsu_error & (|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err ? |
| 1262 | 1'b1 : ~drif_ucb_data_63to54[58] & rdpctl_dsu_error; |
| 1263 | |
| 1264 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit58 ( // FS:wmr_protect |
| 1265 | .scan_in(pff_err_sts_bit58_wmr_scanin), |
| 1266 | .scan_out(pff_err_sts_bit58_wmr_scanout), |
| 1267 | .siclk(aclk_wmr), |
| 1268 | .din(rdpctl_dsu_error_in), |
| 1269 | .dout(rdpctl_dsu_error), |
| 1270 | .en(rdpctl_dsu_error_en), |
| 1271 | .l1clk(l1clk), |
| 1272 | .soclk(soclk)); |
| 1273 | |
| 1274 | /////// |
| 1275 | // OUT of BOUND PA error |
| 1276 | /////// |
| 1277 | assign rdpctl_dummy_dbu = ~rdpctl0_dummy_data_valid_in & rdpctl0_dummy_data_valid & rdpctl0_rd_dummy_addr_err | |
| 1278 | ~rdpctl1_dummy_data_valid_in & rdpctl1_dummy_data_valid & rdpctl1_rd_dummy_addr_err; |
| 1279 | |
| 1280 | assign rdpctl_dbu_error_en = rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu | drif_err_sts_reg_ld; |
| 1281 | assign rdpctl_dbu_error_in = rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu ? 1'b1 : |
| 1282 | ~drif_ucb_data_63to54[57] & rdpctl_dbu_error; |
| 1283 | |
| 1284 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit57 ( // FS:wmr_protect |
| 1285 | .scan_in(pff_err_sts_bit57_wmr_scanin), |
| 1286 | .scan_out(pff_err_sts_bit57_wmr_scanout), |
| 1287 | .siclk(aclk_wmr), |
| 1288 | .din(rdpctl_dbu_error_in), |
| 1289 | .dout(rdpctl_dbu_error), |
| 1290 | .en(rdpctl_dbu_error_en), |
| 1291 | .l1clk(l1clk), |
| 1292 | .soclk(soclk)); |
| 1293 | |
| 1294 | /////// |
| 1295 | // Multiple out of bound PA error |
| 1296 | /////// |
| 1297 | assign rdpctl_meb_error_en = (rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu) & rdpctl_dbu_error | |
| 1298 | drif_err_sts_reg_ld; |
| 1299 | assign rdpctl_meb_error_in = (rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu) & rdpctl_dbu_error ? 1'b1 : |
| 1300 | ~drif_ucb_data_63to54[56] & rdpctl_meb_error; |
| 1301 | |
| 1302 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit56 ( // FS:wmr_protect |
| 1303 | .scan_in(pff_err_sts_bit56_wmr_scanin), |
| 1304 | .scan_out(pff_err_sts_bit56_wmr_scanout), |
| 1305 | .siclk(aclk_wmr), |
| 1306 | .din(rdpctl_meb_error_in), |
| 1307 | .dout(rdpctl_meb_error), |
| 1308 | .en(rdpctl_meb_error_en), |
| 1309 | .l1clk(l1clk), |
| 1310 | .soclk(soclk)); |
| 1311 | |
| 1312 | /////// |
| 1313 | // FBU |
| 1314 | /////// |
| 1315 | assign rdpctl_fbu_error_en = drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc | |
| 1316 | fbdic_err_unrecov | fbdic_chnl_reset_error | drif_err_sts_reg_ld; |
| 1317 | assign rdpctl_fbu_error_in = drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc | |
| 1318 | fbdic_err_unrecov | fbdic_chnl_reset_error ? 1'b1 : |
| 1319 | rdpctl_fbu_error & ~drif_ucb_data_63to54[55]; |
| 1320 | |
| 1321 | mcu_rdpctl_ctl_msff_ctl_macro__en_1 pff_err_sts_bit55 ( // FS:wmr_protect |
| 1322 | .scan_in(pff_err_sts_bit55_wmr_scanin), |
| 1323 | .scan_out(pff_err_sts_bit55_wmr_scanout), |
| 1324 | .siclk(aclk_wmr), |
| 1325 | .din(rdpctl_fbu_error_in), |
| 1326 | .dout(rdpctl_fbu_error), |
| 1327 | .en(rdpctl_fbu_error_en), |
| 1328 | .l1clk(l1clk), |
| 1329 | .soclk(soclk)); |
| 1330 | |
| 1331 | // Unrecoverable error signals to RDATA: [0] => mecc_err, [1] => scb_mecc_err |
| 1332 | assign rdpctl_fbd_unrecov_err[0] = rdpctl_crc_unrecov_err; |
| 1333 | |
| 1334 | mcu_rdpctl_ctl_msff_ctl_macro ff_fbd_unrecov_err ( |
| 1335 | .scan_in(ff_fbd_unrecov_err_scanin), |
| 1336 | .scan_out(ff_fbd_unrecov_err_scanout), |
| 1337 | .din(rdpctl_fbd_unrecov_err_1_in), |
| 1338 | .dout(rdpctl_fbd_unrecov_err[1]), |
| 1339 | .l1clk(l1clk), |
| 1340 | .siclk(siclk), |
| 1341 | .soclk(soclk)); |
| 1342 | |
| 1343 | assign rdpctl_fbd_unrecov_err_1_in = fbdic_err_unrecov | fbdic_chnl_reset_error | |
| 1344 | drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc & rdpctl_fifo_scrub; |
| 1345 | |
| 1346 | // Report CRC unrecoverable error back to FBDIC for MCU Syndrome Register |
| 1347 | assign rdpctl_crc_unrecov_err_in = drif_err_state_crc_fr & (rdpctl_crc_error | rdpctl_crc_error_in) | |
| 1348 | fbdic_chnl_reset_error_mode; |
| 1349 | |
| 1350 | mcu_rdpctl_ctl_msff_ctl_macro ff_crc_unrecov_err ( |
| 1351 | .scan_in(ff_crc_unrecov_err_scanin), |
| 1352 | .scan_out(ff_crc_unrecov_err_scanout), |
| 1353 | .din(rdpctl_crc_unrecov_err_in), |
| 1354 | .dout(rdpctl_crc_unrecov_err), |
| 1355 | .l1clk(l1clk), |
| 1356 | .siclk(siclk), |
| 1357 | .soclk(soclk)); |
| 1358 | |
| 1359 | /////// |
| 1360 | // FBR |
| 1361 | /////// |
| 1362 | assign rdpctl_fbr_error_en = rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov | drif_err_sts_reg_ld; |
| 1363 | assign rdpctl_fbr_error_in = rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov ? 1'b1 : |
| 1364 | rdpctl_fbr_error & ~drif_ucb_data_63to54[54]; |
| 1365 | |
| 1366 | mcu_rdpctl_ctl_msff_ctl_macro__en_1 pff_err_sts_bit54 ( // FS:wmr_protect |
| 1367 | .scan_in(pff_err_sts_bit54_wmr_scanin), |
| 1368 | .scan_out(pff_err_sts_bit54_wmr_scanout), |
| 1369 | .siclk(aclk_wmr), |
| 1370 | .din(rdpctl_fbr_error_in), |
| 1371 | .dout(rdpctl_fbr_error), |
| 1372 | .en(rdpctl_fbr_error_en), |
| 1373 | .l1clk(l1clk), |
| 1374 | .soclk(soclk)); |
| 1375 | |
| 1376 | // Report recoverable errors to RDATA |
| 1377 | assign rdpctl_fbd0_recov_err_in = (rdpctl_no_crc_err & rdpctl_fifo_err_crc & ~rdpctl_fifo_l2bank | fbdic_err_recov) & |
| 1378 | ~fbdic_chnl_reset_error_mode; |
| 1379 | assign rdpctl_fbd1_recov_err_in = rdpctl_no_crc_err & rdpctl_fifo_err_crc & rdpctl_fifo_l2bank & |
| 1380 | ~fbdic_chnl_reset_error_mode; |
| 1381 | |
| 1382 | mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_fbd_recov_err ( |
| 1383 | .scan_in(ff_fbd_recov_err_scanin), |
| 1384 | .scan_out(ff_fbd_recov_err_scanout), |
| 1385 | .din({rdpctl_fbd0_recov_err_in,rdpctl_fbd1_recov_err_in}), |
| 1386 | .dout({rdpctl_fbd0_recov_err,rdpctl_fbd1_recov_err}), |
| 1387 | .l1clk(l1clk), |
| 1388 | .siclk(siclk), |
| 1389 | .soclk(soclk)); |
| 1390 | |
| 1391 | // Report CRC recoverable errors to FBDIC for MCU Syndrome Register |
| 1392 | assign rdpctl_crc_recov_err_in = rdpctl_no_crc_err & rdpctl_fifo_err_crc & ~fbdic_chnl_reset_error_mode; |
| 1393 | mcu_rdpctl_ctl_msff_ctl_macro ff_crc_recov_err ( |
| 1394 | .scan_in(ff_crc_recov_err_scanin), |
| 1395 | .scan_out(ff_crc_recov_err_scanout), |
| 1396 | .din(rdpctl_crc_recov_err_in), |
| 1397 | .dout(rdpctl_crc_recov_err_out), |
| 1398 | .l1clk(l1clk), |
| 1399 | .siclk(siclk), |
| 1400 | .soclk(soclk)); |
| 1401 | |
| 1402 | assign rdpctl_crc_recov_err = rdpctl_crc_recov_err_out | fbdic_cfgrd_crc_error; |
| 1403 | |
| 1404 | // stage error syndrome with error signals to capture in error status register |
| 1405 | |
| 1406 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_32 ff_ecc_d1 ( |
| 1407 | .scan_in(ff_ecc_d1_scanin), |
| 1408 | .scan_out(ff_ecc_d1_scanout), |
| 1409 | .din({readdp0_syndrome[15:0],readdp1_syndrome[15:0]}), |
| 1410 | .dout({rdpctl0_syndrome[15:0],rdpctl1_syndrome[15:0]}), |
| 1411 | .en(rdpctl_rddata_en[2]), |
| 1412 | .l1clk(l1clk), |
| 1413 | .siclk(siclk), |
| 1414 | .soclk(soclk)); |
| 1415 | |
| 1416 | // set it only if there is no prior uncorrectable error and a new uncorrectable one happens |
| 1417 | // OR no prior uncorrectable and no prior correctable and new correctable happens |
| 1418 | |
| 1419 | assign rdpctl_err_sts_reg_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & |
| 1420 | ((~rdpctl_dau_error & ~rdpctl_dsu_error & (|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err) | |
| 1421 | (~rdpctl_dau_error & ~rdpctl_dsu_error & ~rdpctl_dac_error & ~rdpctl_dsc_error & (|readdp_ecc_single_err[1:0]))) | |
| 1422 | drif_err_sts_reg_ld; |
| 1423 | assign rdpctl_err_sts_reg_in[15:0] = rdpctl_scrub_data_valid | rdpctl_l2t_data_valid & ~rdpctl_dau_error & ~rdpctl_dsu_error ? |
| 1424 | (readdp_ecc_multi_err[0] & ~rdpctl_pa_err ? rdpctl0_syndrome[15:0] : |
| 1425 | readdp_ecc_multi_err[1] & ~rdpctl_pa_err ? rdpctl1_syndrome[15:0] : |
| 1426 | ~rdpctl_dac_error & ~rdpctl_dsc_error & readdp_ecc_single_err[0] ? rdpctl0_syndrome[15:0] : |
| 1427 | ~rdpctl_dac_error & ~rdpctl_dsc_error & readdp_ecc_single_err[1] ? rdpctl1_syndrome[15:0] : drif_ucb_data_39to0[15:0]) : |
| 1428 | drif_ucb_data_39to0[15:0]; |
| 1429 | |
| 1430 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_16 pff_err_syn ( // FS:wmr_protect |
| 1431 | .scan_in(pff_err_syn_wmr_scanin), |
| 1432 | .scan_out(pff_err_syn_wmr_scanout), |
| 1433 | .siclk(aclk_wmr), |
| 1434 | .din(rdpctl_err_sts_reg_in[15:0]), |
| 1435 | .dout(rdpctl_err_sts_reg[15:0]), |
| 1436 | .en(rdpctl_err_sts_reg_en), |
| 1437 | .l1clk(l1clk), |
| 1438 | .soclk(soclk)); |
| 1439 | |
| 1440 | ////////////////////////////////////// |
| 1441 | // DRAM ERROR RETRY REGISTER |
| 1442 | ////////////////////////////////////// |
| 1443 | assign rdpctl_err_retry_ld_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & |
| 1444 | ((|readdp_ecc_single_err[1:0]) & ~rdpctl_dsc_error & ~rdpctl_dac_error | |
| 1445 | (|readdp_ecc_multi_err[1:0])) & ~rdpctl_dsu_error & ~rdpctl_dau_error; |
| 1446 | assign rdpctl_err_retry_ld_clr = rdpctl_fifo_deq_d1; |
| 1447 | |
| 1448 | mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1 ff_err_retry_ld ( |
| 1449 | .scan_in(ff_err_retry_ld_scanin), |
| 1450 | .scan_out(ff_err_retry_ld_scanout), |
| 1451 | .din(1'b1), |
| 1452 | .dout(rdpctl_err_retry_ld_out), |
| 1453 | .en(rdpctl_err_retry_ld_en), |
| 1454 | .clr(rdpctl_err_retry_ld_clr), |
| 1455 | .l1clk(l1clk), |
| 1456 | .siclk(siclk), |
| 1457 | .soclk(soclk)); |
| 1458 | |
| 1459 | assign rdpctl_err_retry_ld = rdpctl_err_retry_ld_out | rdpctl_err_retry_ld_en; |
| 1460 | |
| 1461 | assign rdpctl_err_retry_reg[36:0] = {rdpctl_retry_reg_valid, rdpctl_err_retry2_reg[17:0],rdpctl_err_retry1_reg[17:0]}; |
| 1462 | |
| 1463 | // Retry status for first retry read |
| 1464 | assign rdpctl_err_retry1_reg_en = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & ~rdpctl_fifo_err_xactnum_d1 & |
| 1465 | rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid | drif_err_retry_reg_ld; |
| 1466 | assign rdpctl_err_retry1_reg_in[1:0] = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & ~rdpctl_fifo_err_xactnum_d1 & |
| 1467 | rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid ? |
| 1468 | {rdpctl_ecc_error, rdpctl_err_type & rdpctl_ecc_error | ~rdpctl_ecc_error} : |
| 1469 | drif_ucb_data_39to0[1:0]; |
| 1470 | |
| 1471 | assign rdpctl_err_retry1_reg_in[17:2] = rdpctl_retry_syndrome[15:0]; |
| 1472 | |
| 1473 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_18 pff_err_retry1 ( // FS:wmr_protect |
| 1474 | .scan_in(pff_err_retry1_wmr_scanin), |
| 1475 | .scan_out(pff_err_retry1_wmr_scanout), |
| 1476 | .siclk(aclk_wmr), |
| 1477 | .din(rdpctl_err_retry1_reg_in[17:0]), |
| 1478 | .dout(rdpctl_err_retry1_reg[17:0]), |
| 1479 | .en(rdpctl_err_retry1_reg_en), |
| 1480 | .l1clk(l1clk), |
| 1481 | .soclk(soclk)); |
| 1482 | |
| 1483 | // Retry status for second retry read |
| 1484 | assign rdpctl_err_retry2_reg_en = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & rdpctl_fifo_err_xactnum_d1 & |
| 1485 | rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid | drif_err_retry_reg_ld; |
| 1486 | assign rdpctl_err_retry2_reg_in[1:0] = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & rdpctl_fifo_err_xactnum_d1 & |
| 1487 | rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid ? |
| 1488 | {rdpctl_ecc_error, rdpctl_err_type & rdpctl_ecc_error | ~rdpctl_ecc_error} : |
| 1489 | drif_ucb_data_39to0[19:18]; |
| 1490 | |
| 1491 | assign rdpctl_err_retry2_reg_in[17:2] = rdpctl_retry_syndrome[15:0]; |
| 1492 | |
| 1493 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_18 pff_err_retry2 ( // FS:wmr_protect |
| 1494 | .scan_in(pff_err_retry2_wmr_scanin), |
| 1495 | .scan_out(pff_err_retry2_wmr_scanout), |
| 1496 | .siclk(aclk_wmr), |
| 1497 | .din(rdpctl_err_retry2_reg_in[17:0]), |
| 1498 | .dout(rdpctl_err_retry2_reg[17:0]), |
| 1499 | .en(rdpctl_err_retry2_reg_en), |
| 1500 | .l1clk(l1clk), |
| 1501 | .soclk(soclk)); |
| 1502 | |
| 1503 | |
| 1504 | assign rdpctl_err_retry2_reg_en_no_ld = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & rdpctl_fifo_err_xactnum_d1 & |
| 1505 | rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid; |
| 1506 | assign rdpctl_err_retry1_reg_en_no_ld = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & ~rdpctl_fifo_err_xactnum_d1 & |
| 1507 | rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid; |
| 1508 | assign rdpctl_retry_reg_valid_in = rdpctl_retry_reg_valid & (~drif_err_retry_reg_ld | drif_ucb_data_39to0[36]) | |
| 1509 | rdpctl_err_retry2_reg_en_no_ld | |
| 1510 | rdpctl_err_retry1_reg_en_no_ld & (rdpctl_err_retry1_reg_in[1:0] == 2'h3) | |
| 1511 | drif_err_retry_reg_ld & drif_ucb_data_39to0[36]; |
| 1512 | assign rdpctl_retry_reg_valid_en = 1'b1; |
| 1513 | |
| 1514 | mcu_rdpctl_ctl_msff_ctl_macro__en_1 pff_retry_reg_valid ( // FS:wmr_protect |
| 1515 | .scan_in(pff_retry_reg_valid_wmr_scanin), |
| 1516 | .scan_out(pff_retry_reg_valid_wmr_scanout), |
| 1517 | .siclk(aclk_wmr), |
| 1518 | .din(rdpctl_retry_reg_valid_in), |
| 1519 | .dout(rdpctl_retry_reg_valid), |
| 1520 | .en(rdpctl_retry_reg_valid_en), |
| 1521 | .l1clk(l1clk), |
| 1522 | .soclk(soclk)); |
| 1523 | |
| 1524 | assign rdpctl_syndrome_dly_en = ~drif_single_channel_mode | drif_single_channel_mode & rdpctl_rddata_en[2]; |
| 1525 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 ff_syndrome_dly ( |
| 1526 | .scan_in(ff_syndrome_dly_scanin), |
| 1527 | .scan_out(ff_syndrome_dly_scanout), |
| 1528 | .din({rdpctl0_syndrome[15:0],rdpctl1_syndrome[15:0],readdp_ecc_single_err[1:0],readdp_ecc_multi_err[1:0]}), |
| 1529 | .dout({rdpctl0_syndrome_d1[15:0],rdpctl1_syndrome_d1[15:0], |
| 1530 | rdpctl_ecc_single_err_d1[1:0],rdpctl_ecc_multi_err_d1[1:0]}), |
| 1531 | .en(1'b1), |
| 1532 | .l1clk(l1clk), |
| 1533 | .siclk(siclk), |
| 1534 | .soclk(soclk)); |
| 1535 | |
| 1536 | assign rdpctl_retry_syndrome[15:0] = rdpctl_ecc_multi_err_d1[0] ? rdpctl0_syndrome_d1[15:0] : |
| 1537 | rdpctl_ecc_multi_err_d1[1] ? rdpctl1_syndrome_d1[15:0] : |
| 1538 | readdp_ecc_multi_err[0] ? rdpctl0_syndrome[15:0] : |
| 1539 | readdp_ecc_multi_err[1] ? rdpctl1_syndrome[15:0] : |
| 1540 | rdpctl_ecc_single_err_d1[0] ? rdpctl0_syndrome_d1[15:0] : |
| 1541 | rdpctl_ecc_single_err_d1[1] ? rdpctl1_syndrome_d1[15:0] : |
| 1542 | readdp_ecc_single_err[0] ? rdpctl0_syndrome[15:0] : |
| 1543 | rdpctl1_syndrome[15:0]; |
| 1544 | |
| 1545 | ////////////////////////////////////// |
| 1546 | // DRAM ERROR ADDRESS REGISTER |
| 1547 | ////////////////////////////////////// |
| 1548 | // This address reg can only have scrub address as load address is not kept. |
| 1549 | assign rdpctl_err_addr_reg_en = rdpctl_scrub_data_valid & ((|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err | |
| 1550 | (|readdp_ecc_single_err[1:0])) & ~rdpctl_dsc_error & ~rdpctl_dsu_error | drif_err_addr_reg_ld; |
| 1551 | assign rdpctl_err_addr_reg_in[35:0] = rdpctl_scrub_data_valid & ((|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err | |
| 1552 | (|readdp_ecc_single_err[1:0])) & ~rdpctl_dsc_error & ~rdpctl_dsu_error ? rdpctl_err_addr[35:0] : |
| 1553 | drif_ucb_data_39to0[39:4]; |
| 1554 | |
| 1555 | assign rdpctl_err_addr[35:0] = rdpctl_pm_1mcu ? {2'h0, drif_scrub_addr[31:1], drif_scrub_addr[0], rdpctl_scrub_data_cnt[1:0]} : |
| 1556 | rdpctl_pm_2mcu ? {1'b0, drif_scrub_addr[31:1], mcu_id[0], drif_scrub_addr[0], rdpctl_scrub_data_cnt[1:0]} : |
| 1557 | {drif_scrub_addr[31:1], mcu_id[1:0], drif_scrub_addr[0], rdpctl_scrub_data_cnt[1:0]}; |
| 1558 | |
| 1559 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 pff_err_addr_reg ( // FS:wmr_protect |
| 1560 | .scan_in(pff_err_addr_reg_wmr_scanin), |
| 1561 | .scan_out(pff_err_addr_reg_wmr_scanout), |
| 1562 | .siclk(aclk_wmr), |
| 1563 | .din(rdpctl_err_addr_reg_in[35:0]), |
| 1564 | .dout(rdpctl_err_addr_reg[35:0]), |
| 1565 | .en(rdpctl_err_addr_reg_en), |
| 1566 | .l1clk(l1clk), |
| 1567 | .soclk(soclk)); |
| 1568 | |
| 1569 | assign rdpctl_scrub_data_cnt[0] = readdp_ecc_multi_err[0] | readdp_ecc_single_err[0] & ~readdp_ecc_multi_err[1]; |
| 1570 | |
| 1571 | assign rdpctl_scrub_data_cnt_in[1] = ~rdpctl_scrub_data_cnt[1]; |
| 1572 | assign rdpctl_scrub_data_cnt_en = rdpctl_scrub_data_valid; |
| 1573 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 ff_scrub_data_cnt ( |
| 1574 | .scan_in(ff_scrub_data_cnt_scanin), |
| 1575 | .scan_out(ff_scrub_data_cnt_scanout), |
| 1576 | .din(rdpctl_scrub_data_cnt_in[1]), |
| 1577 | .dout(rdpctl_scrub_data_cnt[1]), |
| 1578 | .en(rdpctl_scrub_data_cnt_en), |
| 1579 | .l1clk(l1clk), |
| 1580 | .siclk(siclk), |
| 1581 | .soclk(soclk)); |
| 1582 | |
| 1583 | //////////////////////////////////////// |
| 1584 | // SECC ERROR COUNTER - for generating interrupts and debug triggers to NCU |
| 1585 | //////////////////////////////////////// |
| 1586 | |
| 1587 | assign rdpctl_err_cnt[15:0] = rdpctl_secc_cnt[15:0]; |
| 1588 | |
| 1589 | // interrupt enable bit |
| 1590 | assign rdpctl_secc_int_en = drif_err_cnt_reg_ld | rdpctl_secc_cnt_intr_in; |
| 1591 | assign rdpctl_secc_int_in = rdpctl_secc_cnt_intr_in ? 1'b0 : (|drif_ucb_data_39to0[15:0]); |
| 1592 | |
| 1593 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_secc_int_en ( // FS:wmr_protect |
| 1594 | .scan_in(pff_secc_int_en_wmr_scanin), |
| 1595 | .scan_out(pff_secc_int_en_wmr_scanout), |
| 1596 | .siclk(aclk_wmr), |
| 1597 | .din(rdpctl_secc_int_in), |
| 1598 | .dout(rdpctl_secc_int_enabled), |
| 1599 | .en(rdpctl_secc_int_en), |
| 1600 | .l1clk(l1clk), |
| 1601 | .soclk(soclk)); |
| 1602 | |
| 1603 | // counter value |
| 1604 | assign rdpctl_secc_cnt_en = drif_err_cnt_reg_ld | (|readdp_ecc_single_err[1:0]) & rdpctl_secc_int_enabled & |
| 1605 | (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid); |
| 1606 | |
| 1607 | assign rdpctl_secc_cnt_next[15:0] = (rdpctl_secc_cnt[15:0] == 16'h0) ? 16'h0 : rdpctl_secc_cnt[15:0] - 16'h1; |
| 1608 | |
| 1609 | assign rdpctl_secc_cnt_in[15:0] = (|readdp_ecc_single_err[1:0]) & rdpctl_secc_int_enabled & (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) ? |
| 1610 | rdpctl_secc_cnt_next[15:0] : drif_ucb_data_39to0[15:0]; |
| 1611 | |
| 1612 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_16 pff_secc_cnt ( // FS:wmr_protect |
| 1613 | .scan_in(pff_secc_cnt_wmr_scanin), |
| 1614 | .scan_out(pff_secc_cnt_wmr_scanout), |
| 1615 | .siclk(aclk_wmr), |
| 1616 | .din(rdpctl_secc_cnt_in[15:0]), |
| 1617 | .dout(rdpctl_secc_cnt[15:0]), |
| 1618 | .en(rdpctl_secc_cnt_en), |
| 1619 | .l1clk(l1clk), |
| 1620 | .soclk(soclk)); |
| 1621 | |
| 1622 | assign rdpctl_secc_cnt_intr_in = rdpctl_secc_int_enabled & ~(|rdpctl_secc_cnt[15:0]); |
| 1623 | |
| 1624 | mcu_rdpctl_ctl_msff_ctl_macro ff_secc_cnt_intr ( |
| 1625 | .scan_in(ff_secc_cnt_intr_scanin), |
| 1626 | .scan_out(ff_secc_cnt_intr_scanout), |
| 1627 | .din(rdpctl_secc_cnt_intr_in), |
| 1628 | .dout(rdpctl_secc_cnt_intr), |
| 1629 | .l1clk(l1clk), |
| 1630 | .siclk(siclk), |
| 1631 | .soclk(soclk)); |
| 1632 | |
| 1633 | //////////////////////////////////////// |
| 1634 | // SECC DEBUG TRIGGER ENABLE REGISTER |
| 1635 | //////////////////////////////////////// |
| 1636 | |
| 1637 | assign rdpctl_dbg_trig_enable_in[5:1] = drif_ucb_data_39to0[5:1]; |
| 1638 | |
| 1639 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 pff_dbg_trig ( // FS:wmr_protect |
| 1640 | .scan_in(pff_dbg_trig_wmr_scanin), |
| 1641 | .scan_out(pff_dbg_trig_wmr_scanout), |
| 1642 | .siclk(aclk_wmr), |
| 1643 | .din(rdpctl_dbg_trig_enable_in[5:1]), |
| 1644 | .dout({rdpctl_dtm_atspeed, rdpctl_dtm_mask_chnl[1:0], rdpctl_dbg_trig_enable, rdpctl_mask_err}), |
| 1645 | .en(drif_dbg_trig_reg_ld), |
| 1646 | .l1clk(l1clk), |
| 1647 | .soclk(soclk)); |
| 1648 | |
| 1649 | assign rdpctl_dtm_chnl_enable[1:0] = {2{fbdic_serdes_dtm}} & (~rdpctl_dtm_mask_chnl[1:0]); |
| 1650 | |
| 1651 | //////////////////////////////////////// |
| 1652 | // SECC ERROR LOCATION |
| 1653 | // The interpretation of the parity is as following ecc[15:0] = {p0,p1,p2,p3} where p3 is not used |
| 1654 | // failover mode. |
| 1655 | // The error location is as = {err_in_p3, err_in_p2, ... err_in_d2, err_in_d1, err_in_d0} |
| 1656 | // If the error location bit is 1, and to create mask in failover mode set all the bits left of 1 to 1 |
| 1657 | // (including the bit 1 set in err location) upto bit location 34. |
| 1658 | // Also this error location once logged will not be over written when another error occurs till S/W |
| 1659 | // resets the appropriate bit in the error status register. |
| 1660 | //////////////////////////////////////// |
| 1661 | |
| 1662 | assign rdpctl_secc_loc_en = (|readdp_ecc_single_err[1:0]) & (rdpctl_scrub_data_valid & ~rdpctl_dsc_error | |
| 1663 | rdpctl_l2t_data_valid & ~rdpctl_dac_error) | |
| 1664 | drif_err_loc_reg_ld; |
| 1665 | assign rdpctl_err_loc_in[35:0] = readdp_ecc_single_err[1] & (rdpctl_scrub_data_valid & ~rdpctl_dsc_error | |
| 1666 | rdpctl_l2t_data_valid & ~rdpctl_dac_error) ? rdpctl1_ecc_loc[35:0] : |
| 1667 | readdp_ecc_single_err[0] & (rdpctl_scrub_data_valid & ~rdpctl_dsc_error | |
| 1668 | rdpctl_l2t_data_valid & ~rdpctl_dac_error) ? rdpctl0_ecc_loc[35:0] : drif_ucb_data_39to0[35:0]; |
| 1669 | |
| 1670 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 pff_err_loc ( // FS:wmr_protect |
| 1671 | .scan_in(pff_err_loc_wmr_scanin), |
| 1672 | .scan_out(pff_err_loc_wmr_scanout), |
| 1673 | .siclk(aclk_wmr), |
| 1674 | .din(rdpctl_err_loc_in[35:0]), |
| 1675 | .dout(rdpctl_err_loc[35:0]), |
| 1676 | .en(rdpctl_secc_loc_en), |
| 1677 | .l1clk(l1clk), |
| 1678 | .soclk(soclk)); |
| 1679 | |
| 1680 | //////////////////////////////////////// |
| 1681 | // Scrub valid signals to rdata |
| 1682 | //////////////////////////////////////// |
| 1683 | assign rdpctl_scrb0_err_valid_in = rdpctl_mcu_data_valid & rdpctl_fifo_scrub & ~drif_scrub_addr[0] & ~rdpctl_fifo_err_xaction & |
| 1684 | (~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr); |
| 1685 | assign rdpctl_scrb1_err_valid_in = rdpctl_mcu_data_valid & rdpctl_fifo_scrub & drif_scrub_addr[0] & ~rdpctl_fifo_err_xaction & |
| 1686 | (~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr); |
| 1687 | |
| 1688 | mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_scrub_ecc_err ( |
| 1689 | .scan_in(ff_scrub_ecc_err_scanin), |
| 1690 | .scan_out(ff_scrub_ecc_err_scanout), |
| 1691 | .din({rdpctl_scrb0_err_valid_in,rdpctl_scrb1_err_valid_in}), |
| 1692 | .dout({rdpctl_scrb0_err_valid,rdpctl_scrb1_err_valid}), |
| 1693 | .l1clk(l1clk), |
| 1694 | .siclk(siclk), |
| 1695 | .soclk(soclk)); |
| 1696 | |
| 1697 | ////////////////////////////////////////////////////////////// |
| 1698 | // Dummy request |
| 1699 | ////////////////////////////////////////////////////////////// |
| 1700 | |
| 1701 | mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_rd_dummy_req0 ( |
| 1702 | .scan_in(ff_rd_dummy_req0_scanin), |
| 1703 | .scan_out(ff_rd_dummy_req0_scanout), |
| 1704 | .din(1'b1), |
| 1705 | .dout(rdpctl0_rd_dummy_req), |
| 1706 | .en(rdpctl0_rd_dummy_req_en), |
| 1707 | .clr(rdpctl0_dummy_data_valid), |
| 1708 | .l1clk(l1clk), |
| 1709 | .siclk(siclk), |
| 1710 | .soclk(soclk)); |
| 1711 | |
| 1712 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 ff_rd_dummy0 ( |
| 1713 | .scan_in(ff_rd_dummy0_scanin), |
| 1714 | .scan_out(ff_rd_dummy0_scanout), |
| 1715 | .din({rdpctl0_rd_dummy_req_addr5_in, rdpctl0_rd_dummy_req_id_in[2:0], rdpctl0_rd_dummy_addr_err_in}), |
| 1716 | .dout({rdpctl0_rd_dummy_req_addr5, rdpctl0_rd_dummy_req_id[2:0], rdpctl0_rd_dummy_addr_err}), |
| 1717 | .en(rdpctl0_rd_dummy_req_en), |
| 1718 | .l1clk(l1clk), |
| 1719 | .siclk(siclk), |
| 1720 | .soclk(soclk)); |
| 1721 | |
| 1722 | mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_rd_dummy_req1 ( |
| 1723 | .scan_in(ff_rd_dummy_req1_scanin), |
| 1724 | .scan_out(ff_rd_dummy_req1_scanout), |
| 1725 | .din(1'b1), |
| 1726 | .dout(rdpctl1_rd_dummy_req), |
| 1727 | .en(rdpctl1_rd_dummy_req_en), |
| 1728 | .clr(rdpctl1_dummy_data_valid), |
| 1729 | .l1clk(l1clk), |
| 1730 | .siclk(siclk), |
| 1731 | .soclk(soclk)); |
| 1732 | |
| 1733 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 ff_rd_dummy1 ( |
| 1734 | .scan_in(ff_rd_dummy1_scanin), |
| 1735 | .scan_out(ff_rd_dummy1_scanout), |
| 1736 | .din({rdpctl1_rd_dummy_req_addr5_in, rdpctl1_rd_dummy_req_id_in[2:0], rdpctl1_rd_dummy_addr_err_in}), |
| 1737 | .dout({rdpctl1_rd_dummy_req_addr5, rdpctl1_rd_dummy_req_id[2:0], rdpctl1_rd_dummy_addr_err}), |
| 1738 | .en(rdpctl1_rd_dummy_req_en), |
| 1739 | .l1clk(l1clk), |
| 1740 | .siclk(siclk), |
| 1741 | .soclk(soclk)); |
| 1742 | |
| 1743 | |
| 1744 | // give priority to first dummy requester |
| 1745 | // only want one valid at a time in case one has a pa_err |
| 1746 | assign rdpctl_dummy_priority_in = rdpctl1_rd_dummy_req & ~rdpctl0_rd_dummy_req ? 1'b1 : |
| 1747 | rdpctl0_rd_dummy_req & ~rdpctl1_rd_dummy_req ? 1'b0 : |
| 1748 | rdpctl_dummy_priority; |
| 1749 | |
| 1750 | mcu_rdpctl_ctl_msff_ctl_macro ff_dummy_priority ( |
| 1751 | .scan_in(ff_dummy_priority_scanin), |
| 1752 | .scan_out(ff_dummy_priority_scanout), |
| 1753 | .din(rdpctl_dummy_priority_in), |
| 1754 | .dout(rdpctl_dummy_priority), |
| 1755 | .l1clk(l1clk), |
| 1756 | .siclk(siclk), |
| 1757 | .soclk(soclk)); |
| 1758 | |
| 1759 | assign rdpctl0_dummy_data_valid_in = (~fbdic_rddata_vld & ~rdpctl_mcu_data_valid | |
| 1760 | fbdic_rddata_vld & ~rdpctl_mcu_data_valid & rdpctl0_dummy_data_valid) & |
| 1761 | rdpctl0_rd_dummy_req & (~rdpctl_dummy_priority | ~rdpctl1_rd_dummy_req); |
| 1762 | assign rdpctl1_dummy_data_valid_in = (~fbdic_rddata_vld & ~rdpctl_mcu_data_valid | |
| 1763 | fbdic_rddata_vld & ~rdpctl_mcu_data_valid & rdpctl1_dummy_data_valid) & |
| 1764 | rdpctl1_rd_dummy_req & (rdpctl_dummy_priority | ~rdpctl0_rd_dummy_req); |
| 1765 | |
| 1766 | |
| 1767 | mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_dummy_data_valid ( |
| 1768 | .scan_in(ff_dummy_data_valid_scanin), |
| 1769 | .scan_out(ff_dummy_data_valid_scanout), |
| 1770 | .din({rdpctl0_dummy_data_valid_in,rdpctl1_dummy_data_valid_in}), |
| 1771 | .dout({rdpctl0_dummy_data_valid,rdpctl1_dummy_data_valid}), |
| 1772 | .l1clk(l1clk), |
| 1773 | .siclk(siclk), |
| 1774 | .soclk(soclk)); |
| 1775 | |
| 1776 | // Write enable for scrub data buffer, for data from 1st error retry |
| 1777 | |
| 1778 | assign rdpctl_scrub_wren = drif_single_channel_mode ? rdpctl_scrub_wren_out : |
| 1779 | rdpctl_fifo_err_xaction & ~rdpctl_fifo_err_xactnum & rdpctl_mcu_data_valid; |
| 1780 | assign rdpctl_scrub_wren_in = rdpctl_fifo_err_xaction & ~rdpctl_fifo_err_xactnum & |
| 1781 | fbdic_rddata_vld & rdpctl_rddata_state[0]; |
| 1782 | |
| 1783 | mcu_rdpctl_ctl_msff_ctl_macro ff_scrub_wren ( |
| 1784 | .scan_in(ff_scrub_wren_scanin), |
| 1785 | .scan_out(ff_scrub_wren_scanout), |
| 1786 | .din(rdpctl_scrub_wren_in), |
| 1787 | .dout(rdpctl_scrub_wren_out), |
| 1788 | .l1clk(l1clk), |
| 1789 | .siclk(siclk), |
| 1790 | .soclk(soclk)); |
| 1791 | |
| 1792 | // Mux controls for single-DIMM mode |
| 1793 | assign rdpctl_rddata_en[1:0] = drif_single_channel_mode ? |
| 1794 | {rdpctl_rddata_state[0] | ~fbdic_rddata_vld, ~rdpctl_rddata_state[0] | ~fbdic_rddata_vld} : 2'h3; |
| 1795 | |
| 1796 | assign rdpctl_rddata_en[2] = drif_single_channel_mode ? ~rdpctl_rddata_state[0] : 1'b1; |
| 1797 | |
| 1798 | assign rdpctl_rddata_state_in[1:0] = drif_single_channel_mode ? rdpctl_rddata_state[1:0] + 2'h1 : |
| 1799 | {1'b0, ~rdpctl_rddata_state[0]}; |
| 1800 | mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_2 ff_rddata_state ( |
| 1801 | .scan_in(ff_rddata_state_scanin), |
| 1802 | .scan_out(ff_rddata_state_scanout), |
| 1803 | .din(rdpctl_rddata_state_in[1:0]), |
| 1804 | .dout(rdpctl_rddata_state[1:0]), |
| 1805 | .en(fbdic_rddata_vld), |
| 1806 | .l1clk(l1clk), |
| 1807 | .siclk(siclk), |
| 1808 | .soclk(soclk)); |
| 1809 | |
| 1810 | assign rdpctl_rddata_vld = drif_single_channel_mode ? fbdic_rddata_vld & rdpctl_rddata_state[1] : fbdic_rddata_vld; |
| 1811 | |
| 1812 | // address parity for readdp block |
| 1813 | |
| 1814 | assign rdpctl_radr_parity = fbdic_rddata_vld & (rdpctl_fifo_deq ? rdpctl_fifo_addr_parity_p1 : rdpctl_fifo_addr_parity); |
| 1815 | |
| 1816 | // ECC Error injection from NCU |
| 1817 | mcu_rdpctl_ctl_msff_ctl_macro ff_err_ecci ( |
| 1818 | .scan_in(ff_err_ecci_scanin), |
| 1819 | .scan_out(ff_err_ecci_scanout), |
| 1820 | .din(rdata_err_ecci), |
| 1821 | .dout(rdpctl_err_ecci), |
| 1822 | .l1clk(l1clk), |
| 1823 | .siclk(siclk), |
| 1824 | .soclk(soclk)); |
| 1825 | |
| 1826 | assign rdpctl_inj_ecc_err = rdpctl_err_ecci & ~rdpctl_rddata_state[0] & fbdic_rddata_vld; |
| 1827 | |
| 1828 | // spare gates |
| 1829 | mcu_rdpctl_ctl_spare_ctl_macro__num_6 spares ( |
| 1830 | .scan_in(spares_scanin), |
| 1831 | .scan_out(spares_scanout), |
| 1832 | .l1clk(l1clk), |
| 1833 | .siclk(siclk), |
| 1834 | .soclk(soclk) |
| 1835 | ); |
| 1836 | |
| 1837 | // fixscan start: |
| 1838 | assign ff_pm_mcus_scanin = scan_in ; |
| 1839 | assign ff_dummy_req0_scanin = ff_pm_mcus_scanout ; |
| 1840 | assign ff_dummy_req1_scanin = ff_dummy_req0_scanout ; |
| 1841 | assign ff_ddp_data_valid_scanin = ff_dummy_req1_scanout ; |
| 1842 | assign ff_ecc_loc_scanin = ff_ddp_data_valid_scanout; |
| 1843 | assign ff_data_cnt_scanin = ff_ecc_loc_scanout ; |
| 1844 | assign otq_scanin = ff_data_cnt_scanout ; |
| 1845 | assign ff_drif_clear_ent_scanin = otq_scanout ; |
| 1846 | assign ff_l2t_data_valid_scanin = ff_drif_clear_ent_scanout; |
| 1847 | assign ff_scrub_data_valid_scanin = ff_l2t_data_valid_scanout; |
| 1848 | assign ff_qword_id_scanin = ff_scrub_data_valid_scanout; |
| 1849 | assign ff_rd_req_id_scanin = ff_qword_id_scanout ; |
| 1850 | assign ff_pa_err_scanin = ff_rd_req_id_scanout ; |
| 1851 | assign ff_crc_err_dly_scanin = ff_pa_err_scanout ; |
| 1852 | assign ff_mecc_errors_scanin = ff_crc_err_dly_scanout ; |
| 1853 | assign ff_err_fifo_data_scanin = ff_mecc_errors_scanout ; |
| 1854 | assign ff_fifo_deq_d1_scanin = ff_err_fifo_data_scanout ; |
| 1855 | assign ff_fbd_unrecov_err_scanin = ff_fifo_deq_d1_scanout ; |
| 1856 | assign ff_crc_unrecov_err_scanin = ff_fbd_unrecov_err_scanout; |
| 1857 | assign ff_fbd_recov_err_scanin = ff_crc_unrecov_err_scanout; |
| 1858 | assign ff_crc_recov_err_scanin = ff_fbd_recov_err_scanout ; |
| 1859 | assign ff_ecc_d1_scanin = ff_crc_recov_err_scanout ; |
| 1860 | assign ff_err_retry_ld_scanin = ff_ecc_d1_scanout ; |
| 1861 | assign ff_syndrome_dly_scanin = ff_err_retry_ld_scanout ; |
| 1862 | assign ff_scrub_data_cnt_scanin = ff_syndrome_dly_scanout ; |
| 1863 | assign ff_secc_cnt_intr_scanin = ff_scrub_data_cnt_scanout; |
| 1864 | assign ff_scrub_ecc_err_scanin = ff_secc_cnt_intr_scanout ; |
| 1865 | assign ff_rd_dummy_req0_scanin = ff_scrub_ecc_err_scanout ; |
| 1866 | assign ff_rd_dummy0_scanin = ff_rd_dummy_req0_scanout ; |
| 1867 | assign ff_rd_dummy_req1_scanin = ff_rd_dummy0_scanout ; |
| 1868 | assign ff_rd_dummy1_scanin = ff_rd_dummy_req1_scanout ; |
| 1869 | assign ff_dummy_priority_scanin = ff_rd_dummy1_scanout ; |
| 1870 | assign ff_dummy_data_valid_scanin = ff_dummy_priority_scanout; |
| 1871 | assign ff_scrub_wren_scanin = ff_dummy_data_valid_scanout; |
| 1872 | assign ff_rddata_state_scanin = ff_scrub_wren_scanout ; |
| 1873 | assign ff_err_ecci_scanin = ff_rddata_state_scanout ; |
| 1874 | assign spares_scanin = ff_err_ecci_scanout ; |
| 1875 | assign scan_out = spares_scanout ; |
| 1876 | |
| 1877 | assign pff_err_sts_bit63_wmr_scanin = wmr_scan_in ; |
| 1878 | assign pff_err_sts_bit62_wmr_scanin = pff_err_sts_bit63_wmr_scanout; |
| 1879 | assign pff_err_sts_bit61_wmr_scanin = pff_err_sts_bit62_wmr_scanout; |
| 1880 | assign pff_err_sts_bit60_wmr_scanin = pff_err_sts_bit61_wmr_scanout; |
| 1881 | assign pff_err_sts_bit59_wmr_scanin = pff_err_sts_bit60_wmr_scanout; |
| 1882 | assign pff_err_sts_bit58_wmr_scanin = pff_err_sts_bit59_wmr_scanout; |
| 1883 | assign pff_err_sts_bit57_wmr_scanin = pff_err_sts_bit58_wmr_scanout; |
| 1884 | assign pff_err_sts_bit56_wmr_scanin = pff_err_sts_bit57_wmr_scanout; |
| 1885 | assign pff_err_sts_bit55_wmr_scanin = pff_err_sts_bit56_wmr_scanout; |
| 1886 | assign pff_err_sts_bit54_wmr_scanin = pff_err_sts_bit55_wmr_scanout; |
| 1887 | assign pff_err_syn_wmr_scanin = pff_err_sts_bit54_wmr_scanout; |
| 1888 | assign pff_err_retry1_wmr_scanin = pff_err_syn_wmr_scanout ; |
| 1889 | assign pff_err_retry2_wmr_scanin = pff_err_retry1_wmr_scanout; |
| 1890 | assign pff_retry_reg_valid_wmr_scanin = pff_err_retry2_wmr_scanout; |
| 1891 | assign pff_err_addr_reg_wmr_scanin = pff_retry_reg_valid_wmr_scanout; |
| 1892 | assign pff_secc_int_en_wmr_scanin = pff_err_addr_reg_wmr_scanout; |
| 1893 | assign pff_secc_cnt_wmr_scanin = pff_secc_int_en_wmr_scanout; |
| 1894 | assign pff_dbg_trig_wmr_scanin = pff_secc_cnt_wmr_scanout ; |
| 1895 | assign pff_err_loc_wmr_scanin = pff_dbg_trig_wmr_scanout ; |
| 1896 | assign wmr_scan_out = pff_err_loc_wmr_scanout ; |
| 1897 | // fixscan end: |
| 1898 | endmodule |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | // any PARAMS parms go into naming of macro |
| 1906 | |
| 1907 | module mcu_rdpctl_ctl_l1clkhdr_ctl_macro ( |
| 1908 | l2clk, |
| 1909 | l1en, |
| 1910 | pce_ov, |
| 1911 | stop, |
| 1912 | se, |
| 1913 | l1clk); |
| 1914 | |
| 1915 | |
| 1916 | input l2clk; |
| 1917 | input l1en; |
| 1918 | input pce_ov; |
| 1919 | input stop; |
| 1920 | input se; |
| 1921 | output l1clk; |
| 1922 | |
| 1923 | |
| 1924 | |
| 1925 | |
| 1926 | |
| 1927 | cl_sc1_l1hdr_8x c_0 ( |
| 1928 | |
| 1929 | |
| 1930 | .l2clk(l2clk), |
| 1931 | .pce(l1en), |
| 1932 | .l1clk(l1clk), |
| 1933 | .se(se), |
| 1934 | .pce_ov(pce_ov), |
| 1935 | .stop(stop) |
| 1936 | ); |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | endmodule |
| 1941 | |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | // any PARAMS parms go into naming of macro |
| 1955 | |
| 1956 | module mcu_rdpctl_ctl_msff_ctl_macro__width_2 ( |
| 1957 | din, |
| 1958 | l1clk, |
| 1959 | scan_in, |
| 1960 | siclk, |
| 1961 | soclk, |
| 1962 | dout, |
| 1963 | scan_out); |
| 1964 | wire [1:0] fdin; |
| 1965 | wire [0:0] so; |
| 1966 | |
| 1967 | input [1:0] din; |
| 1968 | input l1clk; |
| 1969 | input scan_in; |
| 1970 | |
| 1971 | |
| 1972 | input siclk; |
| 1973 | input soclk; |
| 1974 | |
| 1975 | output [1:0] dout; |
| 1976 | output scan_out; |
| 1977 | assign fdin[1:0] = din[1:0]; |
| 1978 | |
| 1979 | |
| 1980 | |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | dff #(2) d0_0 ( |
| 1985 | .l1clk(l1clk), |
| 1986 | .siclk(siclk), |
| 1987 | .soclk(soclk), |
| 1988 | .d(fdin[1:0]), |
| 1989 | .si({scan_in,so[0:0]}), |
| 1990 | .so({so[0:0],scan_out}), |
| 1991 | .q(dout[1:0]) |
| 1992 | ); |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | |
| 2000 | |
| 2001 | |
| 2002 | |
| 2003 | |
| 2004 | |
| 2005 | endmodule |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | // any PARAMS parms go into naming of macro |
| 2020 | |
| 2021 | module mcu_rdpctl_ctl_msff_ctl_macro__width_6 ( |
| 2022 | din, |
| 2023 | l1clk, |
| 2024 | scan_in, |
| 2025 | siclk, |
| 2026 | soclk, |
| 2027 | dout, |
| 2028 | scan_out); |
| 2029 | wire [5:0] fdin; |
| 2030 | wire [4:0] so; |
| 2031 | |
| 2032 | input [5:0] din; |
| 2033 | input l1clk; |
| 2034 | input scan_in; |
| 2035 | |
| 2036 | |
| 2037 | input siclk; |
| 2038 | input soclk; |
| 2039 | |
| 2040 | output [5:0] dout; |
| 2041 | output scan_out; |
| 2042 | assign fdin[5:0] = din[5:0]; |
| 2043 | |
| 2044 | |
| 2045 | |
| 2046 | |
| 2047 | |
| 2048 | |
| 2049 | dff #(6) d0_0 ( |
| 2050 | .l1clk(l1clk), |
| 2051 | .siclk(siclk), |
| 2052 | .soclk(soclk), |
| 2053 | .d(fdin[5:0]), |
| 2054 | .si({scan_in,so[4:0]}), |
| 2055 | .so({so[4:0],scan_out}), |
| 2056 | .q(dout[5:0]) |
| 2057 | ); |
| 2058 | |
| 2059 | |
| 2060 | |
| 2061 | |
| 2062 | |
| 2063 | |
| 2064 | |
| 2065 | |
| 2066 | |
| 2067 | |
| 2068 | |
| 2069 | |
| 2070 | endmodule |
| 2071 | |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | // any PARAMS parms go into naming of macro |
| 2085 | |
| 2086 | module mcu_rdpctl_ctl_msff_ctl_macro ( |
| 2087 | din, |
| 2088 | l1clk, |
| 2089 | scan_in, |
| 2090 | siclk, |
| 2091 | soclk, |
| 2092 | dout, |
| 2093 | scan_out); |
| 2094 | wire [0:0] fdin; |
| 2095 | |
| 2096 | input [0:0] din; |
| 2097 | input l1clk; |
| 2098 | input scan_in; |
| 2099 | |
| 2100 | |
| 2101 | input siclk; |
| 2102 | input soclk; |
| 2103 | |
| 2104 | output [0:0] dout; |
| 2105 | output scan_out; |
| 2106 | assign fdin[0:0] = din[0:0]; |
| 2107 | |
| 2108 | |
| 2109 | |
| 2110 | |
| 2111 | |
| 2112 | |
| 2113 | dff #(1) d0_0 ( |
| 2114 | .l1clk(l1clk), |
| 2115 | .siclk(siclk), |
| 2116 | .soclk(soclk), |
| 2117 | .d(fdin[0:0]), |
| 2118 | .si(scan_in), |
| 2119 | .so(scan_out), |
| 2120 | .q(dout[0:0]) |
| 2121 | ); |
| 2122 | |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | |
| 2130 | |
| 2131 | |
| 2132 | |
| 2133 | |
| 2134 | endmodule |
| 2135 | |
| 2136 | |
| 2137 | |
| 2138 | |
| 2139 | |
| 2140 | |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | // any PARAMS parms go into naming of macro |
| 2149 | |
| 2150 | module mcu_rdpctl_ctl_msff_ctl_macro__width_72 ( |
| 2151 | din, |
| 2152 | l1clk, |
| 2153 | scan_in, |
| 2154 | siclk, |
| 2155 | soclk, |
| 2156 | dout, |
| 2157 | scan_out); |
| 2158 | wire [71:0] fdin; |
| 2159 | wire [70:0] so; |
| 2160 | |
| 2161 | input [71:0] din; |
| 2162 | input l1clk; |
| 2163 | input scan_in; |
| 2164 | |
| 2165 | |
| 2166 | input siclk; |
| 2167 | input soclk; |
| 2168 | |
| 2169 | output [71:0] dout; |
| 2170 | output scan_out; |
| 2171 | assign fdin[71:0] = din[71:0]; |
| 2172 | |
| 2173 | |
| 2174 | |
| 2175 | |
| 2176 | |
| 2177 | |
| 2178 | dff #(72) d0_0 ( |
| 2179 | .l1clk(l1clk), |
| 2180 | .siclk(siclk), |
| 2181 | .soclk(soclk), |
| 2182 | .d(fdin[71:0]), |
| 2183 | .si({scan_in,so[70:0]}), |
| 2184 | .so({so[70:0],scan_out}), |
| 2185 | .q(dout[71:0]) |
| 2186 | ); |
| 2187 | |
| 2188 | |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | |
| 2194 | |
| 2195 | |
| 2196 | |
| 2197 | |
| 2198 | |
| 2199 | endmodule |
| 2200 | |
| 2201 | |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | |
| 2212 | |
| 2213 | // any PARAMS parms go into naming of macro |
| 2214 | |
| 2215 | module mcu_rdpctl_ctl_msff_ctl_macro__width_1 ( |
| 2216 | din, |
| 2217 | l1clk, |
| 2218 | scan_in, |
| 2219 | siclk, |
| 2220 | soclk, |
| 2221 | dout, |
| 2222 | scan_out); |
| 2223 | wire [0:0] fdin; |
| 2224 | |
| 2225 | input [0:0] din; |
| 2226 | input l1clk; |
| 2227 | input scan_in; |
| 2228 | |
| 2229 | |
| 2230 | input siclk; |
| 2231 | input soclk; |
| 2232 | |
| 2233 | output [0:0] dout; |
| 2234 | output scan_out; |
| 2235 | assign fdin[0:0] = din[0:0]; |
| 2236 | |
| 2237 | |
| 2238 | |
| 2239 | |
| 2240 | |
| 2241 | |
| 2242 | dff #(1) d0_0 ( |
| 2243 | .l1clk(l1clk), |
| 2244 | .siclk(siclk), |
| 2245 | .soclk(soclk), |
| 2246 | .d(fdin[0:0]), |
| 2247 | .si(scan_in), |
| 2248 | .so(scan_out), |
| 2249 | .q(dout[0:0]) |
| 2250 | ); |
| 2251 | |
| 2252 | |
| 2253 | endmodule |
| 2254 | |
| 2255 | |
| 2256 | |
| 2257 | |
| 2258 | |
| 2259 | |
| 2260 | // any PARAMS parms go into naming of macro |
| 2261 | |
| 2262 | module mcu_rdpctl_ctl_msff_ctl_macro__width_5 ( |
| 2263 | din, |
| 2264 | l1clk, |
| 2265 | scan_in, |
| 2266 | siclk, |
| 2267 | soclk, |
| 2268 | dout, |
| 2269 | scan_out); |
| 2270 | wire [4:0] fdin; |
| 2271 | wire [3:0] so; |
| 2272 | |
| 2273 | input [4:0] din; |
| 2274 | input l1clk; |
| 2275 | input scan_in; |
| 2276 | |
| 2277 | |
| 2278 | input siclk; |
| 2279 | input soclk; |
| 2280 | |
| 2281 | output [4:0] dout; |
| 2282 | output scan_out; |
| 2283 | assign fdin[4:0] = din[4:0]; |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | |
| 2289 | |
| 2290 | dff #(5) d0_0 ( |
| 2291 | .l1clk(l1clk), |
| 2292 | .siclk(siclk), |
| 2293 | .soclk(soclk), |
| 2294 | .d(fdin[4:0]), |
| 2295 | .si({scan_in,so[3:0]}), |
| 2296 | .so({so[3:0],scan_out}), |
| 2297 | .q(dout[4:0]) |
| 2298 | ); |
| 2299 | |
| 2300 | |
| 2301 | |
| 2302 | |
| 2303 | |
| 2304 | |
| 2305 | |
| 2306 | |
| 2307 | |
| 2308 | |
| 2309 | |
| 2310 | |
| 2311 | endmodule |
| 2312 | |
| 2313 | |
| 2314 | |
| 2315 | |
| 2316 | |
| 2317 | |
| 2318 | |
| 2319 | |
| 2320 | |
| 2321 | |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | // any PARAMS parms go into naming of macro |
| 2326 | |
| 2327 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_20 ( |
| 2328 | din, |
| 2329 | en, |
| 2330 | l1clk, |
| 2331 | scan_in, |
| 2332 | siclk, |
| 2333 | soclk, |
| 2334 | dout, |
| 2335 | scan_out); |
| 2336 | wire [19:0] fdin; |
| 2337 | wire [18:0] so; |
| 2338 | |
| 2339 | input [19:0] din; |
| 2340 | input en; |
| 2341 | input l1clk; |
| 2342 | input scan_in; |
| 2343 | |
| 2344 | |
| 2345 | input siclk; |
| 2346 | input soclk; |
| 2347 | |
| 2348 | output [19:0] dout; |
| 2349 | output scan_out; |
| 2350 | assign fdin[19:0] = (din[19:0] & {20{en}}) | (dout[19:0] & ~{20{en}}); |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | |
| 2356 | |
| 2357 | dff #(20) d0_0 ( |
| 2358 | .l1clk(l1clk), |
| 2359 | .siclk(siclk), |
| 2360 | .soclk(soclk), |
| 2361 | .d(fdin[19:0]), |
| 2362 | .si({scan_in,so[18:0]}), |
| 2363 | .so({so[18:0],scan_out}), |
| 2364 | .q(dout[19:0]) |
| 2365 | ); |
| 2366 | |
| 2367 | |
| 2368 | |
| 2369 | |
| 2370 | |
| 2371 | |
| 2372 | |
| 2373 | |
| 2374 | |
| 2375 | |
| 2376 | |
| 2377 | |
| 2378 | endmodule |
| 2379 | |
| 2380 | |
| 2381 | |
| 2382 | |
| 2383 | |
| 2384 | |
| 2385 | |
| 2386 | |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | |
| 2392 | // any PARAMS parms go into naming of macro |
| 2393 | |
| 2394 | module mcu_rdpctl_ctl_msff_ctl_macro__width_16 ( |
| 2395 | din, |
| 2396 | l1clk, |
| 2397 | scan_in, |
| 2398 | siclk, |
| 2399 | soclk, |
| 2400 | dout, |
| 2401 | scan_out); |
| 2402 | wire [15:0] fdin; |
| 2403 | wire [14:0] so; |
| 2404 | |
| 2405 | input [15:0] din; |
| 2406 | input l1clk; |
| 2407 | input scan_in; |
| 2408 | |
| 2409 | |
| 2410 | input siclk; |
| 2411 | input soclk; |
| 2412 | |
| 2413 | output [15:0] dout; |
| 2414 | output scan_out; |
| 2415 | assign fdin[15:0] = din[15:0]; |
| 2416 | |
| 2417 | |
| 2418 | |
| 2419 | |
| 2420 | |
| 2421 | |
| 2422 | dff #(16) d0_0 ( |
| 2423 | .l1clk(l1clk), |
| 2424 | .siclk(siclk), |
| 2425 | .soclk(soclk), |
| 2426 | .d(fdin[15:0]), |
| 2427 | .si({scan_in,so[14:0]}), |
| 2428 | .so({so[14:0],scan_out}), |
| 2429 | .q(dout[15:0]) |
| 2430 | ); |
| 2431 | |
| 2432 | |
| 2433 | |
| 2434 | |
| 2435 | |
| 2436 | |
| 2437 | |
| 2438 | |
| 2439 | |
| 2440 | |
| 2441 | |
| 2442 | |
| 2443 | endmodule |
| 2444 | |
| 2445 | |
| 2446 | |
| 2447 | |
| 2448 | |
| 2449 | |
| 2450 | |
| 2451 | |
| 2452 | |
| 2453 | |
| 2454 | |
| 2455 | |
| 2456 | |
| 2457 | // any PARAMS parms go into naming of macro |
| 2458 | |
| 2459 | module mcu_rdpctl_ctl_msff_ctl_macro__width_3 ( |
| 2460 | din, |
| 2461 | l1clk, |
| 2462 | scan_in, |
| 2463 | siclk, |
| 2464 | soclk, |
| 2465 | dout, |
| 2466 | scan_out); |
| 2467 | wire [2:0] fdin; |
| 2468 | wire [1:0] so; |
| 2469 | |
| 2470 | input [2:0] din; |
| 2471 | input l1clk; |
| 2472 | input scan_in; |
| 2473 | |
| 2474 | |
| 2475 | input siclk; |
| 2476 | input soclk; |
| 2477 | |
| 2478 | output [2:0] dout; |
| 2479 | output scan_out; |
| 2480 | assign fdin[2:0] = din[2:0]; |
| 2481 | |
| 2482 | |
| 2483 | |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | dff #(3) d0_0 ( |
| 2488 | .l1clk(l1clk), |
| 2489 | .siclk(siclk), |
| 2490 | .soclk(soclk), |
| 2491 | .d(fdin[2:0]), |
| 2492 | .si({scan_in,so[1:0]}), |
| 2493 | .so({so[1:0],scan_out}), |
| 2494 | .q(dout[2:0]) |
| 2495 | ); |
| 2496 | |
| 2497 | |
| 2498 | |
| 2499 | |
| 2500 | |
| 2501 | |
| 2502 | |
| 2503 | |
| 2504 | |
| 2505 | |
| 2506 | |
| 2507 | |
| 2508 | endmodule |
| 2509 | |
| 2510 | |
| 2511 | |
| 2512 | |
| 2513 | |
| 2514 | |
| 2515 | |
| 2516 | |
| 2517 | |
| 2518 | |
| 2519 | |
| 2520 | |
| 2521 | |
| 2522 | // any PARAMS parms go into naming of macro |
| 2523 | |
| 2524 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_14 ( |
| 2525 | din, |
| 2526 | en, |
| 2527 | l1clk, |
| 2528 | scan_in, |
| 2529 | siclk, |
| 2530 | soclk, |
| 2531 | dout, |
| 2532 | scan_out); |
| 2533 | wire [13:0] fdin; |
| 2534 | wire [12:0] so; |
| 2535 | |
| 2536 | input [13:0] din; |
| 2537 | input en; |
| 2538 | input l1clk; |
| 2539 | input scan_in; |
| 2540 | |
| 2541 | |
| 2542 | input siclk; |
| 2543 | input soclk; |
| 2544 | |
| 2545 | output [13:0] dout; |
| 2546 | output scan_out; |
| 2547 | assign fdin[13:0] = (din[13:0] & {14{en}}) | (dout[13:0] & ~{14{en}}); |
| 2548 | |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | |
| 2553 | |
| 2554 | dff #(14) d0_0 ( |
| 2555 | .l1clk(l1clk), |
| 2556 | .siclk(siclk), |
| 2557 | .soclk(soclk), |
| 2558 | .d(fdin[13:0]), |
| 2559 | .si({scan_in,so[12:0]}), |
| 2560 | .so({so[12:0],scan_out}), |
| 2561 | .q(dout[13:0]) |
| 2562 | ); |
| 2563 | |
| 2564 | |
| 2565 | |
| 2566 | |
| 2567 | |
| 2568 | |
| 2569 | |
| 2570 | |
| 2571 | |
| 2572 | |
| 2573 | |
| 2574 | |
| 2575 | endmodule |
| 2576 | |
| 2577 | |
| 2578 | |
| 2579 | |
| 2580 | |
| 2581 | |
| 2582 | |
| 2583 | |
| 2584 | |
| 2585 | |
| 2586 | |
| 2587 | |
| 2588 | |
| 2589 | // any PARAMS parms go into naming of macro |
| 2590 | |
| 2591 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 ( |
| 2592 | din, |
| 2593 | en, |
| 2594 | l1clk, |
| 2595 | scan_in, |
| 2596 | siclk, |
| 2597 | soclk, |
| 2598 | dout, |
| 2599 | scan_out); |
| 2600 | wire [0:0] fdin; |
| 2601 | |
| 2602 | input [0:0] din; |
| 2603 | input en; |
| 2604 | input l1clk; |
| 2605 | input scan_in; |
| 2606 | |
| 2607 | |
| 2608 | input siclk; |
| 2609 | input soclk; |
| 2610 | |
| 2611 | output [0:0] dout; |
| 2612 | output scan_out; |
| 2613 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 2614 | |
| 2615 | |
| 2616 | |
| 2617 | |
| 2618 | |
| 2619 | |
| 2620 | dff #(1) d0_0 ( |
| 2621 | .l1clk(l1clk), |
| 2622 | .siclk(siclk), |
| 2623 | .soclk(soclk), |
| 2624 | .d(fdin[0:0]), |
| 2625 | .si(scan_in), |
| 2626 | .so(scan_out), |
| 2627 | .q(dout[0:0]) |
| 2628 | ); |
| 2629 | |
| 2630 | |
| 2631 | |
| 2632 | |
| 2633 | |
| 2634 | |
| 2635 | |
| 2636 | |
| 2637 | |
| 2638 | |
| 2639 | |
| 2640 | |
| 2641 | endmodule |
| 2642 | |
| 2643 | |
| 2644 | |
| 2645 | |
| 2646 | |
| 2647 | |
| 2648 | |
| 2649 | |
| 2650 | |
| 2651 | |
| 2652 | |
| 2653 | |
| 2654 | |
| 2655 | // any PARAMS parms go into naming of macro |
| 2656 | |
| 2657 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1 ( |
| 2658 | din, |
| 2659 | en, |
| 2660 | l1clk, |
| 2661 | scan_in, |
| 2662 | siclk, |
| 2663 | soclk, |
| 2664 | dout, |
| 2665 | scan_out); |
| 2666 | wire [0:0] fdin; |
| 2667 | |
| 2668 | input [0:0] din; |
| 2669 | input en; |
| 2670 | input l1clk; |
| 2671 | input scan_in; |
| 2672 | |
| 2673 | |
| 2674 | input siclk; |
| 2675 | input soclk; |
| 2676 | |
| 2677 | output [0:0] dout; |
| 2678 | output scan_out; |
| 2679 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 2680 | |
| 2681 | |
| 2682 | |
| 2683 | |
| 2684 | |
| 2685 | |
| 2686 | dff #(1) d0_0 ( |
| 2687 | .l1clk(l1clk), |
| 2688 | .siclk(siclk), |
| 2689 | .soclk(soclk), |
| 2690 | .d(fdin[0:0]), |
| 2691 | .si(scan_in), |
| 2692 | .so(scan_out), |
| 2693 | .q(dout[0:0]) |
| 2694 | ); |
| 2695 | |
| 2696 | |
| 2697 | |
| 2698 | |
| 2699 | |
| 2700 | |
| 2701 | |
| 2702 | |
| 2703 | |
| 2704 | |
| 2705 | |
| 2706 | |
| 2707 | endmodule |
| 2708 | |
| 2709 | |
| 2710 | |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | |
| 2715 | |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | |
| 2720 | |
| 2721 | // any PARAMS parms go into naming of macro |
| 2722 | |
| 2723 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_32 ( |
| 2724 | din, |
| 2725 | en, |
| 2726 | l1clk, |
| 2727 | scan_in, |
| 2728 | siclk, |
| 2729 | soclk, |
| 2730 | dout, |
| 2731 | scan_out); |
| 2732 | wire [31:0] fdin; |
| 2733 | wire [30:0] so; |
| 2734 | |
| 2735 | input [31:0] din; |
| 2736 | input en; |
| 2737 | input l1clk; |
| 2738 | input scan_in; |
| 2739 | |
| 2740 | |
| 2741 | input siclk; |
| 2742 | input soclk; |
| 2743 | |
| 2744 | output [31:0] dout; |
| 2745 | output scan_out; |
| 2746 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); |
| 2747 | |
| 2748 | |
| 2749 | |
| 2750 | |
| 2751 | |
| 2752 | |
| 2753 | dff #(32) d0_0 ( |
| 2754 | .l1clk(l1clk), |
| 2755 | .siclk(siclk), |
| 2756 | .soclk(soclk), |
| 2757 | .d(fdin[31:0]), |
| 2758 | .si({scan_in,so[30:0]}), |
| 2759 | .so({so[30:0],scan_out}), |
| 2760 | .q(dout[31:0]) |
| 2761 | ); |
| 2762 | |
| 2763 | |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | |
| 2769 | |
| 2770 | |
| 2771 | |
| 2772 | |
| 2773 | |
| 2774 | endmodule |
| 2775 | |
| 2776 | |
| 2777 | |
| 2778 | |
| 2779 | |
| 2780 | |
| 2781 | |
| 2782 | |
| 2783 | |
| 2784 | |
| 2785 | |
| 2786 | |
| 2787 | |
| 2788 | // any PARAMS parms go into naming of macro |
| 2789 | |
| 2790 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_16 ( |
| 2791 | din, |
| 2792 | en, |
| 2793 | l1clk, |
| 2794 | scan_in, |
| 2795 | siclk, |
| 2796 | soclk, |
| 2797 | dout, |
| 2798 | scan_out); |
| 2799 | wire [15:0] fdin; |
| 2800 | wire [14:0] so; |
| 2801 | |
| 2802 | input [15:0] din; |
| 2803 | input en; |
| 2804 | input l1clk; |
| 2805 | input scan_in; |
| 2806 | |
| 2807 | |
| 2808 | input siclk; |
| 2809 | input soclk; |
| 2810 | |
| 2811 | output [15:0] dout; |
| 2812 | output scan_out; |
| 2813 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); |
| 2814 | |
| 2815 | |
| 2816 | |
| 2817 | |
| 2818 | |
| 2819 | |
| 2820 | dff #(16) d0_0 ( |
| 2821 | .l1clk(l1clk), |
| 2822 | .siclk(siclk), |
| 2823 | .soclk(soclk), |
| 2824 | .d(fdin[15:0]), |
| 2825 | .si({scan_in,so[14:0]}), |
| 2826 | .so({so[14:0],scan_out}), |
| 2827 | .q(dout[15:0]) |
| 2828 | ); |
| 2829 | |
| 2830 | |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | |
| 2836 | |
| 2837 | |
| 2838 | |
| 2839 | |
| 2840 | |
| 2841 | endmodule |
| 2842 | |
| 2843 | |
| 2844 | |
| 2845 | |
| 2846 | |
| 2847 | |
| 2848 | |
| 2849 | |
| 2850 | |
| 2851 | |
| 2852 | |
| 2853 | |
| 2854 | |
| 2855 | // any PARAMS parms go into naming of macro |
| 2856 | |
| 2857 | module mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1 ( |
| 2858 | din, |
| 2859 | en, |
| 2860 | clr, |
| 2861 | l1clk, |
| 2862 | scan_in, |
| 2863 | siclk, |
| 2864 | soclk, |
| 2865 | dout, |
| 2866 | scan_out); |
| 2867 | wire [0:0] fdin; |
| 2868 | |
| 2869 | input [0:0] din; |
| 2870 | input en; |
| 2871 | input clr; |
| 2872 | input l1clk; |
| 2873 | input scan_in; |
| 2874 | |
| 2875 | |
| 2876 | input siclk; |
| 2877 | input soclk; |
| 2878 | |
| 2879 | output [0:0] dout; |
| 2880 | output scan_out; |
| 2881 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}}); |
| 2882 | |
| 2883 | |
| 2884 | |
| 2885 | |
| 2886 | |
| 2887 | |
| 2888 | dff #(1) d0_0 ( |
| 2889 | .l1clk(l1clk), |
| 2890 | .siclk(siclk), |
| 2891 | .soclk(soclk), |
| 2892 | .d(fdin[0:0]), |
| 2893 | .si(scan_in), |
| 2894 | .so(scan_out), |
| 2895 | .q(dout[0:0]) |
| 2896 | ); |
| 2897 | |
| 2898 | |
| 2899 | |
| 2900 | |
| 2901 | |
| 2902 | |
| 2903 | |
| 2904 | |
| 2905 | |
| 2906 | |
| 2907 | |
| 2908 | |
| 2909 | endmodule |
| 2910 | |
| 2911 | |
| 2912 | |
| 2913 | |
| 2914 | |
| 2915 | |
| 2916 | |
| 2917 | |
| 2918 | |
| 2919 | |
| 2920 | |
| 2921 | |
| 2922 | |
| 2923 | // any PARAMS parms go into naming of macro |
| 2924 | |
| 2925 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_18 ( |
| 2926 | din, |
| 2927 | en, |
| 2928 | l1clk, |
| 2929 | scan_in, |
| 2930 | siclk, |
| 2931 | soclk, |
| 2932 | dout, |
| 2933 | scan_out); |
| 2934 | wire [17:0] fdin; |
| 2935 | wire [16:0] so; |
| 2936 | |
| 2937 | input [17:0] din; |
| 2938 | input en; |
| 2939 | input l1clk; |
| 2940 | input scan_in; |
| 2941 | |
| 2942 | |
| 2943 | input siclk; |
| 2944 | input soclk; |
| 2945 | |
| 2946 | output [17:0] dout; |
| 2947 | output scan_out; |
| 2948 | assign fdin[17:0] = (din[17:0] & {18{en}}) | (dout[17:0] & ~{18{en}}); |
| 2949 | |
| 2950 | |
| 2951 | |
| 2952 | |
| 2953 | |
| 2954 | |
| 2955 | dff #(18) d0_0 ( |
| 2956 | .l1clk(l1clk), |
| 2957 | .siclk(siclk), |
| 2958 | .soclk(soclk), |
| 2959 | .d(fdin[17:0]), |
| 2960 | .si({scan_in,so[16:0]}), |
| 2961 | .so({so[16:0],scan_out}), |
| 2962 | .q(dout[17:0]) |
| 2963 | ); |
| 2964 | |
| 2965 | |
| 2966 | |
| 2967 | |
| 2968 | |
| 2969 | |
| 2970 | |
| 2971 | |
| 2972 | |
| 2973 | |
| 2974 | |
| 2975 | |
| 2976 | endmodule |
| 2977 | |
| 2978 | |
| 2979 | |
| 2980 | |
| 2981 | |
| 2982 | |
| 2983 | |
| 2984 | |
| 2985 | |
| 2986 | |
| 2987 | |
| 2988 | |
| 2989 | |
| 2990 | // any PARAMS parms go into naming of macro |
| 2991 | |
| 2992 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 ( |
| 2993 | din, |
| 2994 | en, |
| 2995 | l1clk, |
| 2996 | scan_in, |
| 2997 | siclk, |
| 2998 | soclk, |
| 2999 | dout, |
| 3000 | scan_out); |
| 3001 | wire [35:0] fdin; |
| 3002 | wire [34:0] so; |
| 3003 | |
| 3004 | input [35:0] din; |
| 3005 | input en; |
| 3006 | input l1clk; |
| 3007 | input scan_in; |
| 3008 | |
| 3009 | |
| 3010 | input siclk; |
| 3011 | input soclk; |
| 3012 | |
| 3013 | output [35:0] dout; |
| 3014 | output scan_out; |
| 3015 | assign fdin[35:0] = (din[35:0] & {36{en}}) | (dout[35:0] & ~{36{en}}); |
| 3016 | |
| 3017 | |
| 3018 | |
| 3019 | |
| 3020 | |
| 3021 | |
| 3022 | dff #(36) d0_0 ( |
| 3023 | .l1clk(l1clk), |
| 3024 | .siclk(siclk), |
| 3025 | .soclk(soclk), |
| 3026 | .d(fdin[35:0]), |
| 3027 | .si({scan_in,so[34:0]}), |
| 3028 | .so({so[34:0],scan_out}), |
| 3029 | .q(dout[35:0]) |
| 3030 | ); |
| 3031 | |
| 3032 | |
| 3033 | |
| 3034 | |
| 3035 | |
| 3036 | |
| 3037 | |
| 3038 | |
| 3039 | |
| 3040 | |
| 3041 | |
| 3042 | |
| 3043 | endmodule |
| 3044 | |
| 3045 | |
| 3046 | |
| 3047 | |
| 3048 | |
| 3049 | |
| 3050 | |
| 3051 | |
| 3052 | |
| 3053 | |
| 3054 | |
| 3055 | |
| 3056 | |
| 3057 | // any PARAMS parms go into naming of macro |
| 3058 | |
| 3059 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 ( |
| 3060 | din, |
| 3061 | en, |
| 3062 | l1clk, |
| 3063 | scan_in, |
| 3064 | siclk, |
| 3065 | soclk, |
| 3066 | dout, |
| 3067 | scan_out); |
| 3068 | wire [4:0] fdin; |
| 3069 | wire [3:0] so; |
| 3070 | |
| 3071 | input [4:0] din; |
| 3072 | input en; |
| 3073 | input l1clk; |
| 3074 | input scan_in; |
| 3075 | |
| 3076 | |
| 3077 | input siclk; |
| 3078 | input soclk; |
| 3079 | |
| 3080 | output [4:0] dout; |
| 3081 | output scan_out; |
| 3082 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); |
| 3083 | |
| 3084 | |
| 3085 | |
| 3086 | |
| 3087 | |
| 3088 | |
| 3089 | dff #(5) d0_0 ( |
| 3090 | .l1clk(l1clk), |
| 3091 | .siclk(siclk), |
| 3092 | .soclk(soclk), |
| 3093 | .d(fdin[4:0]), |
| 3094 | .si({scan_in,so[3:0]}), |
| 3095 | .so({so[3:0],scan_out}), |
| 3096 | .q(dout[4:0]) |
| 3097 | ); |
| 3098 | |
| 3099 | |
| 3100 | |
| 3101 | |
| 3102 | |
| 3103 | |
| 3104 | |
| 3105 | |
| 3106 | |
| 3107 | |
| 3108 | |
| 3109 | |
| 3110 | endmodule |
| 3111 | |
| 3112 | |
| 3113 | |
| 3114 | |
| 3115 | |
| 3116 | |
| 3117 | |
| 3118 | |
| 3119 | |
| 3120 | |
| 3121 | |
| 3122 | |
| 3123 | |
| 3124 | // any PARAMS parms go into naming of macro |
| 3125 | |
| 3126 | module mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1__width_1 ( |
| 3127 | din, |
| 3128 | en, |
| 3129 | clr, |
| 3130 | l1clk, |
| 3131 | scan_in, |
| 3132 | siclk, |
| 3133 | soclk, |
| 3134 | dout, |
| 3135 | scan_out); |
| 3136 | wire [0:0] fdin; |
| 3137 | |
| 3138 | input [0:0] din; |
| 3139 | input en; |
| 3140 | input clr; |
| 3141 | input l1clk; |
| 3142 | input scan_in; |
| 3143 | |
| 3144 | |
| 3145 | input siclk; |
| 3146 | input soclk; |
| 3147 | |
| 3148 | output [0:0] dout; |
| 3149 | output scan_out; |
| 3150 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}}); |
| 3151 | |
| 3152 | |
| 3153 | |
| 3154 | |
| 3155 | |
| 3156 | |
| 3157 | dff #(1) d0_0 ( |
| 3158 | .l1clk(l1clk), |
| 3159 | .siclk(siclk), |
| 3160 | .soclk(soclk), |
| 3161 | .d(fdin[0:0]), |
| 3162 | .si(scan_in), |
| 3163 | .so(scan_out), |
| 3164 | .q(dout[0:0]) |
| 3165 | ); |
| 3166 | |
| 3167 | |
| 3168 | |
| 3169 | |
| 3170 | |
| 3171 | |
| 3172 | |
| 3173 | |
| 3174 | |
| 3175 | |
| 3176 | |
| 3177 | |
| 3178 | endmodule |
| 3179 | |
| 3180 | |
| 3181 | |
| 3182 | |
| 3183 | |
| 3184 | |
| 3185 | |
| 3186 | |
| 3187 | |
| 3188 | |
| 3189 | |
| 3190 | |
| 3191 | |
| 3192 | // any PARAMS parms go into naming of macro |
| 3193 | |
| 3194 | module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_2 ( |
| 3195 | din, |
| 3196 | en, |
| 3197 | l1clk, |
| 3198 | scan_in, |
| 3199 | siclk, |
| 3200 | soclk, |
| 3201 | dout, |
| 3202 | scan_out); |
| 3203 | wire [1:0] fdin; |
| 3204 | wire [0:0] so; |
| 3205 | |
| 3206 | input [1:0] din; |
| 3207 | input en; |
| 3208 | input l1clk; |
| 3209 | input scan_in; |
| 3210 | |
| 3211 | |
| 3212 | input siclk; |
| 3213 | input soclk; |
| 3214 | |
| 3215 | output [1:0] dout; |
| 3216 | output scan_out; |
| 3217 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); |
| 3218 | |
| 3219 | |
| 3220 | |
| 3221 | |
| 3222 | |
| 3223 | |
| 3224 | dff #(2) d0_0 ( |
| 3225 | .l1clk(l1clk), |
| 3226 | .siclk(siclk), |
| 3227 | .soclk(soclk), |
| 3228 | .d(fdin[1:0]), |
| 3229 | .si({scan_in,so[0:0]}), |
| 3230 | .so({so[0:0],scan_out}), |
| 3231 | .q(dout[1:0]) |
| 3232 | ); |
| 3233 | |
| 3234 | |
| 3235 | |
| 3236 | |
| 3237 | |
| 3238 | |
| 3239 | |
| 3240 | |
| 3241 | |
| 3242 | |
| 3243 | |
| 3244 | |
| 3245 | endmodule |
| 3246 | |
| 3247 | |
| 3248 | |
| 3249 | |
| 3250 | |
| 3251 | |
| 3252 | |
| 3253 | |
| 3254 | |
| 3255 | // Description: Spare gate macro for control blocks |
| 3256 | // |
| 3257 | // Param num controls the number of times the macro is added |
| 3258 | // flops=0 can be used to use only combination spare logic |
| 3259 | |
| 3260 | |
| 3261 | module mcu_rdpctl_ctl_spare_ctl_macro__num_6 ( |
| 3262 | l1clk, |
| 3263 | scan_in, |
| 3264 | siclk, |
| 3265 | soclk, |
| 3266 | scan_out); |
| 3267 | wire si_0; |
| 3268 | wire so_0; |
| 3269 | wire spare0_flop_unused; |
| 3270 | wire spare0_buf_32x_unused; |
| 3271 | wire spare0_nand3_8x_unused; |
| 3272 | wire spare0_inv_8x_unused; |
| 3273 | wire spare0_aoi22_4x_unused; |
| 3274 | wire spare0_buf_8x_unused; |
| 3275 | wire spare0_oai22_4x_unused; |
| 3276 | wire spare0_inv_16x_unused; |
| 3277 | wire spare0_nand2_16x_unused; |
| 3278 | wire spare0_nor3_4x_unused; |
| 3279 | wire spare0_nand2_8x_unused; |
| 3280 | wire spare0_buf_16x_unused; |
| 3281 | wire spare0_nor2_16x_unused; |
| 3282 | wire spare0_inv_32x_unused; |
| 3283 | wire si_1; |
| 3284 | wire so_1; |
| 3285 | wire spare1_flop_unused; |
| 3286 | wire spare1_buf_32x_unused; |
| 3287 | wire spare1_nand3_8x_unused; |
| 3288 | wire spare1_inv_8x_unused; |
| 3289 | wire spare1_aoi22_4x_unused; |
| 3290 | wire spare1_buf_8x_unused; |
| 3291 | wire spare1_oai22_4x_unused; |
| 3292 | wire spare1_inv_16x_unused; |
| 3293 | wire spare1_nand2_16x_unused; |
| 3294 | wire spare1_nor3_4x_unused; |
| 3295 | wire spare1_nand2_8x_unused; |
| 3296 | wire spare1_buf_16x_unused; |
| 3297 | wire spare1_nor2_16x_unused; |
| 3298 | wire spare1_inv_32x_unused; |
| 3299 | wire si_2; |
| 3300 | wire so_2; |
| 3301 | wire spare2_flop_unused; |
| 3302 | wire spare2_buf_32x_unused; |
| 3303 | wire spare2_nand3_8x_unused; |
| 3304 | wire spare2_inv_8x_unused; |
| 3305 | wire spare2_aoi22_4x_unused; |
| 3306 | wire spare2_buf_8x_unused; |
| 3307 | wire spare2_oai22_4x_unused; |
| 3308 | wire spare2_inv_16x_unused; |
| 3309 | wire spare2_nand2_16x_unused; |
| 3310 | wire spare2_nor3_4x_unused; |
| 3311 | wire spare2_nand2_8x_unused; |
| 3312 | wire spare2_buf_16x_unused; |
| 3313 | wire spare2_nor2_16x_unused; |
| 3314 | wire spare2_inv_32x_unused; |
| 3315 | wire si_3; |
| 3316 | wire so_3; |
| 3317 | wire spare3_flop_unused; |
| 3318 | wire spare3_buf_32x_unused; |
| 3319 | wire spare3_nand3_8x_unused; |
| 3320 | wire spare3_inv_8x_unused; |
| 3321 | wire spare3_aoi22_4x_unused; |
| 3322 | wire spare3_buf_8x_unused; |
| 3323 | wire spare3_oai22_4x_unused; |
| 3324 | wire spare3_inv_16x_unused; |
| 3325 | wire spare3_nand2_16x_unused; |
| 3326 | wire spare3_nor3_4x_unused; |
| 3327 | wire spare3_nand2_8x_unused; |
| 3328 | wire spare3_buf_16x_unused; |
| 3329 | wire spare3_nor2_16x_unused; |
| 3330 | wire spare3_inv_32x_unused; |
| 3331 | wire si_4; |
| 3332 | wire so_4; |
| 3333 | wire spare4_flop_unused; |
| 3334 | wire spare4_buf_32x_unused; |
| 3335 | wire spare4_nand3_8x_unused; |
| 3336 | wire spare4_inv_8x_unused; |
| 3337 | wire spare4_aoi22_4x_unused; |
| 3338 | wire spare4_buf_8x_unused; |
| 3339 | wire spare4_oai22_4x_unused; |
| 3340 | wire spare4_inv_16x_unused; |
| 3341 | wire spare4_nand2_16x_unused; |
| 3342 | wire spare4_nor3_4x_unused; |
| 3343 | wire spare4_nand2_8x_unused; |
| 3344 | wire spare4_buf_16x_unused; |
| 3345 | wire spare4_nor2_16x_unused; |
| 3346 | wire spare4_inv_32x_unused; |
| 3347 | wire si_5; |
| 3348 | wire so_5; |
| 3349 | wire spare5_flop_unused; |
| 3350 | wire spare5_buf_32x_unused; |
| 3351 | wire spare5_nand3_8x_unused; |
| 3352 | wire spare5_inv_8x_unused; |
| 3353 | wire spare5_aoi22_4x_unused; |
| 3354 | wire spare5_buf_8x_unused; |
| 3355 | wire spare5_oai22_4x_unused; |
| 3356 | wire spare5_inv_16x_unused; |
| 3357 | wire spare5_nand2_16x_unused; |
| 3358 | wire spare5_nor3_4x_unused; |
| 3359 | wire spare5_nand2_8x_unused; |
| 3360 | wire spare5_buf_16x_unused; |
| 3361 | wire spare5_nor2_16x_unused; |
| 3362 | wire spare5_inv_32x_unused; |
| 3363 | |
| 3364 | |
| 3365 | input l1clk; |
| 3366 | input scan_in; |
| 3367 | input siclk; |
| 3368 | input soclk; |
| 3369 | output scan_out; |
| 3370 | |
| 3371 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 3372 | .siclk(siclk), |
| 3373 | .soclk(soclk), |
| 3374 | .si(si_0), |
| 3375 | .so(so_0), |
| 3376 | .d(1'b0), |
| 3377 | .q(spare0_flop_unused)); |
| 3378 | assign si_0 = scan_in; |
| 3379 | |
| 3380 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 3381 | .out(spare0_buf_32x_unused)); |
| 3382 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 3383 | .in1(1'b1), |
| 3384 | .in2(1'b1), |
| 3385 | .out(spare0_nand3_8x_unused)); |
| 3386 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 3387 | .out(spare0_inv_8x_unused)); |
| 3388 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 3389 | .in01(1'b1), |
| 3390 | .in10(1'b1), |
| 3391 | .in11(1'b1), |
| 3392 | .out(spare0_aoi22_4x_unused)); |
| 3393 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 3394 | .out(spare0_buf_8x_unused)); |
| 3395 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 3396 | .in01(1'b1), |
| 3397 | .in10(1'b1), |
| 3398 | .in11(1'b1), |
| 3399 | .out(spare0_oai22_4x_unused)); |
| 3400 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 3401 | .out(spare0_inv_16x_unused)); |
| 3402 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 3403 | .in1(1'b1), |
| 3404 | .out(spare0_nand2_16x_unused)); |
| 3405 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 3406 | .in1(1'b0), |
| 3407 | .in2(1'b0), |
| 3408 | .out(spare0_nor3_4x_unused)); |
| 3409 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 3410 | .in1(1'b1), |
| 3411 | .out(spare0_nand2_8x_unused)); |
| 3412 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 3413 | .out(spare0_buf_16x_unused)); |
| 3414 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 3415 | .in1(1'b0), |
| 3416 | .out(spare0_nor2_16x_unused)); |
| 3417 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 3418 | .out(spare0_inv_32x_unused)); |
| 3419 | |
| 3420 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 3421 | .siclk(siclk), |
| 3422 | .soclk(soclk), |
| 3423 | .si(si_1), |
| 3424 | .so(so_1), |
| 3425 | .d(1'b0), |
| 3426 | .q(spare1_flop_unused)); |
| 3427 | assign si_1 = so_0; |
| 3428 | |
| 3429 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 3430 | .out(spare1_buf_32x_unused)); |
| 3431 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 3432 | .in1(1'b1), |
| 3433 | .in2(1'b1), |
| 3434 | .out(spare1_nand3_8x_unused)); |
| 3435 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 3436 | .out(spare1_inv_8x_unused)); |
| 3437 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 3438 | .in01(1'b1), |
| 3439 | .in10(1'b1), |
| 3440 | .in11(1'b1), |
| 3441 | .out(spare1_aoi22_4x_unused)); |
| 3442 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 3443 | .out(spare1_buf_8x_unused)); |
| 3444 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 3445 | .in01(1'b1), |
| 3446 | .in10(1'b1), |
| 3447 | .in11(1'b1), |
| 3448 | .out(spare1_oai22_4x_unused)); |
| 3449 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 3450 | .out(spare1_inv_16x_unused)); |
| 3451 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 3452 | .in1(1'b1), |
| 3453 | .out(spare1_nand2_16x_unused)); |
| 3454 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 3455 | .in1(1'b0), |
| 3456 | .in2(1'b0), |
| 3457 | .out(spare1_nor3_4x_unused)); |
| 3458 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 3459 | .in1(1'b1), |
| 3460 | .out(spare1_nand2_8x_unused)); |
| 3461 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 3462 | .out(spare1_buf_16x_unused)); |
| 3463 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 3464 | .in1(1'b0), |
| 3465 | .out(spare1_nor2_16x_unused)); |
| 3466 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 3467 | .out(spare1_inv_32x_unused)); |
| 3468 | |
| 3469 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 3470 | .siclk(siclk), |
| 3471 | .soclk(soclk), |
| 3472 | .si(si_2), |
| 3473 | .so(so_2), |
| 3474 | .d(1'b0), |
| 3475 | .q(spare2_flop_unused)); |
| 3476 | assign si_2 = so_1; |
| 3477 | |
| 3478 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 3479 | .out(spare2_buf_32x_unused)); |
| 3480 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 3481 | .in1(1'b1), |
| 3482 | .in2(1'b1), |
| 3483 | .out(spare2_nand3_8x_unused)); |
| 3484 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 3485 | .out(spare2_inv_8x_unused)); |
| 3486 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 3487 | .in01(1'b1), |
| 3488 | .in10(1'b1), |
| 3489 | .in11(1'b1), |
| 3490 | .out(spare2_aoi22_4x_unused)); |
| 3491 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 3492 | .out(spare2_buf_8x_unused)); |
| 3493 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 3494 | .in01(1'b1), |
| 3495 | .in10(1'b1), |
| 3496 | .in11(1'b1), |
| 3497 | .out(spare2_oai22_4x_unused)); |
| 3498 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 3499 | .out(spare2_inv_16x_unused)); |
| 3500 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 3501 | .in1(1'b1), |
| 3502 | .out(spare2_nand2_16x_unused)); |
| 3503 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 3504 | .in1(1'b0), |
| 3505 | .in2(1'b0), |
| 3506 | .out(spare2_nor3_4x_unused)); |
| 3507 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 3508 | .in1(1'b1), |
| 3509 | .out(spare2_nand2_8x_unused)); |
| 3510 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 3511 | .out(spare2_buf_16x_unused)); |
| 3512 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 3513 | .in1(1'b0), |
| 3514 | .out(spare2_nor2_16x_unused)); |
| 3515 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 3516 | .out(spare2_inv_32x_unused)); |
| 3517 | |
| 3518 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 3519 | .siclk(siclk), |
| 3520 | .soclk(soclk), |
| 3521 | .si(si_3), |
| 3522 | .so(so_3), |
| 3523 | .d(1'b0), |
| 3524 | .q(spare3_flop_unused)); |
| 3525 | assign si_3 = so_2; |
| 3526 | |
| 3527 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 3528 | .out(spare3_buf_32x_unused)); |
| 3529 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 3530 | .in1(1'b1), |
| 3531 | .in2(1'b1), |
| 3532 | .out(spare3_nand3_8x_unused)); |
| 3533 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 3534 | .out(spare3_inv_8x_unused)); |
| 3535 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 3536 | .in01(1'b1), |
| 3537 | .in10(1'b1), |
| 3538 | .in11(1'b1), |
| 3539 | .out(spare3_aoi22_4x_unused)); |
| 3540 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 3541 | .out(spare3_buf_8x_unused)); |
| 3542 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 3543 | .in01(1'b1), |
| 3544 | .in10(1'b1), |
| 3545 | .in11(1'b1), |
| 3546 | .out(spare3_oai22_4x_unused)); |
| 3547 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 3548 | .out(spare3_inv_16x_unused)); |
| 3549 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 3550 | .in1(1'b1), |
| 3551 | .out(spare3_nand2_16x_unused)); |
| 3552 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 3553 | .in1(1'b0), |
| 3554 | .in2(1'b0), |
| 3555 | .out(spare3_nor3_4x_unused)); |
| 3556 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 3557 | .in1(1'b1), |
| 3558 | .out(spare3_nand2_8x_unused)); |
| 3559 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 3560 | .out(spare3_buf_16x_unused)); |
| 3561 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 3562 | .in1(1'b0), |
| 3563 | .out(spare3_nor2_16x_unused)); |
| 3564 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 3565 | .out(spare3_inv_32x_unused)); |
| 3566 | |
| 3567 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 3568 | .siclk(siclk), |
| 3569 | .soclk(soclk), |
| 3570 | .si(si_4), |
| 3571 | .so(so_4), |
| 3572 | .d(1'b0), |
| 3573 | .q(spare4_flop_unused)); |
| 3574 | assign si_4 = so_3; |
| 3575 | |
| 3576 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 3577 | .out(spare4_buf_32x_unused)); |
| 3578 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 3579 | .in1(1'b1), |
| 3580 | .in2(1'b1), |
| 3581 | .out(spare4_nand3_8x_unused)); |
| 3582 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 3583 | .out(spare4_inv_8x_unused)); |
| 3584 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 3585 | .in01(1'b1), |
| 3586 | .in10(1'b1), |
| 3587 | .in11(1'b1), |
| 3588 | .out(spare4_aoi22_4x_unused)); |
| 3589 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 3590 | .out(spare4_buf_8x_unused)); |
| 3591 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 3592 | .in01(1'b1), |
| 3593 | .in10(1'b1), |
| 3594 | .in11(1'b1), |
| 3595 | .out(spare4_oai22_4x_unused)); |
| 3596 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 3597 | .out(spare4_inv_16x_unused)); |
| 3598 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 3599 | .in1(1'b1), |
| 3600 | .out(spare4_nand2_16x_unused)); |
| 3601 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 3602 | .in1(1'b0), |
| 3603 | .in2(1'b0), |
| 3604 | .out(spare4_nor3_4x_unused)); |
| 3605 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 3606 | .in1(1'b1), |
| 3607 | .out(spare4_nand2_8x_unused)); |
| 3608 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 3609 | .out(spare4_buf_16x_unused)); |
| 3610 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 3611 | .in1(1'b0), |
| 3612 | .out(spare4_nor2_16x_unused)); |
| 3613 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 3614 | .out(spare4_inv_32x_unused)); |
| 3615 | |
| 3616 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), |
| 3617 | .siclk(siclk), |
| 3618 | .soclk(soclk), |
| 3619 | .si(si_5), |
| 3620 | .so(so_5), |
| 3621 | .d(1'b0), |
| 3622 | .q(spare5_flop_unused)); |
| 3623 | assign si_5 = so_4; |
| 3624 | |
| 3625 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), |
| 3626 | .out(spare5_buf_32x_unused)); |
| 3627 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), |
| 3628 | .in1(1'b1), |
| 3629 | .in2(1'b1), |
| 3630 | .out(spare5_nand3_8x_unused)); |
| 3631 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), |
| 3632 | .out(spare5_inv_8x_unused)); |
| 3633 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), |
| 3634 | .in01(1'b1), |
| 3635 | .in10(1'b1), |
| 3636 | .in11(1'b1), |
| 3637 | .out(spare5_aoi22_4x_unused)); |
| 3638 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), |
| 3639 | .out(spare5_buf_8x_unused)); |
| 3640 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), |
| 3641 | .in01(1'b1), |
| 3642 | .in10(1'b1), |
| 3643 | .in11(1'b1), |
| 3644 | .out(spare5_oai22_4x_unused)); |
| 3645 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), |
| 3646 | .out(spare5_inv_16x_unused)); |
| 3647 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), |
| 3648 | .in1(1'b1), |
| 3649 | .out(spare5_nand2_16x_unused)); |
| 3650 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), |
| 3651 | .in1(1'b0), |
| 3652 | .in2(1'b0), |
| 3653 | .out(spare5_nor3_4x_unused)); |
| 3654 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), |
| 3655 | .in1(1'b1), |
| 3656 | .out(spare5_nand2_8x_unused)); |
| 3657 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), |
| 3658 | .out(spare5_buf_16x_unused)); |
| 3659 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), |
| 3660 | .in1(1'b0), |
| 3661 | .out(spare5_nor2_16x_unused)); |
| 3662 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), |
| 3663 | .out(spare5_inv_32x_unused)); |
| 3664 | assign scan_out = so_5; |
| 3665 | |
| 3666 | |
| 3667 | |
| 3668 | endmodule |
| 3669 | |