| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ncu_c2ifd_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define RF_RDEN_OFFSTATE 1'b1 |
| 36 | |
| 37 | //==================================== |
| 38 | `define NCU_INTMANRF_DEPTH 128 |
| 39 | `define NCU_INTMANRF_DATAWIDTH 16 |
| 40 | `define NCU_INTMANRF_ADDRWIDTH 7 |
| 41 | //==================================== |
| 42 | |
| 43 | //==================================== |
| 44 | `define NCU_MONDORF_DEPTH 64 |
| 45 | `define NCU_MONDORF_DATAWIDTH 72 |
| 46 | `define NCU_MONDORF_ADDRWIDTH 6 |
| 47 | //==================================== |
| 48 | |
| 49 | //==================================== |
| 50 | `define NCU_CPUBUFRF_DEPTH 32 |
| 51 | `define NCU_CPUBUFRF_DATAWIDTH 144 |
| 52 | `define NCU_CPUBUFRF_ADDRWIDTH 5 |
| 53 | //==================================== |
| 54 | |
| 55 | //==================================== |
| 56 | `define NCU_IOBUFRF_DEPTH 32 |
| 57 | `define NCU_IOBUFRF_DATAWIDTH 144 |
| 58 | `define NCU_IOBUFRF_ADDRWIDTH 5 |
| 59 | //==================================== |
| 60 | |
| 61 | //==================================== |
| 62 | `define NCU_IOBUF1RF_DEPTH 32 |
| 63 | `define NCU_IOBUF1RF_DATAWIDTH 32 |
| 64 | `define NCU_IOBUF1RF_ADDRWIDTH 5 |
| 65 | //==================================== |
| 66 | |
| 67 | //==================================== |
| 68 | `define NCU_INTBUFRF_DEPTH 32 |
| 69 | `define NCU_INTBUFRF_DATAWIDTH 144 |
| 70 | `define NCU_INTBUFRF_ADDRWIDTH 5 |
| 71 | //==================================== |
| 72 | |
| 73 | //== fix me : need to remove when warm // |
| 74 | //== becomes available // |
| 75 | `define WMR_LENGTH 10'd999 |
| 76 | `define WMR_LENGTH_P1 10'd1000 |
| 77 | |
| 78 | //// NCU CSR_MAN address 80_0000_xxxx //// |
| 79 | `define NCU_CSR_MAN 16'h0000 |
| 80 | `define NCU_CREG_INTMAN 16'h0000 |
| 81 | //`define NCU_CREG_INTVECDISP 16'h0800 |
| 82 | `define NCU_CREG_MONDOINVEC 16'h0a00 |
| 83 | `define NCU_CREG_SERNUM 16'h1000 |
| 84 | `define NCU_CREG_FUSESTAT 16'h1008 |
| 85 | `define NCU_CREG_COREAVAIL 16'h1010 |
| 86 | `define NCU_CREG_BANKAVAIL 16'h1018 |
| 87 | `define NCU_CREG_BANK_ENABLE 16'h1020 |
| 88 | `define NCU_CREG_BANK_ENABLE_STATUS 16'h1028 |
| 89 | `define NCU_CREG_L2_HASH_ENABLE 16'h1030 |
| 90 | `define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038 |
| 91 | |
| 92 | |
| 93 | `define NCU_CREG_MEM32_BASE 16'h2000 |
| 94 | `define NCU_CREG_MEM32_MASK 16'h2008 |
| 95 | `define NCU_CREG_MEM64_BASE 16'h2010 |
| 96 | `define NCU_CREG_MEM64_MASK 16'h2018 |
| 97 | `define NCU_CREG_IOCON_BASE 16'h2020 |
| 98 | `define NCU_CREG_IOCON_MASK 16'h2028 |
| 99 | `define NCU_CREG_MMUFSH 16'h2030 |
| 100 | |
| 101 | `define NCU_CREG_ESR 16'h3000 |
| 102 | `define NCU_CREG_ELE 16'h3008 |
| 103 | `define NCU_CREG_EIE 16'h3010 |
| 104 | `define NCU_CREG_EJR 16'h3018 |
| 105 | `define NCU_CREG_FEE 16'h3020 |
| 106 | `define NCU_CREG_PER 16'h3028 |
| 107 | `define NCU_CREG_SIISYN 16'h3030 |
| 108 | `define NCU_CREG_NCUSYN 16'h3038 |
| 109 | `define NCU_CREG_SCKSEL 16'h3040 |
| 110 | `define NCU_CREG_DBGTRIG_EN 16'h4000 |
| 111 | |
| 112 | //// NUC CSR_MONDO address 80_0004_xxxx //// |
| 113 | `define NCU_CSR_MONDO 16'h0004 |
| 114 | `define NCU_CREG_MDATA0 16'h0000 |
| 115 | `define NCU_CREG_MDATA1 16'h0200 |
| 116 | `define NCU_CREG_MDATA0_ALIAS 16'h0400 |
| 117 | `define NCU_CREG_MDATA1_ALIAS 16'h0600 |
| 118 | `define NCU_CREG_MBUSY 16'h0800 |
| 119 | `define NCU_CREG_MBUSY_ALIAS 16'h0a00 |
| 120 | |
| 121 | |
| 122 | |
| 123 | // ASI shared reg 90_xxxx_xxxx// |
| 124 | `define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x" |
| 125 | `define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x" |
| 126 | `define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x" |
| 127 | `define NCU_ASI_COREAVAIL 16'h0000 |
| 128 | `define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 |
| 129 | `define NCU_ASI_CORE_ENABLE 16'h0020 |
| 130 | `define NCU_ASI_XIR_STEERING 16'h0030 |
| 131 | `define NCU_ASI_CORE_RUNNINGRW 16'h0050 |
| 132 | `define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 |
| 133 | `define NCU_ASI_CORE_RUNNING_W1S 16'h0060 |
| 134 | `define NCU_ASI_CORE_RUNNING_W1C 16'h0068 |
| 135 | `define NCU_ASI_INTVECDISP 16'h0000 |
| 136 | `define NCU_ASI_ERR_STR 16'h1000 |
| 137 | `define NCU_ASI_WMR_VEC_MASK 16'h0018 |
| 138 | `define NCU_ASI_CMP_TICK_ENABLE 16'h0038 |
| 139 | |
| 140 | |
| 141 | //// UCB packet type //// |
| 142 | `define UCB_READ_NACK 4'b0000 // ack/nack types |
| 143 | `define UCB_READ_ACK 4'b0001 |
| 144 | `define UCB_WRITE_ACK 4'b0010 |
| 145 | `define UCB_IFILL_ACK 4'b0011 |
| 146 | `define UCB_IFILL_NACK 4'b0111 |
| 147 | |
| 148 | `define UCB_READ_REQ 4'b0100 // req types |
| 149 | `define UCB_WRITE_REQ 4'b0101 |
| 150 | `define UCB_IFILL_REQ 4'b0110 |
| 151 | |
| 152 | `define UCB_INT 4'b1000 // plain interrupt |
| 153 | `define UCB_INT_VEC 4'b1100 // interrupt with vector |
| 154 | `define UCB_INT_SOC_UE 4'b1001 // soc interrup ue |
| 155 | `define UCB_INT_SOC_CE 4'b1010 // soc interrup ce |
| 156 | `define UCB_RESET_VEC 4'b0101 // reset with vector |
| 157 | `define UCB_IDLE_VEC 4'b1110 // idle with vector |
| 158 | `define UCB_RESUME_VEC 4'b1111 // resume with vector |
| 159 | |
| 160 | `define UCB_INT_SOC 4'b1101 // soc interrup ce |
| 161 | |
| 162 | |
| 163 | //// PCX packet type //// |
| 164 | `define PCX_LOAD_RQ 5'b00000 |
| 165 | `define PCX_IMISS_RQ 5'b10000 |
| 166 | `define PCX_STORE_RQ 5'b00001 |
| 167 | `define PCX_FWD_RQs 5'b01101 |
| 168 | `define PCX_FWD_RPYs 5'b01110 |
| 169 | |
| 170 | //// CPX packet type //// |
| 171 | //`define CPX_LOAD_RET 4'b0000 |
| 172 | `define CPX_LOAD_RET 4'b1000 |
| 173 | `define CPX_ST_ACK 4'b0100 |
| 174 | //`define CPX_IFILL_RET 4'b0001 |
| 175 | `define CPX_IFILL_RET 4'b1001 |
| 176 | `define CPX_INT_RET 4'b0111 |
| 177 | `define CPX_INT_SOC 4'b1101 |
| 178 | //`define CPX_FWD_RQ_RET 4'b1010 |
| 179 | //`define CPX_FWD_RPY_RET 4'b1011 |
| 180 | |
| 181 | |
| 182 | |
| 183 | |
| 184 | //// Global CSR decode //// |
| 185 | `define NCU_CSR 8'h80 |
| 186 | `define NIU_CSR 8'h81 |
| 187 | //`define RNG_CSR 8'h82 |
| 188 | `define DBG1_CSR 8'h86 |
| 189 | `define CCU_CSR 8'h83 |
| 190 | `define MCU_CSR 8'h84 |
| 191 | `define TCU_CSR 8'h85 |
| 192 | `define DMU_CSR 8'h88 |
| 193 | `define RCU_CSR 8'h89 |
| 194 | `define NCU_ASI 8'h90 |
| 195 | /////8'h91 ~ 9F reserved |
| 196 | /////8'hA0 ~ BF L2 CSR//// |
| 197 | `define DMU_PIO 4'hC // C0 ~ CF |
| 198 | /////8'hB0 ~ FE reserved |
| 199 | `define SSI_CSR 8'hFF |
| 200 | |
| 201 | |
| 202 | //// NCU_SSI //// |
| 203 | `define SSI_ADDR 12'hFF_F |
| 204 | `define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088 |
| 205 | `define SSI_ADDR_LOG_REG 40'hFF_0000_0018 |
| 206 | |
| 207 | `define IF_IDLE 2'b00 |
| 208 | `define IF_ACPT 2'b01 |
| 209 | `define IF_DROP 2'b10 |
| 210 | |
| 211 | `define SSI_IDLE 3'b000 |
| 212 | `define SSI_REQ 3'b001 |
| 213 | `define SSI_WDATA 3'b011 |
| 214 | `define SSI_REQ_PAR 3'b101 |
| 215 | `define SSI_ACK 3'b111 |
| 216 | `define SSI_RDATA 3'b110 |
| 217 | `define SSI_ACK_PAR 3'b010 |
| 218 | |
| 219 | |
| 220 | |
| 221 | |
| 222 | |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | |
| 228 | module ncu_c2ifd_ctl ( |
| 229 | l2clk, |
| 230 | cmp_io_sync_en, |
| 231 | io_cmp_sync_en, |
| 232 | tcu_scan_en, |
| 233 | scan_in, |
| 234 | scan_out, |
| 235 | tcu_pce_ov, |
| 236 | tcu_clk_stop, |
| 237 | tcu_aclk, |
| 238 | tcu_bclk, |
| 239 | pcx_ncu_data_px2, |
| 240 | pcx_ncu_vld, |
| 241 | pcx_ncu_req, |
| 242 | pcx_ncu_addr, |
| 243 | pcx_ncu_cputhr, |
| 244 | io_mondo_data_wr, |
| 245 | mondo_data_bypass_d2, |
| 246 | mondo_addr_creg_mdata0_dec_d2, |
| 247 | mondo_addr_creg_mdata1_dec_d2, |
| 248 | mondo_addr_creg_mbusy_dec_d2, |
| 249 | tap_mondo_rd_d2, |
| 250 | cpu_mondo_rd_d2, |
| 251 | cpu_mondo_addr_invld_d2, |
| 252 | io_mondo_data0_din_s, |
| 253 | io_mondo_data1_din_s, |
| 254 | tap_mondo_din_s, |
| 255 | tap_mondo_dout_d2_f, |
| 256 | mb0_mondo_wr_en, |
| 257 | mb0_wdata, |
| 258 | mb0_run, |
| 259 | mondotbl_pei, |
| 260 | mondotbl_pe_f, |
| 261 | mb1_run, |
| 262 | mb1_wdata, |
| 263 | mb1_cpubuf_wr_en, |
| 264 | mb1_addr, |
| 265 | intbuf_din, |
| 266 | mondo_data0_din, |
| 267 | mondo_data0_dout, |
| 268 | mondo_data1_din, |
| 269 | mondo_data1_dout, |
| 270 | mondo_busy_addr_p0, |
| 271 | mondo_busy_addr_p1, |
| 272 | mondo_busy_wr_p1, |
| 273 | mondo_busy_addr_p2, |
| 274 | mondo_busy_wr_p2, |
| 275 | mondo_busy_vec_f, |
| 276 | cpubuf_din) ; |
| 277 | wire pcx_ncu_data_ff_scanin; |
| 278 | wire pcx_ncu_data_ff_scanout; |
| 279 | wire [143:0] pcx_ncu_data; |
| 280 | wire l1clk; |
| 281 | wire pcx_ncu_vld_ff_scanin; |
| 282 | wire pcx_ncu_vld_ff_scanout; |
| 283 | wire [4:0] pcxecc; |
| 284 | wire io_mondo_data0_din_ff_scanin; |
| 285 | wire io_mondo_data0_din_ff_scanout; |
| 286 | wire [63:0] io_mondo_data0_din; |
| 287 | wire io_mondo_data1_din_ff_scanin; |
| 288 | wire io_mondo_data1_din_ff_scanout; |
| 289 | wire [63:0] io_mondo_data1_din; |
| 290 | wire tap_mondo_din_ff_scanin; |
| 291 | wire tap_mondo_din_ff_scanout; |
| 292 | wire [63:0] tap_mondo_din; |
| 293 | wire [71:0] mondo_data0_pre; |
| 294 | wire mondo_data0_din_d1_ff_scanin; |
| 295 | wire mondo_data0_din_d1_ff_scanout; |
| 296 | wire [71:0] mondo_data0_din_d1; |
| 297 | wire mondo_data0_din_d2_ff_scanin; |
| 298 | wire mondo_data0_din_d2_ff_scanout; |
| 299 | wire [71:0] mondo_data0_din_d2; |
| 300 | wire [71:0] mondo_data1_pre; |
| 301 | wire mondo_data1_din_d1_ff_scanin; |
| 302 | wire mondo_data1_din_d1_ff_scanout; |
| 303 | wire [71:0] mondo_data1_din_d1; |
| 304 | wire mondo_data1_din_d2_ff_scanin; |
| 305 | wire mondo_data1_din_d2_ff_scanout; |
| 306 | wire [71:0] mondo_data1_din_d2; |
| 307 | wire mondo_addr_creg_mbusy_dec_d3_ff_scanin; |
| 308 | wire mondo_addr_creg_mbusy_dec_d3_ff_scanout; |
| 309 | wire mondo_addr_creg_mbusy_dec_d3; |
| 310 | wire mondo_busy_din_p1; |
| 311 | wire mondo_busy_din_p2; |
| 312 | wire [71:0] mondo_data0_dout_byp; |
| 313 | wire [71:0] mondo_data1_dout_byp; |
| 314 | wire [71:0] mondo_dout; |
| 315 | wire mondo_busy_dout_d2; |
| 316 | wire mondo_dout_d1_ff_scanin; |
| 317 | wire mondo_dout_d1_ff_scanout; |
| 318 | wire [71:0] mondo_dout_d1; |
| 319 | wire mondotbl_pei_ff_scanin; |
| 320 | wire mondotbl_pei_ff_scanout; |
| 321 | wire mondotbl_pei_f; |
| 322 | wire [7:0] mtbl_pfail; |
| 323 | wire mtbl_perr; |
| 324 | wire cpu_mondo_rd_d3; |
| 325 | wire mtbl_perr_hldr_n; |
| 326 | wire mtbl_perr_hldr; |
| 327 | wire mtbl_perr_hldr_ff_scanin; |
| 328 | wire mtbl_perr_hldr_ff_scanout; |
| 329 | wire mondotbl_pe_f_ff_scanin; |
| 330 | wire mondotbl_pe_f_ff_scanout; |
| 331 | wire cpu_mondo_cpu_id_d1_ff_scanin; |
| 332 | wire cpu_mondo_cpu_id_d1_ff_scanout; |
| 333 | wire [2:0] cpu_mondo_cpu_id_d1; |
| 334 | wire cpu_mondo_cpu_id_d2_ff_scanin; |
| 335 | wire cpu_mondo_cpu_id_d2_ff_scanout; |
| 336 | wire [2:0] cpu_mondo_cpu_id_d2; |
| 337 | wire cpu_mondo_thr_id_d1_ff_scanin; |
| 338 | wire cpu_mondo_thr_id_d1_ff_scanout; |
| 339 | wire [2:0] cpu_mondo_thr_id_d1; |
| 340 | wire cpu_mondo_thr_id_d2_ff_scanin; |
| 341 | wire cpu_mondo_thr_id_d2_ff_scanout; |
| 342 | wire [2:0] cpu_mondo_thr_id_d2; |
| 343 | wire cpu_mondo_bis_d1_ff_scanin; |
| 344 | wire cpu_mondo_bis_d1_ff_scanout; |
| 345 | wire cpu_mondo_bis_d1; |
| 346 | wire cpu_mondo_bis_d2_ff_scanin; |
| 347 | wire cpu_mondo_bis_d2_ff_scanout; |
| 348 | wire cpu_mondo_bis_d2; |
| 349 | wire cpu_mondo_addr10_3_d1_ff_scanin; |
| 350 | wire cpu_mondo_addr10_3_d1_ff_scanout; |
| 351 | wire [7:0] cpu_mondo_addr10_3_d1; |
| 352 | wire cpu_mondo_addr10_3_d2_ff_scanin; |
| 353 | wire cpu_mondo_addr10_3_d2_ff_scanout; |
| 354 | wire [7:0] cpu_mondo_addr10_3_d2; |
| 355 | wire cpu_mondo_size_d1_ff_scanin; |
| 356 | wire cpu_mondo_size_d1_ff_scanout; |
| 357 | wire [7:0] cpu_mondo_size_d1; |
| 358 | wire cpu_mondo_size_d2_ff_scanin; |
| 359 | wire cpu_mondo_size_d2_ff_scanout; |
| 360 | wire [7:0] cpu_mondo_size_d2; |
| 361 | wire pcx_pkt_data_d1_ff_scanin; |
| 362 | wire pcx_pkt_data_d1_ff_scanout; |
| 363 | wire [63:0] pcx_pkt_data_d1; |
| 364 | wire pcx_pkt_data_d2_ff_scanin; |
| 365 | wire pcx_pkt_data_d2_ff_scanout; |
| 366 | wire [63:0] pcx_pkt_data_d2; |
| 367 | wire [7:0] cpu_mondo_cpu_id_dec_d2; |
| 368 | wire [143:0] mondo2cpu_pkt; |
| 369 | wire [4:0] mondofifoecc; |
| 370 | wire mondo2cpu_pkt_ff_scanin; |
| 371 | wire mondo2cpu_pkt_ff_scanout; |
| 372 | wire [121:0] mondo2cpu_pkta; |
| 373 | wire [121:0] mondo2cpu_pkt_n; |
| 374 | wire cpu_mondo_rd_d3_ff_scanin; |
| 375 | wire cpu_mondo_rd_d3_ff_scanout; |
| 376 | wire tap_mondo_dout_d2_ff_scanin; |
| 377 | wire tap_mondo_dout_d2_ff_scanout; |
| 378 | wire [63:0] tap_mondo_dout_d2; |
| 379 | wire tap_mondo_dout_d2_f_ff_scanin; |
| 380 | wire tap_mondo_dout_d2_f_ff_scanout; |
| 381 | wire wr1_a_d1_ff_scanin; |
| 382 | wire wr1_a_d1_ff_scanout; |
| 383 | wire [5:0] wr1_a_d1; |
| 384 | wire wr2_a_d1_ff_scanin; |
| 385 | wire wr2_a_d1_ff_scanout; |
| 386 | wire [5:0] wr2_a_d1; |
| 387 | wire din1_d1_ff_scanin; |
| 388 | wire din1_d1_ff_scanout; |
| 389 | wire din1_d1; |
| 390 | wire din2_d1_ff_scanin; |
| 391 | wire din2_d1_ff_scanout; |
| 392 | wire din2_d1; |
| 393 | wire wen1_d1_ff_scanin; |
| 394 | wire wen1_d1_ff_scanout; |
| 395 | wire wen1_d1; |
| 396 | wire wen2_d1_ff_scanin; |
| 397 | wire wen2_d1_ff_scanout; |
| 398 | wire wen2_d1; |
| 399 | wire [63:0] wr1_a_dec_d1; |
| 400 | wire [63:0] wr2_a_dec_d1; |
| 401 | wire [63:0] wen1_dec_d1; |
| 402 | wire [63:0] wen2_dec_d1; |
| 403 | wire [63:0] vec_n; |
| 404 | wire [63:0] vec; |
| 405 | wire [63:0] vec_n_inv; |
| 406 | wire [63:0] vec_inv; |
| 407 | wire vec_ff_scanin; |
| 408 | wire vec_ff_scanout; |
| 409 | wire mondo_busy_vec_ff_scanin; |
| 410 | wire mondo_busy_vec_ff_scanout; |
| 411 | wire rd_a_d1_ff_scanin; |
| 412 | wire rd_a_d1_ff_scanout; |
| 413 | wire [5:0] rd_a_d1; |
| 414 | wire [63:0] rd_a_dec_d1; |
| 415 | wire mondo_busy_dout_d1; |
| 416 | wire mondo_busy_dout_d2_ff_scanin; |
| 417 | wire mondo_busy_dout_d2_ff_scanout; |
| 418 | wire siclk; |
| 419 | wire soclk; |
| 420 | wire se; |
| 421 | wire pce_ov; |
| 422 | wire stop; |
| 423 | |
| 424 | |
| 425 | //////////////////////////////////////////////////////////////////////// |
| 426 | // Interface signal type declarations |
| 427 | //////////////////////////////////////////////////////////////////////// |
| 428 | // Global interface |
| 429 | input l2clk; |
| 430 | input cmp_io_sync_en; |
| 431 | input io_cmp_sync_en; |
| 432 | |
| 433 | input tcu_scan_en; |
| 434 | input scan_in; |
| 435 | output scan_out; |
| 436 | input tcu_pce_ov; |
| 437 | input tcu_clk_stop; |
| 438 | input tcu_aclk; |
| 439 | input tcu_bclk; |
| 440 | |
| 441 | // Crossbar interface |
| 442 | input [129:0] pcx_ncu_data_px2; |
| 443 | |
| 444 | // c2i fast control interface |
| 445 | output pcx_ncu_vld; |
| 446 | output [4:0] pcx_ncu_req; |
| 447 | output [39:0] pcx_ncu_addr; |
| 448 | output [5:0] pcx_ncu_cputhr; |
| 449 | |
| 450 | input io_mondo_data_wr; |
| 451 | input mondo_data_bypass_d2; |
| 452 | input mondo_addr_creg_mdata0_dec_d2; |
| 453 | input mondo_addr_creg_mdata1_dec_d2; |
| 454 | input mondo_addr_creg_mbusy_dec_d2; |
| 455 | //input cpu_mondo_rd_d1; |
| 456 | input tap_mondo_rd_d2; |
| 457 | input cpu_mondo_rd_d2; |
| 458 | input cpu_mondo_addr_invld_d2; |
| 459 | |
| 460 | // i2c slow datapath interface |
| 461 | input [63:0] io_mondo_data0_din_s; |
| 462 | input [63:0] io_mondo_data1_din_s; |
| 463 | //input [5:0] io_mondo_source_din_s; |
| 464 | |
| 465 | // IOB control interface |
| 466 | input [63:0] tap_mondo_din_s; |
| 467 | output [63:0] tap_mondo_dout_d2_f; |
| 468 | |
| 469 | |
| 470 | // mb0 signals // |
| 471 | input mb0_mondo_wr_en; |
| 472 | //input mb0_intbuf_wr_en; |
| 473 | //input mb0_cpubuf_sel; |
| 474 | input [7:0] mb0_wdata; |
| 475 | input mb0_run; |
| 476 | input mondotbl_pei; |
| 477 | output mondotbl_pe_f; |
| 478 | input mb1_run; |
| 479 | input [7:0] mb1_wdata; |
| 480 | input mb1_cpubuf_wr_en; |
| 481 | input[5:0] mb1_addr; |
| 482 | // i2c fast datapath interface |
| 483 | output [143:0] intbuf_din; |
| 484 | |
| 485 | // Mondo data table interface |
| 486 | output [71:0] mondo_data0_din; |
| 487 | input [71:0] mondo_data0_dout; |
| 488 | |
| 489 | output [71:0] mondo_data1_din; |
| 490 | input [71:0] mondo_data1_dout; |
| 491 | |
| 492 | input [5:0] mondo_busy_addr_p0; |
| 493 | |
| 494 | input [5:0] mondo_busy_addr_p1; |
| 495 | input mondo_busy_wr_p1; |
| 496 | |
| 497 | input [5:0] mondo_busy_addr_p2; |
| 498 | input mondo_busy_wr_p2; |
| 499 | |
| 500 | output [63:0] mondo_busy_vec_f; |
| 501 | |
| 502 | // Cpu buffer interface |
| 503 | output [143:0] cpubuf_din; |
| 504 | |
| 505 | // Internal signals |
| 506 | |
| 507 | |
| 508 | |
| 509 | |
| 510 | |
| 511 | |
| 512 | |
| 513 | |
| 514 | |
| 515 | |
| 516 | |
| 517 | |
| 518 | |
| 519 | |
| 520 | |
| 521 | /***************************************************************** |
| 522 | * Flop data from PCX |
| 523 | *****************************************************************/ |
| 524 | ncu_c2ifd_ctl_msff_ctl_macro__width_129 pcx_ncu_data_ff |
| 525 | ( |
| 526 | .scan_in(pcx_ncu_data_ff_scanin), |
| 527 | .scan_out(pcx_ncu_data_ff_scanout), |
| 528 | .dout (pcx_ncu_data[128:0]), |
| 529 | .l1clk (l1clk), |
| 530 | .din (pcx_ncu_data_px2[128:0]), |
| 531 | .siclk(siclk), |
| 532 | .soclk(soclk) |
| 533 | ); |
| 534 | |
| 535 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 pcx_ncu_vld_ff |
| 536 | ( |
| 537 | .scan_in(pcx_ncu_vld_ff_scanin), |
| 538 | .scan_out(pcx_ncu_vld_ff_scanout), |
| 539 | .dout (pcx_ncu_vld), |
| 540 | .l1clk (l1clk), |
| 541 | .din (pcx_ncu_data_px2[129]), |
| 542 | .siclk(siclk), |
| 543 | .soclk(soclk) |
| 544 | ); |
| 545 | assign cpubuf_din[143:0] = mb1_run ? {18{mb1_wdata[7:0]}} : {pcx_ncu_data[143:0]} ; |
| 546 | //assign cpubuf_din[143:0] = pcx_ncu_data[143:0]; // cpubuf no longer goes to mb0. |
| 547 | |
| 548 | ////// pcx_ncu_vld |
| 549 | assign pcx_ncu_req[4:0] = pcx_ncu_data[128:124]; |
| 550 | assign pcx_ncu_addr[39:0] = pcx_ncu_data[103:64]; |
| 551 | assign pcx_ncu_cputhr[5:0] = pcx_ncu_data[122:117]; |
| 552 | |
| 553 | //// par and ecc gen //// |
| 554 | assign pcx_ncu_data[133:129]=pcxecc[4:0]; |
| 555 | ncu_eccgen6_ctl c2ifdeccgen6 (.din(pcx_ncu_cputhr[5:0]), |
| 556 | .dout(pcxecc[4:0])); |
| 557 | |
| 558 | assign pcx_ncu_data[134] = ~^{pcx_ncu_data[0], pcx_ncu_data[10],pcx_ncu_data[20], pcx_ncu_data[30], |
| 559 | pcx_ncu_data[40],pcx_ncu_data[50],pcx_ncu_data[60], pcx_ncu_data[70], |
| 560 | pcx_ncu_data[80],pcx_ncu_data[90],pcx_ncu_data[100],pcx_ncu_data[110]}; |
| 561 | |
| 562 | assign pcx_ncu_data[135] = ~^{pcx_ncu_data[1], pcx_ncu_data[11],pcx_ncu_data[21], pcx_ncu_data[31], |
| 563 | pcx_ncu_data[41],pcx_ncu_data[51],pcx_ncu_data[61], pcx_ncu_data[70], |
| 564 | pcx_ncu_data[81],pcx_ncu_data[91],pcx_ncu_data[101],pcx_ncu_data[111]}; |
| 565 | |
| 566 | assign pcx_ncu_data[136] = ~^{pcx_ncu_data[2], pcx_ncu_data[12],pcx_ncu_data[22], pcx_ncu_data[32], |
| 567 | pcx_ncu_data[42],pcx_ncu_data[52],pcx_ncu_data[62], pcx_ncu_data[72], |
| 568 | pcx_ncu_data[82],pcx_ncu_data[92],pcx_ncu_data[102],pcx_ncu_data[114]}; |
| 569 | |
| 570 | assign pcx_ncu_data[137] = ~^{pcx_ncu_data[3], pcx_ncu_data[13],pcx_ncu_data[23], pcx_ncu_data[33], |
| 571 | pcx_ncu_data[43],pcx_ncu_data[52],pcx_ncu_data[63], pcx_ncu_data[73], |
| 572 | pcx_ncu_data[83],pcx_ncu_data[93],pcx_ncu_data[103],pcx_ncu_data[124]}; |
| 573 | |
| 574 | assign pcx_ncu_data[138] = ~^{pcx_ncu_data[4], pcx_ncu_data[14],pcx_ncu_data[24], pcx_ncu_data[34], |
| 575 | pcx_ncu_data[44],pcx_ncu_data[54],pcx_ncu_data[64], pcx_ncu_data[74], |
| 576 | pcx_ncu_data[84],pcx_ncu_data[94],pcx_ncu_data[104],pcx_ncu_data[125]}; |
| 577 | |
| 578 | assign pcx_ncu_data[139] = ~^{pcx_ncu_data[5], pcx_ncu_data[15],pcx_ncu_data[25], pcx_ncu_data[35], |
| 579 | pcx_ncu_data[45],pcx_ncu_data[55],pcx_ncu_data[65], pcx_ncu_data[75], |
| 580 | pcx_ncu_data[85],pcx_ncu_data[95],pcx_ncu_data[105],pcx_ncu_data[126]}; |
| 581 | |
| 582 | assign pcx_ncu_data[140] = ~^{pcx_ncu_data[6], pcx_ncu_data[16],pcx_ncu_data[26], pcx_ncu_data[36], |
| 583 | pcx_ncu_data[46],pcx_ncu_data[56],pcx_ncu_data[66], pcx_ncu_data[76], |
| 584 | pcx_ncu_data[86],pcx_ncu_data[96],pcx_ncu_data[106],pcx_ncu_data[127]}; |
| 585 | |
| 586 | assign pcx_ncu_data[141] = ~^{pcx_ncu_data[7], pcx_ncu_data[17],pcx_ncu_data[27], pcx_ncu_data[37], |
| 587 | pcx_ncu_data[47],pcx_ncu_data[57],pcx_ncu_data[67], pcx_ncu_data[77], |
| 588 | pcx_ncu_data[87],pcx_ncu_data[98],pcx_ncu_data[107],pcx_ncu_data[128]}; |
| 589 | |
| 590 | assign pcx_ncu_data[142] = ~^{pcx_ncu_data[8], pcx_ncu_data[18],pcx_ncu_data[28], pcx_ncu_data[38], |
| 591 | pcx_ncu_data[48],pcx_ncu_data[58],pcx_ncu_data[68], pcx_ncu_data[78], |
| 592 | pcx_ncu_data[88],pcx_ncu_data[98],pcx_ncu_data[108]}; |
| 593 | |
| 594 | assign pcx_ncu_data[143] = ~^{pcx_ncu_data[9], pcx_ncu_data[19],pcx_ncu_data[29], pcx_ncu_data[39], |
| 595 | pcx_ncu_data[49],pcx_ncu_data[59],pcx_ncu_data[69], pcx_ncu_data[79], |
| 596 | pcx_ncu_data[89],pcx_ncu_data[99],pcx_ncu_data[109]}; |
| 597 | |
| 598 | /***************************************************************** |
| 599 | * Mondo data0/data1/busy table write data |
| 600 | *****************************************************************/ |
| 601 | // Convert from BSC to CPU clock |
| 602 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 io_mondo_data0_din_ff |
| 603 | ( |
| 604 | .scan_in(io_mondo_data0_din_ff_scanin), |
| 605 | .scan_out(io_mondo_data0_din_ff_scanout), |
| 606 | .dout (io_mondo_data0_din[63:0]), |
| 607 | .l1clk (l1clk), |
| 608 | .en (io_cmp_sync_en), |
| 609 | .din (io_mondo_data0_din_s[63:0]), |
| 610 | .siclk(siclk), |
| 611 | .soclk(soclk) |
| 612 | ); |
| 613 | |
| 614 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 io_mondo_data1_din_ff |
| 615 | ( |
| 616 | .scan_in(io_mondo_data1_din_ff_scanin), |
| 617 | .scan_out(io_mondo_data1_din_ff_scanout), |
| 618 | .dout (io_mondo_data1_din[63:0]), |
| 619 | .l1clk (l1clk), |
| 620 | .en (io_cmp_sync_en), |
| 621 | .din (io_mondo_data1_din_s[63:0]), |
| 622 | .siclk(siclk), |
| 623 | .soclk(soclk) |
| 624 | ); |
| 625 | |
| 626 | |
| 627 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 tap_mondo_din_ff |
| 628 | ( |
| 629 | .scan_in(tap_mondo_din_ff_scanin), |
| 630 | .scan_out(tap_mondo_din_ff_scanout), |
| 631 | .dout (tap_mondo_din[63:0]), |
| 632 | .l1clk (l1clk), |
| 633 | .en (io_cmp_sync_en), |
| 634 | .din (tap_mondo_din_s[63:0]), |
| 635 | .siclk(siclk), |
| 636 | .soclk(soclk) |
| 637 | ); |
| 638 | |
| 639 | |
| 640 | //assign mb0_mondo_sel = mb0_run * mb0_mondo_wr_en; |
| 641 | assign mondo_data0_din[71:0] = mb0_run ? {9{mb0_wdata[7:0]}} : mondo_data0_pre[71:0] ; |
| 642 | //io_mondo_data_wr ? io_mondo_data0_din[63:0] : tap_mondo_din[63:0]; |
| 643 | |
| 644 | assign mondo_data0_pre[63:0] = io_mondo_data_wr ? io_mondo_data0_din[63:0] : tap_mondo_din[63:0]; |
| 645 | assign mondo_data0_pre[64] = ~^{mondo_data0_pre[0], mondo_data0_pre[8], mondo_data0_pre[16], mondo_data0_pre[24], |
| 646 | mondo_data0_pre[32], mondo_data0_pre[40], mondo_data0_pre[48], mondo_data0_pre[56] }; |
| 647 | assign mondo_data0_pre[65] = ~^{mondo_data0_pre[1], mondo_data0_pre[9], mondo_data0_pre[17], mondo_data0_pre[25], |
| 648 | mondo_data0_pre[33], mondo_data0_pre[41], mondo_data0_pre[49], mondo_data0_pre[57] }; |
| 649 | assign mondo_data0_pre[66] = ~^{mondo_data0_pre[2], mondo_data0_pre[10], mondo_data0_pre[18], mondo_data0_pre[26], |
| 650 | mondo_data0_pre[34], mondo_data0_pre[42], mondo_data0_pre[50], mondo_data0_pre[58] }; |
| 651 | assign mondo_data0_pre[67] = ~^{mondo_data0_pre[3], mondo_data0_pre[11], mondo_data0_pre[19], mondo_data0_pre[27], |
| 652 | mondo_data0_pre[35], mondo_data0_pre[43], mondo_data0_pre[51], mondo_data0_pre[59] }; |
| 653 | assign mondo_data0_pre[68] = ~^{mondo_data0_pre[4], mondo_data0_pre[12], mondo_data0_pre[20], mondo_data0_pre[28], |
| 654 | mondo_data0_pre[36], mondo_data0_pre[44], mondo_data0_pre[52], mondo_data0_pre[60] }; |
| 655 | assign mondo_data0_pre[69] = ~^{mondo_data0_pre[5], mondo_data0_pre[13], mondo_data0_pre[21], mondo_data0_pre[29], |
| 656 | mondo_data0_pre[37], mondo_data0_pre[45], mondo_data0_pre[53], mondo_data0_pre[61] }; |
| 657 | assign mondo_data0_pre[70] = ~^{mondo_data0_pre[6], mondo_data0_pre[14], mondo_data0_pre[22], mondo_data0_pre[30], |
| 658 | mondo_data0_pre[38], mondo_data0_pre[46], mondo_data0_pre[54], mondo_data0_pre[62] }; |
| 659 | assign mondo_data0_pre[71] = ~^{mondo_data0_pre[7], mondo_data0_pre[15], mondo_data0_pre[23], mondo_data0_pre[31], |
| 660 | mondo_data0_pre[39], mondo_data0_pre[47], mondo_data0_pre[55], mondo_data0_pre[63] }; |
| 661 | |
| 662 | ncu_c2ifd_ctl_msff_ctl_macro__width_72 mondo_data0_din_d1_ff |
| 663 | ( |
| 664 | .scan_in(mondo_data0_din_d1_ff_scanin), |
| 665 | .scan_out(mondo_data0_din_d1_ff_scanout), |
| 666 | .dout (mondo_data0_din_d1[71:0]), |
| 667 | .l1clk (l1clk), |
| 668 | .din (mondo_data0_din[71:0]), |
| 669 | .siclk(siclk), |
| 670 | .soclk(soclk) |
| 671 | ); |
| 672 | |
| 673 | ncu_c2ifd_ctl_msff_ctl_macro__width_72 mondo_data0_din_d2_ff |
| 674 | ( |
| 675 | .scan_in(mondo_data0_din_d2_ff_scanin), |
| 676 | .scan_out(mondo_data0_din_d2_ff_scanout), |
| 677 | .dout (mondo_data0_din_d2[71:0]), |
| 678 | .l1clk (l1clk), |
| 679 | .din (mondo_data0_din_d1[71:0]), |
| 680 | .siclk(siclk), |
| 681 | .soclk(soclk) |
| 682 | ); |
| 683 | |
| 684 | |
| 685 | |
| 686 | assign mondo_data1_din[71:0] = mb0_run ? {9{mb0_wdata[7:0]}} : mondo_data1_pre[71:0] ; |
| 687 | //io_mondo_data_wr ? io_mondo_data1_din[63:0] : tap_mondo_din[63:0]; |
| 688 | |
| 689 | assign mondo_data1_pre[63:0] = io_mondo_data_wr ? io_mondo_data1_din[63:0] : tap_mondo_din[63:0]; |
| 690 | assign mondo_data1_pre[64] = ~^{mondo_data1_pre[0], mondo_data1_pre[8], mondo_data1_pre[16], mondo_data1_pre[24], |
| 691 | mondo_data1_pre[32], mondo_data1_pre[40], mondo_data1_pre[48], mondo_data1_pre[56] }; |
| 692 | assign mondo_data1_pre[65] = ~^{mondo_data1_pre[1], mondo_data1_pre[9], mondo_data1_pre[17], mondo_data1_pre[25], |
| 693 | mondo_data1_pre[33], mondo_data1_pre[41], mondo_data1_pre[49], mondo_data1_pre[57] }; |
| 694 | assign mondo_data1_pre[66] = ~^{mondo_data1_pre[2], mondo_data1_pre[10], mondo_data1_pre[18], mondo_data1_pre[26], |
| 695 | mondo_data1_pre[34], mondo_data1_pre[42], mondo_data1_pre[50], mondo_data1_pre[58] }; |
| 696 | assign mondo_data1_pre[67] = ~^{mondo_data1_pre[3], mondo_data1_pre[11], mondo_data1_pre[19], mondo_data1_pre[27], |
| 697 | mondo_data1_pre[35], mondo_data1_pre[43], mondo_data1_pre[51], mondo_data1_pre[59] }; |
| 698 | assign mondo_data1_pre[68] = ~^{mondo_data1_pre[4], mondo_data1_pre[12], mondo_data1_pre[20], mondo_data1_pre[28], |
| 699 | mondo_data1_pre[36], mondo_data1_pre[44], mondo_data1_pre[52], mondo_data1_pre[60] }; |
| 700 | assign mondo_data1_pre[69] = ~^{mondo_data1_pre[5], mondo_data1_pre[13], mondo_data1_pre[21], mondo_data1_pre[29], |
| 701 | mondo_data1_pre[37], mondo_data1_pre[45], mondo_data1_pre[53], mondo_data1_pre[61] }; |
| 702 | assign mondo_data1_pre[70] = ~^{mondo_data1_pre[6], mondo_data1_pre[14], mondo_data1_pre[22], mondo_data1_pre[30], |
| 703 | mondo_data1_pre[38], mondo_data1_pre[46], mondo_data1_pre[54], mondo_data1_pre[62] }; |
| 704 | assign mondo_data1_pre[71] = ~^{mondo_data1_pre[7], mondo_data1_pre[15], mondo_data1_pre[23], mondo_data1_pre[31], |
| 705 | mondo_data1_pre[39], mondo_data1_pre[47], mondo_data1_pre[55], mondo_data1_pre[63] }; |
| 706 | |
| 707 | ncu_c2ifd_ctl_msff_ctl_macro__width_72 mondo_data1_din_d1_ff |
| 708 | ( |
| 709 | .scan_in(mondo_data1_din_d1_ff_scanin), |
| 710 | .scan_out(mondo_data1_din_d1_ff_scanout), |
| 711 | .dout (mondo_data1_din_d1[71:0]), |
| 712 | .l1clk (l1clk), |
| 713 | .din (mondo_data1_din[71:0]), |
| 714 | .siclk(siclk), |
| 715 | .soclk(soclk) |
| 716 | ); |
| 717 | |
| 718 | ncu_c2ifd_ctl_msff_ctl_macro__width_72 mondo_data1_din_d2_ff |
| 719 | ( |
| 720 | .scan_in(mondo_data1_din_d2_ff_scanin), |
| 721 | .scan_out(mondo_data1_din_d2_ff_scanout), |
| 722 | .dout (mondo_data1_din_d2[71:0]), |
| 723 | .l1clk (l1clk), |
| 724 | .din (mondo_data1_din_d1[71:0]), |
| 725 | .siclk(siclk), |
| 726 | .soclk(soclk) |
| 727 | ); |
| 728 | |
| 729 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 mondo_addr_creg_mbusy_dec_d3_ff |
| 730 | ( |
| 731 | .scan_in(mondo_addr_creg_mbusy_dec_d3_ff_scanin), |
| 732 | .scan_out(mondo_addr_creg_mbusy_dec_d3_ff_scanout), |
| 733 | .dout (mondo_addr_creg_mbusy_dec_d3), |
| 734 | .l1clk (l1clk), |
| 735 | .din (mondo_addr_creg_mbusy_dec_d2), |
| 736 | .siclk(siclk), |
| 737 | .soclk(soclk) |
| 738 | ); |
| 739 | |
| 740 | assign mondo_busy_din_p1 = io_mondo_data_wr ? 1'b1 : tap_mondo_din[6]; |
| 741 | |
| 742 | assign mondo_busy_din_p2 = pcx_ncu_data[6]; |
| 743 | |
| 744 | |
| 745 | /***************************************************************** |
| 746 | * Mondo data0/data1/busy table read data (CPU read) |
| 747 | *****************************************************************/ |
| 748 | assign mondo_data0_dout_byp[71:0] = mondo_data_bypass_d2 ? mondo_data0_din_d2[71:0] : |
| 749 | mondo_data0_dout[71:0]; |
| 750 | |
| 751 | assign mondo_data1_dout_byp[71:0] = mondo_data_bypass_d2 ? mondo_data1_din_d2[71:0] : |
| 752 | mondo_data1_dout[71:0]; |
| 753 | |
| 754 | // Use AND/OR to implement a mux |
| 755 | assign mondo_dout[71:0] = ({72{mondo_addr_creg_mdata0_dec_d2}} & mondo_data0_dout_byp[71:0]) | |
| 756 | ({72{mondo_addr_creg_mdata1_dec_d2}} & mondo_data1_dout_byp[71:0]) | |
| 757 | ({72{mondo_addr_creg_mbusy_dec_d2}} & {8'b0,57'b0,mondo_busy_dout_d2,6'b0}); |
| 758 | |
| 759 | |
| 760 | ncu_c2ifd_ctl_msff_ctl_macro__width_72 mondo_dout_d1_ff |
| 761 | ( |
| 762 | .scan_in(mondo_dout_d1_ff_scanin), |
| 763 | .scan_out(mondo_dout_d1_ff_scanout), |
| 764 | .dout (mondo_dout_d1[71:0]), |
| 765 | .l1clk (l1clk), |
| 766 | .din (mondo_dout[71:0]), |
| 767 | .siclk(siclk), |
| 768 | .soclk(soclk) |
| 769 | ); |
| 770 | |
| 771 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_1 modotbl_pei_ff |
| 772 | ( |
| 773 | .scan_in(mondotbl_pei_ff_scanin), |
| 774 | .scan_out(mondotbl_pei_ff_scanout), |
| 775 | .dout (mondotbl_pei_f), |
| 776 | .l1clk (l1clk), |
| 777 | .en (io_cmp_sync_en), |
| 778 | .din (mondotbl_pei), |
| 779 | .siclk(siclk), |
| 780 | .soclk(soclk) |
| 781 | ); |
| 782 | |
| 783 | |
| 784 | assign mtbl_pfail[0] = ~^{mondo_dout_d1[0], mondo_dout_d1[8], mondo_dout_d1[16], mondo_dout_d1[24], |
| 785 | mondo_dout_d1[32], mondo_dout_d1[40], mondo_dout_d1[48], mondo_dout_d1[56], mondo_dout_d1[64], |
| 786 | mondotbl_pei_f }; |
| 787 | |
| 788 | assign mtbl_pfail[1] = ~^{mondo_dout_d1[1], mondo_dout_d1[9], mondo_dout_d1[17], mondo_dout_d1[25], |
| 789 | mondo_dout_d1[33], mondo_dout_d1[41], mondo_dout_d1[49], mondo_dout_d1[57], mondo_dout_d1[65] }; |
| 790 | |
| 791 | assign mtbl_pfail[2] = ~^{mondo_dout_d1[2], mondo_dout_d1[10], mondo_dout_d1[18], mondo_dout_d1[26], |
| 792 | mondo_dout_d1[34], mondo_dout_d1[42], mondo_dout_d1[50], mondo_dout_d1[58], mondo_dout_d1[66] }; |
| 793 | |
| 794 | assign mtbl_pfail[3] = ~^{mondo_dout_d1[3], mondo_dout_d1[11], mondo_dout_d1[19], mondo_dout_d1[27], |
| 795 | mondo_dout_d1[35], mondo_dout_d1[43], mondo_dout_d1[51], mondo_dout_d1[59], mondo_dout_d1[67] }; |
| 796 | |
| 797 | assign mtbl_pfail[4] = ~^{mondo_dout_d1[4], mondo_dout_d1[12], mondo_dout_d1[20], mondo_dout_d1[28], |
| 798 | mondo_dout_d1[36], mondo_dout_d1[44], mondo_dout_d1[52], mondo_dout_d1[60], mondo_dout_d1[68] }; |
| 799 | |
| 800 | assign mtbl_pfail[5] = ~^{mondo_dout_d1[5], mondo_dout_d1[13], mondo_dout_d1[21], mondo_dout_d1[29], |
| 801 | mondo_dout_d1[37], mondo_dout_d1[45], mondo_dout_d1[53], mondo_dout_d1[61], mondo_dout_d1[69] }; |
| 802 | |
| 803 | assign mtbl_pfail[6] = ~^{mondo_dout_d1[6], mondo_dout_d1[14], mondo_dout_d1[22], mondo_dout_d1[30], |
| 804 | mondo_dout_d1[38], mondo_dout_d1[46], mondo_dout_d1[54], mondo_dout_d1[62], mondo_dout_d1[70] }; |
| 805 | |
| 806 | assign mtbl_pfail[7] = ~^{mondo_dout_d1[7], mondo_dout_d1[15], mondo_dout_d1[23], mondo_dout_d1[31], |
| 807 | mondo_dout_d1[39], mondo_dout_d1[47], mondo_dout_d1[55], mondo_dout_d1[63], mondo_dout_d1[71] }; |
| 808 | |
| 809 | //// holding logic for domain crossing // |
| 810 | |
| 811 | assign mtbl_perr = (|(mtbl_pfail[7:0])) & cpu_mondo_rd_d3 & ~mondo_addr_creg_mbusy_dec_d3 ; |
| 812 | assign mtbl_perr_hldr_n = cmp_io_sync_en ? mtbl_perr : mtbl_perr_hldr|mtbl_perr ; |
| 813 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 mtbl_perr_hldr_ff |
| 814 | ( |
| 815 | .scan_in(mtbl_perr_hldr_ff_scanin), |
| 816 | .scan_out(mtbl_perr_hldr_ff_scanout), |
| 817 | .dout (mtbl_perr_hldr), |
| 818 | .l1clk (l1clk), |
| 819 | .din (mtbl_perr_hldr_n), |
| 820 | .siclk(siclk), |
| 821 | .soclk(soclk) |
| 822 | ); |
| 823 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_1 mondotbl_pe_f_ff |
| 824 | ( |
| 825 | .scan_in(mondotbl_pe_f_ff_scanin), |
| 826 | .scan_out(mondotbl_pe_f_ff_scanout), |
| 827 | .dout (mondotbl_pe_f), |
| 828 | .l1clk (l1clk), |
| 829 | .en (cmp_io_sync_en), |
| 830 | .din (mtbl_perr_hldr), |
| 831 | .siclk(siclk), |
| 832 | .soclk(soclk) |
| 833 | ); |
| 834 | |
| 835 | |
| 836 | |
| 837 | |
| 838 | |
| 839 | //*************************************************** |
| 840 | //// hold for capturing new synd and ue //// |
| 841 | //assign iobuf_ue_vld_n = cmp_io_sync_en ? (iobuf_vld&iobuf_dout_d1_ue) : |
| 842 | //(iobuf_vld&iobuf_dout_d1_ue)|iobuf_ue_vld; |
| 843 | //jlau_dff #(1) iobuf_ue_vld_ff (.din(iobuf_ue_vld_n), .clk(l2clk), .q(iobuf_ue_vld) ); |
| 844 | // |
| 845 | //// signal for domain crossing //// |
| 846 | //jlau_dffe #(1) iobuf_ue_f_ff ( .din(iobuf_ue_vld), .clk(l2clk), .en(cmp_io_sync_en), |
| 847 | //.q(iobuf_ue_f) ); |
| 848 | //***************************************************/ |
| 849 | |
| 850 | //// |
| 851 | ncu_c2ifd_ctl_msff_ctl_macro__width_3 cpu_mondo_cpu_id_d1_ff |
| 852 | ( |
| 853 | .scan_in(cpu_mondo_cpu_id_d1_ff_scanin), |
| 854 | .scan_out(cpu_mondo_cpu_id_d1_ff_scanout), |
| 855 | .dout (cpu_mondo_cpu_id_d1[2:0]), |
| 856 | .l1clk (l1clk), |
| 857 | .din (pcx_ncu_data[122:120]), |
| 858 | .siclk(siclk), |
| 859 | .soclk(soclk) |
| 860 | ); |
| 861 | ncu_c2ifd_ctl_msff_ctl_macro__width_3 cpu_mondo_cpu_id_d2_ff |
| 862 | ( |
| 863 | .scan_in(cpu_mondo_cpu_id_d2_ff_scanin), |
| 864 | .scan_out(cpu_mondo_cpu_id_d2_ff_scanout), |
| 865 | .dout (cpu_mondo_cpu_id_d2[2:0]), |
| 866 | .l1clk (l1clk), |
| 867 | .din (cpu_mondo_cpu_id_d1[2:0]), |
| 868 | .siclk(siclk), |
| 869 | .soclk(soclk) |
| 870 | ); |
| 871 | //// |
| 872 | ncu_c2ifd_ctl_msff_ctl_macro__width_3 cpu_mondo_thr_id_d1_ff |
| 873 | ( |
| 874 | .scan_in(cpu_mondo_thr_id_d1_ff_scanin), |
| 875 | .scan_out(cpu_mondo_thr_id_d1_ff_scanout), |
| 876 | .dout (cpu_mondo_thr_id_d1[2:0]), |
| 877 | .l1clk (l1clk), |
| 878 | .din (pcx_ncu_data[119:117]), |
| 879 | .siclk(siclk), |
| 880 | .soclk(soclk) |
| 881 | ); |
| 882 | ncu_c2ifd_ctl_msff_ctl_macro__width_3 cpu_mondo_thr_id_d2_ff |
| 883 | ( |
| 884 | .scan_in(cpu_mondo_thr_id_d2_ff_scanin), |
| 885 | .scan_out(cpu_mondo_thr_id_d2_ff_scanout), |
| 886 | .dout (cpu_mondo_thr_id_d2[2:0]), |
| 887 | .l1clk (l1clk), |
| 888 | .din (cpu_mondo_thr_id_d1[2:0]), |
| 889 | .siclk(siclk), |
| 890 | .soclk(soclk) |
| 891 | ); |
| 892 | //// |
| 893 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 cpu_mondo_bis_d1_ff |
| 894 | ( |
| 895 | .scan_in(cpu_mondo_bis_d1_ff_scanin), |
| 896 | .scan_out(cpu_mondo_bis_d1_ff_scanout), |
| 897 | .dout (cpu_mondo_bis_d1), |
| 898 | .l1clk (l1clk), |
| 899 | .din (pcx_ncu_data[114]), |
| 900 | .siclk(siclk), |
| 901 | .soclk(soclk) |
| 902 | ); |
| 903 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 cpu_mondo_bis_d2_ff |
| 904 | ( |
| 905 | .scan_in(cpu_mondo_bis_d2_ff_scanin), |
| 906 | .scan_out(cpu_mondo_bis_d2_ff_scanout), |
| 907 | .dout (cpu_mondo_bis_d2), |
| 908 | .l1clk (l1clk), |
| 909 | .din (cpu_mondo_bis_d1), |
| 910 | .siclk(siclk), |
| 911 | .soclk(soclk) |
| 912 | ); |
| 913 | //// |
| 914 | ncu_c2ifd_ctl_msff_ctl_macro__width_8 cpu_mondo_addr10_3_d1_ff |
| 915 | ( |
| 916 | .scan_in(cpu_mondo_addr10_3_d1_ff_scanin), |
| 917 | .scan_out(cpu_mondo_addr10_3_d1_ff_scanout), |
| 918 | .dout (cpu_mondo_addr10_3_d1[7:0]), |
| 919 | .l1clk (l1clk), |
| 920 | .din (pcx_ncu_data[74:67]), |
| 921 | .siclk(siclk), |
| 922 | .soclk(soclk) |
| 923 | ); |
| 924 | ncu_c2ifd_ctl_msff_ctl_macro__width_8 cpu_mondo_addr10_3_d2_ff |
| 925 | ( |
| 926 | .scan_in(cpu_mondo_addr10_3_d2_ff_scanin), |
| 927 | .scan_out(cpu_mondo_addr10_3_d2_ff_scanout), |
| 928 | .dout (cpu_mondo_addr10_3_d2[7:0]), |
| 929 | .l1clk (l1clk), |
| 930 | .din (cpu_mondo_addr10_3_d1[7:0]), |
| 931 | .siclk(siclk), |
| 932 | .soclk(soclk) |
| 933 | ); |
| 934 | //// |
| 935 | ncu_c2ifd_ctl_msff_ctl_macro__width_8 cpu_mondo_size_d1_ff |
| 936 | ( |
| 937 | .scan_in(cpu_mondo_size_d1_ff_scanin), |
| 938 | .scan_out(cpu_mondo_size_d1_ff_scanout), |
| 939 | .dout (cpu_mondo_size_d1[7:0]), |
| 940 | .l1clk (l1clk), |
| 941 | .din (pcx_ncu_data[111:104]), |
| 942 | .siclk(siclk), |
| 943 | .soclk(soclk) |
| 944 | ); |
| 945 | ncu_c2ifd_ctl_msff_ctl_macro__width_8 cpu_mondo_size_d2_ff |
| 946 | ( |
| 947 | .scan_in(cpu_mondo_size_d2_ff_scanin), |
| 948 | .scan_out(cpu_mondo_size_d2_ff_scanout), |
| 949 | .dout (cpu_mondo_size_d2[7:0]), |
| 950 | .l1clk (l1clk), |
| 951 | .din (cpu_mondo_size_d1[7:0]), |
| 952 | .siclk(siclk), |
| 953 | .soclk(soclk) |
| 954 | ); |
| 955 | //// |
| 956 | ncu_c2ifd_ctl_msff_ctl_macro__width_64 pcx_pkt_data_d1_ff |
| 957 | ( |
| 958 | .scan_in(pcx_pkt_data_d1_ff_scanin), |
| 959 | .scan_out(pcx_pkt_data_d1_ff_scanout), |
| 960 | .dout (pcx_pkt_data_d1[63:0]), |
| 961 | .l1clk (l1clk), |
| 962 | .din (pcx_ncu_data[63:0]), |
| 963 | .siclk(siclk), |
| 964 | .soclk(soclk) |
| 965 | ); |
| 966 | ncu_c2ifd_ctl_msff_ctl_macro__width_64 pcx_pkt_data_d2_ff |
| 967 | ( |
| 968 | .scan_in(pcx_pkt_data_d2_ff_scanin), |
| 969 | .scan_out(pcx_pkt_data_d2_ff_scanout), |
| 970 | .dout (pcx_pkt_data_d2[63:0]), |
| 971 | .l1clk (l1clk), |
| 972 | .din (pcx_pkt_data_d1[63:0]), |
| 973 | .siclk(siclk), |
| 974 | .soclk(soclk) |
| 975 | ); |
| 976 | |
| 977 | assign cpu_mondo_cpu_id_dec_d2[7:0] = 8'b0000_0001 << cpu_mondo_cpu_id_d2[2:0]; |
| 978 | |
| 979 | //assign mb0_intbuf_sel = mb0_run & mb0_intbuf_wr_en; |
| 980 | assign intbuf_din[143:0] = mb0_run ? {18{mb0_wdata[7:0]}} : mondo2cpu_pkt[143:0] ; |
| 981 | |
| 982 | |
| 983 | //////////////////////////////// |
| 984 | ////// intbuf par and ecc ////// |
| 985 | //ncu_eccgen11_ctl c2ifdeccgen11 (.din({cpu_mondo_cpu_id_dec_d2[7:0],cpu_mondo_thr_id_d2[2:0]}), |
| 986 | ncu_eccgen11_ctl c2ifdeccgen11 (.din({mondo2cpu_pkt[121:114],mondo2cpu_pkt[104:102]}), |
| 987 | //.dout(mondo2cpu_pkt[126:122]) ); |
| 988 | .dout(mondofifoecc[4:0]) ); |
| 989 | assign mondo2cpu_pkt[126:122]=mondofifoecc[4:0]; |
| 990 | |
| 991 | assign mondo2cpu_pkt[127] = ~^{mondo2cpu_pkt[0], mondo2cpu_pkt[17],mondo2cpu_pkt[34], |
| 992 | mondo2cpu_pkt[51],mondo2cpu_pkt[68],mondo2cpu_pkt[86],mondo2cpu_pkt[106]}; |
| 993 | assign mondo2cpu_pkt[128] = ~^{mondo2cpu_pkt[1], mondo2cpu_pkt[18],mondo2cpu_pkt[35], |
| 994 | mondo2cpu_pkt[52],mondo2cpu_pkt[69],mondo2cpu_pkt[87],mondo2cpu_pkt[107]}; |
| 995 | assign mondo2cpu_pkt[129] = ~^{mondo2cpu_pkt[2], mondo2cpu_pkt[19],mondo2cpu_pkt[36], |
| 996 | mondo2cpu_pkt[53],mondo2cpu_pkt[70],mondo2cpu_pkt[88],mondo2cpu_pkt[108]}; |
| 997 | assign mondo2cpu_pkt[130] = ~^{mondo2cpu_pkt[3], mondo2cpu_pkt[20],mondo2cpu_pkt[37], |
| 998 | mondo2cpu_pkt[54],mondo2cpu_pkt[71],mondo2cpu_pkt[89],mondo2cpu_pkt[109]}; |
| 999 | assign mondo2cpu_pkt[131] = ~^{mondo2cpu_pkt[4], mondo2cpu_pkt[21],mondo2cpu_pkt[38], |
| 1000 | mondo2cpu_pkt[55],mondo2cpu_pkt[72],mondo2cpu_pkt[90],mondo2cpu_pkt[110]}; |
| 1001 | assign mondo2cpu_pkt[132] = ~^{mondo2cpu_pkt[5], mondo2cpu_pkt[22],mondo2cpu_pkt[39], |
| 1002 | mondo2cpu_pkt[56],mondo2cpu_pkt[73],mondo2cpu_pkt[91],mondo2cpu_pkt[111]}; |
| 1003 | assign mondo2cpu_pkt[133] = ~^{mondo2cpu_pkt[6], mondo2cpu_pkt[23],mondo2cpu_pkt[40], |
| 1004 | mondo2cpu_pkt[57],mondo2cpu_pkt[74],mondo2cpu_pkt[92],mondo2cpu_pkt[112]}; |
| 1005 | assign mondo2cpu_pkt[134] = ~^{mondo2cpu_pkt[7], mondo2cpu_pkt[24],mondo2cpu_pkt[41], |
| 1006 | mondo2cpu_pkt[58],mondo2cpu_pkt[75],mondo2cpu_pkt[93],mondo2cpu_pkt[113]}; |
| 1007 | assign mondo2cpu_pkt[135] = ~^{mondo2cpu_pkt[8], mondo2cpu_pkt[25],mondo2cpu_pkt[42], |
| 1008 | mondo2cpu_pkt[59],mondo2cpu_pkt[76],mondo2cpu_pkt[94]}; |
| 1009 | assign mondo2cpu_pkt[136] = ~^{mondo2cpu_pkt[9], mondo2cpu_pkt[26],mondo2cpu_pkt[43], |
| 1010 | mondo2cpu_pkt[60],mondo2cpu_pkt[78],mondo2cpu_pkt[95]}; |
| 1011 | assign mondo2cpu_pkt[137] = ~^{mondo2cpu_pkt[10],mondo2cpu_pkt[27],mondo2cpu_pkt[44], |
| 1012 | mondo2cpu_pkt[61],mondo2cpu_pkt[79],mondo2cpu_pkt[96]}; |
| 1013 | assign mondo2cpu_pkt[138] = ~^{mondo2cpu_pkt[11],mondo2cpu_pkt[28],mondo2cpu_pkt[45], |
| 1014 | mondo2cpu_pkt[62],mondo2cpu_pkt[80],mondo2cpu_pkt[97]}; |
| 1015 | assign mondo2cpu_pkt[139] = ~^{mondo2cpu_pkt[12],mondo2cpu_pkt[29],mondo2cpu_pkt[46], |
| 1016 | mondo2cpu_pkt[63],mondo2cpu_pkt[81],mondo2cpu_pkt[98]}; |
| 1017 | assign mondo2cpu_pkt[140] = ~^{mondo2cpu_pkt[13],mondo2cpu_pkt[30],mondo2cpu_pkt[47], |
| 1018 | mondo2cpu_pkt[64],mondo2cpu_pkt[82],mondo2cpu_pkt[79]}; |
| 1019 | assign mondo2cpu_pkt[141] = ~^{mondo2cpu_pkt[14],mondo2cpu_pkt[31],mondo2cpu_pkt[48], |
| 1020 | mondo2cpu_pkt[65],mondo2cpu_pkt[83],mondo2cpu_pkt[100]}; |
| 1021 | assign mondo2cpu_pkt[142] = ~^{mondo2cpu_pkt[15],mondo2cpu_pkt[32],mondo2cpu_pkt[49], |
| 1022 | mondo2cpu_pkt[66],mondo2cpu_pkt[84],mondo2cpu_pkt[101]}; |
| 1023 | assign mondo2cpu_pkt[143] = ~^{mondo2cpu_pkt[16],mondo2cpu_pkt[33],mondo2cpu_pkt[50], |
| 1024 | mondo2cpu_pkt[67],mondo2cpu_pkt[85],mondo2cpu_pkt[105]}; |
| 1025 | |
| 1026 | ncu_c2ifd_ctl_msff_ctl_macro__width_122 mondo2cpu_pkt_ff |
| 1027 | ( |
| 1028 | .scan_in(mondo2cpu_pkt_ff_scanin), |
| 1029 | .scan_out(mondo2cpu_pkt_ff_scanout), |
| 1030 | .dout (mondo2cpu_pkta[121:0]), |
| 1031 | .l1clk (l1clk), |
| 1032 | .din (mondo2cpu_pkt_n[121:0]), |
| 1033 | .siclk(siclk), |
| 1034 | .soclk(soclk) |
| 1035 | ); |
| 1036 | |
| 1037 | // make sure to set the err bit when perr happen // |
| 1038 | assign mondo2cpu_pkt[121:0] = {mondo2cpu_pkta[121:108],mondo2cpu_pkta[107]|mtbl_perr,mondo2cpu_pkta[106:0]} ; |
| 1039 | |
| 1040 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 cpu_mondo_rd_d3_ff |
| 1041 | ( |
| 1042 | .scan_in(cpu_mondo_rd_d3_ff_scanin), |
| 1043 | .scan_out(cpu_mondo_rd_d3_ff_scanout), |
| 1044 | .dout (cpu_mondo_rd_d3), |
| 1045 | .l1clk (l1clk), |
| 1046 | .din (cpu_mondo_rd_d2), |
| 1047 | .siclk(siclk), |
| 1048 | .soclk(soclk) |
| 1049 | ); |
| 1050 | |
| 1051 | assign mondo2cpu_pkt_n[121:0] = |
| 1052 | cpu_mondo_rd_d2 ? |
| 1053 | ////// read ack to CPU //// |
| 1054 | {cpu_mondo_cpu_id_dec_d2[7:0], // cpu ID [153:146],[121:114] |
| 1055 | 1'b1, // valid [145] ,[113] |
| 1056 | `CPX_LOAD_RET, // ret type [144:141],[112:109] |
| 1057 | 1'b0, // l2miss [140] ,[108] |
| 1058 | {cpu_mondo_addr_invld_d2,1'b0},// error [139:138],[107:106] |
| 1059 | 1'b1, // NC [137] ,[105] |
| 1060 | cpu_mondo_thr_id_d2[2:0], // thread ID [136:134],[104:102] |
| 1061 | 1'b0, // wv [133] ,[101] |
| 1062 | 2'b0, // w/mmuid [132:131],[100:99] |
| 1063 | 1'b0, // w/f4b [130] ,[98] |
| 1064 | 2'b0, // un-used [129:128],[97:96]== |
| 1065 | mondo_dout[63:32], // [95:64] |
| 1066 | mondo_dout[63:0]} : // intr status [63:0]== |
| 1067 | ////// write ack to CPU ////// |
| 1068 | {cpu_mondo_cpu_id_dec_d2[7:0], // cpu ID [153:146],[121:114] |
| 1069 | 1'b1, // valid [145] ,[113] |
| 1070 | `CPX_ST_ACK, // return type [144:141],[112:109] |
| 1071 | 1'b0, // l2miss [140] ,[108] |
| 1072 | 2'b0, // error [139:138],[107:106] |
| 1073 | 1'b1, // NC [137] ,[105] |
| 1074 | cpu_mondo_thr_id_d2[2:0], // thread ID [136:134],[104:102] |
| 1075 | 6'b0, // unused [133:128],[101:96]== |
| 1076 | 2'b0, // unused [127:126],[95:94] |
| 1077 | cpu_mondo_bis_d2, // bis [125] ,[93] |
| 1078 | 2'b0, // unused [124:123],[92:91] |
| 1079 | cpu_mondo_addr10_3_d2[2:1], // addr[5:4] [122:121],[90:89] |
| 1080 | cpu_mondo_cpu_id_d2[2:0], // cpu_id [120:118],[88:86] |
| 1081 | 1'b0, // [117] ,[85] |
| 1082 | cpu_mondo_addr10_3_d2[7:3], // addr[10:6] [116:112],[84:80] |
| 1083 | 7'b0, // unused [111:105],[79:73] |
| 1084 | cpu_mondo_addr10_3_d2[0], // addr[3] [104] ,[72] |
| 1085 | cpu_mondo_size_d2[7:0], // byte mask [103:96] ,[71:64] |
| 1086 | //32'b0, // unused [95:64] |
| 1087 | pcx_pkt_data_d2[63:0] }; // [63:0] ,[63:0] |
| 1088 | |
| 1089 | |
| 1090 | /***************************************************************** |
| 1091 | * Interrupt status table, Mondo data0/data1/busy table read data (TAP read) |
| 1092 | *****************************************************************/ |
| 1093 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 tap_mondo_dout_d2_ff |
| 1094 | ( |
| 1095 | .scan_in(tap_mondo_dout_d2_ff_scanin), |
| 1096 | .scan_out(tap_mondo_dout_d2_ff_scanout), |
| 1097 | .dout (tap_mondo_dout_d2[63:0]), |
| 1098 | .l1clk (l1clk), |
| 1099 | .en (tap_mondo_rd_d2), |
| 1100 | .din (mondo_dout[63:0]), |
| 1101 | .siclk(siclk), |
| 1102 | .soclk(soclk) |
| 1103 | ); |
| 1104 | |
| 1105 | // Send result back to BSC clock domain |
| 1106 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 tap_mondo_dout_d2_f_ff |
| 1107 | ( |
| 1108 | .scan_in(tap_mondo_dout_d2_f_ff_scanin), |
| 1109 | .scan_out(tap_mondo_dout_d2_f_ff_scanout), |
| 1110 | .dout (tap_mondo_dout_d2_f[63:0]), |
| 1111 | .l1clk (l1clk), |
| 1112 | .en (cmp_io_sync_en), |
| 1113 | .din (tap_mondo_dout_d2[63:0]), |
| 1114 | .siclk(siclk), |
| 1115 | .soclk(soclk) |
| 1116 | ); |
| 1117 | |
| 1118 | |
| 1119 | //=================================================================== |
| 1120 | //=================================================================== |
| 1121 | //================================================ mondo_busy ======= |
| 1122 | |
| 1123 | ncu_c2ifd_ctl_msff_ctl_macro__width_6 wr1_a_d1_ff |
| 1124 | ( |
| 1125 | .scan_in(wr1_a_d1_ff_scanin), |
| 1126 | .scan_out(wr1_a_d1_ff_scanout), |
| 1127 | .dout (wr1_a_d1[5:0]), |
| 1128 | .l1clk (l1clk), |
| 1129 | .din (mondo_busy_addr_p1[5:0]), |
| 1130 | .siclk(siclk), |
| 1131 | .soclk(soclk) |
| 1132 | ); |
| 1133 | |
| 1134 | ncu_c2ifd_ctl_msff_ctl_macro__width_6 wr2_a_d1_ff |
| 1135 | ( |
| 1136 | .scan_in(wr2_a_d1_ff_scanin), |
| 1137 | .scan_out(wr2_a_d1_ff_scanout), |
| 1138 | .dout (wr2_a_d1[5:0]), |
| 1139 | .l1clk (l1clk), |
| 1140 | .din (mondo_busy_addr_p2[5:0]), |
| 1141 | .siclk(siclk), |
| 1142 | .soclk(soclk) |
| 1143 | ); |
| 1144 | |
| 1145 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 din1_d1_ff |
| 1146 | ( |
| 1147 | .scan_in(din1_d1_ff_scanin), |
| 1148 | .scan_out(din1_d1_ff_scanout), |
| 1149 | .dout (din1_d1), |
| 1150 | .l1clk (l1clk), |
| 1151 | .din (mondo_busy_din_p1), |
| 1152 | .siclk(siclk), |
| 1153 | .soclk(soclk) |
| 1154 | ); |
| 1155 | |
| 1156 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 din2_d1_ff |
| 1157 | ( |
| 1158 | .scan_in(din2_d1_ff_scanin), |
| 1159 | .scan_out(din2_d1_ff_scanout), |
| 1160 | .dout (din2_d1), |
| 1161 | .l1clk (l1clk), |
| 1162 | .din (mondo_busy_din_p2), |
| 1163 | .siclk(siclk), |
| 1164 | .soclk(soclk) |
| 1165 | ); |
| 1166 | |
| 1167 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 wen1_d1_ff |
| 1168 | ( |
| 1169 | .scan_in(wen1_d1_ff_scanin), |
| 1170 | .scan_out(wen1_d1_ff_scanout), |
| 1171 | .dout (wen1_d1), |
| 1172 | .l1clk (l1clk), |
| 1173 | .din (mondo_busy_wr_p1), |
| 1174 | .siclk(siclk), |
| 1175 | .soclk(soclk) |
| 1176 | ); |
| 1177 | |
| 1178 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 wen2_d1_ff |
| 1179 | ( |
| 1180 | .scan_in(wen2_d1_ff_scanin), |
| 1181 | .scan_out(wen2_d1_ff_scanout), |
| 1182 | .dout (wen2_d1), |
| 1183 | .l1clk (l1clk), |
| 1184 | .din (mondo_busy_wr_p2), |
| 1185 | .siclk(siclk), |
| 1186 | .soclk(soclk) |
| 1187 | ); |
| 1188 | |
| 1189 | assign wr1_a_dec_d1[63:0] = 64'h0000_0000_0000_0001 << wr1_a_d1[5:0]; |
| 1190 | |
| 1191 | assign wr2_a_dec_d1[63:0] = 64'h0000_0000_0000_0001 << wr2_a_d1[5:0]; |
| 1192 | |
| 1193 | assign wen1_dec_d1[63:0] = {64{wen1_d1}} & wr1_a_dec_d1[63:0]; |
| 1194 | |
| 1195 | assign wen2_dec_d1[63:0] = {64{wen2_d1}} & wr2_a_dec_d1[63:0]; |
| 1196 | |
| 1197 | assign vec_n[0] = wen1_dec_d1[0] ? din1_d1 : |
| 1198 | wen2_dec_d1[0] ? din2_d1 : vec[0] ; |
| 1199 | assign vec_n[1] = wen1_dec_d1[1] ? din1_d1 : |
| 1200 | wen2_dec_d1[1] ? din2_d1 : vec[1] ; |
| 1201 | assign vec_n[2] = wen1_dec_d1[2] ? din1_d1 : |
| 1202 | wen2_dec_d1[2] ? din2_d1 : vec[2] ; |
| 1203 | assign vec_n[3] = wen1_dec_d1[3] ? din1_d1 : |
| 1204 | wen2_dec_d1[3] ? din2_d1 : vec[3] ; |
| 1205 | assign vec_n[4] = wen1_dec_d1[4] ? din1_d1 : |
| 1206 | wen2_dec_d1[4] ? din2_d1 : vec[4] ; |
| 1207 | assign vec_n[5] = wen1_dec_d1[5] ? din1_d1 : |
| 1208 | wen2_dec_d1[5] ? din2_d1 : vec[5] ; |
| 1209 | assign vec_n[6] = wen1_dec_d1[6] ? din1_d1 : |
| 1210 | wen2_dec_d1[6] ? din2_d1 : vec[6] ; |
| 1211 | assign vec_n[7] = wen1_dec_d1[7] ? din1_d1 : |
| 1212 | wen2_dec_d1[7] ? din2_d1 : vec[7] ; |
| 1213 | assign vec_n[8] = wen1_dec_d1[8] ? din1_d1 : |
| 1214 | wen2_dec_d1[8] ? din2_d1 : vec[8] ; |
| 1215 | assign vec_n[9] = wen1_dec_d1[9] ? din1_d1 : |
| 1216 | wen2_dec_d1[9] ? din2_d1 : vec[9] ; |
| 1217 | assign vec_n[10] = wen1_dec_d1[10] ? din1_d1 : |
| 1218 | wen2_dec_d1[10] ? din2_d1 : vec[10] ; |
| 1219 | assign vec_n[11] = wen1_dec_d1[11] ? din1_d1 : |
| 1220 | wen2_dec_d1[11] ? din2_d1 : vec[11] ; |
| 1221 | assign vec_n[12] = wen1_dec_d1[12] ? din1_d1 : |
| 1222 | wen2_dec_d1[12] ? din2_d1 : vec[12] ; |
| 1223 | assign vec_n[13] = wen1_dec_d1[13] ? din1_d1 : |
| 1224 | wen2_dec_d1[13] ? din2_d1 : vec[13] ; |
| 1225 | assign vec_n[14] = wen1_dec_d1[14] ? din1_d1 : |
| 1226 | wen2_dec_d1[14] ? din2_d1 : vec[14] ; |
| 1227 | assign vec_n[15] = wen1_dec_d1[15] ? din1_d1 : |
| 1228 | wen2_dec_d1[15] ? din2_d1 : vec[15] ; |
| 1229 | assign vec_n[16] = wen1_dec_d1[16] ? din1_d1 : |
| 1230 | wen2_dec_d1[16] ? din2_d1 : vec[16] ; |
| 1231 | assign vec_n[17] = wen1_dec_d1[17] ? din1_d1 : |
| 1232 | wen2_dec_d1[17] ? din2_d1 : vec[17] ; |
| 1233 | assign vec_n[18] = wen1_dec_d1[18] ? din1_d1 : |
| 1234 | wen2_dec_d1[18] ? din2_d1 : vec[18] ; |
| 1235 | assign vec_n[19] = wen1_dec_d1[19] ? din1_d1 : |
| 1236 | wen2_dec_d1[19] ? din2_d1 : vec[19] ; |
| 1237 | assign vec_n[20] = wen1_dec_d1[20] ? din1_d1 : |
| 1238 | wen2_dec_d1[20] ? din2_d1 : vec[20] ; |
| 1239 | assign vec_n[21] = wen1_dec_d1[21] ? din1_d1 : |
| 1240 | wen2_dec_d1[21] ? din2_d1 : vec[21] ; |
| 1241 | assign vec_n[22] = wen1_dec_d1[22] ? din1_d1 : |
| 1242 | wen2_dec_d1[22] ? din2_d1 : vec[22] ; |
| 1243 | assign vec_n[23] = wen1_dec_d1[23] ? din1_d1 : |
| 1244 | wen2_dec_d1[23] ? din2_d1 : vec[23] ; |
| 1245 | assign vec_n[24] = wen1_dec_d1[24] ? din1_d1 : |
| 1246 | wen2_dec_d1[24] ? din2_d1 : vec[24] ; |
| 1247 | assign vec_n[25] = wen1_dec_d1[25] ? din1_d1 : |
| 1248 | wen2_dec_d1[25] ? din2_d1 : vec[25] ; |
| 1249 | assign vec_n[26] = wen1_dec_d1[26] ? din1_d1 : |
| 1250 | wen2_dec_d1[26] ? din2_d1 : vec[26] ; |
| 1251 | assign vec_n[27] = wen1_dec_d1[27] ? din1_d1 : |
| 1252 | wen2_dec_d1[27] ? din2_d1 : vec[27] ; |
| 1253 | assign vec_n[28] = wen1_dec_d1[28] ? din1_d1 : |
| 1254 | wen2_dec_d1[28] ? din2_d1 : vec[28] ; |
| 1255 | assign vec_n[29] = wen1_dec_d1[29] ? din1_d1 : |
| 1256 | wen2_dec_d1[29] ? din2_d1 : vec[29] ; |
| 1257 | assign vec_n[30] = wen1_dec_d1[30] ? din1_d1 : |
| 1258 | wen2_dec_d1[30] ? din2_d1 : vec[30] ; |
| 1259 | assign vec_n[31] = wen1_dec_d1[31] ? din1_d1 : |
| 1260 | wen2_dec_d1[31] ? din2_d1 : vec[31] ; |
| 1261 | assign vec_n[32] = wen1_dec_d1[32] ? din1_d1 : |
| 1262 | wen2_dec_d1[32] ? din2_d1 : vec[32] ; |
| 1263 | assign vec_n[33] = wen1_dec_d1[33] ? din1_d1 : |
| 1264 | wen2_dec_d1[33] ? din2_d1 : vec[33] ; |
| 1265 | assign vec_n[34] = wen1_dec_d1[34] ? din1_d1 : |
| 1266 | wen2_dec_d1[34] ? din2_d1 : vec[34] ; |
| 1267 | assign vec_n[35] = wen1_dec_d1[35] ? din1_d1 : |
| 1268 | wen2_dec_d1[35] ? din2_d1 : vec[35] ; |
| 1269 | assign vec_n[36] = wen1_dec_d1[36] ? din1_d1 : |
| 1270 | wen2_dec_d1[36] ? din2_d1 : vec[36] ; |
| 1271 | assign vec_n[37] = wen1_dec_d1[37] ? din1_d1 : |
| 1272 | wen2_dec_d1[37] ? din2_d1 : vec[37] ; |
| 1273 | assign vec_n[38] = wen1_dec_d1[38] ? din1_d1 : |
| 1274 | wen2_dec_d1[38] ? din2_d1 : vec[38] ; |
| 1275 | assign vec_n[39] = wen1_dec_d1[39] ? din1_d1 : |
| 1276 | wen2_dec_d1[39] ? din2_d1 : vec[39] ; |
| 1277 | assign vec_n[40] = wen1_dec_d1[40] ? din1_d1 : |
| 1278 | wen2_dec_d1[40] ? din2_d1 : vec[40] ; |
| 1279 | assign vec_n[41] = wen1_dec_d1[41] ? din1_d1 : |
| 1280 | wen2_dec_d1[41] ? din2_d1 : vec[41] ; |
| 1281 | assign vec_n[42] = wen1_dec_d1[42] ? din1_d1 : |
| 1282 | wen2_dec_d1[42] ? din2_d1 : vec[42] ; |
| 1283 | assign vec_n[43] = wen1_dec_d1[43] ? din1_d1 : |
| 1284 | wen2_dec_d1[43] ? din2_d1 : vec[43] ; |
| 1285 | assign vec_n[44] = wen1_dec_d1[44] ? din1_d1 : |
| 1286 | wen2_dec_d1[44] ? din2_d1 : vec[44] ; |
| 1287 | assign vec_n[45] = wen1_dec_d1[45] ? din1_d1 : |
| 1288 | wen2_dec_d1[45] ? din2_d1 : vec[45] ; |
| 1289 | assign vec_n[46] = wen1_dec_d1[46] ? din1_d1 : |
| 1290 | wen2_dec_d1[46] ? din2_d1 : vec[46] ; |
| 1291 | assign vec_n[47] = wen1_dec_d1[47] ? din1_d1 : |
| 1292 | wen2_dec_d1[47] ? din2_d1 : vec[47] ; |
| 1293 | assign vec_n[48] = wen1_dec_d1[48] ? din1_d1 : |
| 1294 | wen2_dec_d1[48] ? din2_d1 : vec[48] ; |
| 1295 | assign vec_n[49] = wen1_dec_d1[49] ? din1_d1 : |
| 1296 | wen2_dec_d1[49] ? din2_d1 : vec[49] ; |
| 1297 | assign vec_n[50] = wen1_dec_d1[50] ? din1_d1 : |
| 1298 | wen2_dec_d1[50] ? din2_d1 : vec[50] ; |
| 1299 | assign vec_n[51] = wen1_dec_d1[51] ? din1_d1 : |
| 1300 | wen2_dec_d1[51] ? din2_d1 : vec[51] ; |
| 1301 | assign vec_n[52] = wen1_dec_d1[52] ? din1_d1 : |
| 1302 | wen2_dec_d1[52] ? din2_d1 : vec[52] ; |
| 1303 | assign vec_n[53] = wen1_dec_d1[53] ? din1_d1 : |
| 1304 | wen2_dec_d1[53] ? din2_d1 : vec[53] ; |
| 1305 | assign vec_n[54] = wen1_dec_d1[54] ? din1_d1 : |
| 1306 | wen2_dec_d1[54] ? din2_d1 : vec[54] ; |
| 1307 | assign vec_n[55] = wen1_dec_d1[55] ? din1_d1 : |
| 1308 | wen2_dec_d1[55] ? din2_d1 : vec[55] ; |
| 1309 | assign vec_n[56] = wen1_dec_d1[56] ? din1_d1 : |
| 1310 | wen2_dec_d1[56] ? din2_d1 : vec[56] ; |
| 1311 | assign vec_n[57] = wen1_dec_d1[57] ? din1_d1 : |
| 1312 | wen2_dec_d1[57] ? din2_d1 : vec[57] ; |
| 1313 | assign vec_n[58] = wen1_dec_d1[58] ? din1_d1 : |
| 1314 | wen2_dec_d1[58] ? din2_d1 : vec[58] ; |
| 1315 | assign vec_n[59] = wen1_dec_d1[59] ? din1_d1 : |
| 1316 | wen2_dec_d1[59] ? din2_d1 : vec[59] ; |
| 1317 | assign vec_n[60] = wen1_dec_d1[60] ? din1_d1 : |
| 1318 | wen2_dec_d1[60] ? din2_d1 : vec[60] ; |
| 1319 | assign vec_n[61] = wen1_dec_d1[61] ? din1_d1 : |
| 1320 | wen2_dec_d1[61] ? din2_d1 : vec[61] ; |
| 1321 | assign vec_n[62] = wen1_dec_d1[62] ? din1_d1 : |
| 1322 | wen2_dec_d1[62] ? din2_d1 : vec[62] ; |
| 1323 | assign vec_n[63] = wen1_dec_d1[63] ? din1_d1 : |
| 1324 | wen2_dec_d1[63] ? din2_d1 : vec[63] ; |
| 1325 | |
| 1326 | // FF's for storage |
| 1327 | |
| 1328 | |
| 1329 | assign vec_n_inv[63:0] = ~vec_n[63:0] ; |
| 1330 | assign vec[63:0] = ~vec_inv[63:0] ; |
| 1331 | |
| 1332 | ncu_c2ifd_ctl_msff_ctl_macro__width_64 vec_ff |
| 1333 | ( |
| 1334 | .scan_in(vec_ff_scanin), |
| 1335 | .scan_out(vec_ff_scanout), |
| 1336 | .dout (vec_inv[63:0]), |
| 1337 | .l1clk (l1clk), |
| 1338 | .din (vec_n_inv[63:0]), |
| 1339 | .siclk(siclk), |
| 1340 | .soclk(soclk) |
| 1341 | ); |
| 1342 | // send vec to other clock domanin |
| 1343 | ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 mondo_busy_vec_ff |
| 1344 | ( |
| 1345 | .scan_in(mondo_busy_vec_ff_scanin), |
| 1346 | .scan_out(mondo_busy_vec_ff_scanout), |
| 1347 | .dout (mondo_busy_vec_f[63:0]), |
| 1348 | .l1clk (l1clk), |
| 1349 | .en (cmp_io_sync_en), |
| 1350 | .din (vec[63:0]), |
| 1351 | .siclk(siclk), |
| 1352 | .soclk(soclk) |
| 1353 | ); |
| 1354 | // flop read address |
| 1355 | ncu_c2ifd_ctl_msff_ctl_macro__width_6 rd_a_d1_ff |
| 1356 | ( |
| 1357 | .scan_in(rd_a_d1_ff_scanin), |
| 1358 | .scan_out(rd_a_d1_ff_scanout), |
| 1359 | .dout (rd_a_d1[5:0]), |
| 1360 | .l1clk (l1clk), |
| 1361 | .din (mondo_busy_addr_p0[5:0]), |
| 1362 | .siclk(siclk), |
| 1363 | .soclk(soclk) |
| 1364 | ); |
| 1365 | |
| 1366 | assign rd_a_dec_d1[63:0] = 64'h0000_0000_0000_0001 << rd_a_d1[5:0]; |
| 1367 | |
| 1368 | assign mondo_busy_dout_d1 = |(vec[63:0] & rd_a_dec_d1[63:0]); |
| 1369 | ncu_c2ifd_ctl_msff_ctl_macro__width_1 mondo_busy_dout_d2_ff |
| 1370 | ( |
| 1371 | .scan_in(mondo_busy_dout_d2_ff_scanin), |
| 1372 | .scan_out(mondo_busy_dout_d2_ff_scanout), |
| 1373 | .dout (mondo_busy_dout_d2), |
| 1374 | .l1clk (l1clk), |
| 1375 | .din (mondo_busy_dout_d1), |
| 1376 | .siclk(siclk), |
| 1377 | .soclk(soclk) |
| 1378 | ); |
| 1379 | |
| 1380 | //================================================ mondo_busy ======= |
| 1381 | //=================================================================== |
| 1382 | //=================================================================== |
| 1383 | |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | |
| 1388 | /**** adding clock header ****/ |
| 1389 | ncu_c2ifd_ctl_l1clkhdr_ctl_macro clkgen ( |
| 1390 | .l2clk (l2clk), |
| 1391 | .l1en (1'b1), |
| 1392 | .l1clk (l1clk), |
| 1393 | .pce_ov(pce_ov), |
| 1394 | .stop(stop), |
| 1395 | .se(se) |
| 1396 | ); |
| 1397 | |
| 1398 | /*** building tcu port ***/ |
| 1399 | assign siclk = tcu_aclk; |
| 1400 | assign soclk = tcu_bclk; |
| 1401 | assign se = tcu_scan_en; |
| 1402 | assign pce_ov = tcu_pce_ov; |
| 1403 | assign stop = tcu_clk_stop; |
| 1404 | |
| 1405 | // fixscan start: |
| 1406 | assign pcx_ncu_data_ff_scanin = scan_in ; |
| 1407 | assign pcx_ncu_vld_ff_scanin = pcx_ncu_data_ff_scanout ; |
| 1408 | assign io_mondo_data0_din_ff_scanin = pcx_ncu_vld_ff_scanout ; |
| 1409 | assign io_mondo_data1_din_ff_scanin = io_mondo_data0_din_ff_scanout; |
| 1410 | assign tap_mondo_din_ff_scanin = io_mondo_data1_din_ff_scanout; |
| 1411 | assign mondo_data0_din_d1_ff_scanin = tap_mondo_din_ff_scanout ; |
| 1412 | assign mondo_data0_din_d2_ff_scanin = mondo_data0_din_d1_ff_scanout; |
| 1413 | assign mondo_data1_din_d1_ff_scanin = mondo_data0_din_d2_ff_scanout; |
| 1414 | assign mondo_data1_din_d2_ff_scanin = mondo_data1_din_d1_ff_scanout; |
| 1415 | assign mondo_addr_creg_mbusy_dec_d3_ff_scanin = mondo_data1_din_d2_ff_scanout; |
| 1416 | assign mondo_dout_d1_ff_scanin = mondo_addr_creg_mbusy_dec_d3_ff_scanout; |
| 1417 | assign mondotbl_pei_ff_scanin = mondo_dout_d1_ff_scanout ; |
| 1418 | assign mtbl_perr_hldr_ff_scanin = mondotbl_pei_ff_scanout ; |
| 1419 | assign mondotbl_pe_f_ff_scanin = mtbl_perr_hldr_ff_scanout; |
| 1420 | assign cpu_mondo_cpu_id_d1_ff_scanin = mondotbl_pe_f_ff_scanout ; |
| 1421 | assign cpu_mondo_cpu_id_d2_ff_scanin = cpu_mondo_cpu_id_d1_ff_scanout; |
| 1422 | assign cpu_mondo_thr_id_d1_ff_scanin = cpu_mondo_cpu_id_d2_ff_scanout; |
| 1423 | assign cpu_mondo_thr_id_d2_ff_scanin = cpu_mondo_thr_id_d1_ff_scanout; |
| 1424 | assign cpu_mondo_bis_d1_ff_scanin = cpu_mondo_thr_id_d2_ff_scanout; |
| 1425 | assign cpu_mondo_bis_d2_ff_scanin = cpu_mondo_bis_d1_ff_scanout; |
| 1426 | assign cpu_mondo_addr10_3_d1_ff_scanin = cpu_mondo_bis_d2_ff_scanout; |
| 1427 | assign cpu_mondo_addr10_3_d2_ff_scanin = cpu_mondo_addr10_3_d1_ff_scanout; |
| 1428 | assign cpu_mondo_size_d1_ff_scanin = cpu_mondo_addr10_3_d2_ff_scanout; |
| 1429 | assign cpu_mondo_size_d2_ff_scanin = cpu_mondo_size_d1_ff_scanout; |
| 1430 | assign pcx_pkt_data_d1_ff_scanin = cpu_mondo_size_d2_ff_scanout; |
| 1431 | assign pcx_pkt_data_d2_ff_scanin = pcx_pkt_data_d1_ff_scanout; |
| 1432 | assign mondo2cpu_pkt_ff_scanin = pcx_pkt_data_d2_ff_scanout; |
| 1433 | assign cpu_mondo_rd_d3_ff_scanin = mondo2cpu_pkt_ff_scanout ; |
| 1434 | assign tap_mondo_dout_d2_ff_scanin = cpu_mondo_rd_d3_ff_scanout; |
| 1435 | assign tap_mondo_dout_d2_f_ff_scanin = tap_mondo_dout_d2_ff_scanout; |
| 1436 | assign wr1_a_d1_ff_scanin = tap_mondo_dout_d2_f_ff_scanout; |
| 1437 | assign wr2_a_d1_ff_scanin = wr1_a_d1_ff_scanout ; |
| 1438 | assign din1_d1_ff_scanin = wr2_a_d1_ff_scanout ; |
| 1439 | assign din2_d1_ff_scanin = din1_d1_ff_scanout ; |
| 1440 | assign wen1_d1_ff_scanin = din2_d1_ff_scanout ; |
| 1441 | assign wen2_d1_ff_scanin = wen1_d1_ff_scanout ; |
| 1442 | assign vec_ff_scanin = wen2_d1_ff_scanout ; |
| 1443 | assign mondo_busy_vec_ff_scanin = vec_ff_scanout ; |
| 1444 | assign rd_a_d1_ff_scanin = mondo_busy_vec_ff_scanout; |
| 1445 | assign mondo_busy_dout_d2_ff_scanin = rd_a_d1_ff_scanout ; |
| 1446 | assign scan_out = mondo_busy_dout_d2_ff_scanout; |
| 1447 | // fixscan end: |
| 1448 | endmodule // c2i_fdp |
| 1449 | |
| 1450 | // Local Variables: |
| 1451 | // verilog-auto-sense-defines-constant:t |
| 1452 | // End: |
| 1453 | |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | // any PARAMS parms go into naming of macro |
| 1460 | |
| 1461 | module ncu_c2ifd_ctl_msff_ctl_macro__width_129 ( |
| 1462 | din, |
| 1463 | l1clk, |
| 1464 | scan_in, |
| 1465 | siclk, |
| 1466 | soclk, |
| 1467 | dout, |
| 1468 | scan_out); |
| 1469 | wire [128:0] fdin; |
| 1470 | wire [127:0] so; |
| 1471 | |
| 1472 | input [128:0] din; |
| 1473 | input l1clk; |
| 1474 | input scan_in; |
| 1475 | |
| 1476 | |
| 1477 | input siclk; |
| 1478 | input soclk; |
| 1479 | |
| 1480 | output [128:0] dout; |
| 1481 | output scan_out; |
| 1482 | assign fdin[128:0] = din[128:0]; |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | |
| 1487 | |
| 1488 | |
| 1489 | dff #(129) d0_0 ( |
| 1490 | .l1clk(l1clk), |
| 1491 | .siclk(siclk), |
| 1492 | .soclk(soclk), |
| 1493 | .d(fdin[128:0]), |
| 1494 | .si({scan_in,so[127:0]}), |
| 1495 | .so({so[127:0],scan_out}), |
| 1496 | .q(dout[128:0]) |
| 1497 | ); |
| 1498 | |
| 1499 | |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | endmodule |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | |
| 1523 | |
| 1524 | // any PARAMS parms go into naming of macro |
| 1525 | |
| 1526 | module ncu_c2ifd_ctl_msff_ctl_macro__width_1 ( |
| 1527 | din, |
| 1528 | l1clk, |
| 1529 | scan_in, |
| 1530 | siclk, |
| 1531 | soclk, |
| 1532 | dout, |
| 1533 | scan_out); |
| 1534 | wire [0:0] fdin; |
| 1535 | |
| 1536 | input [0:0] din; |
| 1537 | input l1clk; |
| 1538 | input scan_in; |
| 1539 | |
| 1540 | |
| 1541 | input siclk; |
| 1542 | input soclk; |
| 1543 | |
| 1544 | output [0:0] dout; |
| 1545 | output scan_out; |
| 1546 | assign fdin[0:0] = din[0:0]; |
| 1547 | |
| 1548 | |
| 1549 | |
| 1550 | |
| 1551 | |
| 1552 | |
| 1553 | dff #(1) d0_0 ( |
| 1554 | .l1clk(l1clk), |
| 1555 | .siclk(siclk), |
| 1556 | .soclk(soclk), |
| 1557 | .d(fdin[0:0]), |
| 1558 | .si(scan_in), |
| 1559 | .so(scan_out), |
| 1560 | .q(dout[0:0]) |
| 1561 | ); |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | |
| 1569 | |
| 1570 | |
| 1571 | |
| 1572 | |
| 1573 | |
| 1574 | endmodule |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | // any PARAMS parms go into naming of macro |
| 1583 | |
| 1584 | module ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_64 ( |
| 1585 | din, |
| 1586 | en, |
| 1587 | l1clk, |
| 1588 | scan_in, |
| 1589 | siclk, |
| 1590 | soclk, |
| 1591 | dout, |
| 1592 | scan_out); |
| 1593 | wire [63:0] fdin; |
| 1594 | wire [62:0] so; |
| 1595 | |
| 1596 | input [63:0] din; |
| 1597 | input en; |
| 1598 | input l1clk; |
| 1599 | input scan_in; |
| 1600 | |
| 1601 | |
| 1602 | input siclk; |
| 1603 | input soclk; |
| 1604 | |
| 1605 | output [63:0] dout; |
| 1606 | output scan_out; |
| 1607 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | |
| 1614 | dff #(64) d0_0 ( |
| 1615 | .l1clk(l1clk), |
| 1616 | .siclk(siclk), |
| 1617 | .soclk(soclk), |
| 1618 | .d(fdin[63:0]), |
| 1619 | .si({scan_in,so[62:0]}), |
| 1620 | .so({so[62:0],scan_out}), |
| 1621 | .q(dout[63:0]) |
| 1622 | ); |
| 1623 | |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | |
| 1631 | |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | endmodule |
| 1636 | |
| 1637 | |
| 1638 | |
| 1639 | |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | // any PARAMS parms go into naming of macro |
| 1650 | |
| 1651 | module ncu_c2ifd_ctl_msff_ctl_macro__width_72 ( |
| 1652 | din, |
| 1653 | l1clk, |
| 1654 | scan_in, |
| 1655 | siclk, |
| 1656 | soclk, |
| 1657 | dout, |
| 1658 | scan_out); |
| 1659 | wire [71:0] fdin; |
| 1660 | wire [70:0] so; |
| 1661 | |
| 1662 | input [71:0] din; |
| 1663 | input l1clk; |
| 1664 | input scan_in; |
| 1665 | |
| 1666 | |
| 1667 | input siclk; |
| 1668 | input soclk; |
| 1669 | |
| 1670 | output [71:0] dout; |
| 1671 | output scan_out; |
| 1672 | assign fdin[71:0] = din[71:0]; |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | |
| 1677 | |
| 1678 | |
| 1679 | dff #(72) d0_0 ( |
| 1680 | .l1clk(l1clk), |
| 1681 | .siclk(siclk), |
| 1682 | .soclk(soclk), |
| 1683 | .d(fdin[71:0]), |
| 1684 | .si({scan_in,so[70:0]}), |
| 1685 | .so({so[70:0],scan_out}), |
| 1686 | .q(dout[71:0]) |
| 1687 | ); |
| 1688 | |
| 1689 | |
| 1690 | |
| 1691 | |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | endmodule |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | |
| 1712 | |
| 1713 | |
| 1714 | // any PARAMS parms go into naming of macro |
| 1715 | |
| 1716 | module ncu_c2ifd_ctl_msff_ctl_macro__en_1__width_1 ( |
| 1717 | din, |
| 1718 | en, |
| 1719 | l1clk, |
| 1720 | scan_in, |
| 1721 | siclk, |
| 1722 | soclk, |
| 1723 | dout, |
| 1724 | scan_out); |
| 1725 | wire [0:0] fdin; |
| 1726 | |
| 1727 | input [0:0] din; |
| 1728 | input en; |
| 1729 | input l1clk; |
| 1730 | input scan_in; |
| 1731 | |
| 1732 | |
| 1733 | input siclk; |
| 1734 | input soclk; |
| 1735 | |
| 1736 | output [0:0] dout; |
| 1737 | output scan_out; |
| 1738 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 1739 | |
| 1740 | |
| 1741 | |
| 1742 | |
| 1743 | |
| 1744 | |
| 1745 | dff #(1) d0_0 ( |
| 1746 | .l1clk(l1clk), |
| 1747 | .siclk(siclk), |
| 1748 | .soclk(soclk), |
| 1749 | .d(fdin[0:0]), |
| 1750 | .si(scan_in), |
| 1751 | .so(scan_out), |
| 1752 | .q(dout[0:0]) |
| 1753 | ); |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | endmodule |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | |
| 1778 | |
| 1779 | |
| 1780 | // any PARAMS parms go into naming of macro |
| 1781 | |
| 1782 | module ncu_c2ifd_ctl_msff_ctl_macro__width_3 ( |
| 1783 | din, |
| 1784 | l1clk, |
| 1785 | scan_in, |
| 1786 | siclk, |
| 1787 | soclk, |
| 1788 | dout, |
| 1789 | scan_out); |
| 1790 | wire [2:0] fdin; |
| 1791 | wire [1:0] so; |
| 1792 | |
| 1793 | input [2:0] din; |
| 1794 | input l1clk; |
| 1795 | input scan_in; |
| 1796 | |
| 1797 | |
| 1798 | input siclk; |
| 1799 | input soclk; |
| 1800 | |
| 1801 | output [2:0] dout; |
| 1802 | output scan_out; |
| 1803 | assign fdin[2:0] = din[2:0]; |
| 1804 | |
| 1805 | |
| 1806 | |
| 1807 | |
| 1808 | |
| 1809 | |
| 1810 | dff #(3) d0_0 ( |
| 1811 | .l1clk(l1clk), |
| 1812 | .siclk(siclk), |
| 1813 | .soclk(soclk), |
| 1814 | .d(fdin[2:0]), |
| 1815 | .si({scan_in,so[1:0]}), |
| 1816 | .so({so[1:0],scan_out}), |
| 1817 | .q(dout[2:0]) |
| 1818 | ); |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | |
| 1829 | |
| 1830 | |
| 1831 | endmodule |
| 1832 | |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | // any PARAMS parms go into naming of macro |
| 1846 | |
| 1847 | module ncu_c2ifd_ctl_msff_ctl_macro__width_8 ( |
| 1848 | din, |
| 1849 | l1clk, |
| 1850 | scan_in, |
| 1851 | siclk, |
| 1852 | soclk, |
| 1853 | dout, |
| 1854 | scan_out); |
| 1855 | wire [7:0] fdin; |
| 1856 | wire [6:0] so; |
| 1857 | |
| 1858 | input [7:0] din; |
| 1859 | input l1clk; |
| 1860 | input scan_in; |
| 1861 | |
| 1862 | |
| 1863 | input siclk; |
| 1864 | input soclk; |
| 1865 | |
| 1866 | output [7:0] dout; |
| 1867 | output scan_out; |
| 1868 | assign fdin[7:0] = din[7:0]; |
| 1869 | |
| 1870 | |
| 1871 | |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | dff #(8) d0_0 ( |
| 1876 | .l1clk(l1clk), |
| 1877 | .siclk(siclk), |
| 1878 | .soclk(soclk), |
| 1879 | .d(fdin[7:0]), |
| 1880 | .si({scan_in,so[6:0]}), |
| 1881 | .so({so[6:0],scan_out}), |
| 1882 | .q(dout[7:0]) |
| 1883 | ); |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | |
| 1896 | endmodule |
| 1897 | |
| 1898 | |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | |
| 1906 | |
| 1907 | |
| 1908 | |
| 1909 | |
| 1910 | // any PARAMS parms go into naming of macro |
| 1911 | |
| 1912 | module ncu_c2ifd_ctl_msff_ctl_macro__width_64 ( |
| 1913 | din, |
| 1914 | l1clk, |
| 1915 | scan_in, |
| 1916 | siclk, |
| 1917 | soclk, |
| 1918 | dout, |
| 1919 | scan_out); |
| 1920 | wire [63:0] fdin; |
| 1921 | wire [62:0] so; |
| 1922 | |
| 1923 | input [63:0] din; |
| 1924 | input l1clk; |
| 1925 | input scan_in; |
| 1926 | |
| 1927 | |
| 1928 | input siclk; |
| 1929 | input soclk; |
| 1930 | |
| 1931 | output [63:0] dout; |
| 1932 | output scan_out; |
| 1933 | assign fdin[63:0] = din[63:0]; |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | dff #(64) d0_0 ( |
| 1941 | .l1clk(l1clk), |
| 1942 | .siclk(siclk), |
| 1943 | .soclk(soclk), |
| 1944 | .d(fdin[63:0]), |
| 1945 | .si({scan_in,so[62:0]}), |
| 1946 | .so({so[62:0],scan_out}), |
| 1947 | .q(dout[63:0]) |
| 1948 | ); |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | endmodule |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | // any PARAMS parms go into naming of macro |
| 1968 | |
| 1969 | module ncu_c2ifd_ctl_msff_ctl_macro__width_122 ( |
| 1970 | din, |
| 1971 | l1clk, |
| 1972 | scan_in, |
| 1973 | siclk, |
| 1974 | soclk, |
| 1975 | dout, |
| 1976 | scan_out); |
| 1977 | wire [121:0] fdin; |
| 1978 | wire [120:0] so; |
| 1979 | |
| 1980 | input [121:0] din; |
| 1981 | input l1clk; |
| 1982 | input scan_in; |
| 1983 | |
| 1984 | |
| 1985 | input siclk; |
| 1986 | input soclk; |
| 1987 | |
| 1988 | output [121:0] dout; |
| 1989 | output scan_out; |
| 1990 | assign fdin[121:0] = din[121:0]; |
| 1991 | |
| 1992 | |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | dff #(122) d0_0 ( |
| 1998 | .l1clk(l1clk), |
| 1999 | .siclk(siclk), |
| 2000 | .soclk(soclk), |
| 2001 | .d(fdin[121:0]), |
| 2002 | .si({scan_in,so[120:0]}), |
| 2003 | .so({so[120:0],scan_out}), |
| 2004 | .q(dout[121:0]) |
| 2005 | ); |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | endmodule |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | |
| 2023 | |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | |
| 2032 | // any PARAMS parms go into naming of macro |
| 2033 | |
| 2034 | module ncu_c2ifd_ctl_msff_ctl_macro__width_6 ( |
| 2035 | din, |
| 2036 | l1clk, |
| 2037 | scan_in, |
| 2038 | siclk, |
| 2039 | soclk, |
| 2040 | dout, |
| 2041 | scan_out); |
| 2042 | wire [5:0] fdin; |
| 2043 | wire [4:0] so; |
| 2044 | |
| 2045 | input [5:0] din; |
| 2046 | input l1clk; |
| 2047 | input scan_in; |
| 2048 | |
| 2049 | |
| 2050 | input siclk; |
| 2051 | input soclk; |
| 2052 | |
| 2053 | output [5:0] dout; |
| 2054 | output scan_out; |
| 2055 | assign fdin[5:0] = din[5:0]; |
| 2056 | |
| 2057 | |
| 2058 | |
| 2059 | |
| 2060 | |
| 2061 | |
| 2062 | dff #(6) d0_0 ( |
| 2063 | .l1clk(l1clk), |
| 2064 | .siclk(siclk), |
| 2065 | .soclk(soclk), |
| 2066 | .d(fdin[5:0]), |
| 2067 | .si({scan_in,so[4:0]}), |
| 2068 | .so({so[4:0],scan_out}), |
| 2069 | .q(dout[5:0]) |
| 2070 | ); |
| 2071 | |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | endmodule |
| 2084 | |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | // any PARAMS parms go into naming of macro |
| 2098 | |
| 2099 | module ncu_c2ifd_ctl_l1clkhdr_ctl_macro ( |
| 2100 | l2clk, |
| 2101 | l1en, |
| 2102 | pce_ov, |
| 2103 | stop, |
| 2104 | se, |
| 2105 | l1clk); |
| 2106 | |
| 2107 | |
| 2108 | input l2clk; |
| 2109 | input l1en; |
| 2110 | input pce_ov; |
| 2111 | input stop; |
| 2112 | input se; |
| 2113 | output l1clk; |
| 2114 | |
| 2115 | |
| 2116 | |
| 2117 | |
| 2118 | |
| 2119 | cl_sc1_l1hdr_8x c_0 ( |
| 2120 | |
| 2121 | |
| 2122 | .l2clk(l2clk), |
| 2123 | .pce(l1en), |
| 2124 | .l1clk(l1clk), |
| 2125 | .se(se), |
| 2126 | .pce_ov(pce_ov), |
| 2127 | .stop(stop) |
| 2128 | ); |
| 2129 | |
| 2130 | |
| 2131 | |
| 2132 | endmodule |
| 2133 | |
| 2134 | |
| 2135 | |
| 2136 | |
| 2137 | |
| 2138 | |
| 2139 | |
| 2140 | |