| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ncu_ssiuo4_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define UCB_BUS_WIDTH 4 |
| 36 | `define UCB_BUS_WIDTH_M1 3 |
| 37 | `define CYC_NUM 32 |
| 38 | `define CYC_NUM_M1 31 |
| 39 | |
| 40 | module ncu_ssiuo4_ctl ( |
| 41 | iol2clk, |
| 42 | scan_in, |
| 43 | scan_out, |
| 44 | tcu_pce_ov, |
| 45 | tcu_clk_stop, |
| 46 | tcu_aclk, |
| 47 | tcu_bclk, |
| 48 | tcu_scan_en, |
| 49 | vld, |
| 50 | data, |
| 51 | stall, |
| 52 | outdata_buf_busy, |
| 53 | outdata_buf_in, |
| 54 | outdata_vec_in, |
| 55 | outdata_buf_wr) ; |
| 56 | wire [31:0] outdata_vec; |
| 57 | wire [127:0] outdata_buf; |
| 58 | wire stall_d1_ff_scanin; |
| 59 | wire stall_d1_ff_scanout; |
| 60 | wire stall_d1; |
| 61 | wire l1clk; |
| 62 | wire load_outdata; |
| 63 | wire shift_outdata; |
| 64 | wire [31:0] outdata_vec_next; |
| 65 | wire outdata_vec_ff_scanin; |
| 66 | wire outdata_vec_ff_scanout; |
| 67 | wire [127:0] outdata_buf_next; |
| 68 | wire outdata_buf_ff_scanin; |
| 69 | wire outdata_buf_ff_scanout; |
| 70 | wire siclk; |
| 71 | wire soclk; |
| 72 | wire se; |
| 73 | wire pce_ov; |
| 74 | wire stop; |
| 75 | |
| 76 | |
| 77 | // Globals |
| 78 | input iol2clk; |
| 79 | input scan_in; |
| 80 | output scan_out; |
| 81 | input tcu_pce_ov; |
| 82 | input tcu_clk_stop; |
| 83 | input tcu_aclk; |
| 84 | input tcu_bclk; |
| 85 | input tcu_scan_en; |
| 86 | |
| 87 | // UCB bus interface |
| 88 | output vld; |
| 89 | output [`UCB_BUS_WIDTH_M1 :0] data; |
| 90 | input stall; |
| 91 | |
| 92 | // Local interface |
| 93 | output outdata_buf_busy; |
| 94 | input [127:0] outdata_buf_in; |
| 95 | input [`CYC_NUM_M1 :0] outdata_vec_in; |
| 96 | input outdata_buf_wr; |
| 97 | |
| 98 | // Local signals |
| 99 | |
| 100 | //////////////////////////////////////////////////////////////////////// |
| 101 | // Code starts here |
| 102 | //////////////////////////////////////////////////////////////////////// |
| 103 | /************************************************************ |
| 104 | * UCB bus interface flops |
| 105 | ************************************************************/ |
| 106 | assign vld = outdata_vec[0]; |
| 107 | assign data[`UCB_BUS_WIDTH_M1 :0] = outdata_buf[`UCB_BUS_WIDTH_M1 :0]; |
| 108 | |
| 109 | ncu_ssiuo4_ctl_msff_ctl_macro__width_1 stall_d1_ff |
| 110 | ( |
| 111 | .scan_in(stall_d1_ff_scanin), |
| 112 | .scan_out(stall_d1_ff_scanout), |
| 113 | .dout (stall_d1), |
| 114 | .l1clk (l1clk), |
| 115 | .din (stall), |
| 116 | .siclk(siclk), |
| 117 | .soclk(soclk) |
| 118 | ); |
| 119 | |
| 120 | /************************************************************ |
| 121 | * Outbound Data |
| 122 | ************************************************************/ |
| 123 | // accept new data only if there is none being processed |
| 124 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; |
| 125 | |
| 126 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; |
| 127 | |
| 128 | assign shift_outdata = outdata_vec[0] & ~stall_d1; |
| 129 | |
| 130 | assign outdata_vec_next[`CYC_NUM_M1 :0] = |
| 131 | load_outdata ? outdata_vec_in[`CYC_NUM_M1 :0] : |
| 132 | shift_outdata ? {1'b0,outdata_vec[`CYC_NUM_M1 :1]} : |
| 133 | outdata_vec[`CYC_NUM_M1 :0] ; |
| 134 | |
| 135 | ncu_ssiuo4_ctl_msff_ctl_macro__width_32 outdata_vec_ff |
| 136 | ( |
| 137 | .scan_in(outdata_vec_ff_scanin), |
| 138 | .scan_out(outdata_vec_ff_scanout), |
| 139 | .dout (outdata_vec[`CYC_NUM_M1 :0]), |
| 140 | .l1clk (l1clk), |
| 141 | .din (outdata_vec_next[`CYC_NUM_M1 :0]), |
| 142 | .siclk(siclk), |
| 143 | .soclk(soclk) |
| 144 | ); |
| 145 | |
| 146 | assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0] : |
| 147 | shift_outdata ? (outdata_buf[127:0] >> `UCB_BUS_WIDTH ) : |
| 148 | outdata_buf[127:0] ; |
| 149 | |
| 150 | ncu_ssiuo4_ctl_msff_ctl_macro__width_128 outdata_buf_ff |
| 151 | ( |
| 152 | .scan_in(outdata_buf_ff_scanin), |
| 153 | .scan_out(outdata_buf_ff_scanout), |
| 154 | .dout (outdata_buf[127:0]), |
| 155 | .l1clk (l1clk), |
| 156 | .din (outdata_buf_next[127:0]), |
| 157 | .siclk(siclk), |
| 158 | .soclk(soclk) |
| 159 | ); |
| 160 | |
| 161 | |
| 162 | |
| 163 | |
| 164 | /**** adding clock header ****/ |
| 165 | ncu_ssiuo4_ctl_l1clkhdr_ctl_macro clkgen ( |
| 166 | .l2clk (iol2clk), |
| 167 | .l1en (1'b1), |
| 168 | .l1clk (l1clk), |
| 169 | .pce_ov(pce_ov), |
| 170 | .stop(stop), |
| 171 | .se(se) |
| 172 | ); |
| 173 | |
| 174 | /*** building tcu port ***/ |
| 175 | assign siclk = tcu_aclk; |
| 176 | assign soclk = tcu_bclk; |
| 177 | assign se = tcu_scan_en; |
| 178 | assign pce_ov = tcu_pce_ov; |
| 179 | assign stop = tcu_clk_stop; |
| 180 | |
| 181 | // fixscan start: |
| 182 | assign stall_d1_ff_scanin = scan_in ; |
| 183 | assign outdata_vec_ff_scanin = stall_d1_ff_scanout ; |
| 184 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; |
| 185 | assign scan_out = outdata_buf_ff_scanout ; |
| 186 | // fixscan end: |
| 187 | endmodule // ucb_bus_out |
| 188 | |
| 189 | |
| 190 | |
| 191 | |
| 192 | |
| 193 | |
| 194 | |
| 195 | |
| 196 | |
| 197 | |
| 198 | |
| 199 | |
| 200 | // any PARAMS parms go into naming of macro |
| 201 | |
| 202 | module ncu_ssiuo4_ctl_msff_ctl_macro__width_1 ( |
| 203 | din, |
| 204 | l1clk, |
| 205 | scan_in, |
| 206 | siclk, |
| 207 | soclk, |
| 208 | dout, |
| 209 | scan_out); |
| 210 | wire [0:0] fdin; |
| 211 | |
| 212 | input [0:0] din; |
| 213 | input l1clk; |
| 214 | input scan_in; |
| 215 | |
| 216 | |
| 217 | input siclk; |
| 218 | input soclk; |
| 219 | |
| 220 | output [0:0] dout; |
| 221 | output scan_out; |
| 222 | assign fdin[0:0] = din[0:0]; |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | |
| 228 | |
| 229 | dff #(1) d0_0 ( |
| 230 | .l1clk(l1clk), |
| 231 | .siclk(siclk), |
| 232 | .soclk(soclk), |
| 233 | .d(fdin[0:0]), |
| 234 | .si(scan_in), |
| 235 | .so(scan_out), |
| 236 | .q(dout[0:0]) |
| 237 | ); |
| 238 | |
| 239 | |
| 240 | |
| 241 | |
| 242 | |
| 243 | |
| 244 | |
| 245 | |
| 246 | |
| 247 | |
| 248 | |
| 249 | |
| 250 | endmodule |
| 251 | |
| 252 | |
| 253 | |
| 254 | |
| 255 | |
| 256 | |
| 257 | |
| 258 | |
| 259 | |
| 260 | |
| 261 | |
| 262 | |
| 263 | |
| 264 | // any PARAMS parms go into naming of macro |
| 265 | |
| 266 | module ncu_ssiuo4_ctl_msff_ctl_macro__width_32 ( |
| 267 | din, |
| 268 | l1clk, |
| 269 | scan_in, |
| 270 | siclk, |
| 271 | soclk, |
| 272 | dout, |
| 273 | scan_out); |
| 274 | wire [31:0] fdin; |
| 275 | wire [30:0] so; |
| 276 | |
| 277 | input [31:0] din; |
| 278 | input l1clk; |
| 279 | input scan_in; |
| 280 | |
| 281 | |
| 282 | input siclk; |
| 283 | input soclk; |
| 284 | |
| 285 | output [31:0] dout; |
| 286 | output scan_out; |
| 287 | assign fdin[31:0] = din[31:0]; |
| 288 | |
| 289 | |
| 290 | |
| 291 | |
| 292 | |
| 293 | |
| 294 | dff #(32) d0_0 ( |
| 295 | .l1clk(l1clk), |
| 296 | .siclk(siclk), |
| 297 | .soclk(soclk), |
| 298 | .d(fdin[31:0]), |
| 299 | .si({scan_in,so[30:0]}), |
| 300 | .so({so[30:0],scan_out}), |
| 301 | .q(dout[31:0]) |
| 302 | ); |
| 303 | |
| 304 | |
| 305 | |
| 306 | |
| 307 | |
| 308 | |
| 309 | |
| 310 | |
| 311 | |
| 312 | |
| 313 | |
| 314 | |
| 315 | endmodule |
| 316 | |
| 317 | |
| 318 | |
| 319 | |
| 320 | |
| 321 | |
| 322 | |
| 323 | |
| 324 | |
| 325 | |
| 326 | |
| 327 | |
| 328 | |
| 329 | // any PARAMS parms go into naming of macro |
| 330 | |
| 331 | module ncu_ssiuo4_ctl_msff_ctl_macro__width_128 ( |
| 332 | din, |
| 333 | l1clk, |
| 334 | scan_in, |
| 335 | siclk, |
| 336 | soclk, |
| 337 | dout, |
| 338 | scan_out); |
| 339 | wire [127:0] fdin; |
| 340 | wire [126:0] so; |
| 341 | |
| 342 | input [127:0] din; |
| 343 | input l1clk; |
| 344 | input scan_in; |
| 345 | |
| 346 | |
| 347 | input siclk; |
| 348 | input soclk; |
| 349 | |
| 350 | output [127:0] dout; |
| 351 | output scan_out; |
| 352 | assign fdin[127:0] = din[127:0]; |
| 353 | |
| 354 | |
| 355 | |
| 356 | |
| 357 | |
| 358 | |
| 359 | dff #(128) d0_0 ( |
| 360 | .l1clk(l1clk), |
| 361 | .siclk(siclk), |
| 362 | .soclk(soclk), |
| 363 | .d(fdin[127:0]), |
| 364 | .si({scan_in,so[126:0]}), |
| 365 | .so({so[126:0],scan_out}), |
| 366 | .q(dout[127:0]) |
| 367 | ); |
| 368 | |
| 369 | |
| 370 | |
| 371 | |
| 372 | |
| 373 | |
| 374 | |
| 375 | |
| 376 | |
| 377 | |
| 378 | |
| 379 | |
| 380 | endmodule |
| 381 | |
| 382 | |
| 383 | |
| 384 | |
| 385 | |
| 386 | |
| 387 | |
| 388 | |
| 389 | |
| 390 | |
| 391 | |
| 392 | |
| 393 | |
| 394 | // any PARAMS parms go into naming of macro |
| 395 | |
| 396 | module ncu_ssiuo4_ctl_l1clkhdr_ctl_macro ( |
| 397 | l2clk, |
| 398 | l1en, |
| 399 | pce_ov, |
| 400 | stop, |
| 401 | se, |
| 402 | l1clk); |
| 403 | |
| 404 | |
| 405 | input l2clk; |
| 406 | input l1en; |
| 407 | input pce_ov; |
| 408 | input stop; |
| 409 | input se; |
| 410 | output l1clk; |
| 411 | |
| 412 | |
| 413 | |
| 414 | |
| 415 | |
| 416 | cl_sc1_l1hdr_8x c_0 ( |
| 417 | |
| 418 | |
| 419 | .l2clk(l2clk), |
| 420 | .pce(l1en), |
| 421 | .l1clk(l1clk), |
| 422 | .se(se), |
| 423 | .pce_ov(pce_ov), |
| 424 | .stop(stop) |
| 425 | ); |
| 426 | |
| 427 | |
| 428 | |
| 429 | endmodule |
| 430 | |
| 431 | |
| 432 | |
| 433 | |
| 434 | |
| 435 | |
| 436 | |
| 437 | |