| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: MDIO2P_REGS.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
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| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
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| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | //////////////////////////////////////////////////////////////////////////////// |
| 36 | // |
| 37 | // Copyright (c) 2003 Texas Instruments, Inc. |
| 38 | // All rights reserved |
| 39 | // |
| 40 | // This is an unpublished work created in the year stated above. |
| 41 | // Texas Instruments owns all rights in and to the work and intends to |
| 42 | // maintain it and protect it as unpublished copyright. In the event |
| 43 | // of either inadvertant or deliberate publication, the above stated |
| 44 | // date shall be treated as the year of first publication. In the event |
| 45 | // of such publication, Texas Instruments intends to enforce its rights |
| 46 | // in the work under the copyright laws as a published work. |
| 47 | // |
| 48 | // These commodities are under U.S. Government distribution license |
| 49 | // control. As such, they are not be re-exported without prior approval |
| 50 | // from the U.S. Department of Commerce. |
| 51 | // |
| 52 | //////////////////////////////////////////////////////////////////////////////// |
| 53 | |
| 54 | //////////////////////////////////////////////////////////////////////////////// |
| 55 | // |
| 56 | // FUNCTION: MDIO Registers and associated decode |
| 57 | // COMMENTS: Contains data shift register, indirect address register, access |
| 58 | // type decode, and mapping between MDIO and parallel interface |
| 59 | // signals. |
| 60 | // VERSION: #VERSION# |
| 61 | // DATE: #DATE# |
| 62 | // |
| 63 | // Date Author Changes |
| 64 | // ------- ------ ----------------------------------------------------- |
| 65 | // 27Jan05 Andre Asynchronous reset removed |
| 66 | // |
| 67 | //////////////////////////////////////////////////////////////////////////////// |
| 68 | |
| 69 | `timescale 1ns / 1ps |
| 70 | |
| 71 | module MDIO2P_REGS |
| 72 | ( |
| 73 | MDIN, |
| 74 | MDOUT, |
| 75 | MDOE, |
| 76 | IO_MDCLK, |
| 77 | IO_RESET, |
| 78 | IO_CLAUSE45, |
| 79 | IO_PRTID, |
| 80 | IO_DEVID, |
| 81 | IO_BASEAD, |
| 82 | IO_ACRAD, |
| 83 | IO_IPRAD, |
| 84 | PD, |
| 85 | PW, |
| 86 | PR, |
| 87 | PA, |
| 88 | PQ, |
| 89 | FRMR_STATE |
| 90 | ); |
| 91 | |
| 92 | |
| 93 | //////////////////////////////////////////////////////////////////////////////// |
| 94 | // |
| 95 | // Port Declarations |
| 96 | // |
| 97 | //////////////////////////////////////////////////////////////////////////////// |
| 98 | |
| 99 | input IO_RESET; // Global reset |
| 100 | |
| 101 | // Parallel Interface |
| 102 | input[15:0] PD; // Data in |
| 103 | output PW; // Write enable |
| 104 | output PR; // Read indicator |
| 105 | output[9:0] PA; // Address |
| 106 | output[15:0] PQ; // Data out |
| 107 | |
| 108 | // MDIO Interface |
| 109 | input IO_MDCLK; // Clock |
| 110 | input MDIN; // Data in |
| 111 | output MDOUT; // Data out |
| 112 | output MDOE; // Output enable |
| 113 | |
| 114 | // Configuration |
| 115 | input IO_CLAUSE45; // Clause45 |
| 116 | input[4:0] IO_PRTID; // Port address ID |
| 117 | input[4:0] IO_DEVID; // Device address ID |
| 118 | input[4:0] IO_BASEAD; // Base address |
| 119 | input[3:0] IO_ACRAD; // AddrCtl register address |
| 120 | input[3:0] IO_IPRAD; // Indirect port register address |
| 121 | |
| 122 | // Interface to Framer |
| 123 | input[5:0] FRMR_STATE; // LFSR encoded frame state |
| 124 | |
| 125 | |
| 126 | //////////////////////////////////////////////////////////////////////////////// |
| 127 | // |
| 128 | // Outputs which are not wires |
| 129 | // |
| 130 | //////////////////////////////////////////////////////////////////////////////// |
| 131 | |
| 132 | reg PW; |
| 133 | reg PR; |
| 134 | reg MDOUT; |
| 135 | reg MDOE; |
| 136 | |
| 137 | |
| 138 | //////////////////////////////////////////////////////////////////////////////// |
| 139 | // |
| 140 | // Parameters |
| 141 | // - Frame states are decoded from FRMR_STATE. See MDIO2P_FRMR for details |
| 142 | // of the state sequence |
| 143 | // |
| 144 | //////////////////////////////////////////////////////////////////////////////// |
| 145 | |
| 146 | parameter frmr_PRE = 6'b000000; |
| 147 | parameter frmr_SOF = 6'b001001; |
| 148 | parameter frmr_ADD = 6'b011001; |
| 149 | parameter frmr_TA = 6'b110011; |
| 150 | parameter frmr_EOF = 6'b100000; |
| 151 | |
| 152 | |
| 153 | //////////////////////////////////////////////////////////////////////////////// |
| 154 | // |
| 155 | // Internal Declarations |
| 156 | // |
| 157 | //////////////////////////////////////////////////////////////////////////////// |
| 158 | |
| 159 | // Flops |
| 160 | reg valid; // Access is valid |
| 161 | reg[1:0] opcode; // Operation type |
| 162 | reg acacc; // AddrCtl access |
| 163 | reg[15:0] data; // Data shift register |
| 164 | reg[15:0] addrctl; // Indirect address |
| 165 | |
| 166 | // Combinatorials |
| 167 | reg next_valid; // Next value for valid |
| 168 | reg[1:0] next_opcode; // Next value for opcode |
| 169 | reg next_acacc; // Next value for acacc |
| 170 | reg next_mdoe; // Next value for MDOE |
| 171 | reg[15:0] next_data; // Next value for data |
| 172 | reg[15:0] next_addrctl; // Next value for addrctl |
| 173 | |
| 174 | wire vsmmdbase; // Vendor Specific MMD base registers |
| 175 | |
| 176 | |
| 177 | //////////////////////////////////////////////////////////////////////////////// |
| 178 | // |
| 179 | // General decode |
| 180 | // - vsmmdbase identifies LS 16 register locations, which must be readable if |
| 181 | // mapped to DEVID 30 or 31 (Clause 45 only). |
| 182 | // |
| 183 | //////////////////////////////////////////////////////////////////////////////// |
| 184 | |
| 185 | assign vsmmdbase = &IO_DEVID[4:1] & ~|addrctl[15:4]; |
| 186 | |
| 187 | |
| 188 | //////////////////////////////////////////////////////////////////////////////// |
| 189 | // |
| 190 | // Access Decode |
| 191 | // - All access require a match of PRTAD to IO_PRTID |
| 192 | // - Clause 22 accesses require a further match to one of the register addresses |
| 193 | // (IO_ACRAD or IO_IPRAD). In both cases, the MSB of REGAD must be 1 |
| 194 | // - Clause 45 accesses must be to the address register, or indirect to an |
| 195 | // address within the range specified by IO_BASEAD, or to an address in the |
| 196 | // range 0-15 if the device is 30 or 31. |
| 197 | // |
| 198 | //////////////////////////////////////////////////////////////////////////////// |
| 199 | |
| 200 | always @(FRMR_STATE or MDIN or PD or MDOE or valid or acacc or |
| 201 | opcode or addrctl or data or vsmmdbase or IO_CLAUSE45 or IO_PRTID or |
| 202 | IO_DEVID or IO_BASEAD or IO_ACRAD or IO_IPRAD) |
| 203 | begin |
| 204 | // defaults |
| 205 | next_valid = valid; |
| 206 | next_acacc = acacc; |
| 207 | next_opcode = opcode; |
| 208 | next_mdoe = MDOE; |
| 209 | next_addrctl = addrctl; |
| 210 | next_data = {data[14:0], MDIN}; |
| 211 | |
| 212 | MDOUT = data[15]; |
| 213 | PW = 1'b0; |
| 214 | PR = 1'b0; |
| 215 | |
| 216 | casez(FRMR_STATE) |
| 217 | // Start of frame or Preamble //////////////////////////////////////////// |
| 218 | // - Reset as no active request |
| 219 | |
| 220 | frmr_PRE, frmr_SOF : |
| 221 | begin |
| 222 | next_valid = 1'b0; |
| 223 | next_acacc = 1'b0; |
| 224 | next_mdoe = 1'b0; |
| 225 | end |
| 226 | |
| 227 | |
| 228 | // Address and access type fully received //////////////////////////////// |
| 229 | // - Determine whether to respond to access |
| 230 | // - At this time, the data register contains the following: |
| 231 | // [4:0] - DEVAD/REGAD |
| 232 | // [9:5] - PRTAD/PHYAD |
| 233 | // [11:10] - Opcode (01 = write, 10 = read for Clause 22, 00 = Address |
| 234 | // write, 01 = data write, 10 = post inc read, 11 = |
| 235 | // read for Clause 45) |
| 236 | // [12] - clause specifier (1 for 22, 0 for 45) |
| 237 | |
| 238 | frmr_ADD : |
| 239 | begin |
| 240 | next_opcode = data[11:10]; |
| 241 | |
| 242 | if(data[9:5] == IO_PRTID) |
| 243 | begin |
| 244 | if(IO_CLAUSE45 & ~data[12]) |
| 245 | begin |
| 246 | if((data[4:0] == IO_DEVID)) |
| 247 | begin |
| 248 | next_acacc = ~|data[11:10]; |
| 249 | next_valid = (addrctl[15] & (addrctl[14:10] == IO_BASEAD)) | |
| 250 | vsmmdbase | next_acacc; |
| 251 | end |
| 252 | end |
| 253 | else if(~IO_CLAUSE45 & data[12]) |
| 254 | begin |
| 255 | next_acacc = data[3:0] == IO_ACRAD; |
| 256 | next_valid = (data[11] ^ data[10]) & data[4] & |
| 257 | (next_acacc | (data[3:0] == IO_IPRAD)); |
| 258 | end |
| 259 | next_mdoe = next_valid & data[11]; |
| 260 | end |
| 261 | end |
| 262 | |
| 263 | // Turn around cycle ///////////////////////////////////////////////////// |
| 264 | // - Drive MDOUT low |
| 265 | // - Read data is loaded into the data register during any read. Choices |
| 266 | // are AddrCtl, P2STCI portal or vendor specific MMD base registers. |
| 267 | // Selection need not be fully qualified, as MDOUT is only valid when |
| 268 | // MDOE is active. |
| 269 | |
| 270 | frmr_TA : |
| 271 | begin |
| 272 | MDOUT = 1'b0; |
| 273 | |
| 274 | if(opcode[1]) |
| 275 | begin |
| 276 | if(acacc) |
| 277 | next_data = addrctl; |
| 278 | else if(vsmmdbase) |
| 279 | next_data = {(addrctl[3:0] == 4'h8), 15'b0}; |
| 280 | else |
| 281 | begin |
| 282 | next_data = PD; |
| 283 | PR = valid; |
| 284 | end |
| 285 | end |
| 286 | end |
| 287 | |
| 288 | |
| 289 | // End of Frame ////////////////////////////////////////////////////////// |
| 290 | // - Disable output |
| 291 | // - Activate PW to write to P2STCI portal on any valid Clause 22 write |
| 292 | // not destined for AddrCtl, or any valid Clause 45 write above 8000. |
| 293 | // - Load AddrCtl on a Clause 22 write, or a Clause 45 address access |
| 294 | // - Increment AddrCtl (provided the address is not all 1's) on a Clause |
| 295 | // 22 access to the P2STCI portal when bit 15 is set, or a Clause 45 |
| 296 | // post-increment read. |
| 297 | |
| 298 | frmr_EOF : |
| 299 | begin |
| 300 | next_mdoe = 1'b0; |
| 301 | if(valid) |
| 302 | begin |
| 303 | if(IO_CLAUSE45) |
| 304 | begin |
| 305 | PW = ~acacc & ~opcode[1] & addrctl[15]; |
| 306 | if(acacc) |
| 307 | next_addrctl = next_data; |
| 308 | else if ((opcode == 2'b10) & ~&addrctl) |
| 309 | next_addrctl = addrctl + 1; |
| 310 | end |
| 311 | else |
| 312 | begin |
| 313 | PW = ~acacc & ~opcode[1]; |
| 314 | if(acacc & ~opcode[1]) |
| 315 | next_addrctl = {next_data[15], 5'b0, next_data[9:0]}; |
| 316 | else if(~acacc & addrctl[15] & ~&addrctl[9:0]) |
| 317 | next_addrctl = addrctl + 1; |
| 318 | end |
| 319 | end |
| 320 | end |
| 321 | endcase |
| 322 | end |
| 323 | |
| 324 | |
| 325 | //////////////////////////////////////////////////////////////////////////////// |
| 326 | // |
| 327 | // Sequential registers |
| 328 | // |
| 329 | //////////////////////////////////////////////////////////////////////////////// |
| 330 | |
| 331 | always @(posedge IO_MDCLK) |
| 332 | begin |
| 333 | if(IO_RESET) |
| 334 | begin |
| 335 | MDOE <= 1'b0; |
| 336 | addrctl <= 16'h0; |
| 337 | end |
| 338 | else |
| 339 | begin |
| 340 | MDOE <= next_mdoe; |
| 341 | addrctl <= next_addrctl; |
| 342 | end |
| 343 | end |
| 344 | |
| 345 | |
| 346 | always @(posedge IO_MDCLK) |
| 347 | begin |
| 348 | data <= next_data; |
| 349 | valid <= next_valid; |
| 350 | opcode <= next_opcode; |
| 351 | acacc <= next_acacc; |
| 352 | end |
| 353 | |
| 354 | |
| 355 | //////////////////////////////////////////////////////////////////////////////// |
| 356 | // |
| 357 | // Output Assignments |
| 358 | // |
| 359 | //////////////////////////////////////////////////////////////////////////////// |
| 360 | |
| 361 | assign PA = addrctl[9:0]; |
| 362 | assign PQ = next_data; |
| 363 | |
| 364 | endmodule |