| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: clkgen_mac.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | ///////////////////////////////////////////////////////////////////////////////////// |
| 36 | // |
| 37 | // Copyright (C) 2003 by Sun Microsystems, Inc. |
| 38 | // |
| 39 | // All rights reserved. No part of this design may be reproduced, |
| 40 | // stored in a retrieval system, or transmitted, in any form or by |
| 41 | // any means, electronic, mechanical, photocopying, recording, or |
| 42 | // otherwise, without prior written permission of Sun Microsystems, |
| 43 | // Inc. |
| 44 | // |
| 45 | // Sun Proprietary/Confidential |
| 46 | // |
| 47 | // Filename: clkgen_mac.v |
| 48 | // Description: Wrapper around clkgen_mac_io which |
| 49 | // provides l2clks locally within clusters. |
| 50 | // Services the IO domain of N2 MAC cluster. |
| 51 | // |
| 52 | // Primary Contact: carlos.castil@sun.com / john.lo@sun.com |
| 53 | // |
| 54 | // Revision History |
| 55 | // Feb 23,05 carlos.castil First Draft |
| 56 | // |
| 57 | // Mar 11,05 carlos.castil Removed IO_CLK_EXT |
| 58 | // Changed input name IO_CLK to gclk |
| 59 | // Changed input name tcu_sel_ext_clk to tcu_div_bypass |
| 60 | // Added scan ports scan_in, scan_out and tcu_scan_en |
| 61 | ///////////////////////////////////////////////////////////////////////////////////// |
| 62 | `timescale 1ns/1ns |
| 63 | |
| 64 | module clkgen_mac ( |
| 65 | niu_clk, |
| 66 | aclk, |
| 67 | bclk, |
| 68 | niu_reset_l, |
| 69 | pce_ov, |
| 70 | |
| 71 | tcu_pce_ov, |
| 72 | tcu_div_bypass, |
| 73 | tcu_scan_en, |
| 74 | |
| 75 | gl_mac_io_clk_stop, |
| 76 | gl_mac_io_out, |
| 77 | gl_mac_, |
| 78 | |
| 79 | tcu_scan_mode, |
| 80 | tcu_atpg_mode, |
| 81 | tcu_wr_inhibit, |
| 82 | |
| 83 | tcu_clk_stop, |
| 84 | |
| 85 | cluster_arst_l, |
| 86 | |
| 87 | cmp_gclk_c1_mac, |
| 88 | |
| 89 | tcu_aclk, |
| 90 | tcu_bclk, |
| 91 | |
| 92 | scan_in, |
| 93 | scan_out |
| 94 | ); |
| 95 | |
| 96 | // ************************** |
| 97 | // port declaration |
| 98 | // ************************** |
| 99 | |
| 100 | // clock outputs |
| 101 | output niu_clk; // Clock to core logic is output of L1 header |
| 102 | output aclk; // buffered version of aclk |
| 103 | output bclk; // buffered version of bclk |
| 104 | |
| 105 | // test signal outputs |
| 106 | output scan_out; |
| 107 | output pce_ov; // buffered version of pce_ov |
| 108 | |
| 109 | output tcu_clk_stop; |
| 110 | |
| 111 | // reset output |
| 112 | output niu_reset_l; |
| 113 | |
| 114 | // test inputs |
| 115 | input tcu_pce_ov; |
| 116 | input tcu_div_bypass; // bypasses clk divider to mux in ext clk |
| 117 | input tcu_scan_en; |
| 118 | input gl_mac_io_clk_stop; |
| 119 | input scan_in; |
| 120 | input tcu_wr_inhibit; |
| 121 | input tcu_atpg_mode; |
| 122 | input tcu_scan_mode; |
| 123 | |
| 124 | // inputs from ccu |
| 125 | input gl_mac_io_out; // phase signal from ccu (div/4 or div/2) |
| 126 | |
| 127 | // clock inputs |
| 128 | input cmp_gclk_c1_mac; // global clk - this is either cmp or dr |
| 129 | input tcu_aclk; |
| 130 | input tcu_bclk; |
| 131 | |
| 132 | // reset |
| 133 | input cluster_arst_l; |
| 134 | input gl_mac_; |
| 135 | |
| 136 | |
| 137 | wire pce_ov; |
| 138 | wire wmr_protect; |
| 139 | wire wmr_; |
| 140 | wire niu_reset_l; |
| 141 | wire cmp_slow_sync_en; |
| 142 | wire slow_cmp_sync_en; |
| 143 | wire aclk_wmr; |
| 144 | wire iol2clk; |
| 145 | wire array_wr_inhibit_wire; |
| 146 | |
| 147 | assign tcu_clk_stop = tcu_atpg_mode ? 1'b0 : gl_mac_io_clk_stop; |
| 148 | |
| 149 | cl_a1_l1hdr_8x io_l1hdr ( |
| 150 | .l2clk (iol2clk), |
| 151 | .se (tcu_scan_en), |
| 152 | .pce (1'b1), |
| 153 | .pce_ov (pce_ov), |
| 154 | .stop (1'b0), |
| 155 | .l1clk (niu_clk) |
| 156 | ); |
| 157 | |
| 158 | |
| 159 | clkgen_mac_io clkgen_mac_io ( |
| 160 | .l2clk (iol2clk), // outputs |
| 161 | .aclk (aclk), |
| 162 | .bclk (bclk), |
| 163 | .scan_out (scan_out), |
| 164 | .pce_ov (pce_ov), |
| 165 | .aclk_wmr (aclk_wmr), |
| 166 | .wmr_protect (wmr_protect), |
| 167 | .wmr_ (wmr_), |
| 168 | .por_ (niu_reset_l), |
| 169 | .cmp_slow_sync_en (cmp_slow_sync_en), |
| 170 | .slow_cmp_sync_en (slow_cmp_sync_en), |
| 171 | |
| 172 | // .tcu_clk_stop (gl_mac_io_clk_stop), // inputs |
| 173 | .tcu_clk_stop (tcu_clk_stop), |
| 174 | .tcu_pce_ov (tcu_pce_ov), |
| 175 | |
| 176 | .rst_wmr_protect (1'b0), |
| 177 | .rst_wmr_ (1'b1), |
| 178 | |
| 179 | .rst_por_ (gl_mac_), |
| 180 | |
| 181 | .array_wr_inhibit (array_wr_inhibit_wire), |
| 182 | |
| 183 | .ccu_cmp_slow_sync_en (1'b0 & array_wr_inhibit_wire & aclk_wmr & tcu_scan_mode), |
| 184 | .ccu_slow_cmp_sync_en (1'b0 & cmp_slow_sync_en & slow_cmp_sync_en & tcu_scan_mode), |
| 185 | |
| 186 | .tcu_div_bypass (tcu_div_bypass), |
| 187 | .ccu_div_ph (gl_mac_io_out), |
| 188 | |
| 189 | .tcu_atpg_mode (tcu_atpg_mode), |
| 190 | .tcu_wr_inhibit (tcu_wr_inhibit), |
| 191 | |
| 192 | .cluster_div_en (1'b1), |
| 193 | |
| 194 | .gclk (cmp_gclk_c1_mac), |
| 195 | .clk_ext (1'b0), |
| 196 | |
| 197 | .cluster_arst_l (cluster_arst_l), // new |
| 198 | .ccu_serdes_dtm (1'b0), // new |
| 199 | |
| 200 | .tcu_aclk (tcu_aclk), |
| 201 | .tcu_bclk (tcu_bclk), |
| 202 | |
| 203 | .scan_en (tcu_scan_en), |
| 204 | .scan_in (scan_in) |
| 205 | ); |
| 206 | |
| 207 | |
| 208 | endmodule // clkgen_mac |