| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: esr_bscan.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | //////////////////////////////////////////////////////////////////////////// |
| 36 | // |
| 37 | // |
| 38 | // Released: 1/16/05 |
| 39 | // Contacts: john.lo@sun.com / carlos.castil@sun.com |
| 40 | // Description: Boundary scan logic for N2 MAC Serdes |
| 41 | // Block Type: Boundary Scan |
| 42 | // Chip Name: |
| 43 | // Unit Name: |
| 44 | // Module: |
| 45 | // Where Instantiated: |
| 46 | // |
| 47 | // |
| 48 | // (c) 2005 Sun Microsystems, Inc. |
| 49 | // Sun Proprietary/Confidential |
| 50 | // Internal use only. |
| 51 | // |
| 52 | // All rights reserved. No part of this design may be reproduced stored |
| 53 | // in a retrieval system, or transmitted, in any form or by any means, |
| 54 | // electronic, mechanical, photocopying, recording, or otherwise, without |
| 55 | // prior written permission of Sun Microsystems, Inc. |
| 56 | // |
| 57 | /////////////////////////////////////////////////////////////////////////////// |
| 58 | |
| 59 | |
| 60 | module esr_bscan ( |
| 61 | peu_mac_sbs_input, |
| 62 | mac_mcu_3_sbs_output, |
| 63 | |
| 64 | tcu_sbs_scan_en, |
| 65 | tcu_sbs_aclk, |
| 66 | tcu_sbs_bclk, |
| 67 | tcu_sbs_clk, |
| 68 | tcu_sbs_uclk, |
| 69 | |
| 70 | tcu_sbs_acmode, |
| 71 | tcu_sbs_actestsignal, |
| 72 | |
| 73 | // from hedwig.v |
| 74 | BSRXP0_0, |
| 75 | BSRXP1_0, |
| 76 | BSRXP2_0, |
| 77 | BSRXP3_0, |
| 78 | BSRXN0_0, |
| 79 | BSRXN1_0, |
| 80 | BSRXN2_0, |
| 81 | BSRXN3_0, |
| 82 | BSRXP0_1, |
| 83 | BSRXP1_1, |
| 84 | BSRXP2_1, |
| 85 | BSRXP3_1, |
| 86 | BSRXN0_1, |
| 87 | BSRXN1_1, |
| 88 | BSRXN2_1, |
| 89 | BSRXN3_1, |
| 90 | |
| 91 | cfgtx0_0_17, // to hedwig |
| 92 | cfgtx1_0_17, // to hedwig |
| 93 | cfgtx2_0_17, // to hedwig |
| 94 | cfgtx3_0_17, // to hedwig |
| 95 | |
| 96 | cfgtx0_1_17, // to hedwig |
| 97 | cfgtx1_1_17, // to hedwig |
| 98 | cfgtx2_1_17, // to hedwig |
| 99 | cfgtx3_1_17, // to hedwig |
| 100 | |
| 101 | cfgrx0_0_b25_b24, // to hedwig |
| 102 | cfgrx1_0_b25_b24, // to hedwig |
| 103 | cfgrx2_0_b25_b24, // to hedwig |
| 104 | cfgrx3_0_b25_b24, // to hedwig |
| 105 | |
| 106 | cfgrx0_1_b25_b24, // to hedwig |
| 107 | cfgrx1_1_b25_b24, // to hedwig |
| 108 | cfgrx2_1_b25_b24, // to hedwig |
| 109 | cfgrx3_1_b25_b24 // to hedwig |
| 110 | ); |
| 111 | |
| 112 | |
| 113 | input peu_mac_sbs_input; |
| 114 | output mac_mcu_3_sbs_output; |
| 115 | |
| 116 | input tcu_sbs_scan_en; // from tcu |
| 117 | input tcu_sbs_aclk; // from tcu |
| 118 | input tcu_sbs_bclk; // from tcu |
| 119 | input tcu_sbs_clk; // from tcu |
| 120 | input tcu_sbs_uclk; // from tcu |
| 121 | |
| 122 | input tcu_sbs_acmode; // from tcu |
| 123 | input tcu_sbs_actestsignal; // from tcu |
| 124 | |
| 125 | // to esr_bscan.v |
| 126 | input BSRXP0_0; |
| 127 | input BSRXP1_0; |
| 128 | input BSRXP2_0; |
| 129 | input BSRXP3_0; |
| 130 | input BSRXN0_0; |
| 131 | input BSRXN1_0; |
| 132 | input BSRXN2_0; |
| 133 | input BSRXN3_0; |
| 134 | input BSRXP0_1; |
| 135 | input BSRXP1_1; |
| 136 | input BSRXP2_1; |
| 137 | input BSRXP3_1; |
| 138 | input BSRXN0_1; |
| 139 | input BSRXN1_1; |
| 140 | input BSRXN2_1; |
| 141 | input BSRXN3_1; |
| 142 | |
| 143 | output cfgtx0_0_17; // to hedwig |
| 144 | output cfgtx1_0_17; // to hedwig |
| 145 | output cfgtx2_0_17; // to hedwig |
| 146 | output cfgtx3_0_17; // to hedwig |
| 147 | |
| 148 | output cfgtx0_1_17; // to hedwig |
| 149 | output cfgtx1_1_17; // to hedwig |
| 150 | output cfgtx2_1_17; // to hedwig |
| 151 | output cfgtx3_1_17; // to hedwig |
| 152 | |
| 153 | output [1:0] cfgrx0_0_b25_b24; // to hedwig |
| 154 | output [1:0] cfgrx1_0_b25_b24; // to hedwig |
| 155 | output [1:0] cfgrx2_0_b25_b24; // to hedwig |
| 156 | output [1:0] cfgrx3_0_b25_b24; // to hedwig |
| 157 | |
| 158 | output [1:0] cfgrx0_1_b25_b24; // to hedwig |
| 159 | output [1:0] cfgrx1_1_b25_b24; // to hedwig |
| 160 | output [1:0] cfgrx2_1_b25_b24; // to hedwig |
| 161 | output [1:0] cfgrx3_1_b25_b24; // to hedwig |
| 162 | |
| 163 | wire siclk; |
| 164 | wire soclk; |
| 165 | wire l1clk; |
| 166 | |
| 167 | wire bs_tx_0_0; |
| 168 | wire bs_rxp_0_0; |
| 169 | wire bs_rxn_0_0; |
| 170 | |
| 171 | wire bs_tx_1_0; |
| 172 | wire bs_rxp_1_0; |
| 173 | wire bs_rxn_1_0; |
| 174 | |
| 175 | wire bs_tx_2_0; |
| 176 | wire bs_rxp_2_0; |
| 177 | wire bs_rxn_2_0; |
| 178 | |
| 179 | wire bs_tx_3_0; |
| 180 | wire bs_rxp_3_0; |
| 181 | wire bs_rxn_3_0; |
| 182 | |
| 183 | wire bs_tx_0_1; |
| 184 | wire bs_rxp_0_1; |
| 185 | wire bs_rxn_0_1; |
| 186 | |
| 187 | wire bs_tx_1_1; |
| 188 | wire bs_rxp_1_1; |
| 189 | wire bs_rxn_1_1; |
| 190 | |
| 191 | wire bs_tx_2_1; |
| 192 | wire bs_rxp_2_1; |
| 193 | wire bs_rxn_2_1; |
| 194 | |
| 195 | wire bs_tx_3_1; |
| 196 | wire bs_rxp_3_1; |
| 197 | wire bs_rxn_3_1; |
| 198 | |
| 199 | // According to Sungabe's spec, the following signals are required to float. |
| 200 | // vlint flag_net_has_no_load off |
| 201 | // vlint flag_dangling_net_within_module off |
| 202 | wire float0; |
| 203 | wire float1; |
| 204 | wire float2; |
| 205 | wire float3; |
| 206 | wire float4; |
| 207 | wire float5; |
| 208 | wire float6; |
| 209 | wire float7; |
| 210 | wire float8; |
| 211 | wire float9; |
| 212 | wire float10; |
| 213 | wire float11; |
| 214 | wire float12; |
| 215 | wire float13; |
| 216 | wire float14; |
| 217 | wire float15; |
| 218 | // vlint flag_net_has_no_load on |
| 219 | // vlint flag_dangling_net_within_module on |
| 220 | |
| 221 | |
| 222 | // ///////////////////////////////////////////////////////////////////////////// |
| 223 | // Scan Renames |
| 224 | // ///////////////////////////////////////////////////////////////////////////// |
| 225 | |
| 226 | assign siclk = tcu_sbs_aclk; |
| 227 | assign soclk = tcu_sbs_bclk; |
| 228 | |
| 229 | //////////////////////////////////////////////////////////////////////////////// |
| 230 | // Clock header |
| 231 | // ///////////////////////////////////////////////////////////////////////////// |
| 232 | |
| 233 | cl_a1_l1hdr_8x clkgen ( |
| 234 | |
| 235 | .l2clk (tcu_sbs_clk), |
| 236 | .pce (1'b1), |
| 237 | .l1clk (l1clk), |
| 238 | .se (tcu_sbs_scan_en), |
| 239 | .pce_ov (1'b1), |
| 240 | .stop (1'b0) |
| 241 | ); |
| 242 | |
| 243 | // ///////////////////////////////////////////////////////////////////////////// |
| 244 | // Boundary Scan Initialization per IEEE 1149.6 |
| 245 | // ///////////////////////////////////////////////////////////////////////////// |
| 246 | |
| 247 | assign cfgrx0_0_b25_b24 = {bs_rxn_0_0,bs_rxp_0_0}; |
| 248 | assign cfgrx1_0_b25_b24 = {bs_rxn_1_0,bs_rxp_1_0}; |
| 249 | assign cfgrx2_0_b25_b24 = {bs_rxn_2_0,bs_rxp_2_0}; |
| 250 | assign cfgrx3_0_b25_b24 = {bs_rxn_3_0,bs_rxp_3_0}; |
| 251 | |
| 252 | assign cfgrx0_1_b25_b24 = {bs_rxn_0_1,bs_rxp_0_1}; |
| 253 | assign cfgrx1_1_b25_b24 = {bs_rxn_1_1,bs_rxp_1_1}; |
| 254 | assign cfgrx2_1_b25_b24 = {bs_rxn_2_1,bs_rxp_2_1}; |
| 255 | assign cfgrx3_1_b25_b24 = {bs_rxn_3_1,bs_rxp_3_1}; |
| 256 | |
| 257 | // ///////////////////////////////////////////////////////////////////////////// |
| 258 | // Boundary Scan Output |
| 259 | // ///////////////////////////////////////////////////////////////////////////// |
| 260 | |
| 261 | assign mac_mcu_3_sbs_output = bs_rxn_3_1; |
| 262 | |
| 263 | // ///////////////////////////////////////////////////////////////////////////// |
| 264 | // Port 0 Channel 0 Boundary scan cells |
| 265 | // ///////////////////////////////////////////////////////////////////////////// |
| 266 | |
| 267 | |
| 268 | cl_a1_bsac_cell_4x inst_bstx_0_0 ( |
| 269 | .q (cfgtx0_0_17), |
| 270 | .so (bs_tx_0_0), |
| 271 | .d (1'b0), |
| 272 | .l1clk (1'b1), |
| 273 | .si (peu_mac_sbs_input), |
| 274 | .siclk (siclk), |
| 275 | .soclk (soclk), |
| 276 | .updateclk (tcu_sbs_uclk), |
| 277 | .ac_mode (tcu_sbs_acmode), |
| 278 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 279 | |
| 280 | // vlint flag_null_instance_port off |
| 281 | cl_a1_msffjtag_4x inst_bsrxp_0_0 ( |
| 282 | .q (float0), |
| 283 | .so (bs_rxp_0_0), |
| 284 | .d (BSRXP0_0), |
| 285 | .l1clk (l1clk), |
| 286 | .si (bs_tx_0_0), |
| 287 | .siclk (siclk), |
| 288 | .soclk (soclk), |
| 289 | .reset (1'b0), |
| 290 | .updateclk (tcu_sbs_uclk) ); |
| 291 | // vlint flag_null_instance_port on |
| 292 | |
| 293 | // vlint flag_null_instance_port off |
| 294 | cl_a1_msffjtag_4x inst_bsrxn_0_0 ( |
| 295 | .q (float1), |
| 296 | .so (bs_rxn_0_0), |
| 297 | .d (BSRXN0_0), |
| 298 | .l1clk (l1clk), |
| 299 | .si (bs_rxp_0_0), |
| 300 | .siclk (siclk), |
| 301 | .soclk (soclk), |
| 302 | .reset (1'b0), |
| 303 | .updateclk (tcu_sbs_uclk) ); |
| 304 | // vlint flag_null_instance_port on |
| 305 | |
| 306 | // ///////////////////////////////////////////////////////////////////////////// |
| 307 | // Port 0 Channel 1 Boundary scan cells |
| 308 | // ///////////////////////////////////////////////////////////////////////////// |
| 309 | |
| 310 | cl_a1_bsac_cell_4x inst_bstx_1_0 ( |
| 311 | .q (cfgtx1_0_17), |
| 312 | .so (bs_tx_1_0), |
| 313 | .d (1'b0), |
| 314 | .l1clk (1'b1), |
| 315 | .si (bs_rxn_0_0), |
| 316 | .siclk (siclk), |
| 317 | .soclk (soclk), |
| 318 | .updateclk (tcu_sbs_uclk), |
| 319 | .ac_mode (tcu_sbs_acmode), |
| 320 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 321 | |
| 322 | // vlint flag_null_instance_port off |
| 323 | cl_a1_msffjtag_4x inst_bsrxp_1_0 ( |
| 324 | .q (float2), |
| 325 | .so (bs_rxp_1_0), |
| 326 | .d (BSRXP1_0), |
| 327 | .l1clk (l1clk), |
| 328 | .si (bs_tx_1_0), |
| 329 | .siclk (siclk), |
| 330 | .soclk (soclk), |
| 331 | .reset (1'b0), |
| 332 | .updateclk (tcu_sbs_uclk) ); |
| 333 | // vlint flag_null_instance_port on |
| 334 | |
| 335 | // vlint flag_null_instance_port off |
| 336 | cl_a1_msffjtag_4x inst_bsrxn_1_0 ( |
| 337 | .q (float3), |
| 338 | .so (bs_rxn_1_0), |
| 339 | .d (BSRXN1_0), |
| 340 | .l1clk (l1clk), |
| 341 | .si (bs_rxp_1_0), |
| 342 | .siclk (siclk), |
| 343 | .soclk (soclk), |
| 344 | .reset (1'b0), |
| 345 | .updateclk (tcu_sbs_uclk) ); |
| 346 | // vlint flag_null_instance_port on |
| 347 | |
| 348 | // ///////////////////////////////////////////////////////////////////////////// |
| 349 | // Port 0 Channel 2 Boundary scan cells |
| 350 | // ///////////////////////////////////////////////////////////////////////////// |
| 351 | |
| 352 | cl_a1_bsac_cell_4x inst_bstx_2_0 ( |
| 353 | .q (cfgtx2_0_17), |
| 354 | .so (bs_tx_2_0), |
| 355 | .d (1'b0), |
| 356 | .l1clk (1'b1), |
| 357 | .si (bs_rxn_1_0), |
| 358 | .siclk (siclk), |
| 359 | .soclk (soclk), |
| 360 | .updateclk (tcu_sbs_uclk), |
| 361 | .ac_mode (tcu_sbs_acmode), |
| 362 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 363 | |
| 364 | // vlint flag_null_instance_port off |
| 365 | cl_a1_msffjtag_4x inst_bsrxp_2_0 ( |
| 366 | .q (float4), |
| 367 | .so (bs_rxp_2_0), |
| 368 | .d (BSRXP2_0), |
| 369 | .l1clk (l1clk), |
| 370 | .si (bs_tx_2_0), |
| 371 | .siclk (siclk), |
| 372 | .soclk (soclk), |
| 373 | .reset (1'b0), |
| 374 | .updateclk (tcu_sbs_uclk) ); |
| 375 | // vlint flag_null_instance_port on |
| 376 | |
| 377 | // vlint flag_null_instance_port off |
| 378 | cl_a1_msffjtag_4x inst_bsrxn_2_0 ( |
| 379 | .q (float5), |
| 380 | .so (bs_rxn_2_0), |
| 381 | .d (BSRXN2_0), |
| 382 | .l1clk (l1clk), |
| 383 | .si (bs_rxp_2_0), |
| 384 | .siclk (siclk), |
| 385 | .soclk (soclk), |
| 386 | .reset (1'b0), |
| 387 | .updateclk (tcu_sbs_uclk) ); |
| 388 | // vlint flag_null_instance_port on |
| 389 | |
| 390 | |
| 391 | // ///////////////////////////////////////////////////////////////////////////// |
| 392 | // Port 0 Channel 3 Boundary scan cells |
| 393 | // ///////////////////////////////////////////////////////////////////////////// |
| 394 | |
| 395 | cl_a1_bsac_cell_4x inst_bstx_3_0 ( |
| 396 | .q (cfgtx3_0_17), |
| 397 | .so (bs_tx_3_0), |
| 398 | .d (1'b0), |
| 399 | .l1clk (1'b1), |
| 400 | .si (bs_rxn_2_0), |
| 401 | .siclk (siclk), |
| 402 | .soclk (soclk), |
| 403 | .updateclk (tcu_sbs_uclk), |
| 404 | .ac_mode (tcu_sbs_acmode), |
| 405 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 406 | |
| 407 | // vlint flag_null_instance_port off |
| 408 | cl_a1_msffjtag_4x inst_bsrxp_3_0 ( |
| 409 | .q (float6), |
| 410 | .so (bs_rxp_3_0), |
| 411 | .d (BSRXP3_0), |
| 412 | .l1clk (l1clk), |
| 413 | .si (bs_tx_3_0), |
| 414 | .siclk (siclk), |
| 415 | .soclk (soclk), |
| 416 | .reset (1'b0), |
| 417 | .updateclk (tcu_sbs_uclk) ); |
| 418 | // vlint flag_null_instance_port on |
| 419 | |
| 420 | // vlint flag_null_instance_port off |
| 421 | cl_a1_msffjtag_4x inst_bsrxn_3_0 ( |
| 422 | .q (float7), |
| 423 | .so (bs_rxn_3_0), |
| 424 | .d (BSRXN3_0), |
| 425 | .l1clk (l1clk), |
| 426 | .si (bs_rxp_3_0), |
| 427 | .siclk (siclk), |
| 428 | .soclk (soclk), |
| 429 | .reset (1'b0), |
| 430 | .updateclk (tcu_sbs_uclk) ); |
| 431 | // vlint flag_null_instance_port on |
| 432 | |
| 433 | // ///////////////////////////////////////////////////////////////////////////// |
| 434 | // Port 1 Channel 0 Boundary scan cells |
| 435 | // ///////////////////////////////////////////////////////////////////////////// |
| 436 | |
| 437 | |
| 438 | cl_a1_bsac_cell_4x inst_bstx_0_1 ( |
| 439 | .q (cfgtx0_1_17), |
| 440 | .so (bs_tx_0_1), |
| 441 | .d (1'b0), |
| 442 | .l1clk (1'b1), |
| 443 | .si (bs_rxn_3_0), |
| 444 | .siclk (siclk), |
| 445 | .soclk (soclk), |
| 446 | .updateclk (tcu_sbs_uclk), |
| 447 | .ac_mode (tcu_sbs_acmode), |
| 448 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 449 | |
| 450 | // vlint flag_null_instance_port off |
| 451 | cl_a1_msffjtag_4x inst_bsrxp_0_1 ( |
| 452 | .q (float8), |
| 453 | .so (bs_rxp_0_1), |
| 454 | .d (BSRXP0_1), |
| 455 | .l1clk (l1clk), |
| 456 | .si (bs_tx_0_1), |
| 457 | .siclk (siclk), |
| 458 | .soclk (soclk), |
| 459 | .reset (1'b0), |
| 460 | .updateclk (tcu_sbs_uclk) ); |
| 461 | // vlint flag_null_instance_port on |
| 462 | |
| 463 | // vlint flag_null_instance_port off |
| 464 | cl_a1_msffjtag_4x inst_bsrxn_0_1 ( |
| 465 | .q (float9), |
| 466 | .so (bs_rxn_0_1), |
| 467 | .d (BSRXN0_1), |
| 468 | .l1clk (l1clk), |
| 469 | .si (bs_rxp_0_1), |
| 470 | .siclk (siclk), |
| 471 | .soclk (soclk), |
| 472 | .reset (1'b0), |
| 473 | .updateclk (tcu_sbs_uclk) ); |
| 474 | // vlint flag_null_instance_port on |
| 475 | |
| 476 | |
| 477 | // ///////////////////////////////////////////////////////////////////////////// |
| 478 | // Port 1 Channel 1 Boundary scan cells |
| 479 | // ///////////////////////////////////////////////////////////////////////////// |
| 480 | |
| 481 | cl_a1_bsac_cell_4x inst_bstx_1_1 ( |
| 482 | .q (cfgtx1_1_17), |
| 483 | .so (bs_tx_1_1), |
| 484 | .d (1'b0), |
| 485 | .l1clk (1'b1), |
| 486 | .si (bs_rxn_0_1), |
| 487 | .siclk (siclk), |
| 488 | .soclk (soclk), |
| 489 | .updateclk (tcu_sbs_uclk), |
| 490 | .ac_mode (tcu_sbs_acmode), |
| 491 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 492 | |
| 493 | // vlint flag_null_instance_port off |
| 494 | cl_a1_msffjtag_4x inst_bsrxp_1_1 ( |
| 495 | .q (float10), |
| 496 | .so (bs_rxp_1_1), |
| 497 | .d (BSRXP1_1), |
| 498 | .l1clk (l1clk), |
| 499 | .si (bs_tx_1_1), |
| 500 | .siclk (siclk), |
| 501 | .soclk (soclk), |
| 502 | .reset (1'b0), |
| 503 | .updateclk (tcu_sbs_uclk) ); |
| 504 | // vlint flag_null_instance_port on |
| 505 | |
| 506 | // vlint flag_null_instance_port off |
| 507 | cl_a1_msffjtag_4x inst_bsrxn_1_1 ( |
| 508 | .q (float11), |
| 509 | .so (bs_rxn_1_1), |
| 510 | .d (BSRXN1_1), |
| 511 | .l1clk (l1clk), |
| 512 | .si (bs_rxp_1_1), |
| 513 | .siclk (siclk), |
| 514 | .soclk (soclk), |
| 515 | .reset (1'b0), |
| 516 | .updateclk (tcu_sbs_uclk) ); |
| 517 | // vlint flag_null_instance_port on |
| 518 | |
| 519 | // ///////////////////////////////////////////////////////////////////////////// |
| 520 | // Port 1 Channel 2 Boundary scan cells |
| 521 | // ///////////////////////////////////////////////////////////////////////////// |
| 522 | |
| 523 | cl_a1_bsac_cell_4x inst_bstx_2_1 ( |
| 524 | .q (cfgtx2_1_17), |
| 525 | .so (bs_tx_2_1), |
| 526 | .d (1'b0), |
| 527 | .l1clk (1'b1), |
| 528 | .si (bs_rxn_1_1), |
| 529 | .siclk (siclk), |
| 530 | .soclk (soclk), |
| 531 | .updateclk (tcu_sbs_uclk), |
| 532 | .ac_mode (tcu_sbs_acmode), |
| 533 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 534 | |
| 535 | // vlint flag_null_instance_port off |
| 536 | cl_a1_msffjtag_4x inst_bsrxp_2_1 ( |
| 537 | .q (float12), |
| 538 | .so (bs_rxp_2_1), |
| 539 | .d (BSRXP2_1), |
| 540 | .l1clk (l1clk), |
| 541 | .si (bs_tx_2_1), |
| 542 | .siclk (siclk), |
| 543 | .soclk (soclk), |
| 544 | .reset (1'b0), |
| 545 | .updateclk (tcu_sbs_uclk) ); |
| 546 | // vlint flag_null_instance_port on |
| 547 | |
| 548 | // vlint flag_null_instance_port off |
| 549 | cl_a1_msffjtag_4x inst_bsrxn_2_1 ( |
| 550 | .q (float13), |
| 551 | .so (bs_rxn_2_1), |
| 552 | .d (BSRXN2_1), |
| 553 | .l1clk (l1clk), |
| 554 | .si (bs_rxp_2_1), |
| 555 | .siclk (siclk), |
| 556 | .soclk (soclk), |
| 557 | .reset (1'b0), |
| 558 | .updateclk (tcu_sbs_uclk) ); |
| 559 | // vlint flag_null_instance_port on |
| 560 | |
| 561 | |
| 562 | // ///////////////////////////////////////////////////////////////////////////// |
| 563 | // Port 1 Channel 3 Boundary scan cells |
| 564 | // ///////////////////////////////////////////////////////////////////////////// |
| 565 | |
| 566 | cl_a1_bsac_cell_4x inst_bstx_3_1 ( |
| 567 | .q (cfgtx3_1_17), |
| 568 | .so (bs_tx_3_1), |
| 569 | .d (1'b0), |
| 570 | .l1clk (1'b1), |
| 571 | .si (bs_rxn_2_1), |
| 572 | .siclk (siclk), |
| 573 | .soclk (soclk), |
| 574 | .updateclk (tcu_sbs_uclk), |
| 575 | .ac_mode (tcu_sbs_acmode), |
| 576 | .ac_test_signal (tcu_sbs_actestsignal) ); |
| 577 | |
| 578 | // vlint flag_null_instance_port off |
| 579 | cl_a1_msffjtag_4x inst_bsrxp_3_1 ( |
| 580 | .q (float14), |
| 581 | .so (bs_rxp_3_1), |
| 582 | .d (BSRXP3_1), |
| 583 | .l1clk (l1clk), |
| 584 | .si (bs_tx_3_1), |
| 585 | .siclk (siclk), |
| 586 | .soclk (soclk), |
| 587 | .reset (1'b0), |
| 588 | .updateclk (tcu_sbs_uclk) ); |
| 589 | // vlint flag_null_instance_port on |
| 590 | |
| 591 | // vlint flag_null_instance_port off |
| 592 | cl_a1_msffjtag_4x inst_bsrxn_3_1 ( |
| 593 | .q (float15), |
| 594 | .so (bs_rxn_3_1), |
| 595 | .d (BSRXN3_1), |
| 596 | .l1clk (l1clk), |
| 597 | .si (bs_rxp_3_1), |
| 598 | .siclk (siclk), |
| 599 | .soclk (soclk), |
| 600 | .reset (1'b0), |
| 601 | .updateclk (tcu_sbs_uclk) ); |
| 602 | // vlint flag_null_instance_port on |
| 603 | |
| 604 | |
| 605 | |
| 606 | endmodule // esr_bscan |
| 607 | |