| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fflp_fcram_arb.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /**********************************************************************/ |
| 36 | /*project name: NIU */ |
| 37 | /*module name: fflp_fcram_arb */ |
| 38 | /*description: Aabitration between CPU access and flow */ |
| 39 | /* classification */ |
| 40 | /* */ |
| 41 | /*child modules in: none */ |
| 42 | /*interface modules: */ |
| 43 | /*author name: Jeanne Cai */ |
| 44 | /*date created: 16-03-2004 */ |
| 45 | /* */ |
| 46 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ |
| 47 | /* Sun Proprietary and Confidential */ |
| 48 | /* */ |
| 49 | /*modifications: */ |
| 50 | /**********************************************************************/ |
| 51 | |
| 52 | |
| 53 | module fflp_fcram_arb |
| 54 | ( |
| 55 | cclk, |
| 56 | reset, |
| 57 | fcram_lookup_ratio, |
| 58 | fc_lookup_req, |
| 59 | fwd_no_fc_sched_sm, |
| 60 | cpu_fcram_req_sync, |
| 61 | srch_burst_done, |
| 62 | cpu_burst_done_sm, |
| 63 | |
| 64 | fwd_sched, |
| 65 | do_srch_cycle, |
| 66 | do_cpu_cycle, |
| 67 | fc_fifo_ren |
| 68 | ); |
| 69 | |
| 70 | input cclk; |
| 71 | input reset; |
| 72 | input[3:0] fcram_lookup_ratio; |
| 73 | input fc_lookup_req; |
| 74 | input fwd_no_fc_sched_sm; |
| 75 | input cpu_fcram_req_sync; |
| 76 | input srch_burst_done; |
| 77 | input cpu_burst_done_sm; |
| 78 | |
| 79 | output fwd_sched; |
| 80 | output do_srch_cycle; |
| 81 | output do_cpu_cycle; |
| 82 | output fc_fifo_ren; |
| 83 | |
| 84 | reg fwd_fc_sched_sm; |
| 85 | reg cpu_sched_sm; |
| 86 | reg[1:0] next_state; |
| 87 | |
| 88 | wire fwd_sched_in; |
| 89 | wire fwd_sched; |
| 90 | wire fwd_fc_sched; |
| 91 | wire cpu_sched; |
| 92 | wire fwd_sched_cnt_en; |
| 93 | wire[3:0] fwd_sched_cnt_in; |
| 94 | wire[3:0] fwd_sched_cnt; |
| 95 | wire fwd_reqs_served; |
| 96 | wire[1:0] state; |
| 97 | |
| 98 | wire cpu_fcram_req_sync_d; |
| 99 | wire cpu_req_pulse; |
| 100 | wire is_cpu_req_en; |
| 101 | wire is_cpu_req_in; |
| 102 | wire is_cpu_req; |
| 103 | |
| 104 | wire do_srch_cycle_en; |
| 105 | wire do_srch_cycle_in; |
| 106 | wire do_srch_cycle; |
| 107 | wire do_cpu_cycle_en; |
| 108 | wire do_cpu_cycle_in; |
| 109 | wire do_cpu_cycle; |
| 110 | |
| 111 | wire fwd_sched_1; |
| 112 | wire fwd_sched_2; |
| 113 | wire fc_fifo_ren_in; |
| 114 | wire fc_fifo_ren; |
| 115 | |
| 116 | //state machine states |
| 117 | parameter |
| 118 | FWD_ARB = 2'b00, |
| 119 | FWD_IDLE = 2'b01, |
| 120 | CPU_ARB = 2'b10, |
| 121 | CPU_IDLE = 2'b11; |
| 122 | |
| 123 | always @ (state or fc_lookup_req or is_cpu_req or |
| 124 | srch_burst_done or cpu_burst_done_sm or |
| 125 | do_cpu_cycle or fwd_reqs_served) |
| 126 | |
| 127 | begin |
| 128 | |
| 129 | fwd_fc_sched_sm = 1'b0; |
| 130 | cpu_sched_sm = 1'b0; |
| 131 | next_state = 2'b0; |
| 132 | |
| 133 | case (state) //synopsys parallel_case full_case |
| 134 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_fcram_arb:state" |
| 135 | |
| 136 | FWD_ARB: |
| 137 | begin |
| 138 | if (do_cpu_cycle & !cpu_burst_done_sm) |
| 139 | begin |
| 140 | fwd_fc_sched_sm = 1'b0; |
| 141 | cpu_sched_sm = 1'b0; |
| 142 | next_state = state; |
| 143 | end |
| 144 | else if (fc_lookup_req) |
| 145 | begin |
| 146 | fwd_fc_sched_sm = 1'b1; |
| 147 | next_state = FWD_IDLE; |
| 148 | end |
| 149 | else if (is_cpu_req) |
| 150 | begin |
| 151 | cpu_sched_sm = 1'b1; |
| 152 | next_state = CPU_IDLE; |
| 153 | end |
| 154 | else |
| 155 | next_state = state; |
| 156 | |
| 157 | end |
| 158 | |
| 159 | FWD_IDLE: |
| 160 | begin |
| 161 | if (srch_burst_done & fwd_reqs_served) |
| 162 | next_state = CPU_ARB; |
| 163 | else if (srch_burst_done) |
| 164 | next_state = FWD_ARB; |
| 165 | else |
| 166 | next_state = state; |
| 167 | end |
| 168 | |
| 169 | CPU_ARB: |
| 170 | begin |
| 171 | if (is_cpu_req) |
| 172 | begin |
| 173 | cpu_sched_sm = 1'b1; |
| 174 | next_state = CPU_IDLE; |
| 175 | end |
| 176 | else if (fc_lookup_req) |
| 177 | begin |
| 178 | fwd_fc_sched_sm = 1'b1; |
| 179 | next_state = FWD_IDLE; |
| 180 | end |
| 181 | else |
| 182 | next_state = FWD_ARB; |
| 183 | end |
| 184 | |
| 185 | CPU_IDLE: |
| 186 | begin |
| 187 | next_state = FWD_ARB; |
| 188 | end |
| 189 | |
| 190 | default: next_state = FWD_ARB; |
| 191 | |
| 192 | endcase |
| 193 | |
| 194 | end |
| 195 | |
| 196 | assign fwd_sched_in = fwd_fc_sched_sm | fwd_no_fc_sched_sm; |
| 197 | |
| 198 | dffr #(2) state_reg (cclk, reset, next_state, state); |
| 199 | dffr #(1) fwd_sched_reg (cclk, reset, fwd_sched_in, fwd_sched); |
| 200 | dffr #(1) fwd_fc_sched_reg (cclk, reset, fwd_fc_sched_sm, fwd_fc_sched); |
| 201 | dffr #(1) cpu_sched_reg (cclk, reset, cpu_sched_sm, cpu_sched); |
| 202 | |
| 203 | dffr #(1) fwd_sched_1_reg (cclk, reset, fwd_sched, fwd_sched_1); |
| 204 | dffr #(1) fwd_sched_2_reg (cclk, reset, fwd_sched_1, fwd_sched_2); |
| 205 | dffr #(1) fc_fifo_ren_reg (cclk, reset, fc_fifo_ren_in, fc_fifo_ren); |
| 206 | |
| 207 | assign fc_fifo_ren_in = fwd_sched | fwd_sched_1 | fwd_sched_2; |
| 208 | |
| 209 | |
| 210 | /*********************************************************************/ |
| 211 | //allocate load balance, cpu bandwidth |
| 212 | /*********************************************************************/ |
| 213 | assign fwd_reqs_served = (fwd_sched_cnt == fcram_lookup_ratio); |
| 214 | assign fwd_sched_cnt_en = fwd_fc_sched_sm | cpu_sched_sm; |
| 215 | assign fwd_sched_cnt_in = (cpu_sched_sm | fwd_reqs_served & fwd_fc_sched_sm) ? 4'b0000 : (fwd_sched_cnt + 4'd1); |
| 216 | |
| 217 | dffre #(4) fwd_sched_cnt_reg (cclk, reset, fwd_sched_cnt_en, fwd_sched_cnt_in, fwd_sched_cnt); |
| 218 | |
| 219 | |
| 220 | /**********************/ |
| 221 | //CPU Request |
| 222 | /**********************/ |
| 223 | assign cpu_req_pulse = cpu_fcram_req_sync & !cpu_fcram_req_sync_d; |
| 224 | assign is_cpu_req_en = cpu_req_pulse | cpu_sched; |
| 225 | assign is_cpu_req_in = cpu_req_pulse ? 1'b1 : 1'b0; |
| 226 | |
| 227 | dffr #(1) cpu_req_dly_reg (cclk, reset, cpu_fcram_req_sync, cpu_fcram_req_sync_d); |
| 228 | dffre #(1) is_cpu_req_reg (cclk, reset, is_cpu_req_en, is_cpu_req_in, is_cpu_req); |
| 229 | |
| 230 | assign do_srch_cycle_en = fwd_fc_sched | srch_burst_done; |
| 231 | assign do_srch_cycle_in = fwd_fc_sched ? 1'b1 : 1'b0; |
| 232 | assign do_cpu_cycle_en = cpu_sched | cpu_burst_done_sm; |
| 233 | assign do_cpu_cycle_in = cpu_sched ? 1'b1 : 1'b0; |
| 234 | |
| 235 | dffre #(1) do_srch_cycle_reg (cclk, reset, do_srch_cycle_en, do_srch_cycle_in, do_srch_cycle); |
| 236 | dffre #(1) do_cpu_cycle_reg (cclk, reset, do_cpu_cycle_en, do_cpu_cycle_in, do_cpu_cycle); |
| 237 | |
| 238 | |
| 239 | |
| 240 | endmodule |