| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fflp_flow_fifo.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /**********************************************************************/ |
| 36 | /*project name: NIU */ |
| 37 | /*module name: fflp_flow_fifo */ |
| 38 | /*description: contains the data storage for cam search results to */ |
| 39 | /* hash table lookup and final merge function. */ |
| 40 | /* */ |
| 41 | /*parent module in: */ |
| 42 | /*child modules in: none */ |
| 43 | /*interface modules: */ |
| 44 | /*author name: Jeanne Cai */ |
| 45 | /*date created: 03-17-04 */ |
| 46 | /* */ |
| 47 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ |
| 48 | /* Sun Proprietary and Confidential */ |
| 49 | /* */ |
| 50 | /*modifications: */ |
| 51 | /* */ |
| 52 | module fflp_flow_fifo |
| 53 | ( |
| 54 | clk, |
| 55 | reset, |
| 56 | dout, |
| 57 | hdr_fifo_empty, |
| 58 | hdr_fifo_full, |
| 59 | din, |
| 60 | wen, |
| 61 | ren |
| 62 | ); |
| 63 | |
| 64 | parameter dwidth = 16; |
| 65 | |
| 66 | input clk; |
| 67 | input reset; |
| 68 | input [dwidth-1:0] din; |
| 69 | input wen; //increments wptr and writes in din |
| 70 | input ren; //increments rptr |
| 71 | |
| 72 | output [dwidth-1:0] dout; |
| 73 | output hdr_fifo_empty; |
| 74 | output hdr_fifo_full; |
| 75 | |
| 76 | |
| 77 | wire[dwidth-1:0] dout; |
| 78 | |
| 79 | `ifdef NEPTUNE |
| 80 | reg[dwidth-1:0] data_mem[0:3]; |
| 81 | reg[2:0] wptr; |
| 82 | reg[2:0] rptr; |
| 83 | |
| 84 | wire[1:0] wptr1 = wptr[1:0]; |
| 85 | wire[1:0] rptr1 = rptr[1:0]; |
| 86 | |
| 87 | wire hdr_fifo_full = (wptr[2] != rptr[2]) & (wptr1 == rptr1); |
| 88 | wire hdr_fifo_empty = (wptr[2] == rptr[2]) & (wptr1 == rptr1); |
| 89 | |
| 90 | `else |
| 91 | reg[dwidth-1:0] data_mem[0:1]; |
| 92 | reg[1:0] wptr; |
| 93 | reg[1:0] rptr; |
| 94 | |
| 95 | wire wptr1 = wptr[0]; |
| 96 | wire rptr1 = rptr[0]; |
| 97 | |
| 98 | wire hdr_fifo_full = (wptr[1] != rptr[1]) & (wptr1 == rptr1); |
| 99 | wire hdr_fifo_empty = (wptr[1] == rptr[1]) & (wptr1 == rptr1); |
| 100 | |
| 101 | `endif |
| 102 | |
| 103 | |
| 104 | always @(posedge clk) |
| 105 | if (wen) |
| 106 | data_mem[wptr1] <= din; |
| 107 | |
| 108 | assign dout = data_mem[rptr1]; |
| 109 | |
| 110 | always @(posedge clk) |
| 111 | if (reset) |
| 112 | wptr <= 0; |
| 113 | else if (wen) |
| 114 | wptr <= wptr + 1; |
| 115 | else |
| 116 | wptr <= wptr; |
| 117 | |
| 118 | always @(posedge clk) |
| 119 | if (reset) |
| 120 | rptr <= 0; |
| 121 | else if (ren) |
| 122 | rptr <= rptr + 1; |
| 123 | else |
| 124 | rptr <= rptr; |
| 125 | |
| 126 | |
| 127 | endmodule |