| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lfs.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
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| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /************************************************************************* |
| 38 | * |
| 39 | * File Name : lfs.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : link fault signaling state machine. |
| 42 | * seq_cnt and col_cnt are two independent counter/sensor |
| 43 | * which are reset/controlled independently. Their result |
| 44 | * values are used by lfs_sm for changing states. |
| 45 | * Parent Module: rx_xmac |
| 46 | * Child Module: lfs_sm |
| 47 | * Interface Mod: |
| 48 | * Date Created : 7/30/01 |
| 49 | * |
| 50 | * Copyright (c) 2003, Sun Microsystems, Inc. |
| 51 | * Sun Proprietary and Confidential |
| 52 | * |
| 53 | * Modification : |
| 54 | * |
| 55 | * Synthesis Notes: |
| 56 | * |
| 57 | *************************************************************************/ |
| 58 | |
| 59 | `include "xmac.h" |
| 60 | |
| 61 | module lfs ( |
| 62 | rx_clk, |
| 63 | rx_reset, |
| 64 | lfs_disable_rxclk, |
| 65 | rxc_a, |
| 66 | rxc_b, |
| 67 | rx_data_64bit_reg0, |
| 68 | // outputs |
| 69 | link_fault, // to rx_xmac only |
| 70 | inc_link_fault_count, // to xmac_sync.v |
| 71 | remote_fault_oc, // to xmac_slv. |
| 72 | local_fault_oc, // to xmac_slv. |
| 73 | lfs_state // dynamic signal |
| 74 | ); |
| 75 | |
| 76 | input rx_clk; |
| 77 | input rx_reset; |
| 78 | input lfs_disable_rxclk; |
| 79 | input [3:0] rxc_a; |
| 80 | input [3:0] rxc_b; |
| 81 | input [63:0] rx_data_64bit_reg0; |
| 82 | // outputs |
| 83 | output link_fault; // to bothe xmac_sync then to xmac_slv |
| 84 | output inc_link_fault_count; // to xmac_sync.v |
| 85 | output remote_fault_oc; // to xtlm_sm, tx_xmac, xmac_slv via xmac_syn |
| 86 | output local_fault_oc; // to xtlm_sm, tx_xmac, xmac_slv via xmac_syn |
| 87 | output [1:0] lfs_state; // dynamic signal |
| 88 | |
| 89 | // internal signals |
| 90 | wire [63:0] rx_data_64bit_reg0; |
| 91 | wire [3:0] rxc_a_reg; |
| 92 | wire [3:0] rxc_b_reg; |
| 93 | wire col_cnt_en; |
| 94 | wire rst_col_cnt; |
| 95 | wire rst_seq_cnt; |
| 96 | wire last_seq_type; |
| 97 | // vlint flag_net_has_no_load off |
| 98 | // vlint flag_dangling_net_within_module off |
| 99 | wire load_fault_type; |
| 100 | wire diff_seq_type_in_col_ab; |
| 101 | // vlint flag_dangling_net_within_module on |
| 102 | // vlint flag_net_has_no_load on |
| 103 | |
| 104 | // post 1st silicon metal eco -loj @6-15-06 |
| 105 | // Remove the following extra pipeline. |
| 106 | // RegDff #(4) rxc_a_reg_RegDff (.din(rxc_a),.clk(rx_clk), |
| 107 | // .qout(rxc_a_reg)); |
| 108 | // RegDff #(4) rxc_b_reg_RegDff (.din(rxc_b),.clk(rx_clk), |
| 109 | // .qout(rxc_b_reg)); |
| 110 | assign rxc_a_reg = rxc_a; |
| 111 | assign rxc_b_reg = rxc_b; |
| 112 | |
| 113 | // We need to use unconditioned (unfiltered) rxc signals. |
| 114 | // Can not use rx_dv_8bit_reg0 since it is conditioned by sop_sm. |
| 115 | // rxc_a and rxc_b are chosen since they are not conditioned by sop_sm. |
| 116 | wire local_fault_sequence_a = |
| 117 | ( rxc_a_reg[0] & (rx_data_64bit_reg0[`BYTE0] == `SEQ)) & |
| 118 | (~rxc_a_reg[1] & (rx_data_64bit_reg0[`BYTE1] == 8'h00)) & |
| 119 | (~rxc_a_reg[2] & (rx_data_64bit_reg0[`BYTE2] == 8'h00)) & |
| 120 | (~rxc_a_reg[3] & (rx_data_64bit_reg0[`BYTE3] == 8'h01)) ; |
| 121 | |
| 122 | wire local_fault_sequence_b = |
| 123 | ( rxc_b_reg[0] & (rx_data_64bit_reg0[`BYTE4] == `SEQ)) & |
| 124 | (~rxc_b_reg[1] & (rx_data_64bit_reg0[`BYTE5] == 8'h00)) & |
| 125 | (~rxc_b_reg[2] & (rx_data_64bit_reg0[`BYTE6] == 8'h00)) & |
| 126 | (~rxc_b_reg[3] & (rx_data_64bit_reg0[`BYTE7] == 8'h01)) ; |
| 127 | |
| 128 | wire local_fault_sequence = local_fault_sequence_a | |
| 129 | local_fault_sequence_b; |
| 130 | |
| 131 | wire remote_fault_sequence_a = |
| 132 | ( rxc_a_reg[0] & (rx_data_64bit_reg0[`BYTE0] == `SEQ)) & |
| 133 | (~rxc_a_reg[1] & (rx_data_64bit_reg0[`BYTE1] == 8'h00)) & |
| 134 | (~rxc_a_reg[2] & (rx_data_64bit_reg0[`BYTE2] == 8'h00)) & |
| 135 | (~rxc_a_reg[3] & (rx_data_64bit_reg0[`BYTE3] == 8'h02)) ; |
| 136 | |
| 137 | wire remote_fault_sequence_b = |
| 138 | ( rxc_b_reg[0] & (rx_data_64bit_reg0[`BYTE4] == `SEQ)) & |
| 139 | (~rxc_b_reg[1] & (rx_data_64bit_reg0[`BYTE5] == 8'h00)) & |
| 140 | (~rxc_b_reg[2] & (rx_data_64bit_reg0[`BYTE6] == 8'h00)) & |
| 141 | (~rxc_b_reg[3] & (rx_data_64bit_reg0[`BYTE7] == 8'h02)) ; |
| 142 | |
| 143 | wire remote_fault_sequence = remote_fault_sequence_a | |
| 144 | remote_fault_sequence_b; |
| 145 | |
| 146 | wire fault_sequence = local_fault_sequence | remote_fault_sequence; |
| 147 | wire fault_col_a = local_fault_sequence_a | remote_fault_sequence_a; |
| 148 | wire fault_col_b = local_fault_sequence_b | remote_fault_sequence_b; |
| 149 | wire col_a_eq_0 = ~remote_fault_sequence_a & ~local_fault_sequence_a; |
| 150 | wire col_b_eq_0 = ~remote_fault_sequence_b & ~local_fault_sequence_b; |
| 151 | |
| 152 | |
| 153 | /* ----------------------- seq_type logic ------------------------------ */ |
| 154 | // seq_type : current sequence type |
| 155 | // seq_type == 1 if local fault |
| 156 | // seq_type == 0 if remote fault |
| 157 | |
| 158 | wire remote_fault_oc = link_fault & ~last_seq_type; |
| 159 | wire local_fault_oc = link_fault & last_seq_type; |
| 160 | |
| 161 | wire seq_type = (col_a_eq_0 & local_fault_sequence_b) | |
| 162 | (local_fault_sequence_a & col_b_eq_0) | |
| 163 | (local_fault_sequence_a & local_fault_sequence_b) | |
| 164 | (remote_fault_sequence_a & local_fault_sequence_b); |
| 165 | |
| 166 | // last_seq_type |
| 167 | xREG #(1) last_seq_type_xREG (.din(seq_type),.clk(rx_clk), |
| 168 | .en(fault_sequence),.reset(rx_reset), |
| 169 | .qout(last_seq_type)); |
| 170 | |
| 171 | |
| 172 | /* ----------------------- seq_cnt logic ------------------------------- */ |
| 173 | /* seq_cnt:A count of the number of received Sequence ordered_sets of |
| 174 | * the same type. |
| 175 | */ |
| 176 | |
| 177 | assign diff_seq_type_in_col_ab = ( local_fault_sequence_a & remote_fault_sequence_b) | |
| 178 | (remote_fault_sequence_a & local_fault_sequence_b); |
| 179 | |
| 180 | // eco @7-17-06 |
| 181 | // wire diff_seq_type = (last_seq_type != seq_type) | diff_seq_type_in_col_ab; |
| 182 | wire diff_seq_type = fault_sequence & ((last_seq_type != seq_type) | diff_seq_type_in_col_ab); |
| 183 | // wire diff_seq_type = 1'b0; // eco 7-19-06 |
| 184 | // |
| 185 | reg [2:0] seq_cnt; |
| 186 | always @ (posedge rx_clk) |
| 187 | if (rx_reset | rst_seq_cnt | diff_seq_type) |
| 188 | seq_cnt <= 0; |
| 189 | else if (fault_sequence) |
| 190 | seq_cnt <= seq_cnt + {2'b0,fault_col_a} + {2'b0,fault_col_b}; |
| 191 | else |
| 192 | seq_cnt <= seq_cnt; // hold |
| 193 | // |
| 194 | wire seq_cnt_less_3 = seq_cnt < 3; |
| 195 | |
| 196 | |
| 197 | /* ----------------------- col_cnt logic ------------------------------- */ |
| 198 | /* col_cnt: A count of the number of columns received not containing |
| 199 | * a fault_sequence. This counter increments at RX_CLK rate |
| 200 | * (on both the rising and falling clock transitions) unless |
| 201 | * reset. |
| 202 | */ |
| 203 | |
| 204 | reg [7:0] col_cnt; |
| 205 | always @ (posedge rx_clk) |
| 206 | if (rx_reset | rst_col_cnt | fault_sequence) |
| 207 | col_cnt <= 0; |
| 208 | else if (col_cnt_en) |
| 209 | col_cnt <= col_cnt + 2; |
| 210 | else |
| 211 | col_cnt <= col_cnt; // keep |
| 212 | |
| 213 | wire col_cnt_limit = col_cnt[7]; |
| 214 | |
| 215 | |
| 216 | PlsGen PlsGen(.reset(rx_reset),.clk(rx_clk),.iSigIn(link_fault), |
| 217 | .oPlsOut(inc_link_fault_count)); |
| 218 | |
| 219 | /* ----------------------- lfs_sm instantiation ------------------------ */ |
| 220 | lfs_sm lfs_sm( |
| 221 | .rx_clk(rx_clk), |
| 222 | .rx_reset(rx_reset), |
| 223 | .lfs_disable_rxclk(lfs_disable_rxclk), |
| 224 | .fault_sequence(fault_sequence), |
| 225 | .col_cnt_limit(col_cnt_limit), |
| 226 | .diff_seq_type(diff_seq_type), |
| 227 | .seq_cnt_less_3(seq_cnt_less_3), |
| 228 | .rst_col_cnt(rst_col_cnt), |
| 229 | .rst_seq_cnt(rst_seq_cnt), |
| 230 | .link_fault(link_fault), |
| 231 | .col_cnt_en(col_cnt_en), |
| 232 | .load_fault_type(load_fault_type), |
| 233 | .lfs_state(lfs_state) // dynamic signal |
| 234 | ); |
| 235 | |
| 236 | |
| 237 | |
| 238 | |
| 239 | endmodule // lfs |
| 240 | |
| 241 | |