| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mif_exec_sm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mif_exec_sm(/*AUTOARG*/ |
| 36 | // Outputs |
| 37 | illegal_instr, set_read_instr, clr_read_instr, set_mdo_en, |
| 38 | clr_mdo_en, ta_clr_mdo_en, mdi_en, shift_en, clr_idle_timer, |
| 39 | wr_done, rd_done, ex_state, |
| 40 | // Inputs |
| 41 | clk, reset, ld_instr, rd_op_code, wr_op_code, read_instr, |
| 42 | idle_done, tx_bit_done, rx_bit_done |
| 43 | ); |
| 44 | input clk; |
| 45 | input reset; |
| 46 | input ld_instr; |
| 47 | input rd_op_code; |
| 48 | input wr_op_code; |
| 49 | input read_instr; |
| 50 | input idle_done; |
| 51 | input tx_bit_done; |
| 52 | input rx_bit_done; |
| 53 | output illegal_instr; |
| 54 | output set_read_instr; |
| 55 | output clr_read_instr; |
| 56 | output set_mdo_en; |
| 57 | output clr_mdo_en; |
| 58 | output ta_clr_mdo_en; |
| 59 | output mdi_en; |
| 60 | output shift_en; |
| 61 | output clr_idle_timer; |
| 62 | output wr_done; |
| 63 | output rd_done; |
| 64 | output [5:0] ex_state; |
| 65 | |
| 66 | |
| 67 | parameter IDLE = 6'h0, DECODE = 6'h1, WAIT = 6'h2, |
| 68 | SEND_0 = 6'h3, SEND_1 = 6'h4, SEND_2 = 6'h5, SEND_3 = 6'h6, |
| 69 | SEND_4 = 6'h7, SEND_5 = 6'h8, SEND_6 = 6'h9, SEND_7 = 6'hA, |
| 70 | SEND_8 = 6'hB, SEND_9 = 6'hC, SEND_10 = 6'hD, SEND_11 = 6'hE, |
| 71 | SEND_12 = 6'hF, SEND_13 = 6'h10, SEND_13_CHK = 6'h11, RD_TA_b14 = 6'h12, |
| 72 | SEND_14 = 6'h13, SEND_15 = 6'h14, SEND_16 = 6'h15, SEND_17 = 6'h16, |
| 73 | SEND_18 = 6'h17, SEND_19 = 6'h18, SEND_20 = 6'h19, SEND_21 = 6'h1A, |
| 74 | SEND_22 = 6'h1B, SEND_23 = 6'h1C, SEND_24 = 6'h1D, SEND_25 = 6'h1E, |
| 75 | SEND_26 = 6'h1F, SEND_27 = 6'h20, SEND_28 = 6'h21, SEND_29 = 6'h22, |
| 76 | SEND_30 = 6'h23, SEND_31 = 6'h24, SEND_31A = 6'h25, |
| 77 | RCV_14 = 6'h26, RCV_15 = 6'h27, RCV_16 = 6'h28, RCV_17 = 6'h29, |
| 78 | RCV_18 = 6'h2A, RCV_19 = 6'h2B, RCV_20 = 6'h2C, RCV_21 = 6'h2D, |
| 79 | RCV_22 = 6'h2E, RCV_23 = 6'h2F, RCV_24 = 6'h30, RCV_25 = 6'h31, |
| 80 | RCV_26 = 6'h32, RCV_27 = 6'h33, RCV_28 = 6'h34, RCV_29 = 6'h35, |
| 81 | RCV_30 = 6'h36, RCV_31 = 6'h37, |
| 82 | WR_DONE = 6'h38, RD_DONE = 6'h39; |
| 83 | |
| 84 | wire [5:0] ex_state; |
| 85 | reg illegal_instr; |
| 86 | reg set_read_instr; |
| 87 | reg clr_read_instr; |
| 88 | reg set_mdo_en; |
| 89 | reg clr_mdo_en; |
| 90 | reg ta_clr_mdo_en; |
| 91 | reg mdi_en; |
| 92 | reg shift_en; |
| 93 | reg clr_idle_timer; |
| 94 | reg wr_done; |
| 95 | reg rd_done; |
| 96 | reg [5:0] new_ex_state; |
| 97 | |
| 98 | always @ (/*AUTOSENSE*/ex_state or idle_done or ld_instr or rd_op_code |
| 99 | or read_instr or rx_bit_done or tx_bit_done or wr_op_code) |
| 100 | |
| 101 | begin |
| 102 | illegal_instr = 0; |
| 103 | set_read_instr = 0; |
| 104 | clr_read_instr = 0; |
| 105 | set_mdo_en = 0; |
| 106 | clr_mdo_en = 0; |
| 107 | ta_clr_mdo_en = 0; |
| 108 | mdi_en = 0; |
| 109 | shift_en = 0; |
| 110 | clr_idle_timer = 0; |
| 111 | wr_done = 0; |
| 112 | rd_done = 0; |
| 113 | new_ex_state = IDLE; |
| 114 | |
| 115 | case (ex_state) //synopsys parallel_case |
| 116 | |
| 117 | IDLE: |
| 118 | begin |
| 119 | if (ld_instr) |
| 120 | begin |
| 121 | set_mdo_en = 1; |
| 122 | clr_idle_timer = 1; |
| 123 | new_ex_state = DECODE; |
| 124 | end |
| 125 | else new_ex_state = IDLE; |
| 126 | end |
| 127 | |
| 128 | DECODE: |
| 129 | begin |
| 130 | if (rd_op_code) |
| 131 | begin |
| 132 | set_read_instr = 1; |
| 133 | new_ex_state = WAIT; |
| 134 | end |
| 135 | else if (wr_op_code) |
| 136 | begin |
| 137 | clr_read_instr = 1; |
| 138 | new_ex_state = WAIT; |
| 139 | end |
| 140 | else |
| 141 | begin |
| 142 | illegal_instr = 1; |
| 143 | new_ex_state = IDLE; |
| 144 | end |
| 145 | end |
| 146 | |
| 147 | WAIT:// 2 |
| 148 | begin |
| 149 | if (idle_done & tx_bit_done) // sync up idle_count and div_count |
| 150 | begin |
| 151 | shift_en = 1; // the first data will be latched by frame_clk at the same time. This is to shift out 2nd data. |
| 152 | new_ex_state = SEND_0; |
| 153 | end |
| 154 | else new_ex_state = WAIT; |
| 155 | end |
| 156 | |
| 157 | SEND_0:// 3 // 1st mdio data |
| 158 | begin |
| 159 | if (tx_bit_done) |
| 160 | begin |
| 161 | shift_en = 1; // This is to shift out 3rd data. |
| 162 | new_ex_state = SEND_1; |
| 163 | end |
| 164 | else new_ex_state = SEND_0; |
| 165 | end |
| 166 | |
| 167 | SEND_1:// 4 // 2nd mdio data |
| 168 | begin |
| 169 | if (tx_bit_done) |
| 170 | begin |
| 171 | shift_en = 1; |
| 172 | new_ex_state = SEND_2; |
| 173 | end |
| 174 | else new_ex_state = SEND_1; |
| 175 | end |
| 176 | |
| 177 | SEND_2:// 5 // 3rd mdio data |
| 178 | begin |
| 179 | if (tx_bit_done) |
| 180 | begin |
| 181 | shift_en = 1; |
| 182 | new_ex_state = SEND_3; |
| 183 | end |
| 184 | else new_ex_state = SEND_2; |
| 185 | end |
| 186 | |
| 187 | SEND_3:// 6 // 4th mdio data |
| 188 | begin |
| 189 | if (tx_bit_done) |
| 190 | begin |
| 191 | shift_en = 1; |
| 192 | new_ex_state = SEND_4; |
| 193 | end |
| 194 | else new_ex_state = SEND_3; |
| 195 | end |
| 196 | |
| 197 | SEND_4:// 7 // 5th mdio data |
| 198 | begin |
| 199 | if (tx_bit_done) |
| 200 | begin |
| 201 | shift_en = 1; |
| 202 | new_ex_state = SEND_5; |
| 203 | end |
| 204 | else new_ex_state = SEND_4; |
| 205 | end |
| 206 | |
| 207 | SEND_5:// 8 // 6th mdio data |
| 208 | begin |
| 209 | if (tx_bit_done) |
| 210 | begin |
| 211 | shift_en = 1; |
| 212 | new_ex_state = SEND_6; |
| 213 | end |
| 214 | else new_ex_state = SEND_5; |
| 215 | end |
| 216 | |
| 217 | SEND_6:// 9 // 7th mdio data |
| 218 | begin |
| 219 | if (tx_bit_done) |
| 220 | begin |
| 221 | shift_en = 1; |
| 222 | new_ex_state = SEND_7; |
| 223 | end |
| 224 | else new_ex_state = SEND_6; |
| 225 | end |
| 226 | |
| 227 | SEND_7:// A // 8th mdio data |
| 228 | begin |
| 229 | if (tx_bit_done) |
| 230 | begin |
| 231 | shift_en = 1; |
| 232 | new_ex_state = SEND_8; |
| 233 | end |
| 234 | else new_ex_state = SEND_7; |
| 235 | end |
| 236 | |
| 237 | SEND_8:// B // 9th mdio data |
| 238 | begin |
| 239 | if (tx_bit_done) |
| 240 | begin |
| 241 | shift_en = 1; |
| 242 | new_ex_state = SEND_9; |
| 243 | end |
| 244 | else new_ex_state = SEND_8; |
| 245 | end |
| 246 | |
| 247 | SEND_9:// C // 10th mdio data |
| 248 | begin |
| 249 | if (tx_bit_done) |
| 250 | begin |
| 251 | shift_en = 1; |
| 252 | new_ex_state = SEND_10; |
| 253 | end |
| 254 | else new_ex_state = SEND_9; |
| 255 | end |
| 256 | |
| 257 | SEND_10:// D // 11th mdio data |
| 258 | begin |
| 259 | if (tx_bit_done) |
| 260 | begin |
| 261 | shift_en = 1; |
| 262 | new_ex_state = SEND_11; |
| 263 | end |
| 264 | else new_ex_state = SEND_10; |
| 265 | end |
| 266 | |
| 267 | SEND_11:// E // 12th mdio data |
| 268 | begin |
| 269 | if (tx_bit_done) |
| 270 | begin |
| 271 | shift_en = 1; |
| 272 | new_ex_state = SEND_12; |
| 273 | end |
| 274 | else new_ex_state = SEND_11; |
| 275 | end |
| 276 | |
| 277 | SEND_12:// F // 13th mdio data |
| 278 | begin |
| 279 | if (tx_bit_done) |
| 280 | begin |
| 281 | shift_en = 1; |
| 282 | new_ex_state = SEND_13; |
| 283 | end |
| 284 | else new_ex_state = SEND_12; |
| 285 | end |
| 286 | |
| 287 | SEND_13:// 6'h10 // 14th mdio data |
| 288 | begin |
| 289 | if (tx_bit_done) |
| 290 | begin |
| 291 | shift_en = 1; // This is to shift out 16th bit |
| 292 | new_ex_state = SEND_13_CHK; |
| 293 | end |
| 294 | else new_ex_state = SEND_13; |
| 295 | end |
| 296 | //--------------------------------------------------------------------- |
| 297 | SEND_13_CHK:// 6'h11 (a pulse) // This ex_state check what to do next. Either do a write or read data. |
| 298 | begin |
| 299 | if (read_instr) |
| 300 | begin |
| 301 | ta_clr_mdo_en = 1; |
| 302 | new_ex_state = RD_TA_b14; // read |
| 303 | end |
| 304 | else new_ex_state = SEND_14; |
| 305 | end |
| 306 | |
| 307 | RD_TA_b14:// 6'h12 // for read_op // 15th mdio data // 1st TA time = 1'bZ |
| 308 | begin |
| 309 | if (tx_bit_done) new_ex_state = RCV_14; // 26 |
| 310 | else new_ex_state = RD_TA_b14; // stay&wait for tx_bit_done |
| 311 | end |
| 312 | //--------------------------------------------------------------------- |
| 313 | |
| 314 | SEND_14:// 6'h13 // for write_op // 15th mdio data // 1st TA time = 1'b1 |
| 315 | begin |
| 316 | if (tx_bit_done) |
| 317 | begin |
| 318 | shift_en = 1; // This is to shift out 17th bit |
| 319 | new_ex_state = SEND_15; |
| 320 | end |
| 321 | else new_ex_state = SEND_14; |
| 322 | end |
| 323 | |
| 324 | SEND_15:// 6'h14 // 16th mdio data |
| 325 | begin |
| 326 | if (tx_bit_done) |
| 327 | begin |
| 328 | shift_en = 1; |
| 329 | new_ex_state = SEND_16; |
| 330 | end |
| 331 | else new_ex_state = SEND_15; |
| 332 | end |
| 333 | |
| 334 | SEND_16:// 6'h15 // 17th mdio data |
| 335 | begin |
| 336 | if (tx_bit_done) |
| 337 | begin |
| 338 | shift_en = 1; |
| 339 | new_ex_state = SEND_17; |
| 340 | end |
| 341 | else new_ex_state = SEND_16; |
| 342 | end |
| 343 | |
| 344 | SEND_17:// 6'h16 // 18th mdio data |
| 345 | begin |
| 346 | if (tx_bit_done) |
| 347 | begin |
| 348 | shift_en = 1; |
| 349 | new_ex_state = SEND_18; |
| 350 | end |
| 351 | else new_ex_state = SEND_17; |
| 352 | end |
| 353 | |
| 354 | SEND_18:// 6'h17 // 19th mdio data |
| 355 | begin |
| 356 | if (tx_bit_done) |
| 357 | begin |
| 358 | shift_en = 1; |
| 359 | new_ex_state = SEND_19; |
| 360 | end |
| 361 | else new_ex_state = SEND_18; |
| 362 | end |
| 363 | |
| 364 | SEND_19:// 6'h18 // 20th mdio data |
| 365 | begin |
| 366 | if (tx_bit_done) |
| 367 | begin |
| 368 | shift_en = 1; |
| 369 | new_ex_state = SEND_20; |
| 370 | end |
| 371 | else new_ex_state = SEND_19; |
| 372 | end |
| 373 | |
| 374 | SEND_20:// 6'h19 // 21st mdio data |
| 375 | begin |
| 376 | if (tx_bit_done) |
| 377 | begin |
| 378 | shift_en = 1; |
| 379 | new_ex_state = SEND_21; |
| 380 | end |
| 381 | else new_ex_state = SEND_20; |
| 382 | end |
| 383 | |
| 384 | SEND_21:// 6'h1A // 22nd mdio data |
| 385 | begin |
| 386 | if (tx_bit_done) |
| 387 | begin |
| 388 | shift_en = 1; |
| 389 | new_ex_state = SEND_22; |
| 390 | end |
| 391 | else new_ex_state = SEND_21; |
| 392 | end |
| 393 | |
| 394 | SEND_22:// 6'h1B // 23rd mdio data |
| 395 | begin |
| 396 | if (tx_bit_done) |
| 397 | begin |
| 398 | shift_en = 1; |
| 399 | new_ex_state = SEND_23; |
| 400 | end |
| 401 | else new_ex_state = SEND_22; |
| 402 | end |
| 403 | |
| 404 | SEND_23:// 6'h1C // 24th mdio data |
| 405 | begin |
| 406 | if (tx_bit_done) |
| 407 | begin |
| 408 | shift_en = 1; |
| 409 | new_ex_state = SEND_24; |
| 410 | end |
| 411 | else new_ex_state = SEND_23; |
| 412 | end |
| 413 | |
| 414 | SEND_24:// 6'h1D // 25th mdio data |
| 415 | begin |
| 416 | if (tx_bit_done) |
| 417 | begin |
| 418 | shift_en = 1; |
| 419 | new_ex_state = SEND_25; |
| 420 | end |
| 421 | else new_ex_state = SEND_24; |
| 422 | end |
| 423 | |
| 424 | SEND_25:// 6'h1E // 26th mdio data |
| 425 | begin |
| 426 | if (tx_bit_done) |
| 427 | begin |
| 428 | shift_en = 1; |
| 429 | new_ex_state = SEND_26; |
| 430 | end |
| 431 | else new_ex_state = SEND_25; |
| 432 | end |
| 433 | |
| 434 | SEND_26:// 6'h1F // 27th mdio data |
| 435 | begin |
| 436 | if (tx_bit_done) |
| 437 | begin |
| 438 | shift_en = 1; |
| 439 | new_ex_state = SEND_27; |
| 440 | end |
| 441 | else new_ex_state = SEND_26; |
| 442 | end |
| 443 | |
| 444 | SEND_27:// 6'h20 // 28th mdio data |
| 445 | begin |
| 446 | if (tx_bit_done) |
| 447 | begin |
| 448 | shift_en = 1; |
| 449 | new_ex_state = SEND_28; |
| 450 | end |
| 451 | else new_ex_state = SEND_27; |
| 452 | end |
| 453 | |
| 454 | SEND_28:// 6'h21 // 29th mdio data |
| 455 | begin |
| 456 | if (tx_bit_done) |
| 457 | begin |
| 458 | shift_en = 1; |
| 459 | new_ex_state = SEND_29; |
| 460 | end |
| 461 | else new_ex_state = SEND_28; |
| 462 | end |
| 463 | |
| 464 | SEND_29:// 6'h22 // 30th mdio data |
| 465 | begin |
| 466 | if (tx_bit_done) |
| 467 | begin |
| 468 | shift_en = 1; |
| 469 | new_ex_state = SEND_30; |
| 470 | end |
| 471 | else new_ex_state = SEND_29; |
| 472 | end |
| 473 | |
| 474 | SEND_30:// 6'h23 // 31st mdio data |
| 475 | begin |
| 476 | if (tx_bit_done) |
| 477 | begin |
| 478 | shift_en = 1; |
| 479 | new_ex_state = SEND_31; |
| 480 | end |
| 481 | else new_ex_state = SEND_30; |
| 482 | end |
| 483 | |
| 484 | SEND_31:// 6'h24 // 32nd mdio_data |
| 485 | begin |
| 486 | clr_mdo_en = 1; |
| 487 | if (tx_bit_done) new_ex_state = SEND_31A; |
| 488 | else new_ex_state = SEND_31; |
| 489 | end |
| 490 | |
| 491 | SEND_31A:// 6'h25 |
| 492 | begin |
| 493 | if (tx_bit_done) new_ex_state = WR_DONE; |
| 494 | else new_ex_state = SEND_31A; |
| 495 | end |
| 496 | |
| 497 | RCV_14:// 6'h26 // 16th 2nd TA = 1'bZ. MMD drive 1'b0; -loj @1/27/05 |
| 498 | begin |
| 499 | if (rx_bit_done) |
| 500 | begin |
| 501 | mdi_en = 1; |
| 502 | new_ex_state = RCV_15; |
| 503 | end |
| 504 | else new_ex_state = RCV_14; |
| 505 | end |
| 506 | |
| 507 | RCV_15:// 6'h27 // 1st rcv data |
| 508 | begin |
| 509 | if (rx_bit_done) |
| 510 | begin |
| 511 | mdi_en = 1; |
| 512 | shift_en = 1; |
| 513 | new_ex_state = RCV_16; |
| 514 | end |
| 515 | else new_ex_state = RCV_15; |
| 516 | end |
| 517 | |
| 518 | RCV_16:// 6'h28 // 2nd rcv data |
| 519 | begin |
| 520 | if (rx_bit_done) |
| 521 | begin |
| 522 | mdi_en = 1; |
| 523 | shift_en = 1; |
| 524 | new_ex_state = RCV_17; |
| 525 | end |
| 526 | else new_ex_state = RCV_16; |
| 527 | end |
| 528 | |
| 529 | RCV_17:// 6'h29 // 3rd rcv data |
| 530 | begin |
| 531 | if (rx_bit_done) |
| 532 | begin |
| 533 | mdi_en = 1; |
| 534 | shift_en = 1; |
| 535 | new_ex_state = RCV_18; |
| 536 | end |
| 537 | else new_ex_state = RCV_17; |
| 538 | end |
| 539 | |
| 540 | RCV_18:// 6'h2A // 4th rcv data |
| 541 | begin |
| 542 | if (rx_bit_done) |
| 543 | begin |
| 544 | mdi_en = 1; |
| 545 | shift_en = 1; |
| 546 | new_ex_state = RCV_19; |
| 547 | end |
| 548 | else new_ex_state = RCV_18; |
| 549 | end |
| 550 | |
| 551 | RCV_19:// 6'h2B // 5th rcv data |
| 552 | begin |
| 553 | if (rx_bit_done) |
| 554 | begin |
| 555 | mdi_en = 1; |
| 556 | shift_en = 1; |
| 557 | new_ex_state = RCV_20; |
| 558 | end |
| 559 | else new_ex_state = RCV_19; |
| 560 | end |
| 561 | |
| 562 | RCV_20:// 6'h2C // 6th rcv data |
| 563 | begin |
| 564 | if (rx_bit_done) |
| 565 | begin |
| 566 | mdi_en = 1; |
| 567 | shift_en = 1; |
| 568 | new_ex_state = RCV_21; |
| 569 | end |
| 570 | else new_ex_state = RCV_20; |
| 571 | end |
| 572 | |
| 573 | RCV_21:// 6'h2D // 7th rcv data |
| 574 | begin |
| 575 | if (rx_bit_done) |
| 576 | begin |
| 577 | mdi_en = 1; |
| 578 | shift_en = 1; |
| 579 | new_ex_state = RCV_22; |
| 580 | end |
| 581 | else new_ex_state = RCV_21; |
| 582 | end |
| 583 | |
| 584 | RCV_22:// 6'h2E // 8th rcv data |
| 585 | begin |
| 586 | if (rx_bit_done) |
| 587 | begin |
| 588 | mdi_en = 1; |
| 589 | shift_en = 1; |
| 590 | new_ex_state = RCV_23; |
| 591 | end |
| 592 | else new_ex_state = RCV_22; |
| 593 | end |
| 594 | |
| 595 | RCV_23:// 6'h2F // 9th rcv data |
| 596 | begin |
| 597 | if (rx_bit_done) |
| 598 | begin |
| 599 | mdi_en = 1; |
| 600 | shift_en = 1; |
| 601 | new_ex_state = RCV_24; |
| 602 | end |
| 603 | else new_ex_state = RCV_23; |
| 604 | end |
| 605 | |
| 606 | RCV_24:// 6'h30 // 10th rcv data |
| 607 | begin |
| 608 | if (rx_bit_done) |
| 609 | begin |
| 610 | mdi_en = 1; |
| 611 | shift_en = 1; |
| 612 | new_ex_state = RCV_25; |
| 613 | end |
| 614 | else new_ex_state = RCV_24; |
| 615 | end |
| 616 | |
| 617 | RCV_25:// 6'h31 // 11th rcv data |
| 618 | begin |
| 619 | if (rx_bit_done) |
| 620 | begin |
| 621 | mdi_en = 1; |
| 622 | shift_en = 1; |
| 623 | new_ex_state = RCV_26; |
| 624 | end |
| 625 | else new_ex_state = RCV_25; |
| 626 | end |
| 627 | |
| 628 | RCV_26:// 6'h32 // 12th rcv data |
| 629 | begin |
| 630 | if (rx_bit_done) |
| 631 | begin |
| 632 | mdi_en = 1; |
| 633 | shift_en = 1; |
| 634 | new_ex_state = RCV_27; |
| 635 | end |
| 636 | else new_ex_state = RCV_26; |
| 637 | end |
| 638 | |
| 639 | RCV_27:// 6'h33 // 13th rcv data |
| 640 | begin |
| 641 | if (rx_bit_done) |
| 642 | begin |
| 643 | mdi_en = 1; |
| 644 | shift_en = 1; |
| 645 | new_ex_state = RCV_28; |
| 646 | end |
| 647 | else new_ex_state = RCV_27; |
| 648 | end |
| 649 | |
| 650 | RCV_28:// 6'h34 // 14th rcv data |
| 651 | begin |
| 652 | if (rx_bit_done) |
| 653 | begin |
| 654 | mdi_en = 1; |
| 655 | shift_en = 1; |
| 656 | new_ex_state = RCV_29; |
| 657 | end |
| 658 | else new_ex_state = RCV_28; |
| 659 | end |
| 660 | |
| 661 | RCV_29:// 6'h35 // 15th rcv data |
| 662 | begin |
| 663 | if (rx_bit_done) |
| 664 | begin |
| 665 | mdi_en = 1; |
| 666 | shift_en = 1; |
| 667 | new_ex_state = RCV_30; |
| 668 | end |
| 669 | else new_ex_state = RCV_29; |
| 670 | end |
| 671 | |
| 672 | RCV_30:// 6'h36 // 16th rcv data |
| 673 | begin |
| 674 | if (rx_bit_done) |
| 675 | begin |
| 676 | mdi_en = 1; |
| 677 | shift_en = 1; |
| 678 | new_ex_state = RCV_31; |
| 679 | end |
| 680 | else new_ex_state = RCV_30; |
| 681 | end |
| 682 | |
| 683 | RCV_31:// 6'h37 // This state is not doing anything. -loj 1/28/05 |
| 684 | begin |
| 685 | if (rx_bit_done) |
| 686 | begin |
| 687 | mdi_en = 1; // useless mdi_en -loj 1/28/05 |
| 688 | new_ex_state = RD_DONE; |
| 689 | end |
| 690 | else new_ex_state = RCV_31; |
| 691 | end |
| 692 | |
| 693 | WR_DONE:// 6'h38 |
| 694 | begin |
| 695 | wr_done = 1; |
| 696 | new_ex_state = IDLE; |
| 697 | end |
| 698 | |
| 699 | RD_DONE:// 6'h39 |
| 700 | begin |
| 701 | rd_done = 1; |
| 702 | new_ex_state = IDLE; |
| 703 | end |
| 704 | endcase |
| 705 | end // always @ (clk or... |
| 706 | |
| 707 | |
| 708 | RegRst #(6) ex_state_RegRst (.clk(clk),.reset(reset),.din(new_ex_state),.qout(ex_state)); |
| 709 | |
| 710 | endmodule |