| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_dmc_txcache.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * |
| 38 | * Orignal Author(s): Arvind Srinivasan |
| 39 | * Modifier(s): |
| 40 | * Project(s): Neptune |
| 41 | * |
| 42 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 43 | * |
| 44 | * All Rights Reserved. |
| 45 | * |
| 46 | * This verilog model is the confidential and proprietary property of |
| 47 | * Sun Microsystems, Inc., and the possession or use of this model |
| 48 | * requires a written license from Sun Microsystems, Inc. |
| 49 | * |
| 50 | **********************************************************************/ |
| 51 | |
| 52 | // 4K + Parity +tags |
| 53 | module niu_dmc_txcache( // |
| 54 | |
| 55 | `ifdef NEPTUNE |
| 56 | `else |
| 57 | tcu_aclk, |
| 58 | tcu_bclk, |
| 59 | tcu_se_scancollar_in, |
| 60 | tcu_se_scancollar_out, |
| 61 | tcu_array_wr_inhibit, |
| 62 | tds_tdmc_mbist_scan_in, |
| 63 | tds_tdmc_mbist_scan_out, |
| 64 | tcu_mbist_bisi_en, |
| 65 | tcu_tds_tdmc_mbist_start, |
| 66 | tds_tdmc_tcu_mbist_fail, |
| 67 | tds_tdmc_tcu_mbist_done, |
| 68 | tcu_scan_en, |
| 69 | tcu_mbist_user_mode, |
| 70 | l2clk_2x, |
| 71 | hdr_sram_rvalue_tdmc, |
| 72 | hdr_sram_rid_tdmc, |
| 73 | hdr_sram_wr_en_tdmc, |
| 74 | hdr_sram_red_clr_tdmc, |
| 75 | sram_hdr_read_data_tdmc, |
| 76 | tds_tcu_dmo_data_out, |
| 77 | sram_reset, |
| 78 | iol2clk, |
| 79 | |
| 80 | |
| 81 | `endif // !ifdef NEPTUNE |
| 82 | |
| 83 | WriteStrobe, // Strobe for Write Port |
| 84 | WriteClock, // Clock for Write Port |
| 85 | ReadStrobe, // Strobe for Read Port |
| 86 | ReadAddr, // Address for Read Port |
| 87 | WriteAddr, // Address for Write Port |
| 88 | DataIn, // Data Output for Write Port |
| 89 | DataOut, // Data Input for Read Port |
| 90 | ParityStatus, // Result of Parity Comparison |
| 91 | parity_corrupt_dma_match, |
| 92 | parity_corrupt_config, |
| 93 | Reset_L |
| 94 | ); |
| 95 | |
| 96 | |
| 97 | input WriteStrobe; |
| 98 | input WriteClock; |
| 99 | input ReadStrobe; |
| 100 | input [7:0] ReadAddr; |
| 101 | input [7:0] WriteAddr; |
| 102 | input [131:0] DataIn; |
| 103 | |
| 104 | input [31:0] parity_corrupt_dma_match; |
| 105 | |
| 106 | input [31:0] parity_corrupt_config; |
| 107 | input Reset_L; |
| 108 | output [131:0] DataOut; |
| 109 | output ParityStatus; |
| 110 | |
| 111 | `ifdef NEPTUNE |
| 112 | `else |
| 113 | |
| 114 | // mbist if |
| 115 | input tcu_aclk; |
| 116 | input tcu_bclk; |
| 117 | input tcu_se_scancollar_in; |
| 118 | input tcu_se_scancollar_out; |
| 119 | input tcu_array_wr_inhibit; |
| 120 | input tcu_scan_en; |
| 121 | |
| 122 | input tds_tdmc_mbist_scan_in; |
| 123 | output tds_tdmc_mbist_scan_out; |
| 124 | |
| 125 | |
| 126 | input tcu_tds_tdmc_mbist_start; |
| 127 | input tcu_mbist_bisi_en; |
| 128 | output tds_tdmc_tcu_mbist_fail; |
| 129 | output tds_tdmc_tcu_mbist_done; |
| 130 | |
| 131 | |
| 132 | input l2clk_2x; |
| 133 | input iol2clk; |
| 134 | input tcu_mbist_user_mode; |
| 135 | |
| 136 | |
| 137 | input [6:0] hdr_sram_rvalue_tdmc; |
| 138 | input [1:0] hdr_sram_rid_tdmc; |
| 139 | input hdr_sram_wr_en_tdmc; |
| 140 | input hdr_sram_red_clr_tdmc; |
| 141 | output [6:0] sram_hdr_read_data_tdmc; |
| 142 | output [39:0] tds_tcu_dmo_data_out; |
| 143 | input sram_reset; |
| 144 | |
| 145 | |
| 146 | |
| 147 | `endif // !ifdef NEPTUNE |
| 148 | |
| 149 | |
| 150 | wire [131:0] RamDataOut; |
| 151 | wire [131:0] DataOut; |
| 152 | wire [15:0] parity_in; |
| 153 | wire [15:0] parity_out; |
| 154 | |
| 155 | wire ParityStatus; |
| 156 | |
| 157 | `ifdef NEPTUNE |
| 158 | `else |
| 159 | wire [7:0] niu_mb2_wdata; |
| 160 | wire [7:0] niu_mb2_addr; |
| 161 | wire [6:0] sram_hdr_read_data_tdmc; |
| 162 | wire niu_mb2_wr_en; |
| 163 | wire niu_mb2_rd_en; |
| 164 | wire niu_mb2_run; |
| 165 | wire [39:0] tds_tcu_dmo_data_out; |
| 166 | // wire scan_wire; // cc Added per Carlos |
| 167 | |
| 168 | wire [147:0] concat_niu_mb2_ram_256_148_wdata={ |
| 169 | niu_mb2_wdata[3:0], |
| 170 | niu_mb2_wdata, |
| 171 | niu_mb2_wdata, |
| 172 | niu_mb2_wdata, |
| 173 | niu_mb2_wdata, |
| 174 | niu_mb2_wdata, |
| 175 | niu_mb2_wdata, |
| 176 | niu_mb2_wdata, |
| 177 | niu_mb2_wdata, |
| 178 | niu_mb2_wdata, |
| 179 | niu_mb2_wdata, |
| 180 | niu_mb2_wdata, |
| 181 | niu_mb2_wdata, |
| 182 | niu_mb2_wdata, |
| 183 | niu_mb2_wdata, |
| 184 | niu_mb2_wdata, |
| 185 | niu_mb2_wdata, |
| 186 | niu_mb2_wdata, |
| 187 | niu_mb2_wdata |
| 188 | }; |
| 189 | |
| 190 | wire [147:0] niu_mb2_ram_256_148_data_out = {parity_out,RamDataOut}; |
| 191 | `endif |
| 192 | |
| 193 | |
| 194 | niu_tdmc_cacheparity niu_tdmc_cacheparity ( |
| 195 | .SysClk(WriteClock), |
| 196 | .Reset_L(Reset_L), |
| 197 | .data_in(DataIn), |
| 198 | .parity(parity_in), |
| 199 | .write_strobe(WriteStrobe), |
| 200 | .write_addr(WriteAddr[2:0]), |
| 201 | .parity_corrupt_dma_match(parity_corrupt_dma_match), |
| 202 | .parity_corrupt_config(parity_corrupt_config), |
| 203 | .data_out(DataOut), // floped version of RamDataOut |
| 204 | .ram_data_out(RamDataOut), |
| 205 | .ram_parity_out(parity_out), |
| 206 | .parity_status(ParityStatus) |
| 207 | ); |
| 208 | |
| 209 | |
| 210 | |
| 211 | niu_ram_256_148 niu_ram_256_148 ( |
| 212 | |
| 213 | `ifdef NEPTUNE |
| 214 | `else |
| 215 | |
| 216 | .tcu_scan_en (tcu_scan_en), |
| 217 | .tcu_aclk(tcu_aclk), |
| 218 | .tcu_bclk(tcu_bclk), |
| 219 | .tcu_se_scancollar_in(tcu_se_scancollar_in), |
| 220 | .tcu_se_scancollar_out(tcu_se_scancollar_out), |
| 221 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), |
| 222 | .scan_in(1'b0), // cc |
| 223 | .scan_out(), // cc |
| 224 | // array name = <array_name> |
| 225 | // 8 bit wdata used for 152 bits |
| 226 | .mbi_wdata(concat_niu_mb2_ram_256_148_wdata[147:0]), |
| 227 | .mbi_rd_adr(niu_mb2_addr), |
| 228 | .mbi_wr_adr(niu_mb2_addr), |
| 229 | .mbi_wr_en(niu_mb2_wr_en), |
| 230 | .mbi_rd_en(niu_mb2_rd_en), |
| 231 | .mbi_run(niu_mb2_run), |
| 232 | .l2clk_2x(l2clk_2x), |
| 233 | // signals for efuse |
| 234 | |
| 235 | .hdr_sram_rvalue (hdr_sram_rvalue_tdmc), |
| 236 | .hdr_sram_rid (hdr_sram_rid_tdmc), |
| 237 | .hdr_sram_wr_en (hdr_sram_wr_en_tdmc), |
| 238 | .hdr_sram_red_clr (hdr_sram_red_clr_tdmc), |
| 239 | .sram_hdr_read_data (sram_hdr_read_data_tdmc), |
| 240 | .reset (sram_reset), |
| 241 | `endif |
| 242 | |
| 243 | .data_inp({parity_in,DataIn}), |
| 244 | .addr_rd(ReadAddr), |
| 245 | .addr_wt(WriteAddr), |
| 246 | .wt_enable(WriteStrobe), |
| 247 | .cs_rd(ReadStrobe), |
| 248 | `ifdef NEPTUNE |
| 249 | .clk(WriteClock), |
| 250 | `else |
| 251 | .clk(iol2clk), |
| 252 | `endif |
| 253 | |
| 254 | .data_out({parity_out,RamDataOut}) |
| 255 | ); |
| 256 | |
| 257 | // reg [131:0] regFile[255:0]; |
| 258 | |
| 259 | /*--------------------------------------------------------------*/ |
| 260 | // Read logic |
| 261 | /*--------------------------------------------------------------*/ |
| 262 | // always @(posedge ReadClock or negedge Reset_L) |
| 263 | // if (!Reset_L) DataOut <= 146'h0; |
| 264 | // else if (ReadStrobe) DataOut <= regFile[ReadAddr]; |
| 265 | |
| 266 | /*--------------------------------------------------------------*/ |
| 267 | // Write logic |
| 268 | /*--------------------------------------------------------------*/ |
| 269 | // always @(posedge WriteClock or negedge Reset_L) |
| 270 | // if (!Reset_L) regFile[0] <= 146'h0; |
| 271 | // else if (WriteStrobe) regFile[WriteAddr] <= DataIn; |
| 272 | |
| 273 | `ifdef NEPTUNE |
| 274 | `else |
| 275 | |
| 276 | niu_mb2 niu_mb2 (/*AUTOJUNK*/ |
| 277 | // Outputs |
| 278 | .niu_mb2_rd_en (niu_mb2_rd_en), |
| 279 | .niu_mb2_wr_en (niu_mb2_wr_en), |
| 280 | .niu_mb2_addr (niu_mb2_addr[7:0]), |
| 281 | .niu_mb2_wdata (niu_mb2_wdata[7:0]), |
| 282 | .niu_mb2_run (niu_mb2_run), |
| 283 | .niu_tcu_mbist_fail_2(tds_tdmc_tcu_mbist_fail), |
| 284 | .niu_tcu_mbist_done_2(tds_tdmc_tcu_mbist_done), |
| 285 | .mb2_scan_out (tds_tdmc_mbist_scan_out), |
| 286 | // signals for DMO |
| 287 | .mb2_dmo_dout(tds_tcu_dmo_data_out), |
| 288 | // Inputs |
| 289 | .l1clk (WriteClock), |
| 290 | .rst_l (Reset_L), |
| 291 | .tcu_mbist_user_mode(tcu_mbist_user_mode), |
| 292 | .mb2_scan_in (tds_tdmc_mbist_scan_in), |
| 293 | .tcu_aclk (tcu_aclk), |
| 294 | .tcu_bclk (tcu_bclk), |
| 295 | .tcu_niu_mbist_start_2(tcu_tds_tdmc_mbist_start), |
| 296 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), |
| 297 | .niu_mb2_tdmc_data_out({niu_mb2_ram_256_148_data_out[147:0]}) ); |
| 298 | `endif |
| 299 | endmodule |
| 300 | // Local Variables: |
| 301 | // verilog-library-directories:(".") |
| 302 | // End: |