| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_ipp_sum_data.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
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| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
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| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | `timescale 1ns/10ps |
| 37 | |
| 38 | /********************************************************** |
| 39 | *********************************************************** |
| 40 | |
| 41 | Project : Niu |
| 42 | |
| 43 | File name : niu_ipp_sum_data.v |
| 44 | |
| 45 | Module(s) name : niu_ipp_sum_data |
| 46 | Original: : sum_data.v main.2, label: |
| 47 | |
| 48 | Parent modules : niu_ipp_sum.v |
| 49 | |
| 50 | Child modules : niu_ipp_sum_lib.v, niu_ipp_sum_lib.h, |
| 51 | |
| 52 | Author's name : George Chu |
| 53 | |
| 54 | Date : March. 2004 |
| 55 | |
| 56 | Description : Data logic of the ipp checksum. |
| 57 | |
| 58 | Synthesis Notes: |
| 59 | |
| 60 | Modification History: |
| 61 | |
| 62 | Date Description |
| 63 | ---- ----------- |
| 64 | |
| 65 | ************************************************************ |
| 66 | ***********************************************************/ |
| 67 | |
| 68 | module niu_ipp_sum_data (din_wrd, hdr_off, |
| 69 | byt_ena, sel_awd, |
| 70 | sel_asw7, |
| 71 | sel_asw6, |
| 72 | sel_asw5, |
| 73 | sel_asw3, |
| 74 | sel_asw2, |
| 75 | sel_asw1, |
| 76 | sel_bwd7, |
| 77 | sel_bwd5, |
| 78 | sel_bwd4, |
| 79 | sel_bwd3, |
| 80 | sel_bwd1, |
| 81 | sel_add, |
| 82 | inp_uln, |
| 83 | get_uln, |
| 84 | add_uln, |
| 85 | clr, clk, |
| 86 | sum_prt_cksum, c_dsum_fail); |
| 87 | |
| 88 | input [127:0] din_wrd; |
| 89 | input [3:0] hdr_off; |
| 90 | input [15:0] byt_ena; |
| 91 | input [1:0] sel_awd; |
| 92 | input sel_asw7; |
| 93 | input sel_asw6; |
| 94 | input sel_asw5; |
| 95 | input sel_asw3; |
| 96 | input sel_asw2; |
| 97 | input sel_asw1; |
| 98 | input sel_bwd7; |
| 99 | input sel_bwd5; |
| 100 | input sel_bwd4; |
| 101 | input sel_bwd3; |
| 102 | input sel_bwd1; |
| 103 | input sel_add; |
| 104 | input [15:0] inp_uln; |
| 105 | input get_uln; |
| 106 | input add_uln; |
| 107 | input clr; |
| 108 | input clk; |
| 109 | output [15:0] sum_prt_cksum; |
| 110 | output c_dsum_fail; |
| 111 | |
| 112 | wire [15:0] sum_prt_cksum; |
| 113 | wire c_dsum_fail; |
| 114 | |
| 115 | wire [15:0] sum_wrd1; |
| 116 | wire [15:0] sum_wrd2; |
| 117 | wire [15:0] sum_wrd3; |
| 118 | wire [15:0] sum_wrd4; |
| 119 | wire [15:0] sum_wrd5; |
| 120 | wire [15:0] sum_wrd6; |
| 121 | wire [15:0] sum_wrd7; |
| 122 | |
| 123 | wire sel_add_q = sel_add || add_uln; |
| 124 | |
| 125 | ipp_sum_dev_01_0q su_dev_01_0q_0 ( |
| 126 | .inp_wd3 (sum_wrd4[15:0]), |
| 127 | .inp_wd2 (sum_wrd2[15:0]), |
| 128 | .inp_wd1 (sum_wrd1[15:0]), |
| 129 | .inp_wrd (din_wrd[15:00]), |
| 130 | .byt_ena (byt_ena[01:00]), |
| 131 | .sel_awd (sel_awd[1:0]), |
| 132 | .sel_add (sel_add_q), |
| 133 | .clr (clr), |
| 134 | .clk (clk), |
| 135 | .prt_cksum (sum_prt_cksum[15:0]), |
| 136 | .cksum_fail (c_dsum_fail) |
| 137 | ); |
| 138 | |
| 139 | ipp_sum_dev_01_ut su_dev_01_ut_1 ( |
| 140 | .inp_uln (inp_uln[15:00]), |
| 141 | .inp_wrd (din_wrd[31:16]), |
| 142 | .hdr_off (hdr_off[03:0]), |
| 143 | .byt_ena (byt_ena[03:02]), |
| 144 | .sel_asw (sel_asw1), |
| 145 | .sel_bwd (sel_bwd1), |
| 146 | .sel_add (sel_add), |
| 147 | .get_uln (get_uln), |
| 148 | .clr (clr), |
| 149 | .clk (clk), |
| 150 | .sum_wrd (sum_wrd1[15:0]) |
| 151 | ); |
| 152 | |
| 153 | ipp_sum_dev_01_0s su_dev_01_0s_2 ( |
| 154 | .inp_wd1 (sum_wrd3[15:0]), |
| 155 | .inp_wrd (din_wrd[47:32]), |
| 156 | .byt_ena (byt_ena[05:04]), |
| 157 | .sel_awd (sel_awd[0]), |
| 158 | .sel_asw (sel_asw2), |
| 159 | .sel_add (sel_add), |
| 160 | .clr (clr), |
| 161 | .clk (clk), |
| 162 | .sum_wrd (sum_wrd2[15:0]) |
| 163 | ); |
| 164 | |
| 165 | ipp_sum_dev_01_0t su_dev_01_0t_3 ( |
| 166 | .inp_wrd (din_wrd[63:48]), |
| 167 | .hdr_off (hdr_off[03:0]), |
| 168 | .byt_ena (byt_ena[07:06]), |
| 169 | .sel_asw (sel_asw3), |
| 170 | .sel_bwd (sel_bwd3), |
| 171 | .sel_add (sel_add), |
| 172 | .clr (clr), |
| 173 | .clk (clk), |
| 174 | .sum_wrd (sum_wrd3[15:0]) |
| 175 | ); |
| 176 | |
| 177 | ipp_sum_dev_01_0r su_dev_01_0r_4 ( |
| 178 | .inp_wd2 (sum_wrd6[15:0]), |
| 179 | .inp_wd1 (sum_wrd5[15:0]), |
| 180 | .inp_wrd (din_wrd[79:64]), |
| 181 | .hdr_off (hdr_off[03:0]), |
| 182 | .byt_ena (byt_ena[09:08]), |
| 183 | .sel_awd (sel_awd[1:0]), |
| 184 | .sel_bwd (sel_bwd4), |
| 185 | .sel_add (sel_add), |
| 186 | .clr (clr), |
| 187 | .clk (clk), |
| 188 | .sum_wrd (sum_wrd4[15:0]) |
| 189 | ); |
| 190 | |
| 191 | ipp_sum_dev_01_0t su_dev_01_0t_5 ( |
| 192 | .inp_wrd (din_wrd[95:80]), |
| 193 | .hdr_off (hdr_off[03:0]), |
| 194 | .byt_ena (byt_ena[11:10]), |
| 195 | .sel_asw (sel_asw5), |
| 196 | .sel_bwd (sel_bwd5), |
| 197 | .sel_add (sel_add), |
| 198 | .clr (clr), |
| 199 | .clk (clk), |
| 200 | .sum_wrd (sum_wrd5[15:0]) |
| 201 | ); |
| 202 | |
| 203 | ipp_sum_dev_01_0s su_dev_01_0s_6 ( |
| 204 | .inp_wd1 (sum_wrd7[15:0]), |
| 205 | .inp_wrd (din_wrd[111:96]), |
| 206 | .byt_ena (byt_ena[13:12]), |
| 207 | .sel_awd (sel_awd[0]), |
| 208 | .sel_asw (sel_asw6), |
| 209 | .sel_add (sel_add), |
| 210 | .clr (clr), |
| 211 | .clk (clk), |
| 212 | .sum_wrd (sum_wrd6[15:0]) |
| 213 | ); |
| 214 | |
| 215 | ipp_sum_dev_01_0t su_dev_01_0t_7 ( |
| 216 | .inp_wrd (din_wrd[127:112]), |
| 217 | .hdr_off (hdr_off[03:0]), |
| 218 | .byt_ena (byt_ena[15:14]), |
| 219 | .sel_asw (sel_asw7), |
| 220 | .sel_bwd (sel_bwd7), |
| 221 | .sel_add (sel_add), |
| 222 | .clr (clr), |
| 223 | .clk (clk), |
| 224 | .sum_wrd (sum_wrd7[15:0]) |
| 225 | ); |
| 226 | |
| 227 | endmodule |
| 228 | |